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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc16236 { 174, 2, 0, 8, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #174 = ADJCALLSTACKDOWN
16237 { 175, 2, 0, 8, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000001ULL, nullptr, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #175 = ADJCALLSTACKUP
17661 { 1599, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, ImplicitList1, OperandInfo149, -1 ,nullptr }, // Inst #1599 = SI_IF_BREAK
17684 { 1622, 2, 0, 12, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo164, -1 ,nullptr }, // Inst #1622 = SI_NON_UNIFORM_BRCOND_PSEUDO
17685 { 1623, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo), 0x1ULL, nullptr, ImplicitList1, OperandInfo165, -1 ,nullptr }, // Inst #1623 = SI_PC_ADD_REL_OFFSET
17733 { 1671, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1671 = S_ABSDIFF_I32
17734 { 1672, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, ImplicitList1, OperandInfo194, -1 ,nullptr }, // Inst #1672 = S_ABS_I32
17735 { 1673, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, ImplicitList1, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1673 = S_ADDC_U32
17735 { 1673, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, ImplicitList1, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1673 = S_ADDC_U32
17736 { 1674, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x21ULL, nullptr, ImplicitList1, OperandInfo195, -1 ,nullptr }, // Inst #1674 = S_ADDK_I32
17737 { 1675, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1675 = S_ADD_I32
17738 { 1676, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1676 = S_ADD_U32
17739 { 1677, 4, 2, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList1, OperandInfo196, -1 ,nullptr }, // Inst #1677 = S_ADD_U64_CO_PSEUDO
17740 { 1678, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x1ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #1678 = S_ADD_U64_PSEUDO
17745 { 1683, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1683 = S_ANDN2_B32
17746 { 1684, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1684 = S_ANDN2_B32_term
17747 { 1685, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #1685 = S_ANDN2_B64
17748 { 1686, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #1686 = S_ANDN2_B64_term
17753 { 1691, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1691 = S_AND_B32
17754 { 1692, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #1692 = S_AND_B64
17757 { 1695, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1695 = S_ASHR_I32
17758 { 1696, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo199, -1 ,nullptr }, // Inst #1696 = S_ASHR_I64
17867 { 1805, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, ImplicitList1, OperandInfo194, -1 ,nullptr }, // Inst #1805 = S_BCNT0_I32_B32
17868 { 1806, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, ImplicitList1, OperandInfo216, -1 ,nullptr }, // Inst #1806 = S_BCNT0_I32_B64
17869 { 1807, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, ImplicitList1, OperandInfo194, -1 ,nullptr }, // Inst #1807 = S_BCNT1_I32_B32
17870 { 1808, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, ImplicitList1, OperandInfo216, -1 ,nullptr }, // Inst #1808 = S_BCNT1_I32_B64
17871 { 1809, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1809 = S_BFE_I32
17872 { 1810, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo199, -1 ,nullptr }, // Inst #1810 = S_BFE_I64
17873 { 1811, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1811 = S_BFE_U32
17874 { 1812, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo199, -1 ,nullptr }, // Inst #1812 = S_BFE_U64
18008 { 1946, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x21ULL, ImplicitList1, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1946 = S_CMOVK_I32
18009 { 1947, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm), 0x5ULL, ImplicitList1, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1947 = S_CMOV_B32
18010 { 1948, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm), 0x5ULL, ImplicitList1, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #1948 = S_CMOV_B64
18011 { 1949, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x21ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1949 = S_CMPK_EQ_I32
18012 { 1950, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x4000000021ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1950 = S_CMPK_EQ_U32
18013 { 1951, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x21ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1951 = S_CMPK_GE_I32
18014 { 1952, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x4000000021ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1952 = S_CMPK_GE_U32
18015 { 1953, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x21ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1953 = S_CMPK_GT_I32
18016 { 1954, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x4000000021ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1954 = S_CMPK_GT_U32
18017 { 1955, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x21ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1955 = S_CMPK_LE_I32
18018 { 1956, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x4000000021ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1956 = S_CMPK_LE_U32
18019 { 1957, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x21ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1957 = S_CMPK_LG_I32
18020 { 1958, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x4000000021ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1958 = S_CMPK_LG_U32
18021 { 1959, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x21ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1959 = S_CMPK_LT_I32
18022 { 1960, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x4000000021ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1960 = S_CMPK_LT_U32
18023 { 1961, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, ImplicitList1, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1961 = S_CSELECT_B32
18024 { 1962, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, ImplicitList1, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1962 = S_CSELECT_B64
18055 { 1993, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1993 = S_LSHL1_ADD_U32
18056 { 1994, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1994 = S_LSHL2_ADD_U32
18057 { 1995, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1995 = S_LSHL3_ADD_U32
18058 { 1996, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1996 = S_LSHL4_ADD_U32
18059 { 1997, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1997 = S_LSHL_B32
18060 { 1998, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo199, -1 ,nullptr }, // Inst #1998 = S_LSHL_B64
18061 { 1999, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1999 = S_LSHR_B32
18062 { 2000, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo199, -1 ,nullptr }, // Inst #2000 = S_LSHR_B64
18063 { 2001, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2001 = S_MAX_I32
18064 { 2002, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2002 = S_MAX_U32
18067 { 2005, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2005 = S_MIN_I32
18068 { 2006, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2006 = S_MIN_U32
18081 { 2019, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x21ULL, nullptr, ImplicitList1, OperandInfo195, -1 ,nullptr }, // Inst #2019 = S_MULK_I32
18085 { 2023, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2023 = S_NAND_B32
18086 { 2024, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #2024 = S_NAND_B64
18089 { 2027, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2027 = S_NOR_B32
18090 { 2028, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #2028 = S_NOR_B64
18093 { 2031, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, ImplicitList1, OperandInfo194, -1 ,nullptr }, // Inst #2031 = S_NOT_B32
18094 { 2032, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, ImplicitList1, OperandInfo198, -1 ,nullptr }, // Inst #2032 = S_NOT_B64
18097 { 2035, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2035 = S_ORN2_B32
18098 { 2036, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #2036 = S_ORN2_B64
18101 { 2039, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2039 = S_OR_B32
18102 { 2040, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2040 = S_OR_B32_term
18103 { 2041, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #2041 = S_OR_B64
18138 { 2076, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, ImplicitList1, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2076 = S_SUBB_U32
18138 { 2076, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, ImplicitList1, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2076 = S_SUBB_U32
18141 { 2079, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2079 = S_SUB_I32
18142 { 2080, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2080 = S_SUB_U32
18143 { 2081, 4, 2, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList1, OperandInfo196, -1 ,nullptr }, // Inst #2081 = S_SUB_U64_CO_PSEUDO
18144 { 2082, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x1ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #2082 = S_SUB_U64_PSEUDO
18151 { 2089, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, ImplicitList1, OperandInfo194, -1 ,nullptr }, // Inst #2089 = S_WQM_B32
18152 { 2090, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, ImplicitList1, OperandInfo198, -1 ,nullptr }, // Inst #2090 = S_WQM_B64
18153 { 2091, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2091 = S_XNOR_B32
18154 { 2092, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #2092 = S_XNOR_B64
18157 { 2095, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2095 = S_XOR_B32
18158 { 2096, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2096 = S_XOR_B32_term
18159 { 2097, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #2097 = S_XOR_B64
18160 { 2098, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #2098 = S_XOR_B64_term
27038 { 10976, 2, 0, 4, 1, 0, 0x11ULL, nullptr, ImplicitList1, OperandInfo705, -1 ,nullptr }, // Inst #10976 = S_BITCMP0_B32
27039 { 10977, 2, 0, 4, 1, 0, 0x11ULL, nullptr, ImplicitList1, OperandInfo259, -1 ,nullptr }, // Inst #10977 = S_BITCMP0_B64
27040 { 10978, 2, 0, 4, 1, 0, 0x11ULL, nullptr, ImplicitList1, OperandInfo705, -1 ,nullptr }, // Inst #10978 = S_BITCMP1_B32
27041 { 10979, 2, 0, 4, 1, 0, 0x11ULL, nullptr, ImplicitList1, OperandInfo259, -1 ,nullptr }, // Inst #10979 = S_BITCMP1_B64
27339 { 11277, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList1, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11277 = S_CBRANCH_SCC0
27340 { 11278, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList1, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11278 = S_CBRANCH_SCC0_pad_s_nop
27341 { 11279, 1, 0, 4, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList1, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11279 = S_CBRANCH_SCC1
27342 { 11280, 1, 0, 8, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x41ULL, ImplicitList1, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #11280 = S_CBRANCH_SCC1_pad_s_nop
27393 { 11331, 2, 0, 4, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x11ULL, nullptr, ImplicitList1, OperandInfo705, -1 ,nullptr }, // Inst #11331 = S_CMP_EQ_I32
27394 { 11332, 2, 0, 4, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x11ULL, nullptr, ImplicitList1, OperandInfo705, -1 ,nullptr }, // Inst #11332 = S_CMP_EQ_U32
27395 { 11333, 2, 0, 4, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x11ULL, nullptr, ImplicitList1, OperandInfo708, -1 ,nullptr }, // Inst #11333 = S_CMP_EQ_U64
27396 { 11334, 2, 0, 4, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x11ULL, nullptr, ImplicitList1, OperandInfo705, -1 ,nullptr }, // Inst #11334 = S_CMP_GE_I32
27397 { 11335, 2, 0, 4, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x11ULL, nullptr, ImplicitList1, OperandInfo705, -1 ,nullptr }, // Inst #11335 = S_CMP_GE_U32
27398 { 11336, 2, 0, 4, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x11ULL, nullptr, ImplicitList1, OperandInfo705, -1 ,nullptr }, // Inst #11336 = S_CMP_GT_I32
27399 { 11337, 2, 0, 4, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x11ULL, nullptr, ImplicitList1, OperandInfo705, -1 ,nullptr }, // Inst #11337 = S_CMP_GT_U32
27400 { 11338, 2, 0, 4, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x11ULL, nullptr, ImplicitList1, OperandInfo705, -1 ,nullptr }, // Inst #11338 = S_CMP_LE_I32
27401 { 11339, 2, 0, 4, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x11ULL, nullptr, ImplicitList1, OperandInfo705, -1 ,nullptr }, // Inst #11339 = S_CMP_LE_U32
27402 { 11340, 2, 0, 4, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x11ULL, nullptr, ImplicitList1, OperandInfo705, -1 ,nullptr }, // Inst #11340 = S_CMP_LG_I32
27403 { 11341, 2, 0, 4, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x11ULL, nullptr, ImplicitList1, OperandInfo705, -1 ,nullptr }, // Inst #11341 = S_CMP_LG_U32
27404 { 11342, 2, 0, 4, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x11ULL, nullptr, ImplicitList1, OperandInfo708, -1 ,nullptr }, // Inst #11342 = S_CMP_LG_U64
27405 { 11343, 2, 0, 4, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x11ULL, nullptr, ImplicitList1, OperandInfo705, -1 ,nullptr }, // Inst #11343 = S_CMP_LT_I32
27406 { 11344, 2, 0, 4, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x11ULL, nullptr, ImplicitList1, OperandInfo705, -1 ,nullptr }, // Inst #11344 = S_CMP_LT_U32
27684 { 11622, 2, 0, 4, 1, 0, 0x11ULL, nullptr, ImplicitList1, OperandInfo705, -1 ,nullptr }, // Inst #11622 = S_SETVSKIP