|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenDisassemblerTables.inc32912 tmp = fieldFromInstruction(insn, 17, 8);
32913 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
32914 tmp = fieldFromInstruction(insn, 0, 9);
32915 if (DecodeVRegOrLds_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
32918 tmp = fieldFromInstruction(insn, 0, 8);
32919 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
32920 tmp = fieldFromInstruction(insn, 8, 8);
32921 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
32924 tmp = fieldFromInstruction(insn, 0, 8);
32925 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
32926 tmp = fieldFromInstruction(insn, 8, 8);
32927 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
32930 tmp = fieldFromInstruction(insn, 0, 8);
32931 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
32932 tmp = fieldFromInstruction(insn, 8, 8);
32933 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
32936 tmp = fieldFromInstruction(insn, 0, 16);
32937 MI.addOperand(MCOperand::createImm(tmp));
32940 tmp = fieldFromInstruction(insn, 0, 16);
32941 if (decodeSoppBrTarget(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
32946 tmp = fieldFromInstruction(insn, 0, 8);
32947 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
32948 tmp = fieldFromInstruction(insn, 8, 8);
32949 MI.addOperand(MCOperand::createImm(tmp));
32952 tmp = fieldFromInstruction(insn, 40, 8);
32953 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
32954 tmp = fieldFromInstruction(insn, 32, 8);
32955 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
32956 tmp = fieldFromInstruction(insn, 48, 5) << 2;
32957 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
32958 tmp = fieldFromInstruction(insn, 8, 4);
32959 MI.addOperand(MCOperand::createImm(tmp));
32960 tmp = fieldFromInstruction(insn, 3, 3);
32961 MI.addOperand(MCOperand::createImm(tmp));
32962 tmp = fieldFromInstruction(insn, 12, 1);
32963 MI.addOperand(MCOperand::createImm(tmp));
32964 tmp = fieldFromInstruction(insn, 7, 1);
32965 MI.addOperand(MCOperand::createImm(tmp));
32966 tmp = fieldFromInstruction(insn, 13, 1);
32967 MI.addOperand(MCOperand::createImm(tmp));
32968 tmp = fieldFromInstruction(insn, 25, 1);
32969 MI.addOperand(MCOperand::createImm(tmp));
32970 tmp = fieldFromInstruction(insn, 15, 1);
32971 MI.addOperand(MCOperand::createImm(tmp));
32972 tmp = fieldFromInstruction(insn, 16, 1);
32973 MI.addOperand(MCOperand::createImm(tmp));
32974 tmp = fieldFromInstruction(insn, 17, 1);
32975 MI.addOperand(MCOperand::createImm(tmp));
32976 tmp = fieldFromInstruction(insn, 63, 1);
32977 MI.addOperand(MCOperand::createImm(tmp));
32980 tmp = fieldFromInstruction(insn, 40, 8);
32981 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
32982 tmp = fieldFromInstruction(insn, 32, 8);
32983 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
32984 tmp = fieldFromInstruction(insn, 48, 5) << 2;
32985 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
32986 tmp = fieldFromInstruction(insn, 8, 4);
32987 MI.addOperand(MCOperand::createImm(tmp));
32988 tmp = fieldFromInstruction(insn, 12, 1);
32989 MI.addOperand(MCOperand::createImm(tmp));
32990 tmp = fieldFromInstruction(insn, 13, 1);
32991 MI.addOperand(MCOperand::createImm(tmp));
32992 tmp = fieldFromInstruction(insn, 25, 1);
32993 MI.addOperand(MCOperand::createImm(tmp));
32994 tmp = fieldFromInstruction(insn, 15, 1);
32995 MI.addOperand(MCOperand::createImm(tmp));
32996 tmp = fieldFromInstruction(insn, 16, 1);
32997 MI.addOperand(MCOperand::createImm(tmp));
32998 tmp = fieldFromInstruction(insn, 17, 1);
32999 MI.addOperand(MCOperand::createImm(tmp));
33000 tmp = fieldFromInstruction(insn, 14, 1);
33001 MI.addOperand(MCOperand::createImm(tmp));
33002 tmp = fieldFromInstruction(insn, 63, 1);
33003 MI.addOperand(MCOperand::createImm(tmp));
33006 tmp = fieldFromInstruction(insn, 40, 8);
33007 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33008 tmp = fieldFromInstruction(insn, 32, 8);
33009 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33010 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33011 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33012 tmp = fieldFromInstruction(insn, 8, 4);
33013 MI.addOperand(MCOperand::createImm(tmp));
33014 tmp = fieldFromInstruction(insn, 3, 3);
33015 MI.addOperand(MCOperand::createImm(tmp));
33016 tmp = fieldFromInstruction(insn, 12, 1);
33017 MI.addOperand(MCOperand::createImm(tmp));
33018 tmp = fieldFromInstruction(insn, 7, 1);
33019 MI.addOperand(MCOperand::createImm(tmp));
33020 tmp = fieldFromInstruction(insn, 13, 1);
33021 MI.addOperand(MCOperand::createImm(tmp));
33022 tmp = fieldFromInstruction(insn, 25, 1);
33023 MI.addOperand(MCOperand::createImm(tmp));
33024 tmp = fieldFromInstruction(insn, 15, 1);
33025 MI.addOperand(MCOperand::createImm(tmp));
33026 tmp = fieldFromInstruction(insn, 16, 1);
33027 MI.addOperand(MCOperand::createImm(tmp));
33028 tmp = fieldFromInstruction(insn, 17, 1);
33029 MI.addOperand(MCOperand::createImm(tmp));
33032 tmp = fieldFromInstruction(insn, 40, 8);
33033 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33034 tmp = fieldFromInstruction(insn, 32, 8);
33035 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33036 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33037 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33038 tmp = fieldFromInstruction(insn, 8, 4);
33039 MI.addOperand(MCOperand::createImm(tmp));
33040 tmp = fieldFromInstruction(insn, 12, 1);
33041 MI.addOperand(MCOperand::createImm(tmp));
33042 tmp = fieldFromInstruction(insn, 13, 1);
33043 MI.addOperand(MCOperand::createImm(tmp));
33044 tmp = fieldFromInstruction(insn, 25, 1);
33045 MI.addOperand(MCOperand::createImm(tmp));
33046 tmp = fieldFromInstruction(insn, 15, 1);
33047 MI.addOperand(MCOperand::createImm(tmp));
33048 tmp = fieldFromInstruction(insn, 16, 1);
33049 MI.addOperand(MCOperand::createImm(tmp));
33050 tmp = fieldFromInstruction(insn, 17, 1);
33051 MI.addOperand(MCOperand::createImm(tmp));
33052 tmp = fieldFromInstruction(insn, 14, 1);
33053 MI.addOperand(MCOperand::createImm(tmp));
33056 tmp = fieldFromInstruction(insn, 40, 8);
33057 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33058 tmp = fieldFromInstruction(insn, 40, 8);
33059 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33060 tmp = fieldFromInstruction(insn, 32, 8);
33061 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33062 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33063 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33064 tmp = fieldFromInstruction(insn, 8, 4);
33065 MI.addOperand(MCOperand::createImm(tmp));
33066 tmp = fieldFromInstruction(insn, 3, 3);
33067 MI.addOperand(MCOperand::createImm(tmp));
33068 tmp = fieldFromInstruction(insn, 12, 1);
33069 MI.addOperand(MCOperand::createImm(tmp));
33070 tmp = fieldFromInstruction(insn, 7, 1);
33071 MI.addOperand(MCOperand::createImm(tmp));
33072 tmp = fieldFromInstruction(insn, 13, 1);
33073 MI.addOperand(MCOperand::createImm(tmp));
33074 tmp = fieldFromInstruction(insn, 25, 1);
33075 MI.addOperand(MCOperand::createImm(tmp));
33076 tmp = fieldFromInstruction(insn, 15, 1);
33077 MI.addOperand(MCOperand::createImm(tmp));
33078 tmp = fieldFromInstruction(insn, 16, 1);
33079 MI.addOperand(MCOperand::createImm(tmp));
33080 tmp = fieldFromInstruction(insn, 17, 1);
33081 MI.addOperand(MCOperand::createImm(tmp));
33084 tmp = fieldFromInstruction(insn, 40, 8);
33085 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33086 tmp = fieldFromInstruction(insn, 40, 8);
33087 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33088 tmp = fieldFromInstruction(insn, 32, 8);
33089 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33090 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33091 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33092 tmp = fieldFromInstruction(insn, 8, 4);
33093 MI.addOperand(MCOperand::createImm(tmp));
33094 tmp = fieldFromInstruction(insn, 3, 3);
33095 MI.addOperand(MCOperand::createImm(tmp));
33096 tmp = fieldFromInstruction(insn, 12, 1);
33097 MI.addOperand(MCOperand::createImm(tmp));
33098 tmp = fieldFromInstruction(insn, 7, 1);
33099 MI.addOperand(MCOperand::createImm(tmp));
33100 tmp = fieldFromInstruction(insn, 13, 1);
33101 MI.addOperand(MCOperand::createImm(tmp));
33102 tmp = fieldFromInstruction(insn, 25, 1);
33103 MI.addOperand(MCOperand::createImm(tmp));
33104 tmp = fieldFromInstruction(insn, 15, 1);
33105 MI.addOperand(MCOperand::createImm(tmp));
33106 tmp = fieldFromInstruction(insn, 16, 1);
33107 MI.addOperand(MCOperand::createImm(tmp));
33108 tmp = fieldFromInstruction(insn, 17, 1);
33109 MI.addOperand(MCOperand::createImm(tmp));
33112 tmp = fieldFromInstruction(insn, 40, 8);
33113 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33114 tmp = fieldFromInstruction(insn, 32, 8);
33115 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33116 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33117 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33118 tmp = fieldFromInstruction(insn, 53, 5) << 2;
33119 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33120 tmp = fieldFromInstruction(insn, 8, 4);
33121 MI.addOperand(MCOperand::createImm(tmp));
33122 tmp = fieldFromInstruction(insn, 3, 3);
33123 MI.addOperand(MCOperand::createImm(tmp));
33124 tmp = fieldFromInstruction(insn, 12, 1);
33125 MI.addOperand(MCOperand::createImm(tmp));
33126 tmp = fieldFromInstruction(insn, 7, 1);
33127 MI.addOperand(MCOperand::createImm(tmp));
33128 tmp = fieldFromInstruction(insn, 13, 1);
33129 MI.addOperand(MCOperand::createImm(tmp));
33130 tmp = fieldFromInstruction(insn, 25, 1);
33131 MI.addOperand(MCOperand::createImm(tmp));
33132 tmp = fieldFromInstruction(insn, 15, 1);
33133 MI.addOperand(MCOperand::createImm(tmp));
33134 tmp = fieldFromInstruction(insn, 16, 1);
33135 MI.addOperand(MCOperand::createImm(tmp));
33136 tmp = fieldFromInstruction(insn, 17, 1);
33137 MI.addOperand(MCOperand::createImm(tmp));
33138 tmp = fieldFromInstruction(insn, 63, 1);
33139 MI.addOperand(MCOperand::createImm(tmp));
33142 tmp = fieldFromInstruction(insn, 40, 8);
33143 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33144 tmp = fieldFromInstruction(insn, 32, 8);
33145 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33146 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33147 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33148 tmp = fieldFromInstruction(insn, 53, 5) << 2;
33149 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33150 tmp = fieldFromInstruction(insn, 8, 4);
33151 MI.addOperand(MCOperand::createImm(tmp));
33152 tmp = fieldFromInstruction(insn, 12, 1);
33153 MI.addOperand(MCOperand::createImm(tmp));
33154 tmp = fieldFromInstruction(insn, 13, 1);
33155 MI.addOperand(MCOperand::createImm(tmp));
33156 tmp = fieldFromInstruction(insn, 25, 1);
33157 MI.addOperand(MCOperand::createImm(tmp));
33158 tmp = fieldFromInstruction(insn, 15, 1);
33159 MI.addOperand(MCOperand::createImm(tmp));
33160 tmp = fieldFromInstruction(insn, 16, 1);
33161 MI.addOperand(MCOperand::createImm(tmp));
33162 tmp = fieldFromInstruction(insn, 17, 1);
33163 MI.addOperand(MCOperand::createImm(tmp));
33164 tmp = fieldFromInstruction(insn, 14, 1);
33165 MI.addOperand(MCOperand::createImm(tmp));
33166 tmp = fieldFromInstruction(insn, 63, 1);
33167 MI.addOperand(MCOperand::createImm(tmp));
33170 tmp = fieldFromInstruction(insn, 40, 8);
33171 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33172 tmp = fieldFromInstruction(insn, 32, 8);
33173 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33174 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33175 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33176 tmp = fieldFromInstruction(insn, 53, 5) << 2;
33177 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33178 tmp = fieldFromInstruction(insn, 8, 4);
33179 MI.addOperand(MCOperand::createImm(tmp));
33180 tmp = fieldFromInstruction(insn, 3, 3);
33181 MI.addOperand(MCOperand::createImm(tmp));
33182 tmp = fieldFromInstruction(insn, 12, 1);
33183 MI.addOperand(MCOperand::createImm(tmp));
33184 tmp = fieldFromInstruction(insn, 7, 1);
33185 MI.addOperand(MCOperand::createImm(tmp));
33186 tmp = fieldFromInstruction(insn, 13, 1);
33187 MI.addOperand(MCOperand::createImm(tmp));
33188 tmp = fieldFromInstruction(insn, 25, 1);
33189 MI.addOperand(MCOperand::createImm(tmp));
33190 tmp = fieldFromInstruction(insn, 15, 1);
33191 MI.addOperand(MCOperand::createImm(tmp));
33192 tmp = fieldFromInstruction(insn, 16, 1);
33193 MI.addOperand(MCOperand::createImm(tmp));
33194 tmp = fieldFromInstruction(insn, 17, 1);
33195 MI.addOperand(MCOperand::createImm(tmp));
33196 tmp = fieldFromInstruction(insn, 63, 1);
33197 MI.addOperand(MCOperand::createImm(tmp));
33200 tmp = fieldFromInstruction(insn, 40, 8);
33201 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33202 tmp = fieldFromInstruction(insn, 32, 8);
33203 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33204 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33205 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33206 tmp = fieldFromInstruction(insn, 53, 5) << 2;
33207 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33208 tmp = fieldFromInstruction(insn, 8, 4);
33209 MI.addOperand(MCOperand::createImm(tmp));
33210 tmp = fieldFromInstruction(insn, 12, 1);
33211 MI.addOperand(MCOperand::createImm(tmp));
33212 tmp = fieldFromInstruction(insn, 13, 1);
33213 MI.addOperand(MCOperand::createImm(tmp));
33214 tmp = fieldFromInstruction(insn, 25, 1);
33215 MI.addOperand(MCOperand::createImm(tmp));
33216 tmp = fieldFromInstruction(insn, 15, 1);
33217 MI.addOperand(MCOperand::createImm(tmp));
33218 tmp = fieldFromInstruction(insn, 16, 1);
33219 MI.addOperand(MCOperand::createImm(tmp));
33220 tmp = fieldFromInstruction(insn, 17, 1);
33221 MI.addOperand(MCOperand::createImm(tmp));
33222 tmp = fieldFromInstruction(insn, 14, 1);
33223 MI.addOperand(MCOperand::createImm(tmp));
33224 tmp = fieldFromInstruction(insn, 63, 1);
33225 MI.addOperand(MCOperand::createImm(tmp));
33228 tmp = fieldFromInstruction(insn, 40, 8);
33229 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33230 tmp = fieldFromInstruction(insn, 32, 8);
33231 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33232 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33233 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33234 tmp = fieldFromInstruction(insn, 53, 5) << 2;
33235 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33236 tmp = fieldFromInstruction(insn, 8, 4);
33237 MI.addOperand(MCOperand::createImm(tmp));
33238 tmp = fieldFromInstruction(insn, 3, 3);
33239 MI.addOperand(MCOperand::createImm(tmp));
33240 tmp = fieldFromInstruction(insn, 12, 1);
33241 MI.addOperand(MCOperand::createImm(tmp));
33242 tmp = fieldFromInstruction(insn, 7, 1);
33243 MI.addOperand(MCOperand::createImm(tmp));
33244 tmp = fieldFromInstruction(insn, 13, 1);
33245 MI.addOperand(MCOperand::createImm(tmp));
33246 tmp = fieldFromInstruction(insn, 25, 1);
33247 MI.addOperand(MCOperand::createImm(tmp));
33248 tmp = fieldFromInstruction(insn, 15, 1);
33249 MI.addOperand(MCOperand::createImm(tmp));
33250 tmp = fieldFromInstruction(insn, 16, 1);
33251 MI.addOperand(MCOperand::createImm(tmp));
33252 tmp = fieldFromInstruction(insn, 17, 1);
33253 MI.addOperand(MCOperand::createImm(tmp));
33254 tmp = fieldFromInstruction(insn, 63, 1);
33255 MI.addOperand(MCOperand::createImm(tmp));
33258 tmp = fieldFromInstruction(insn, 40, 8);
33259 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33260 tmp = fieldFromInstruction(insn, 32, 8);
33261 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33262 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33263 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33264 tmp = fieldFromInstruction(insn, 53, 5) << 2;
33265 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33266 tmp = fieldFromInstruction(insn, 8, 4);
33267 MI.addOperand(MCOperand::createImm(tmp));
33268 tmp = fieldFromInstruction(insn, 12, 1);
33269 MI.addOperand(MCOperand::createImm(tmp));
33270 tmp = fieldFromInstruction(insn, 13, 1);
33271 MI.addOperand(MCOperand::createImm(tmp));
33272 tmp = fieldFromInstruction(insn, 25, 1);
33273 MI.addOperand(MCOperand::createImm(tmp));
33274 tmp = fieldFromInstruction(insn, 15, 1);
33275 MI.addOperand(MCOperand::createImm(tmp));
33276 tmp = fieldFromInstruction(insn, 16, 1);
33277 MI.addOperand(MCOperand::createImm(tmp));
33278 tmp = fieldFromInstruction(insn, 17, 1);
33279 MI.addOperand(MCOperand::createImm(tmp));
33280 tmp = fieldFromInstruction(insn, 14, 1);
33281 MI.addOperand(MCOperand::createImm(tmp));
33282 tmp = fieldFromInstruction(insn, 63, 1);
33283 MI.addOperand(MCOperand::createImm(tmp));
33286 tmp = fieldFromInstruction(insn, 40, 8);
33287 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33288 tmp = fieldFromInstruction(insn, 32, 8);
33289 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33290 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33291 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33292 tmp = fieldFromInstruction(insn, 53, 5) << 2;
33293 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33294 tmp = fieldFromInstruction(insn, 8, 4);
33295 MI.addOperand(MCOperand::createImm(tmp));
33296 tmp = fieldFromInstruction(insn, 3, 3);
33297 MI.addOperand(MCOperand::createImm(tmp));
33298 tmp = fieldFromInstruction(insn, 12, 1);
33299 MI.addOperand(MCOperand::createImm(tmp));
33300 tmp = fieldFromInstruction(insn, 7, 1);
33301 MI.addOperand(MCOperand::createImm(tmp));
33302 tmp = fieldFromInstruction(insn, 13, 1);
33303 MI.addOperand(MCOperand::createImm(tmp));
33304 tmp = fieldFromInstruction(insn, 25, 1);
33305 MI.addOperand(MCOperand::createImm(tmp));
33306 tmp = fieldFromInstruction(insn, 15, 1);
33307 MI.addOperand(MCOperand::createImm(tmp));
33308 tmp = fieldFromInstruction(insn, 16, 1);
33309 MI.addOperand(MCOperand::createImm(tmp));
33310 tmp = fieldFromInstruction(insn, 17, 1);
33311 MI.addOperand(MCOperand::createImm(tmp));
33312 tmp = fieldFromInstruction(insn, 63, 1);
33313 MI.addOperand(MCOperand::createImm(tmp));
33316 tmp = fieldFromInstruction(insn, 40, 8);
33317 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33318 tmp = fieldFromInstruction(insn, 32, 8);
33319 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33320 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33321 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33322 tmp = fieldFromInstruction(insn, 53, 5) << 2;
33323 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33324 tmp = fieldFromInstruction(insn, 8, 4);
33325 MI.addOperand(MCOperand::createImm(tmp));
33326 tmp = fieldFromInstruction(insn, 12, 1);
33327 MI.addOperand(MCOperand::createImm(tmp));
33328 tmp = fieldFromInstruction(insn, 13, 1);
33329 MI.addOperand(MCOperand::createImm(tmp));
33330 tmp = fieldFromInstruction(insn, 25, 1);
33331 MI.addOperand(MCOperand::createImm(tmp));
33332 tmp = fieldFromInstruction(insn, 15, 1);
33333 MI.addOperand(MCOperand::createImm(tmp));
33334 tmp = fieldFromInstruction(insn, 16, 1);
33335 MI.addOperand(MCOperand::createImm(tmp));
33336 tmp = fieldFromInstruction(insn, 17, 1);
33337 MI.addOperand(MCOperand::createImm(tmp));
33338 tmp = fieldFromInstruction(insn, 14, 1);
33339 MI.addOperand(MCOperand::createImm(tmp));
33340 tmp = fieldFromInstruction(insn, 63, 1);
33341 MI.addOperand(MCOperand::createImm(tmp));
33344 tmp = fieldFromInstruction(insn, 40, 8);
33345 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33346 tmp = fieldFromInstruction(insn, 32, 8);
33347 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33348 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33349 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33350 tmp = fieldFromInstruction(insn, 53, 5) << 2;
33351 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33352 tmp = fieldFromInstruction(insn, 8, 4);
33353 MI.addOperand(MCOperand::createImm(tmp));
33354 tmp = fieldFromInstruction(insn, 3, 3);
33355 MI.addOperand(MCOperand::createImm(tmp));
33356 tmp = fieldFromInstruction(insn, 12, 1);
33357 MI.addOperand(MCOperand::createImm(tmp));
33358 tmp = fieldFromInstruction(insn, 7, 1);
33359 MI.addOperand(MCOperand::createImm(tmp));
33360 tmp = fieldFromInstruction(insn, 13, 1);
33361 MI.addOperand(MCOperand::createImm(tmp));
33362 tmp = fieldFromInstruction(insn, 25, 1);
33363 MI.addOperand(MCOperand::createImm(tmp));
33364 tmp = fieldFromInstruction(insn, 15, 1);
33365 MI.addOperand(MCOperand::createImm(tmp));
33366 tmp = fieldFromInstruction(insn, 16, 1);
33367 MI.addOperand(MCOperand::createImm(tmp));
33368 tmp = fieldFromInstruction(insn, 17, 1);
33369 MI.addOperand(MCOperand::createImm(tmp));
33370 tmp = fieldFromInstruction(insn, 63, 1);
33371 MI.addOperand(MCOperand::createImm(tmp));
33374 tmp = fieldFromInstruction(insn, 40, 8);
33375 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33376 tmp = fieldFromInstruction(insn, 32, 8);
33377 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33378 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33379 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33380 tmp = fieldFromInstruction(insn, 53, 5) << 2;
33381 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33382 tmp = fieldFromInstruction(insn, 8, 4);
33383 MI.addOperand(MCOperand::createImm(tmp));
33384 tmp = fieldFromInstruction(insn, 12, 1);
33385 MI.addOperand(MCOperand::createImm(tmp));
33386 tmp = fieldFromInstruction(insn, 13, 1);
33387 MI.addOperand(MCOperand::createImm(tmp));
33388 tmp = fieldFromInstruction(insn, 25, 1);
33389 MI.addOperand(MCOperand::createImm(tmp));
33390 tmp = fieldFromInstruction(insn, 15, 1);
33391 MI.addOperand(MCOperand::createImm(tmp));
33392 tmp = fieldFromInstruction(insn, 16, 1);
33393 MI.addOperand(MCOperand::createImm(tmp));
33394 tmp = fieldFromInstruction(insn, 17, 1);
33395 MI.addOperand(MCOperand::createImm(tmp));
33396 tmp = fieldFromInstruction(insn, 14, 1);
33397 MI.addOperand(MCOperand::createImm(tmp));
33398 tmp = fieldFromInstruction(insn, 63, 1);
33399 MI.addOperand(MCOperand::createImm(tmp));
33402 tmp = fieldFromInstruction(insn, 40, 8);
33403 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33404 tmp = fieldFromInstruction(insn, 32, 8);
33405 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33406 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33407 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33408 tmp = fieldFromInstruction(insn, 53, 5) << 2;
33409 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33410 tmp = fieldFromInstruction(insn, 8, 4);
33411 MI.addOperand(MCOperand::createImm(tmp));
33412 tmp = fieldFromInstruction(insn, 3, 3);
33413 MI.addOperand(MCOperand::createImm(tmp));
33414 tmp = fieldFromInstruction(insn, 12, 1);
33415 MI.addOperand(MCOperand::createImm(tmp));
33416 tmp = fieldFromInstruction(insn, 7, 1);
33417 MI.addOperand(MCOperand::createImm(tmp));
33418 tmp = fieldFromInstruction(insn, 13, 1);
33419 MI.addOperand(MCOperand::createImm(tmp));
33420 tmp = fieldFromInstruction(insn, 25, 1);
33421 MI.addOperand(MCOperand::createImm(tmp));
33422 tmp = fieldFromInstruction(insn, 15, 1);
33423 MI.addOperand(MCOperand::createImm(tmp));
33424 tmp = fieldFromInstruction(insn, 16, 1);
33425 MI.addOperand(MCOperand::createImm(tmp));
33426 tmp = fieldFromInstruction(insn, 17, 1);
33427 MI.addOperand(MCOperand::createImm(tmp));
33428 tmp = fieldFromInstruction(insn, 63, 1);
33429 MI.addOperand(MCOperand::createImm(tmp));
33432 tmp = fieldFromInstruction(insn, 40, 8);
33433 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33434 tmp = fieldFromInstruction(insn, 32, 8);
33435 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33436 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33437 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33438 tmp = fieldFromInstruction(insn, 53, 5) << 2;
33439 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33440 tmp = fieldFromInstruction(insn, 8, 4);
33441 MI.addOperand(MCOperand::createImm(tmp));
33442 tmp = fieldFromInstruction(insn, 12, 1);
33443 MI.addOperand(MCOperand::createImm(tmp));
33444 tmp = fieldFromInstruction(insn, 13, 1);
33445 MI.addOperand(MCOperand::createImm(tmp));
33446 tmp = fieldFromInstruction(insn, 25, 1);
33447 MI.addOperand(MCOperand::createImm(tmp));
33448 tmp = fieldFromInstruction(insn, 15, 1);
33449 MI.addOperand(MCOperand::createImm(tmp));
33450 tmp = fieldFromInstruction(insn, 16, 1);
33451 MI.addOperand(MCOperand::createImm(tmp));
33452 tmp = fieldFromInstruction(insn, 17, 1);
33453 MI.addOperand(MCOperand::createImm(tmp));
33454 tmp = fieldFromInstruction(insn, 14, 1);
33455 MI.addOperand(MCOperand::createImm(tmp));
33456 tmp = fieldFromInstruction(insn, 63, 1);
33457 MI.addOperand(MCOperand::createImm(tmp));
33460 tmp = fieldFromInstruction(insn, 40, 8);
33461 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33462 tmp = fieldFromInstruction(insn, 32, 8);
33463 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33464 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33465 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33466 tmp = fieldFromInstruction(insn, 53, 5) << 2;
33467 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33468 tmp = fieldFromInstruction(insn, 8, 4);
33469 MI.addOperand(MCOperand::createImm(tmp));
33470 tmp = fieldFromInstruction(insn, 3, 3);
33471 MI.addOperand(MCOperand::createImm(tmp));
33472 tmp = fieldFromInstruction(insn, 12, 1);
33473 MI.addOperand(MCOperand::createImm(tmp));
33474 tmp = fieldFromInstruction(insn, 7, 1);
33475 MI.addOperand(MCOperand::createImm(tmp));
33476 tmp = fieldFromInstruction(insn, 13, 1);
33477 MI.addOperand(MCOperand::createImm(tmp));
33478 tmp = fieldFromInstruction(insn, 25, 1);
33479 MI.addOperand(MCOperand::createImm(tmp));
33480 tmp = fieldFromInstruction(insn, 15, 1);
33481 MI.addOperand(MCOperand::createImm(tmp));
33482 tmp = fieldFromInstruction(insn, 16, 1);
33483 MI.addOperand(MCOperand::createImm(tmp));
33484 tmp = fieldFromInstruction(insn, 17, 1);
33485 MI.addOperand(MCOperand::createImm(tmp));
33486 tmp = fieldFromInstruction(insn, 63, 1);
33487 MI.addOperand(MCOperand::createImm(tmp));
33490 tmp = fieldFromInstruction(insn, 40, 8);
33491 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33492 tmp = fieldFromInstruction(insn, 32, 8);
33493 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33494 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33495 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33496 tmp = fieldFromInstruction(insn, 53, 5) << 2;
33497 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33498 tmp = fieldFromInstruction(insn, 8, 4);
33499 MI.addOperand(MCOperand::createImm(tmp));
33500 tmp = fieldFromInstruction(insn, 12, 1);
33501 MI.addOperand(MCOperand::createImm(tmp));
33502 tmp = fieldFromInstruction(insn, 13, 1);
33503 MI.addOperand(MCOperand::createImm(tmp));
33504 tmp = fieldFromInstruction(insn, 25, 1);
33505 MI.addOperand(MCOperand::createImm(tmp));
33506 tmp = fieldFromInstruction(insn, 15, 1);
33507 MI.addOperand(MCOperand::createImm(tmp));
33508 tmp = fieldFromInstruction(insn, 16, 1);
33509 MI.addOperand(MCOperand::createImm(tmp));
33510 tmp = fieldFromInstruction(insn, 17, 1);
33511 MI.addOperand(MCOperand::createImm(tmp));
33512 tmp = fieldFromInstruction(insn, 14, 1);
33513 MI.addOperand(MCOperand::createImm(tmp));
33514 tmp = fieldFromInstruction(insn, 63, 1);
33515 MI.addOperand(MCOperand::createImm(tmp));
33518 tmp = fieldFromInstruction(insn, 40, 8);
33519 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33520 tmp = fieldFromInstruction(insn, 32, 8);
33521 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33522 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33523 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33524 tmp = fieldFromInstruction(insn, 53, 5) << 2;
33525 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33526 tmp = fieldFromInstruction(insn, 8, 4);
33527 MI.addOperand(MCOperand::createImm(tmp));
33528 tmp = fieldFromInstruction(insn, 3, 3);
33529 MI.addOperand(MCOperand::createImm(tmp));
33530 tmp = fieldFromInstruction(insn, 12, 1);
33531 MI.addOperand(MCOperand::createImm(tmp));
33532 tmp = fieldFromInstruction(insn, 7, 1);
33533 MI.addOperand(MCOperand::createImm(tmp));
33534 tmp = fieldFromInstruction(insn, 13, 1);
33535 MI.addOperand(MCOperand::createImm(tmp));
33536 tmp = fieldFromInstruction(insn, 25, 1);
33537 MI.addOperand(MCOperand::createImm(tmp));
33538 tmp = fieldFromInstruction(insn, 15, 1);
33539 MI.addOperand(MCOperand::createImm(tmp));
33540 tmp = fieldFromInstruction(insn, 16, 1);
33541 MI.addOperand(MCOperand::createImm(tmp));
33542 tmp = fieldFromInstruction(insn, 17, 1);
33543 MI.addOperand(MCOperand::createImm(tmp));
33544 tmp = fieldFromInstruction(insn, 63, 1);
33545 MI.addOperand(MCOperand::createImm(tmp));
33548 tmp = fieldFromInstruction(insn, 40, 8);
33549 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33550 tmp = fieldFromInstruction(insn, 32, 8);
33551 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33552 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33553 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33554 tmp = fieldFromInstruction(insn, 53, 5) << 2;
33555 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33556 tmp = fieldFromInstruction(insn, 8, 4);
33557 MI.addOperand(MCOperand::createImm(tmp));
33558 tmp = fieldFromInstruction(insn, 12, 1);
33559 MI.addOperand(MCOperand::createImm(tmp));
33560 tmp = fieldFromInstruction(insn, 13, 1);
33561 MI.addOperand(MCOperand::createImm(tmp));
33562 tmp = fieldFromInstruction(insn, 25, 1);
33563 MI.addOperand(MCOperand::createImm(tmp));
33564 tmp = fieldFromInstruction(insn, 15, 1);
33565 MI.addOperand(MCOperand::createImm(tmp));
33566 tmp = fieldFromInstruction(insn, 16, 1);
33567 MI.addOperand(MCOperand::createImm(tmp));
33568 tmp = fieldFromInstruction(insn, 17, 1);
33569 MI.addOperand(MCOperand::createImm(tmp));
33570 tmp = fieldFromInstruction(insn, 14, 1);
33571 MI.addOperand(MCOperand::createImm(tmp));
33572 tmp = fieldFromInstruction(insn, 63, 1);
33573 MI.addOperand(MCOperand::createImm(tmp));
33576 tmp = fieldFromInstruction(insn, 40, 8);
33577 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33578 tmp = fieldFromInstruction(insn, 32, 8);
33579 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33580 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33581 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33582 tmp = fieldFromInstruction(insn, 53, 5) << 2;
33583 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33584 tmp = fieldFromInstruction(insn, 8, 4);
33585 MI.addOperand(MCOperand::createImm(tmp));
33586 tmp = fieldFromInstruction(insn, 3, 3);
33587 MI.addOperand(MCOperand::createImm(tmp));
33588 tmp = fieldFromInstruction(insn, 12, 1);
33589 MI.addOperand(MCOperand::createImm(tmp));
33590 tmp = fieldFromInstruction(insn, 7, 1);
33591 MI.addOperand(MCOperand::createImm(tmp));
33592 tmp = fieldFromInstruction(insn, 13, 1);
33593 MI.addOperand(MCOperand::createImm(tmp));
33594 tmp = fieldFromInstruction(insn, 25, 1);
33595 MI.addOperand(MCOperand::createImm(tmp));
33596 tmp = fieldFromInstruction(insn, 15, 1);
33597 MI.addOperand(MCOperand::createImm(tmp));
33598 tmp = fieldFromInstruction(insn, 16, 1);
33599 MI.addOperand(MCOperand::createImm(tmp));
33600 tmp = fieldFromInstruction(insn, 17, 1);
33601 MI.addOperand(MCOperand::createImm(tmp));
33604 tmp = fieldFromInstruction(insn, 40, 8);
33605 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33606 tmp = fieldFromInstruction(insn, 32, 8);
33607 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33608 tmp = fieldFromInstruction(insn, 48, 5) << 2;
33609 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33610 tmp = fieldFromInstruction(insn, 53, 5) << 2;
33611 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33612 tmp = fieldFromInstruction(insn, 8, 4);
33613 MI.addOperand(MCOperand::createImm(tmp));
33614 tmp = fieldFromInstruction(insn, 12, 1);
33615 MI.addOperand(MCOperand::createImm(tmp));
33616 tmp = fieldFromInstruction(insn, 13, 1);
33617 MI.addOperand(MCOperand::createImm(tmp));
33618 tmp = fieldFromInstruction(insn, 25, 1);
33619 MI.addOperand(MCOperand::createImm(tmp));
33620 tmp = fieldFromInstruction(insn, 15, 1);
33621 MI.addOperand(MCOperand::createImm(tmp));
33622 tmp = fieldFromInstruction(insn, 16, 1);
33623 MI.addOperand(MCOperand::createImm(tmp));
33624 tmp = fieldFromInstruction(insn, 17, 1);
33625 MI.addOperand(MCOperand::createImm(tmp));
33626 tmp = fieldFromInstruction(insn, 14, 1);
33627 MI.addOperand(MCOperand::createImm(tmp));
33630 tmp = fieldFromInstruction(insn, 17, 8);
33631 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33632 tmp = fieldFromInstruction(insn, 17, 8);
33633 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33634 tmp = fieldFromInstruction(insn, 52, 2);
33635 MI.addOperand(MCOperand::createImm(tmp));
33636 tmp = fieldFromInstruction(insn, 32, 8);
33637 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33638 tmp = fieldFromInstruction(insn, 54, 2);
33639 MI.addOperand(MCOperand::createImm(tmp));
33640 tmp = fieldFromInstruction(insn, 9, 8);
33641 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33642 tmp = fieldFromInstruction(insn, 40, 9);
33643 MI.addOperand(MCOperand::createImm(tmp));
33644 tmp = fieldFromInstruction(insn, 60, 4);
33645 MI.addOperand(MCOperand::createImm(tmp));
33646 tmp = fieldFromInstruction(insn, 56, 4);
33647 MI.addOperand(MCOperand::createImm(tmp));
33648 tmp = fieldFromInstruction(insn, 51, 1);
33649 MI.addOperand(MCOperand::createImm(tmp));
33652 tmp = fieldFromInstruction(insn, 17, 8);
33653 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33654 tmp = fieldFromInstruction(insn, 17, 8);
33655 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33656 tmp = fieldFromInstruction(insn, 32, 8);
33657 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33658 tmp = fieldFromInstruction(insn, 9, 8);
33659 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33660 tmp = fieldFromInstruction(insn, 40, 9);
33661 MI.addOperand(MCOperand::createImm(tmp));
33662 tmp = fieldFromInstruction(insn, 60, 4);
33663 MI.addOperand(MCOperand::createImm(tmp));
33664 tmp = fieldFromInstruction(insn, 56, 4);
33665 MI.addOperand(MCOperand::createImm(tmp));
33666 tmp = fieldFromInstruction(insn, 51, 1);
33667 MI.addOperand(MCOperand::createImm(tmp));
33670 tmp = fieldFromInstruction(insn, 17, 8);
33671 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33672 tmp = fieldFromInstruction(insn, 52, 2);
33673 MI.addOperand(MCOperand::createImm(tmp));
33674 tmp = fieldFromInstruction(insn, 32, 8);
33675 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33676 tmp = fieldFromInstruction(insn, 54, 2);
33677 MI.addOperand(MCOperand::createImm(tmp));
33678 tmp = fieldFromInstruction(insn, 9, 8);
33679 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33680 tmp = fieldFromInstruction(insn, 17, 8);
33681 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33682 tmp = fieldFromInstruction(insn, 40, 9);
33683 MI.addOperand(MCOperand::createImm(tmp));
33684 tmp = fieldFromInstruction(insn, 60, 4);
33685 MI.addOperand(MCOperand::createImm(tmp));
33686 tmp = fieldFromInstruction(insn, 56, 4);
33687 MI.addOperand(MCOperand::createImm(tmp));
33688 tmp = fieldFromInstruction(insn, 51, 1);
33689 MI.addOperand(MCOperand::createImm(tmp));
33692 tmp = fieldFromInstruction(insn, 17, 8);
33693 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33694 tmp = fieldFromInstruction(insn, 17, 8);
33695 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33696 tmp = fieldFromInstruction(insn, 32, 8);
33697 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33698 tmp = fieldFromInstruction(insn, 40, 9);
33699 MI.addOperand(MCOperand::createImm(tmp));
33700 tmp = fieldFromInstruction(insn, 60, 4);
33701 MI.addOperand(MCOperand::createImm(tmp));
33702 tmp = fieldFromInstruction(insn, 56, 4);
33703 MI.addOperand(MCOperand::createImm(tmp));
33704 tmp = fieldFromInstruction(insn, 51, 1);
33705 MI.addOperand(MCOperand::createImm(tmp));
33708 tmp = fieldFromInstruction(insn, 17, 8);
33709 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33710 tmp = fieldFromInstruction(insn, 17, 8);
33711 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33712 tmp = fieldFromInstruction(insn, 52, 2);
33713 MI.addOperand(MCOperand::createImm(tmp));
33714 tmp = fieldFromInstruction(insn, 32, 8);
33715 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33716 tmp = fieldFromInstruction(insn, 40, 9);
33717 MI.addOperand(MCOperand::createImm(tmp));
33718 tmp = fieldFromInstruction(insn, 60, 4);
33719 MI.addOperand(MCOperand::createImm(tmp));
33720 tmp = fieldFromInstruction(insn, 56, 4);
33721 MI.addOperand(MCOperand::createImm(tmp));
33722 tmp = fieldFromInstruction(insn, 51, 1);
33723 MI.addOperand(MCOperand::createImm(tmp));
33726 tmp = fieldFromInstruction(insn, 17, 8);
33727 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33728 tmp = fieldFromInstruction(insn, 17, 8);
33729 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33730 tmp = fieldFromInstruction(insn, 32, 8);
33731 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33732 tmp = fieldFromInstruction(insn, 9, 8);
33733 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33734 tmp = fieldFromInstruction(insn, 40, 24);
33735 MI.addOperand(MCOperand::createImm(tmp));
33736 tmp = fieldFromInstruction(insn, 0, 9);
33737 MI.addOperand(MCOperand::createImm(tmp));
33740 tmp = fieldFromInstruction(insn, 17, 8);
33741 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33742 tmp = fieldFromInstruction(insn, 32, 8);
33743 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33744 tmp = fieldFromInstruction(insn, 9, 8);
33745 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33746 tmp = fieldFromInstruction(insn, 17, 8);
33747 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33748 tmp = fieldFromInstruction(insn, 40, 24);
33749 MI.addOperand(MCOperand::createImm(tmp));
33750 tmp = fieldFromInstruction(insn, 0, 9);
33751 MI.addOperand(MCOperand::createImm(tmp));
33754 tmp = fieldFromInstruction(insn, 17, 8);
33755 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33756 tmp = fieldFromInstruction(insn, 17, 8);
33757 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33758 tmp = fieldFromInstruction(insn, 32, 8);
33759 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33760 tmp = fieldFromInstruction(insn, 40, 24);
33761 MI.addOperand(MCOperand::createImm(tmp));
33762 tmp = fieldFromInstruction(insn, 0, 9);
33763 MI.addOperand(MCOperand::createImm(tmp));
33766 tmp = fieldFromInstruction(insn, 17, 8);
33767 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33768 tmp = fieldFromInstruction(insn, 0, 9);
33769 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33770 tmp = fieldFromInstruction(insn, 9, 8);
33771 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33774 tmp = fieldFromInstruction(insn, 17, 8);
33775 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33776 tmp = fieldFromInstruction(insn, 0, 9);
33777 if (decodeOperand_VSrcV216(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33778 tmp = fieldFromInstruction(insn, 9, 8);
33779 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33780 tmp = fieldFromInstruction(insn, 17, 8);
33781 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33784 tmp = fieldFromInstruction(insn, 17, 8);
33785 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33786 tmp = fieldFromInstruction(insn, 0, 9);
33787 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33788 tmp = fieldFromInstruction(insn, 9, 8);
33789 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33790 tmp = fieldFromInstruction(insn, 17, 8);
33791 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33794 tmp = fieldFromInstruction(insn, 17, 8);
33795 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33796 tmp = fieldFromInstruction(insn, 0, 9);
33797 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33798 tmp = fieldFromInstruction(insn, 9, 8);
33799 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33802 tmp = fieldFromInstruction(insn, 17, 8);
33803 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33804 tmp = fieldFromInstruction(insn, 0, 9);
33805 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33806 tmp = fieldFromInstruction(insn, 9, 8);
33807 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33808 tmp = fieldFromInstruction(insn, 17, 8);
33809 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33812 tmp = fieldFromInstruction(insn, 17, 8);
33813 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33814 tmp = fieldFromInstruction(insn, 0, 9);
33815 if (decodeOperand_VSrcV216(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33816 tmp = fieldFromInstruction(insn, 9, 8);
33817 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33820 tmp = fieldFromInstruction(insn, 0, 9);
33821 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33822 tmp = fieldFromInstruction(insn, 9, 8);
33823 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33826 tmp = fieldFromInstruction(insn, 0, 9);
33827 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33828 tmp = fieldFromInstruction(insn, 9, 8);
33829 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33832 tmp = fieldFromInstruction(insn, 0, 9);
33833 if (decodeOperand_VSrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33834 tmp = fieldFromInstruction(insn, 9, 8);
33835 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33838 tmp = fieldFromInstruction(insn, 0, 9);
33839 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33840 tmp = fieldFromInstruction(insn, 9, 8);
33841 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33844 tmp = fieldFromInstruction(insn, 0, 9);
33845 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33846 tmp = fieldFromInstruction(insn, 9, 8);
33847 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33850 tmp = fieldFromInstruction(insn, 17, 8);
33851 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33852 tmp = fieldFromInstruction(insn, 0, 9);
33853 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33856 tmp = fieldFromInstruction(insn, 17, 8);
33857 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33858 tmp = fieldFromInstruction(insn, 0, 9);
33859 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33862 tmp = fieldFromInstruction(insn, 17, 8);
33863 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33864 tmp = fieldFromInstruction(insn, 0, 9);
33865 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33868 tmp = fieldFromInstruction(insn, 17, 8);
33869 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33870 tmp = fieldFromInstruction(insn, 0, 9);
33871 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33874 tmp = fieldFromInstruction(insn, 17, 8);
33875 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33876 tmp = fieldFromInstruction(insn, 0, 9);
33877 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33880 tmp = fieldFromInstruction(insn, 17, 8);
33881 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33882 tmp = fieldFromInstruction(insn, 0, 9);
33883 if (DecodeVS_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33886 tmp = fieldFromInstruction(insn, 17, 8);
33887 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33888 tmp = fieldFromInstruction(insn, 0, 9);
33889 if (decodeOperand_VSrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33892 tmp = fieldFromInstruction(insn, 17, 8);
33893 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33894 tmp = fieldFromInstruction(insn, 0, 9);
33895 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33896 tmp = fieldFromInstruction(insn, 0, 9);
33897 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33898 tmp = fieldFromInstruction(insn, 17, 8);
33899 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33902 tmp = fieldFromInstruction(insn, 16, 7);
33903 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33904 tmp = fieldFromInstruction(insn, 0, 8);
33905 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33906 tmp = fieldFromInstruction(insn, 8, 8);
33907 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33910 tmp = fieldFromInstruction(insn, 16, 7);
33911 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33912 tmp = fieldFromInstruction(insn, 0, 8);
33913 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33914 tmp = fieldFromInstruction(insn, 8, 8);
33915 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33918 tmp = fieldFromInstruction(insn, 16, 7);
33919 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33920 tmp = fieldFromInstruction(insn, 0, 8);
33921 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33922 tmp = fieldFromInstruction(insn, 8, 8);
33923 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33926 tmp = fieldFromInstruction(insn, 16, 7);
33927 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33928 tmp = fieldFromInstruction(insn, 0, 8);
33929 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33930 tmp = fieldFromInstruction(insn, 8, 8);
33931 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33934 tmp = fieldFromInstruction(insn, 16, 7);
33935 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33936 tmp = fieldFromInstruction(insn, 0, 16);
33937 MI.addOperand(MCOperand::createImm(tmp));
33940 tmp = fieldFromInstruction(insn, 16, 7);
33941 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33942 tmp = fieldFromInstruction(insn, 16, 7);
33943 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33944 tmp = fieldFromInstruction(insn, 0, 16);
33945 MI.addOperand(MCOperand::createImm(tmp));
33948 tmp = fieldFromInstruction(insn, 16, 7);
33949 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33950 tmp = fieldFromInstruction(insn, 0, 16);
33951 if (decodeSoppBrTarget(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33954 tmp = fieldFromInstruction(insn, 0, 16);
33955 if (decodeSoppBrTarget(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33956 tmp = fieldFromInstruction(insn, 16, 7);
33957 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33960 tmp = fieldFromInstruction(insn, 16, 7);
33961 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33962 tmp = fieldFromInstruction(insn, 0, 8);
33963 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33966 tmp = fieldFromInstruction(insn, 16, 7);
33967 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33968 tmp = fieldFromInstruction(insn, 0, 8);
33969 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33972 tmp = fieldFromInstruction(insn, 16, 7);
33973 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33974 tmp = fieldFromInstruction(insn, 0, 8);
33975 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33978 tmp = fieldFromInstruction(insn, 16, 7);
33979 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33980 tmp = fieldFromInstruction(insn, 0, 8);
33981 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33984 tmp = fieldFromInstruction(insn, 16, 7);
33985 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33988 tmp = fieldFromInstruction(insn, 0, 8);
33989 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33992 tmp = fieldFromInstruction(insn, 18, 8);
33993 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33994 tmp = fieldFromInstruction(insn, 0, 8);
33995 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
33996 tmp = fieldFromInstruction(insn, 10, 6);
33997 MI.addOperand(MCOperand::createImm(tmp));
33998 tmp = fieldFromInstruction(insn, 8, 2);
33999 MI.addOperand(MCOperand::createImm(tmp));
34002 tmp = fieldFromInstruction(insn, 18, 8);
34003 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34004 tmp = fieldFromInstruction(insn, 18, 8);
34005 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34006 tmp = fieldFromInstruction(insn, 0, 8);
34007 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34008 tmp = fieldFromInstruction(insn, 10, 6);
34009 MI.addOperand(MCOperand::createImm(tmp));
34010 tmp = fieldFromInstruction(insn, 8, 2);
34011 MI.addOperand(MCOperand::createImm(tmp));
34014 tmp = fieldFromInstruction(insn, 18, 8);
34015 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34016 tmp = fieldFromInstruction(insn, 0, 8);
34017 MI.addOperand(MCOperand::createImm(tmp));
34018 tmp = fieldFromInstruction(insn, 10, 6);
34019 MI.addOperand(MCOperand::createImm(tmp));
34020 tmp = fieldFromInstruction(insn, 8, 2);
34021 MI.addOperand(MCOperand::createImm(tmp));
34024 tmp = fieldFromInstruction(insn, 17, 8);
34025 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34026 tmp = fieldFromInstruction(insn, 0, 9);
34027 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34028 tmp = fieldFromInstruction(insn, 32, 32);
34029 MI.addOperand(MCOperand::createImm(tmp));
34030 tmp = fieldFromInstruction(insn, 9, 8);
34031 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34034 tmp = fieldFromInstruction(insn, 17, 8);
34035 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34036 tmp = fieldFromInstruction(insn, 0, 9);
34037 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34038 tmp = fieldFromInstruction(insn, 9, 8);
34039 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34040 tmp = fieldFromInstruction(insn, 32, 32);
34041 MI.addOperand(MCOperand::createImm(tmp));
34044 tmp = fieldFromInstruction(insn, 17, 8);
34045 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34046 tmp = fieldFromInstruction(insn, 0, 9);
34047 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34048 tmp = fieldFromInstruction(insn, 9, 8);
34049 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34050 tmp = fieldFromInstruction(insn, 32, 32);
34051 MI.addOperand(MCOperand::createImm(tmp));
34054 tmp = fieldFromInstruction(insn, 32, 32);
34055 MI.addOperand(MCOperand::createImm(tmp));
34056 tmp = fieldFromInstruction(insn, 0, 16);
34057 MI.addOperand(MCOperand::createImm(tmp));
34060 tmp = fieldFromInstruction(insn, 0, 8);
34061 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34062 tmp = 0x0;
34063 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34064 tmp |= fieldFromInstruction(insn, 11, 1) << 2;
34065 tmp |= fieldFromInstruction(insn, 59, 1) << 3;
34066 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34067 MI.addOperand(MCOperand::createImm(tmp));
34068 tmp = fieldFromInstruction(insn, 32, 9);
34069 if (decodeOperand_VSrcV216(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34070 tmp = 0x0;
34071 tmp |= fieldFromInstruction(insn, 12, 1) << 2;
34072 tmp |= fieldFromInstruction(insn, 60, 1) << 3;
34073 MI.addOperand(MCOperand::createImm(tmp));
34074 tmp = fieldFromInstruction(insn, 41, 9);
34075 if (decodeOperand_VSrcV216(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34076 tmp = fieldFromInstruction(insn, 13, 2) << 2;
34077 MI.addOperand(MCOperand::createImm(tmp));
34078 tmp = fieldFromInstruction(insn, 50, 9);
34079 if (decodeOperand_VSrcV216(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34080 tmp = fieldFromInstruction(insn, 15, 1);
34081 MI.addOperand(MCOperand::createImm(tmp));
34084 tmp = fieldFromInstruction(insn, 0, 8);
34085 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34086 tmp = 0x0;
34087 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34088 tmp |= fieldFromInstruction(insn, 11, 1) << 2;
34089 tmp |= fieldFromInstruction(insn, 59, 1) << 3;
34090 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34091 MI.addOperand(MCOperand::createImm(tmp));
34092 tmp = fieldFromInstruction(insn, 32, 9);
34093 if (decodeOperand_VSrcV216(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34094 tmp = 0x0;
34095 tmp |= fieldFromInstruction(insn, 12, 1) << 2;
34096 tmp |= fieldFromInstruction(insn, 60, 1) << 3;
34097 MI.addOperand(MCOperand::createImm(tmp));
34098 tmp = fieldFromInstruction(insn, 41, 9);
34099 if (decodeOperand_VSrcV216(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34100 tmp = fieldFromInstruction(insn, 15, 1);
34101 MI.addOperand(MCOperand::createImm(tmp));
34104 tmp = fieldFromInstruction(insn, 0, 8);
34105 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34106 tmp = 0x0;
34107 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34108 tmp |= fieldFromInstruction(insn, 11, 1) << 2;
34109 tmp |= fieldFromInstruction(insn, 59, 1) << 3;
34110 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34111 MI.addOperand(MCOperand::createImm(tmp));
34112 tmp = fieldFromInstruction(insn, 32, 9);
34113 if (decodeOperand_VSrcV216(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34114 tmp = 0x0;
34115 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34116 tmp |= fieldFromInstruction(insn, 12, 1) << 2;
34117 tmp |= fieldFromInstruction(insn, 60, 1) << 3;
34118 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34119 MI.addOperand(MCOperand::createImm(tmp));
34120 tmp = fieldFromInstruction(insn, 41, 9);
34121 if (decodeOperand_VSrcV216(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34122 tmp = 0x0;
34123 tmp |= fieldFromInstruction(insn, 10, 1) << 1;
34124 tmp |= fieldFromInstruction(insn, 13, 2) << 2;
34125 tmp |= fieldFromInstruction(insn, 63, 1) << 0;
34126 MI.addOperand(MCOperand::createImm(tmp));
34127 tmp = fieldFromInstruction(insn, 50, 9);
34128 if (decodeOperand_VSrcV216(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34129 tmp = fieldFromInstruction(insn, 15, 1);
34130 MI.addOperand(MCOperand::createImm(tmp));
34133 tmp = fieldFromInstruction(insn, 0, 8);
34134 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34135 tmp = 0x0;
34136 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34137 tmp |= fieldFromInstruction(insn, 11, 1) << 2;
34138 tmp |= fieldFromInstruction(insn, 59, 1) << 3;
34139 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34140 MI.addOperand(MCOperand::createImm(tmp));
34141 tmp = fieldFromInstruction(insn, 32, 9);
34142 if (decodeOperand_VSrcV216(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34143 tmp = 0x0;
34144 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34145 tmp |= fieldFromInstruction(insn, 12, 1) << 2;
34146 tmp |= fieldFromInstruction(insn, 60, 1) << 3;
34147 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34148 MI.addOperand(MCOperand::createImm(tmp));
34149 tmp = fieldFromInstruction(insn, 41, 9);
34150 if (decodeOperand_VSrcV216(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34151 tmp = fieldFromInstruction(insn, 15, 1);
34152 MI.addOperand(MCOperand::createImm(tmp));
34155 tmp = fieldFromInstruction(insn, 0, 8);
34156 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34157 tmp = 0x0;
34158 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34159 tmp |= fieldFromInstruction(insn, 11, 1) << 2;
34160 tmp |= fieldFromInstruction(insn, 59, 1) << 3;
34161 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34162 MI.addOperand(MCOperand::createImm(tmp));
34163 tmp = fieldFromInstruction(insn, 32, 9);
34164 if (decodeOperand_VSrcV216(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34165 tmp = 0x0;
34166 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34167 tmp |= fieldFromInstruction(insn, 12, 1) << 2;
34168 tmp |= fieldFromInstruction(insn, 60, 1) << 3;
34169 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34170 MI.addOperand(MCOperand::createImm(tmp));
34171 tmp = fieldFromInstruction(insn, 41, 9);
34172 if (decodeOperand_VSrcV216(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34173 tmp = 0x0;
34174 tmp |= fieldFromInstruction(insn, 10, 1) << 1;
34175 tmp |= fieldFromInstruction(insn, 13, 2) << 2;
34176 tmp |= fieldFromInstruction(insn, 63, 1) << 0;
34177 MI.addOperand(MCOperand::createImm(tmp));
34178 tmp = fieldFromInstruction(insn, 50, 9);
34179 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34180 tmp = fieldFromInstruction(insn, 15, 1);
34181 MI.addOperand(MCOperand::createImm(tmp));
34184 tmp = fieldFromInstruction(insn, 0, 8);
34185 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34186 tmp = 0x0;
34187 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34188 tmp |= fieldFromInstruction(insn, 11, 1) << 2;
34189 tmp |= fieldFromInstruction(insn, 59, 1) << 3;
34190 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34191 MI.addOperand(MCOperand::createImm(tmp));
34192 tmp = fieldFromInstruction(insn, 32, 9);
34193 if (decodeOperand_VSrcV216(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34194 tmp = 0x0;
34195 tmp |= fieldFromInstruction(insn, 12, 1) << 2;
34196 tmp |= fieldFromInstruction(insn, 60, 1) << 3;
34197 MI.addOperand(MCOperand::createImm(tmp));
34198 tmp = fieldFromInstruction(insn, 41, 9);
34199 if (decodeOperand_VSrcV216(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34200 tmp = 0x0;
34201 tmp |= fieldFromInstruction(insn, 10, 1) << 1;
34202 tmp |= fieldFromInstruction(insn, 13, 2) << 2;
34203 tmp |= fieldFromInstruction(insn, 63, 1) << 0;
34204 MI.addOperand(MCOperand::createImm(tmp));
34205 tmp = fieldFromInstruction(insn, 50, 9);
34206 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34207 tmp = fieldFromInstruction(insn, 15, 1);
34208 MI.addOperand(MCOperand::createImm(tmp));
34211 tmp = fieldFromInstruction(insn, 0, 8);
34212 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34213 tmp = 0x0;
34214 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34215 tmp |= fieldFromInstruction(insn, 11, 1) << 2;
34216 tmp |= fieldFromInstruction(insn, 59, 1) << 3;
34217 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34218 MI.addOperand(MCOperand::createImm(tmp));
34219 tmp = fieldFromInstruction(insn, 32, 9);
34220 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34221 tmp = 0x0;
34222 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34223 tmp |= fieldFromInstruction(insn, 12, 1) << 2;
34224 tmp |= fieldFromInstruction(insn, 60, 1) << 3;
34225 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34226 MI.addOperand(MCOperand::createImm(tmp));
34227 tmp = fieldFromInstruction(insn, 41, 9);
34228 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34229 tmp = 0x0;
34230 tmp |= fieldFromInstruction(insn, 10, 1) << 1;
34231 tmp |= fieldFromInstruction(insn, 13, 2) << 2;
34232 tmp |= fieldFromInstruction(insn, 63, 1) << 0;
34233 MI.addOperand(MCOperand::createImm(tmp));
34234 tmp = fieldFromInstruction(insn, 50, 9);
34235 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34236 tmp = fieldFromInstruction(insn, 15, 1);
34237 MI.addOperand(MCOperand::createImm(tmp));
34240 tmp = fieldFromInstruction(insn, 0, 8);
34241 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34242 tmp = 0x0;
34243 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34244 tmp |= fieldFromInstruction(insn, 11, 1) << 2;
34245 tmp |= fieldFromInstruction(insn, 59, 1) << 3;
34246 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34247 MI.addOperand(MCOperand::createImm(tmp));
34248 tmp = fieldFromInstruction(insn, 32, 9);
34249 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34250 tmp = 0x0;
34251 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34252 tmp |= fieldFromInstruction(insn, 12, 1) << 2;
34253 tmp |= fieldFromInstruction(insn, 60, 1) << 3;
34254 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34255 MI.addOperand(MCOperand::createImm(tmp));
34256 tmp = fieldFromInstruction(insn, 41, 9);
34257 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34258 tmp = 0x0;
34259 tmp |= fieldFromInstruction(insn, 10, 1) << 1;
34260 tmp |= fieldFromInstruction(insn, 13, 2) << 2;
34261 tmp |= fieldFromInstruction(insn, 63, 1) << 0;
34262 MI.addOperand(MCOperand::createImm(tmp));
34263 tmp = fieldFromInstruction(insn, 50, 9);
34264 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34265 tmp = fieldFromInstruction(insn, 15, 1);
34266 MI.addOperand(MCOperand::createImm(tmp));
34269 tmp = fieldFromInstruction(insn, 0, 8);
34270 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34271 tmp = 0x0;
34272 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34273 tmp |= fieldFromInstruction(insn, 11, 1) << 2;
34274 tmp |= fieldFromInstruction(insn, 59, 1) << 3;
34275 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34276 MI.addOperand(MCOperand::createImm(tmp));
34277 tmp = fieldFromInstruction(insn, 32, 9);
34278 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34279 tmp = 0x0;
34280 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34281 tmp |= fieldFromInstruction(insn, 12, 1) << 2;
34282 tmp |= fieldFromInstruction(insn, 60, 1) << 3;
34283 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34284 MI.addOperand(MCOperand::createImm(tmp));
34285 tmp = fieldFromInstruction(insn, 41, 9);
34286 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34287 tmp = 0x0;
34288 tmp |= fieldFromInstruction(insn, 10, 1) << 1;
34289 tmp |= fieldFromInstruction(insn, 13, 2) << 2;
34290 tmp |= fieldFromInstruction(insn, 63, 1) << 0;
34291 MI.addOperand(MCOperand::createImm(tmp));
34292 tmp = fieldFromInstruction(insn, 50, 9);
34293 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34294 tmp = fieldFromInstruction(insn, 15, 1);
34295 MI.addOperand(MCOperand::createImm(tmp));
34296 tmp = fieldFromInstruction(insn, 0, 8);
34297 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34300 tmp = fieldFromInstruction(insn, 0, 8);
34301 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34302 tmp = 0x0;
34303 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34304 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34305 MI.addOperand(MCOperand::createImm(tmp));
34306 tmp = fieldFromInstruction(insn, 32, 9);
34307 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34308 tmp = 0x0;
34309 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34310 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34311 MI.addOperand(MCOperand::createImm(tmp));
34312 tmp = fieldFromInstruction(insn, 41, 9);
34313 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34314 tmp = fieldFromInstruction(insn, 15, 1);
34315 MI.addOperand(MCOperand::createImm(tmp));
34318 tmp = 0x0;
34319 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34320 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34321 MI.addOperand(MCOperand::createImm(tmp));
34322 tmp = fieldFromInstruction(insn, 32, 9);
34323 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34324 tmp = 0x0;
34325 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34326 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34327 MI.addOperand(MCOperand::createImm(tmp));
34328 tmp = fieldFromInstruction(insn, 41, 9);
34329 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34330 tmp = fieldFromInstruction(insn, 15, 1);
34331 MI.addOperand(MCOperand::createImm(tmp));
34334 tmp = fieldFromInstruction(insn, 0, 8);
34335 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34336 tmp = 0x0;
34337 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34338 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34339 MI.addOperand(MCOperand::createImm(tmp));
34340 tmp = fieldFromInstruction(insn, 32, 9);
34341 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34342 tmp = 0x0;
34343 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34344 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34345 MI.addOperand(MCOperand::createImm(tmp));
34346 tmp = fieldFromInstruction(insn, 41, 9);
34347 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34348 tmp = fieldFromInstruction(insn, 15, 1);
34349 MI.addOperand(MCOperand::createImm(tmp));
34352 tmp = 0x0;
34353 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34354 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34355 MI.addOperand(MCOperand::createImm(tmp));
34356 tmp = fieldFromInstruction(insn, 32, 9);
34357 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34358 tmp = 0x0;
34359 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34360 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34361 MI.addOperand(MCOperand::createImm(tmp));
34362 tmp = fieldFromInstruction(insn, 41, 9);
34363 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34364 tmp = fieldFromInstruction(insn, 15, 1);
34365 MI.addOperand(MCOperand::createImm(tmp));
34368 tmp = fieldFromInstruction(insn, 0, 8);
34369 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34370 tmp = fieldFromInstruction(insn, 32, 9);
34371 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34372 tmp = fieldFromInstruction(insn, 41, 9);
34373 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34376 tmp = fieldFromInstruction(insn, 0, 8);
34377 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34378 tmp = 0x0;
34379 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34380 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34381 MI.addOperand(MCOperand::createImm(tmp));
34382 tmp = fieldFromInstruction(insn, 32, 9);
34383 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34384 tmp = fieldFromInstruction(insn, 41, 9);
34385 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34388 tmp = fieldFromInstruction(insn, 0, 8);
34389 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34390 tmp = fieldFromInstruction(insn, 32, 9);
34391 if (decodeOperand_VSrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34392 tmp = fieldFromInstruction(insn, 41, 9);
34393 if (decodeOperand_VSrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34396 tmp = fieldFromInstruction(insn, 0, 8);
34397 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34398 tmp = 0x0;
34399 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34400 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34401 MI.addOperand(MCOperand::createImm(tmp));
34402 tmp = fieldFromInstruction(insn, 32, 9);
34403 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34404 tmp = fieldFromInstruction(insn, 41, 9);
34405 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34408 tmp = fieldFromInstruction(insn, 32, 9);
34409 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34410 tmp = fieldFromInstruction(insn, 41, 9);
34411 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34414 tmp = 0x0;
34415 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34416 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34417 MI.addOperand(MCOperand::createImm(tmp));
34418 tmp = fieldFromInstruction(insn, 32, 9);
34419 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34420 tmp = fieldFromInstruction(insn, 41, 9);
34421 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34424 tmp = fieldFromInstruction(insn, 32, 9);
34425 if (decodeOperand_VSrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34426 tmp = fieldFromInstruction(insn, 41, 9);
34427 if (decodeOperand_VSrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34430 tmp = 0x0;
34431 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34432 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34433 MI.addOperand(MCOperand::createImm(tmp));
34434 tmp = fieldFromInstruction(insn, 32, 9);
34435 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34436 tmp = fieldFromInstruction(insn, 41, 9);
34437 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34440 tmp = fieldFromInstruction(insn, 0, 8);
34441 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34442 tmp = fieldFromInstruction(insn, 32, 9);
34443 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34444 tmp = fieldFromInstruction(insn, 41, 9);
34445 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34448 tmp = fieldFromInstruction(insn, 0, 8);
34449 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34450 tmp = 0x0;
34451 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34452 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34453 MI.addOperand(MCOperand::createImm(tmp));
34454 tmp = fieldFromInstruction(insn, 32, 9);
34455 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34456 tmp = fieldFromInstruction(insn, 41, 9);
34457 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34460 tmp = fieldFromInstruction(insn, 32, 9);
34461 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34462 tmp = fieldFromInstruction(insn, 41, 9);
34463 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34466 tmp = 0x0;
34467 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34468 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34469 MI.addOperand(MCOperand::createImm(tmp));
34470 tmp = fieldFromInstruction(insn, 32, 9);
34471 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34472 tmp = fieldFromInstruction(insn, 41, 9);
34473 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34476 tmp = fieldFromInstruction(insn, 0, 8);
34477 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34478 tmp = 0x0;
34479 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34480 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34481 MI.addOperand(MCOperand::createImm(tmp));
34482 tmp = fieldFromInstruction(insn, 32, 9);
34483 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34484 tmp = 0x0;
34485 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34486 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34487 MI.addOperand(MCOperand::createImm(tmp));
34488 tmp = fieldFromInstruction(insn, 41, 9);
34489 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34490 tmp = fieldFromInstruction(insn, 15, 1);
34491 MI.addOperand(MCOperand::createImm(tmp));
34494 tmp = 0x0;
34495 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34496 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34497 MI.addOperand(MCOperand::createImm(tmp));
34498 tmp = fieldFromInstruction(insn, 32, 9);
34499 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34500 tmp = 0x0;
34501 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34502 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34503 MI.addOperand(MCOperand::createImm(tmp));
34504 tmp = fieldFromInstruction(insn, 41, 9);
34505 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34506 tmp = fieldFromInstruction(insn, 15, 1);
34507 MI.addOperand(MCOperand::createImm(tmp));
34510 tmp = fieldFromInstruction(insn, 0, 8);
34511 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34512 tmp = 0x0;
34513 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34514 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34515 MI.addOperand(MCOperand::createImm(tmp));
34516 tmp = fieldFromInstruction(insn, 32, 9);
34517 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34518 tmp = 0x0;
34519 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34520 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34521 MI.addOperand(MCOperand::createImm(tmp));
34522 tmp = fieldFromInstruction(insn, 41, 9);
34523 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34524 tmp = fieldFromInstruction(insn, 50, 9);
34525 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34528 tmp = fieldFromInstruction(insn, 0, 8);
34529 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34530 tmp = 0x0;
34531 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34532 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34533 MI.addOperand(MCOperand::createImm(tmp));
34534 tmp = fieldFromInstruction(insn, 32, 9);
34535 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34536 tmp = 0x0;
34537 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34538 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34539 MI.addOperand(MCOperand::createImm(tmp));
34540 tmp = fieldFromInstruction(insn, 41, 9);
34541 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34542 tmp = fieldFromInstruction(insn, 15, 1);
34543 MI.addOperand(MCOperand::createImm(tmp));
34544 tmp = fieldFromInstruction(insn, 59, 2);
34545 MI.addOperand(MCOperand::createImm(tmp));
34548 tmp = fieldFromInstruction(insn, 0, 8);
34549 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34550 tmp = fieldFromInstruction(insn, 32, 9);
34551 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34552 tmp = fieldFromInstruction(insn, 41, 9);
34553 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34556 tmp = fieldFromInstruction(insn, 0, 8);
34557 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34558 tmp = 0x0;
34559 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34560 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34561 MI.addOperand(MCOperand::createImm(tmp));
34562 tmp = fieldFromInstruction(insn, 32, 9);
34563 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34564 tmp = 0x0;
34565 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34566 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34567 MI.addOperand(MCOperand::createImm(tmp));
34568 tmp = fieldFromInstruction(insn, 41, 9);
34569 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34570 tmp = fieldFromInstruction(insn, 0, 8);
34571 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34572 tmp = fieldFromInstruction(insn, 15, 1);
34573 MI.addOperand(MCOperand::createImm(tmp));
34574 tmp = fieldFromInstruction(insn, 59, 2);
34575 MI.addOperand(MCOperand::createImm(tmp));
34578 tmp = fieldFromInstruction(insn, 0, 8);
34579 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34580 tmp = fieldFromInstruction(insn, 32, 9);
34581 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34582 tmp = fieldFromInstruction(insn, 41, 9);
34583 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34584 tmp = fieldFromInstruction(insn, 15, 1);
34585 MI.addOperand(MCOperand::createImm(tmp));
34588 tmp = fieldFromInstruction(insn, 0, 8);
34589 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34590 tmp = fieldFromInstruction(insn, 8, 7);
34591 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34592 tmp = fieldFromInstruction(insn, 32, 9);
34593 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34594 tmp = fieldFromInstruction(insn, 41, 9);
34595 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34596 tmp = fieldFromInstruction(insn, 50, 9);
34597 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34598 tmp = fieldFromInstruction(insn, 15, 1);
34599 MI.addOperand(MCOperand::createImm(tmp));
34602 tmp = fieldFromInstruction(insn, 0, 8);
34603 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34604 tmp = 0x0;
34605 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34606 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34607 MI.addOperand(MCOperand::createImm(tmp));
34608 tmp = fieldFromInstruction(insn, 32, 9);
34609 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34610 tmp = 0x0;
34611 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34612 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34613 MI.addOperand(MCOperand::createImm(tmp));
34614 tmp = fieldFromInstruction(insn, 41, 9);
34615 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34616 tmp = fieldFromInstruction(insn, 15, 1);
34617 MI.addOperand(MCOperand::createImm(tmp));
34618 tmp = fieldFromInstruction(insn, 59, 2);
34619 MI.addOperand(MCOperand::createImm(tmp));
34622 tmp = fieldFromInstruction(insn, 0, 8);
34623 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34624 tmp = 0x0;
34625 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34626 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34627 MI.addOperand(MCOperand::createImm(tmp));
34628 tmp = fieldFromInstruction(insn, 32, 9);
34629 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34630 tmp = 0x0;
34631 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34632 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34633 MI.addOperand(MCOperand::createImm(tmp));
34634 tmp = fieldFromInstruction(insn, 41, 9);
34635 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34636 tmp = fieldFromInstruction(insn, 0, 8);
34637 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34638 tmp = fieldFromInstruction(insn, 15, 1);
34639 MI.addOperand(MCOperand::createImm(tmp));
34640 tmp = fieldFromInstruction(insn, 59, 2);
34641 MI.addOperand(MCOperand::createImm(tmp));
34644 tmp = fieldFromInstruction(insn, 0, 8);
34645 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34646 tmp = 0x0;
34647 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34648 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34649 MI.addOperand(MCOperand::createImm(tmp));
34650 tmp = fieldFromInstruction(insn, 32, 9);
34651 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34652 tmp = 0x0;
34653 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34654 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34655 MI.addOperand(MCOperand::createImm(tmp));
34656 tmp = fieldFromInstruction(insn, 41, 9);
34657 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34658 tmp = fieldFromInstruction(insn, 15, 1);
34659 MI.addOperand(MCOperand::createImm(tmp));
34660 tmp = fieldFromInstruction(insn, 59, 2);
34661 MI.addOperand(MCOperand::createImm(tmp));
34664 tmp = fieldFromInstruction(insn, 0, 8);
34665 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34666 tmp = 0x0;
34667 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34668 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34669 MI.addOperand(MCOperand::createImm(tmp));
34670 tmp = fieldFromInstruction(insn, 32, 9);
34671 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34672 tmp = 0x0;
34673 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34674 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34675 MI.addOperand(MCOperand::createImm(tmp));
34676 tmp = fieldFromInstruction(insn, 41, 9);
34677 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34678 tmp = 0x0;
34679 tmp |= fieldFromInstruction(insn, 10, 1) << 1;
34680 tmp |= fieldFromInstruction(insn, 63, 1) << 0;
34681 MI.addOperand(MCOperand::createImm(tmp));
34682 tmp = fieldFromInstruction(insn, 50, 9);
34683 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34684 tmp = fieldFromInstruction(insn, 15, 1);
34685 MI.addOperand(MCOperand::createImm(tmp));
34686 tmp = fieldFromInstruction(insn, 59, 2);
34687 MI.addOperand(MCOperand::createImm(tmp));
34690 tmp = fieldFromInstruction(insn, 0, 8);
34691 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34692 tmp = fieldFromInstruction(insn, 32, 9);
34693 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34694 tmp = fieldFromInstruction(insn, 41, 9);
34695 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34696 tmp = fieldFromInstruction(insn, 50, 9);
34697 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34698 tmp = fieldFromInstruction(insn, 15, 1);
34699 MI.addOperand(MCOperand::createImm(tmp));
34702 tmp = fieldFromInstruction(insn, 0, 8);
34703 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34704 tmp = fieldFromInstruction(insn, 32, 9);
34705 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34706 tmp = fieldFromInstruction(insn, 41, 9);
34707 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34708 tmp = fieldFromInstruction(insn, 50, 9);
34709 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34712 tmp = fieldFromInstruction(insn, 0, 8);
34713 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34714 tmp = 0x0;
34715 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34716 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34717 MI.addOperand(MCOperand::createImm(tmp));
34718 tmp = fieldFromInstruction(insn, 32, 9);
34719 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34720 tmp = 0x0;
34721 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34722 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34723 MI.addOperand(MCOperand::createImm(tmp));
34724 tmp = fieldFromInstruction(insn, 41, 9);
34725 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34726 tmp = 0x0;
34727 tmp |= fieldFromInstruction(insn, 10, 1) << 1;
34728 tmp |= fieldFromInstruction(insn, 63, 1) << 0;
34729 MI.addOperand(MCOperand::createImm(tmp));
34730 tmp = fieldFromInstruction(insn, 50, 9);
34731 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34732 tmp = fieldFromInstruction(insn, 15, 1);
34733 MI.addOperand(MCOperand::createImm(tmp));
34734 tmp = fieldFromInstruction(insn, 59, 2);
34735 MI.addOperand(MCOperand::createImm(tmp));
34738 tmp = fieldFromInstruction(insn, 0, 8);
34739 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34740 tmp = 0x0;
34741 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34742 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34743 MI.addOperand(MCOperand::createImm(tmp));
34744 tmp = fieldFromInstruction(insn, 32, 9);
34745 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34746 tmp = 0x0;
34747 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34748 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34749 MI.addOperand(MCOperand::createImm(tmp));
34750 tmp = fieldFromInstruction(insn, 41, 9);
34751 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34752 tmp = 0x0;
34753 tmp |= fieldFromInstruction(insn, 10, 1) << 1;
34754 tmp |= fieldFromInstruction(insn, 63, 1) << 0;
34755 MI.addOperand(MCOperand::createImm(tmp));
34756 tmp = fieldFromInstruction(insn, 50, 9);
34757 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34758 tmp = fieldFromInstruction(insn, 15, 1);
34759 MI.addOperand(MCOperand::createImm(tmp));
34762 tmp = fieldFromInstruction(insn, 0, 8);
34763 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34764 tmp = 0x0;
34765 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34766 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34767 MI.addOperand(MCOperand::createImm(tmp));
34768 tmp = fieldFromInstruction(insn, 32, 9);
34769 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34770 tmp = 0x0;
34771 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34772 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34773 MI.addOperand(MCOperand::createImm(tmp));
34774 tmp = fieldFromInstruction(insn, 41, 9);
34775 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34776 tmp = fieldFromInstruction(insn, 15, 1);
34777 MI.addOperand(MCOperand::createImm(tmp));
34778 tmp = fieldFromInstruction(insn, 59, 2);
34779 MI.addOperand(MCOperand::createImm(tmp));
34782 tmp = fieldFromInstruction(insn, 0, 8);
34783 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34784 tmp = 0x0;
34785 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34786 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34787 MI.addOperand(MCOperand::createImm(tmp));
34788 tmp = fieldFromInstruction(insn, 32, 9);
34789 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34790 tmp = 0x0;
34791 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
34792 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
34793 MI.addOperand(MCOperand::createImm(tmp));
34794 tmp = fieldFromInstruction(insn, 41, 9);
34795 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34796 tmp = fieldFromInstruction(insn, 15, 1);
34797 MI.addOperand(MCOperand::createImm(tmp));
34798 tmp = fieldFromInstruction(insn, 59, 2);
34799 MI.addOperand(MCOperand::createImm(tmp));
34802 tmp = fieldFromInstruction(insn, 0, 8);
34803 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34804 tmp = fieldFromInstruction(insn, 8, 7);
34805 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34806 tmp = fieldFromInstruction(insn, 32, 9);
34807 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34808 tmp = fieldFromInstruction(insn, 41, 9);
34809 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34810 tmp = fieldFromInstruction(insn, 50, 9);
34811 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34814 tmp = fieldFromInstruction(insn, 0, 8);
34815 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34816 tmp = fieldFromInstruction(insn, 8, 7);
34817 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34818 tmp = fieldFromInstruction(insn, 32, 9);
34819 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34820 tmp = fieldFromInstruction(insn, 41, 9);
34821 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34822 tmp = fieldFromInstruction(insn, 50, 9);
34823 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34826 tmp = fieldFromInstruction(insn, 0, 8);
34827 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34828 tmp = fieldFromInstruction(insn, 32, 9);
34829 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34830 tmp = fieldFromInstruction(insn, 41, 9);
34831 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34832 tmp = fieldFromInstruction(insn, 50, 9);
34833 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34834 tmp = fieldFromInstruction(insn, 15, 1);
34835 MI.addOperand(MCOperand::createImm(tmp));
34838 tmp = fieldFromInstruction(insn, 0, 8);
34839 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34840 tmp = fieldFromInstruction(insn, 32, 9);
34841 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34842 tmp = fieldFromInstruction(insn, 41, 9);
34843 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34844 tmp = fieldFromInstruction(insn, 50, 9);
34845 if (DecodeVS_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34846 tmp = fieldFromInstruction(insn, 15, 1);
34847 MI.addOperand(MCOperand::createImm(tmp));
34850 tmp = fieldFromInstruction(insn, 0, 8);
34851 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34852 tmp = fieldFromInstruction(insn, 8, 7);
34853 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34854 tmp = fieldFromInstruction(insn, 32, 9);
34855 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34856 tmp = fieldFromInstruction(insn, 41, 9);
34857 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34858 tmp = fieldFromInstruction(insn, 50, 9);
34859 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34860 tmp = fieldFromInstruction(insn, 15, 1);
34861 MI.addOperand(MCOperand::createImm(tmp));
34864 tmp = fieldFromInstruction(insn, 0, 8);
34865 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34866 tmp = fieldFromInstruction(insn, 32, 9);
34867 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34870 tmp = fieldFromInstruction(insn, 0, 8);
34871 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34872 tmp = 0x0;
34873 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34874 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34875 MI.addOperand(MCOperand::createImm(tmp));
34876 tmp = fieldFromInstruction(insn, 32, 9);
34877 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34878 tmp = fieldFromInstruction(insn, 15, 1);
34879 MI.addOperand(MCOperand::createImm(tmp));
34882 tmp = fieldFromInstruction(insn, 0, 8);
34883 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34884 tmp = fieldFromInstruction(insn, 32, 9);
34885 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34886 tmp = fieldFromInstruction(insn, 15, 1);
34887 MI.addOperand(MCOperand::createImm(tmp));
34888 tmp = fieldFromInstruction(insn, 59, 2);
34889 MI.addOperand(MCOperand::createImm(tmp));
34892 tmp = fieldFromInstruction(insn, 0, 8);
34893 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34894 tmp = fieldFromInstruction(insn, 32, 9);
34895 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34896 tmp = fieldFromInstruction(insn, 15, 1);
34897 MI.addOperand(MCOperand::createImm(tmp));
34898 tmp = fieldFromInstruction(insn, 59, 2);
34899 MI.addOperand(MCOperand::createImm(tmp));
34902 tmp = fieldFromInstruction(insn, 0, 8);
34903 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34904 tmp = 0x0;
34905 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34906 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34907 MI.addOperand(MCOperand::createImm(tmp));
34908 tmp = fieldFromInstruction(insn, 32, 9);
34909 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34910 tmp = fieldFromInstruction(insn, 15, 1);
34911 MI.addOperand(MCOperand::createImm(tmp));
34914 tmp = fieldFromInstruction(insn, 0, 8);
34915 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34916 tmp = 0x0;
34917 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34918 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34919 MI.addOperand(MCOperand::createImm(tmp));
34920 tmp = fieldFromInstruction(insn, 32, 9);
34921 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34922 tmp = fieldFromInstruction(insn, 15, 1);
34923 MI.addOperand(MCOperand::createImm(tmp));
34924 tmp = fieldFromInstruction(insn, 59, 2);
34925 MI.addOperand(MCOperand::createImm(tmp));
34928 tmp = fieldFromInstruction(insn, 0, 8);
34929 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34930 tmp = 0x0;
34931 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34932 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34933 MI.addOperand(MCOperand::createImm(tmp));
34934 tmp = fieldFromInstruction(insn, 32, 9);
34935 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34936 tmp = fieldFromInstruction(insn, 15, 1);
34937 MI.addOperand(MCOperand::createImm(tmp));
34938 tmp = fieldFromInstruction(insn, 59, 2);
34939 MI.addOperand(MCOperand::createImm(tmp));
34942 tmp = fieldFromInstruction(insn, 0, 8);
34943 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34944 tmp = 0x0;
34945 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34946 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34947 MI.addOperand(MCOperand::createImm(tmp));
34948 tmp = fieldFromInstruction(insn, 32, 9);
34949 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34950 tmp = fieldFromInstruction(insn, 15, 1);
34951 MI.addOperand(MCOperand::createImm(tmp));
34952 tmp = fieldFromInstruction(insn, 59, 2);
34953 MI.addOperand(MCOperand::createImm(tmp));
34956 tmp = fieldFromInstruction(insn, 0, 8);
34957 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34958 tmp = 0x0;
34959 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34960 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34961 MI.addOperand(MCOperand::createImm(tmp));
34962 tmp = fieldFromInstruction(insn, 32, 9);
34963 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34964 tmp = fieldFromInstruction(insn, 15, 1);
34965 MI.addOperand(MCOperand::createImm(tmp));
34966 tmp = fieldFromInstruction(insn, 59, 2);
34967 MI.addOperand(MCOperand::createImm(tmp));
34970 tmp = fieldFromInstruction(insn, 0, 8);
34971 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34972 tmp = 0x0;
34973 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
34974 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
34975 MI.addOperand(MCOperand::createImm(tmp));
34976 tmp = fieldFromInstruction(insn, 32, 9);
34977 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34978 tmp = fieldFromInstruction(insn, 15, 1);
34979 MI.addOperand(MCOperand::createImm(tmp));
34980 tmp = fieldFromInstruction(insn, 59, 2);
34981 MI.addOperand(MCOperand::createImm(tmp));
34984 tmp = fieldFromInstruction(insn, 0, 8);
34985 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34986 tmp = fieldFromInstruction(insn, 32, 9);
34987 if (DecodeVS_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34990 tmp = fieldFromInstruction(insn, 0, 8);
34991 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34992 tmp = fieldFromInstruction(insn, 32, 9);
34993 if (decodeOperand_VSrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
34994 tmp = fieldFromInstruction(insn, 15, 1);
34995 MI.addOperand(MCOperand::createImm(tmp));
34996 tmp = fieldFromInstruction(insn, 59, 2);
34997 MI.addOperand(MCOperand::createImm(tmp));
35000 tmp = fieldFromInstruction(insn, 0, 8);
35001 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35002 tmp = 0x0;
35003 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
35004 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
35005 MI.addOperand(MCOperand::createImm(tmp));
35006 tmp = fieldFromInstruction(insn, 32, 9);
35007 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35008 tmp = fieldFromInstruction(insn, 15, 1);
35009 MI.addOperand(MCOperand::createImm(tmp));
35012 tmp = fieldFromInstruction(insn, 0, 8);
35013 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35014 tmp = 0x0;
35015 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
35016 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
35017 MI.addOperand(MCOperand::createImm(tmp));
35018 tmp = fieldFromInstruction(insn, 41, 9);
35019 if (DecodeVS_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35020 tmp = fieldFromInstruction(insn, 32, 6);
35021 MI.addOperand(MCOperand::createImm(tmp));
35022 tmp = fieldFromInstruction(insn, 38, 2);
35023 MI.addOperand(MCOperand::createImm(tmp));
35024 tmp = fieldFromInstruction(insn, 15, 1);
35025 MI.addOperand(MCOperand::createImm(tmp));
35026 tmp = fieldFromInstruction(insn, 59, 2);
35027 MI.addOperand(MCOperand::createImm(tmp));
35030 tmp = fieldFromInstruction(insn, 0, 8);
35031 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35032 tmp = fieldFromInstruction(insn, 41, 9);
35033 MI.addOperand(MCOperand::createImm(tmp));
35034 tmp = fieldFromInstruction(insn, 32, 6);
35035 MI.addOperand(MCOperand::createImm(tmp));
35036 tmp = fieldFromInstruction(insn, 38, 2);
35037 MI.addOperand(MCOperand::createImm(tmp));
35038 tmp = fieldFromInstruction(insn, 15, 1);
35039 MI.addOperand(MCOperand::createImm(tmp));
35040 tmp = fieldFromInstruction(insn, 59, 2);
35041 MI.addOperand(MCOperand::createImm(tmp));
35044 tmp = fieldFromInstruction(insn, 0, 8);
35045 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35046 tmp = fieldFromInstruction(insn, 32, 9);
35047 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35048 tmp = fieldFromInstruction(insn, 41, 9);
35049 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35052 tmp = fieldFromInstruction(insn, 0, 8);
35053 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35054 tmp = fieldFromInstruction(insn, 32, 9);
35055 if (decodeOperand_VSrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35056 tmp = fieldFromInstruction(insn, 41, 9);
35057 if (decodeOperand_VSrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35060 tmp = fieldFromInstruction(insn, 0, 8);
35061 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35062 tmp = 0x0;
35063 tmp |= fieldFromInstruction(insn, 11, 1) << 2;
35064 tmp |= fieldFromInstruction(insn, 14, 1) << 3;
35065 MI.addOperand(MCOperand::createImm(tmp));
35066 tmp = fieldFromInstruction(insn, 32, 9);
35067 if (decodeOperand_VSrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35068 tmp = fieldFromInstruction(insn, 12, 1) << 2;
35069 MI.addOperand(MCOperand::createImm(tmp));
35070 tmp = fieldFromInstruction(insn, 41, 9);
35071 if (decodeOperand_VSrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35072 tmp = fieldFromInstruction(insn, 15, 1);
35073 MI.addOperand(MCOperand::createImm(tmp));
35076 tmp = fieldFromInstruction(insn, 0, 8);
35077 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35078 tmp = fieldFromInstruction(insn, 8, 7);
35079 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35080 tmp = fieldFromInstruction(insn, 32, 9);
35081 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35082 tmp = fieldFromInstruction(insn, 41, 9);
35083 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35084 tmp = fieldFromInstruction(insn, 15, 1);
35085 MI.addOperand(MCOperand::createImm(tmp));
35088 tmp = fieldFromInstruction(insn, 0, 8);
35089 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35090 tmp = 0x0;
35091 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
35092 tmp |= fieldFromInstruction(insn, 11, 1) << 2;
35093 tmp |= fieldFromInstruction(insn, 14, 1) << 3;
35094 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
35095 MI.addOperand(MCOperand::createImm(tmp));
35096 tmp = fieldFromInstruction(insn, 32, 9);
35097 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35098 tmp = 0x0;
35099 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
35100 tmp |= fieldFromInstruction(insn, 12, 1) << 2;
35101 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
35102 MI.addOperand(MCOperand::createImm(tmp));
35103 tmp = fieldFromInstruction(insn, 41, 9);
35104 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35105 tmp = fieldFromInstruction(insn, 15, 1);
35106 MI.addOperand(MCOperand::createImm(tmp));
35109 tmp = fieldFromInstruction(insn, 0, 8);
35110 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35111 tmp = 0x0;
35112 tmp |= fieldFromInstruction(insn, 11, 1) << 2;
35113 tmp |= fieldFromInstruction(insn, 14, 1) << 3;
35114 MI.addOperand(MCOperand::createImm(tmp));
35115 tmp = fieldFromInstruction(insn, 32, 9);
35116 if (decodeOperand_VSrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35117 tmp = fieldFromInstruction(insn, 12, 1) << 2;
35118 MI.addOperand(MCOperand::createImm(tmp));
35119 tmp = fieldFromInstruction(insn, 41, 9);
35120 if (decodeOperand_VSrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35121 tmp = fieldFromInstruction(insn, 13, 1) << 2;
35122 MI.addOperand(MCOperand::createImm(tmp));
35123 tmp = fieldFromInstruction(insn, 50, 9);
35124 if (decodeOperand_VSrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35125 tmp = fieldFromInstruction(insn, 15, 1);
35126 MI.addOperand(MCOperand::createImm(tmp));
35129 tmp = fieldFromInstruction(insn, 0, 8);
35130 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35131 tmp = 0x0;
35132 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
35133 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
35134 MI.addOperand(MCOperand::createImm(tmp));
35135 tmp = fieldFromInstruction(insn, 41, 9);
35136 if (DecodeVS_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35137 tmp = fieldFromInstruction(insn, 32, 6);
35138 MI.addOperand(MCOperand::createImm(tmp));
35139 tmp = fieldFromInstruction(insn, 38, 2);
35140 MI.addOperand(MCOperand::createImm(tmp));
35141 tmp = fieldFromInstruction(insn, 40, 1);
35142 MI.addOperand(MCOperand::createImm(tmp));
35143 tmp = fieldFromInstruction(insn, 15, 1);
35144 MI.addOperand(MCOperand::createImm(tmp));
35145 tmp = fieldFromInstruction(insn, 59, 2);
35146 MI.addOperand(MCOperand::createImm(tmp));
35149 tmp = fieldFromInstruction(insn, 0, 8);
35150 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35151 tmp = 0x0;
35152 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
35153 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
35154 MI.addOperand(MCOperand::createImm(tmp));
35155 tmp = fieldFromInstruction(insn, 41, 9);
35156 if (DecodeVS_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35157 tmp = fieldFromInstruction(insn, 32, 6);
35158 MI.addOperand(MCOperand::createImm(tmp));
35159 tmp = fieldFromInstruction(insn, 38, 2);
35160 MI.addOperand(MCOperand::createImm(tmp));
35161 tmp = 0x0;
35162 tmp |= fieldFromInstruction(insn, 10, 1) << 1;
35163 tmp |= fieldFromInstruction(insn, 63, 1) << 0;
35164 MI.addOperand(MCOperand::createImm(tmp));
35165 tmp = fieldFromInstruction(insn, 50, 9);
35166 if (DecodeVS_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35167 tmp = fieldFromInstruction(insn, 40, 1);
35168 MI.addOperand(MCOperand::createImm(tmp));
35169 tmp = fieldFromInstruction(insn, 15, 1);
35170 MI.addOperand(MCOperand::createImm(tmp));
35171 tmp = fieldFromInstruction(insn, 59, 2);
35172 MI.addOperand(MCOperand::createImm(tmp));
35175 tmp = fieldFromInstruction(insn, 0, 8);
35176 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35177 tmp = 0x0;
35178 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
35179 tmp |= fieldFromInstruction(insn, 11, 1) << 2;
35180 tmp |= fieldFromInstruction(insn, 14, 1) << 3;
35181 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
35182 MI.addOperand(MCOperand::createImm(tmp));
35183 tmp = fieldFromInstruction(insn, 32, 9);
35184 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35185 tmp = 0x0;
35186 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
35187 tmp |= fieldFromInstruction(insn, 12, 1) << 2;
35188 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
35189 MI.addOperand(MCOperand::createImm(tmp));
35190 tmp = fieldFromInstruction(insn, 41, 9);
35191 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35192 tmp = 0x0;
35193 tmp |= fieldFromInstruction(insn, 10, 1) << 1;
35194 tmp |= fieldFromInstruction(insn, 13, 1) << 2;
35195 tmp |= fieldFromInstruction(insn, 63, 1) << 0;
35196 MI.addOperand(MCOperand::createImm(tmp));
35197 tmp = fieldFromInstruction(insn, 50, 9);
35198 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35199 tmp = fieldFromInstruction(insn, 15, 1);
35200 MI.addOperand(MCOperand::createImm(tmp));
35203 tmp = fieldFromInstruction(insn, 0, 8);
35204 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35205 tmp = 0x0;
35206 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
35207 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
35208 MI.addOperand(MCOperand::createImm(tmp));
35209 tmp = fieldFromInstruction(insn, 41, 9);
35210 if (DecodeVS_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35211 tmp = fieldFromInstruction(insn, 32, 6);
35212 MI.addOperand(MCOperand::createImm(tmp));
35213 tmp = fieldFromInstruction(insn, 38, 2);
35214 MI.addOperand(MCOperand::createImm(tmp));
35215 tmp = 0x0;
35216 tmp |= fieldFromInstruction(insn, 10, 1) << 1;
35217 tmp |= fieldFromInstruction(insn, 63, 1) << 0;
35218 MI.addOperand(MCOperand::createImm(tmp));
35219 tmp = fieldFromInstruction(insn, 50, 9);
35220 if (DecodeVS_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35221 tmp = fieldFromInstruction(insn, 40, 1);
35222 MI.addOperand(MCOperand::createImm(tmp));
35223 tmp = fieldFromInstruction(insn, 15, 1);
35224 MI.addOperand(MCOperand::createImm(tmp));
35227 tmp = fieldFromInstruction(insn, 0, 8);
35228 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35229 tmp = fieldFromInstruction(insn, 32, 9);
35230 if (DecodeVRegOrLds_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35231 tmp = fieldFromInstruction(insn, 41, 9);
35232 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35235 tmp = fieldFromInstruction(insn, 0, 8);
35236 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35237 tmp = fieldFromInstruction(insn, 32, 9);
35238 if (DecodeSRegOrLds_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35239 tmp = fieldFromInstruction(insn, 41, 9);
35240 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35241 tmp = fieldFromInstruction(insn, 0, 8);
35242 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35245 tmp = fieldFromInstruction(insn, 0, 8);
35246 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35247 tmp = 0x0;
35248 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
35249 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
35250 MI.addOperand(MCOperand::createImm(tmp));
35251 tmp = fieldFromInstruction(insn, 32, 9);
35252 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35253 tmp = 0x0;
35254 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
35255 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
35256 MI.addOperand(MCOperand::createImm(tmp));
35257 tmp = fieldFromInstruction(insn, 41, 9);
35258 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35259 tmp = fieldFromInstruction(insn, 15, 1);
35260 MI.addOperand(MCOperand::createImm(tmp));
35263 tmp = fieldFromInstruction(insn, 0, 8);
35264 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35265 tmp = 0x0;
35266 tmp |= fieldFromInstruction(insn, 11, 1) << 2;
35267 tmp |= fieldFromInstruction(insn, 14, 1) << 3;
35268 MI.addOperand(MCOperand::createImm(tmp));
35269 tmp = fieldFromInstruction(insn, 32, 9);
35270 if (decodeOperand_VSrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35271 tmp = fieldFromInstruction(insn, 12, 1) << 2;
35272 MI.addOperand(MCOperand::createImm(tmp));
35273 tmp = fieldFromInstruction(insn, 41, 9);
35274 if (decodeOperand_VSrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35275 tmp = fieldFromInstruction(insn, 13, 1) << 2;
35276 MI.addOperand(MCOperand::createImm(tmp));
35277 tmp = fieldFromInstruction(insn, 50, 9);
35278 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35279 tmp = fieldFromInstruction(insn, 15, 1);
35280 MI.addOperand(MCOperand::createImm(tmp));
35283 tmp = fieldFromInstruction(insn, 0, 8);
35284 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35285 tmp = 0x0;
35286 tmp |= fieldFromInstruction(insn, 11, 1) << 2;
35287 tmp |= fieldFromInstruction(insn, 14, 1) << 3;
35288 MI.addOperand(MCOperand::createImm(tmp));
35289 tmp = fieldFromInstruction(insn, 32, 9);
35290 if (DecodeVS_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35291 tmp = fieldFromInstruction(insn, 12, 1) << 2;
35292 MI.addOperand(MCOperand::createImm(tmp));
35293 tmp = fieldFromInstruction(insn, 41, 9);
35294 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35295 tmp = fieldFromInstruction(insn, 13, 1) << 2;
35296 MI.addOperand(MCOperand::createImm(tmp));
35297 tmp = fieldFromInstruction(insn, 50, 9);
35298 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35299 tmp = fieldFromInstruction(insn, 0, 8);
35300 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35303 tmp = fieldFromInstruction(insn, 32, 8);
35304 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35305 tmp = fieldFromInstruction(insn, 40, 8);
35306 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35307 tmp = fieldFromInstruction(insn, 0, 16);
35308 MI.addOperand(MCOperand::createImm(tmp));
35309 tmp = fieldFromInstruction(insn, 17, 1);
35310 MI.addOperand(MCOperand::createImm(tmp));
35313 tmp = fieldFromInstruction(insn, 32, 8);
35314 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35315 tmp = fieldFromInstruction(insn, 40, 8);
35316 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35317 tmp = fieldFromInstruction(insn, 48, 8);
35318 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35319 tmp = fieldFromInstruction(insn, 0, 16);
35320 MI.addOperand(MCOperand::createImm(tmp));
35321 tmp = fieldFromInstruction(insn, 17, 1);
35322 MI.addOperand(MCOperand::createImm(tmp));
35325 tmp = fieldFromInstruction(insn, 32, 8);
35326 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35327 tmp = fieldFromInstruction(insn, 40, 8);
35328 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35329 tmp = fieldFromInstruction(insn, 48, 8);
35330 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35331 tmp = fieldFromInstruction(insn, 0, 8);
35332 MI.addOperand(MCOperand::createImm(tmp));
35333 tmp = fieldFromInstruction(insn, 8, 8);
35334 MI.addOperand(MCOperand::createImm(tmp));
35335 tmp = fieldFromInstruction(insn, 17, 1);
35336 MI.addOperand(MCOperand::createImm(tmp));
35339 tmp = fieldFromInstruction(insn, 32, 8);
35340 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35341 tmp = fieldFromInstruction(insn, 0, 16);
35342 MI.addOperand(MCOperand::createImm(tmp));
35345 tmp = fieldFromInstruction(insn, 56, 8);
35346 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35347 tmp = fieldFromInstruction(insn, 32, 8);
35348 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35349 tmp = fieldFromInstruction(insn, 40, 8);
35350 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35351 tmp = fieldFromInstruction(insn, 0, 16);
35352 MI.addOperand(MCOperand::createImm(tmp));
35353 tmp = fieldFromInstruction(insn, 17, 1);
35354 MI.addOperand(MCOperand::createImm(tmp));
35357 tmp = fieldFromInstruction(insn, 56, 8);
35358 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35359 tmp = fieldFromInstruction(insn, 32, 8);
35360 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35361 tmp = fieldFromInstruction(insn, 40, 8);
35362 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35363 tmp = fieldFromInstruction(insn, 48, 8);
35364 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35365 tmp = fieldFromInstruction(insn, 0, 16);
35366 MI.addOperand(MCOperand::createImm(tmp));
35367 tmp = fieldFromInstruction(insn, 17, 1);
35368 MI.addOperand(MCOperand::createImm(tmp));
35371 tmp = fieldFromInstruction(insn, 56, 8);
35372 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35373 tmp = fieldFromInstruction(insn, 32, 8);
35374 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35375 tmp = fieldFromInstruction(insn, 40, 8);
35376 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35377 tmp = fieldFromInstruction(insn, 48, 8);
35378 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35379 tmp = fieldFromInstruction(insn, 0, 8);
35380 MI.addOperand(MCOperand::createImm(tmp));
35381 tmp = fieldFromInstruction(insn, 8, 8);
35382 MI.addOperand(MCOperand::createImm(tmp));
35383 tmp = fieldFromInstruction(insn, 17, 1);
35384 MI.addOperand(MCOperand::createImm(tmp));
35387 tmp = fieldFromInstruction(insn, 56, 8);
35388 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35389 tmp = fieldFromInstruction(insn, 32, 8);
35390 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35391 tmp = fieldFromInstruction(insn, 0, 16);
35392 MI.addOperand(MCOperand::createImm(tmp));
35393 tmp = fieldFromInstruction(insn, 17, 1);
35394 MI.addOperand(MCOperand::createImm(tmp));
35397 tmp = fieldFromInstruction(insn, 56, 8);
35398 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35399 tmp = fieldFromInstruction(insn, 32, 8);
35400 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35401 tmp = fieldFromInstruction(insn, 0, 8);
35402 MI.addOperand(MCOperand::createImm(tmp));
35403 tmp = fieldFromInstruction(insn, 8, 8);
35404 MI.addOperand(MCOperand::createImm(tmp));
35405 tmp = fieldFromInstruction(insn, 17, 1);
35406 MI.addOperand(MCOperand::createImm(tmp));
35409 tmp = fieldFromInstruction(insn, 56, 8);
35410 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35411 tmp = fieldFromInstruction(insn, 0, 16);
35412 MI.addOperand(MCOperand::createImm(tmp));
35413 tmp = fieldFromInstruction(insn, 17, 1);
35414 MI.addOperand(MCOperand::createImm(tmp));
35417 tmp = fieldFromInstruction(insn, 56, 8);
35418 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35419 tmp = fieldFromInstruction(insn, 32, 8);
35420 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35421 tmp = fieldFromInstruction(insn, 0, 16);
35422 MI.addOperand(MCOperand::createImm(tmp));
35425 tmp = fieldFromInstruction(insn, 32, 8);
35426 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35427 tmp = fieldFromInstruction(insn, 40, 8);
35428 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35429 tmp = fieldFromInstruction(insn, 0, 16);
35430 MI.addOperand(MCOperand::createImm(tmp));
35431 tmp = fieldFromInstruction(insn, 17, 1);
35432 MI.addOperand(MCOperand::createImm(tmp));
35435 tmp = fieldFromInstruction(insn, 32, 8);
35436 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35437 tmp = fieldFromInstruction(insn, 40, 8);
35438 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35439 tmp = fieldFromInstruction(insn, 48, 8);
35440 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35441 tmp = fieldFromInstruction(insn, 0, 16);
35442 MI.addOperand(MCOperand::createImm(tmp));
35443 tmp = fieldFromInstruction(insn, 17, 1);
35444 MI.addOperand(MCOperand::createImm(tmp));
35447 tmp = fieldFromInstruction(insn, 32, 8);
35448 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35449 tmp = fieldFromInstruction(insn, 40, 8);
35450 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35451 tmp = fieldFromInstruction(insn, 48, 8);
35452 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35453 tmp = fieldFromInstruction(insn, 0, 8);
35454 MI.addOperand(MCOperand::createImm(tmp));
35455 tmp = fieldFromInstruction(insn, 8, 8);
35456 MI.addOperand(MCOperand::createImm(tmp));
35457 tmp = fieldFromInstruction(insn, 17, 1);
35458 MI.addOperand(MCOperand::createImm(tmp));
35461 tmp = fieldFromInstruction(insn, 56, 8);
35462 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35463 tmp = fieldFromInstruction(insn, 32, 8);
35464 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35465 tmp = fieldFromInstruction(insn, 40, 8);
35466 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35467 tmp = fieldFromInstruction(insn, 0, 16);
35468 MI.addOperand(MCOperand::createImm(tmp));
35469 tmp = fieldFromInstruction(insn, 17, 1);
35470 MI.addOperand(MCOperand::createImm(tmp));
35473 tmp = fieldFromInstruction(insn, 56, 8);
35474 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35475 tmp = fieldFromInstruction(insn, 32, 8);
35476 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35477 tmp = fieldFromInstruction(insn, 40, 8);
35478 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35479 tmp = fieldFromInstruction(insn, 48, 8);
35480 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35481 tmp = fieldFromInstruction(insn, 0, 16);
35482 MI.addOperand(MCOperand::createImm(tmp));
35483 tmp = fieldFromInstruction(insn, 17, 1);
35484 MI.addOperand(MCOperand::createImm(tmp));
35487 tmp = fieldFromInstruction(insn, 56, 8);
35488 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35489 tmp = fieldFromInstruction(insn, 32, 8);
35490 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35491 tmp = fieldFromInstruction(insn, 40, 8);
35492 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35493 tmp = fieldFromInstruction(insn, 48, 8);
35494 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35495 tmp = fieldFromInstruction(insn, 0, 8);
35496 MI.addOperand(MCOperand::createImm(tmp));
35497 tmp = fieldFromInstruction(insn, 8, 8);
35498 MI.addOperand(MCOperand::createImm(tmp));
35499 tmp = fieldFromInstruction(insn, 17, 1);
35500 MI.addOperand(MCOperand::createImm(tmp));
35503 tmp = fieldFromInstruction(insn, 56, 8);
35504 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35505 tmp = fieldFromInstruction(insn, 32, 8);
35506 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35507 tmp = fieldFromInstruction(insn, 0, 16);
35508 MI.addOperand(MCOperand::createImm(tmp));
35509 tmp = fieldFromInstruction(insn, 17, 1);
35510 MI.addOperand(MCOperand::createImm(tmp));
35513 tmp = fieldFromInstruction(insn, 56, 8);
35514 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35515 tmp = fieldFromInstruction(insn, 32, 8);
35516 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35517 tmp = fieldFromInstruction(insn, 0, 8);
35518 MI.addOperand(MCOperand::createImm(tmp));
35519 tmp = fieldFromInstruction(insn, 8, 8);
35520 MI.addOperand(MCOperand::createImm(tmp));
35521 tmp = fieldFromInstruction(insn, 17, 1);
35522 MI.addOperand(MCOperand::createImm(tmp));
35525 tmp = fieldFromInstruction(insn, 32, 8);
35526 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35527 tmp = fieldFromInstruction(insn, 0, 16);
35528 MI.addOperand(MCOperand::createImm(tmp));
35529 tmp = fieldFromInstruction(insn, 17, 1);
35530 MI.addOperand(MCOperand::createImm(tmp));
35533 tmp = fieldFromInstruction(insn, 40, 8);
35534 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35535 tmp = fieldFromInstruction(insn, 0, 16);
35536 MI.addOperand(MCOperand::createImm(tmp));
35537 tmp = fieldFromInstruction(insn, 17, 1);
35538 MI.addOperand(MCOperand::createImm(tmp));
35541 tmp = fieldFromInstruction(insn, 56, 8);
35542 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35543 tmp = fieldFromInstruction(insn, 32, 8);
35544 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35545 tmp = fieldFromInstruction(insn, 40, 8);
35546 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35547 tmp = fieldFromInstruction(insn, 0, 16);
35548 MI.addOperand(MCOperand::createImm(tmp));
35551 tmp = fieldFromInstruction(insn, 32, 8);
35552 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35553 tmp = fieldFromInstruction(insn, 40, 8);
35554 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35555 tmp = fieldFromInstruction(insn, 0, 16);
35556 MI.addOperand(MCOperand::createImm(tmp));
35557 tmp = fieldFromInstruction(insn, 17, 1);
35558 MI.addOperand(MCOperand::createImm(tmp));
35561 tmp = fieldFromInstruction(insn, 32, 8);
35562 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35563 tmp = fieldFromInstruction(insn, 40, 8);
35564 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35565 tmp = fieldFromInstruction(insn, 0, 16);
35566 MI.addOperand(MCOperand::createImm(tmp));
35567 tmp = fieldFromInstruction(insn, 17, 1);
35568 MI.addOperand(MCOperand::createImm(tmp));
35571 tmp = fieldFromInstruction(insn, 56, 8);
35572 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35573 tmp = fieldFromInstruction(insn, 32, 8);
35574 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35575 tmp = fieldFromInstruction(insn, 0, 16);
35576 MI.addOperand(MCOperand::createImm(tmp));
35577 tmp = fieldFromInstruction(insn, 17, 1);
35578 MI.addOperand(MCOperand::createImm(tmp));
35581 tmp = fieldFromInstruction(insn, 56, 8);
35582 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35583 tmp = fieldFromInstruction(insn, 32, 8);
35584 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35585 tmp = fieldFromInstruction(insn, 0, 16);
35586 MI.addOperand(MCOperand::createImm(tmp));
35587 tmp = fieldFromInstruction(insn, 17, 1);
35588 MI.addOperand(MCOperand::createImm(tmp));
35591 tmp = fieldFromInstruction(insn, 56, 8);
35592 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35593 tmp = fieldFromInstruction(insn, 32, 8);
35594 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35595 tmp = fieldFromInstruction(insn, 0, 12);
35596 MI.addOperand(MCOperand::createImm(tmp));
35597 tmp = fieldFromInstruction(insn, 16, 1);
35598 MI.addOperand(MCOperand::createImm(tmp));
35599 tmp = fieldFromInstruction(insn, 17, 1);
35600 MI.addOperand(MCOperand::createImm(tmp));
35601 tmp = fieldFromInstruction(insn, 12, 1);
35602 MI.addOperand(MCOperand::createImm(tmp));
35605 tmp = fieldFromInstruction(insn, 56, 8);
35606 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35607 tmp = fieldFromInstruction(insn, 32, 8);
35608 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35609 tmp = fieldFromInstruction(insn, 0, 12);
35610 MI.addOperand(MCOperand::createImm(tmp));
35611 tmp = fieldFromInstruction(insn, 16, 1);
35612 MI.addOperand(MCOperand::createImm(tmp));
35613 tmp = fieldFromInstruction(insn, 17, 1);
35614 MI.addOperand(MCOperand::createImm(tmp));
35615 tmp = fieldFromInstruction(insn, 12, 1);
35616 MI.addOperand(MCOperand::createImm(tmp));
35619 tmp = fieldFromInstruction(insn, 56, 8);
35620 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35621 tmp = fieldFromInstruction(insn, 48, 7);
35622 if (DecodeSReg_32_XEXEC_HIRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35623 tmp = fieldFromInstruction(insn, 0, 12);
35624 MI.addOperand(MCOperand::createImm(tmp));
35625 tmp = fieldFromInstruction(insn, 16, 1);
35626 MI.addOperand(MCOperand::createImm(tmp));
35627 tmp = fieldFromInstruction(insn, 17, 1);
35628 MI.addOperand(MCOperand::createImm(tmp));
35629 tmp = fieldFromInstruction(insn, 12, 1);
35630 MI.addOperand(MCOperand::createImm(tmp));
35633 tmp = fieldFromInstruction(insn, 56, 8);
35634 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35635 tmp = fieldFromInstruction(insn, 32, 8);
35636 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35637 tmp = fieldFromInstruction(insn, 48, 7);
35638 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35639 tmp = fieldFromInstruction(insn, 0, 12);
35640 MI.addOperand(MCOperand::createImm(tmp));
35641 tmp = fieldFromInstruction(insn, 16, 1);
35642 MI.addOperand(MCOperand::createImm(tmp));
35643 tmp = fieldFromInstruction(insn, 17, 1);
35644 MI.addOperand(MCOperand::createImm(tmp));
35645 tmp = fieldFromInstruction(insn, 12, 1);
35646 MI.addOperand(MCOperand::createImm(tmp));
35649 tmp = fieldFromInstruction(insn, 56, 8);
35650 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35651 tmp = fieldFromInstruction(insn, 32, 8);
35652 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35653 tmp = fieldFromInstruction(insn, 0, 12);
35654 MI.addOperand(MCOperand::createImm(tmp));
35655 tmp = fieldFromInstruction(insn, 16, 1);
35656 MI.addOperand(MCOperand::createImm(tmp));
35657 tmp = fieldFromInstruction(insn, 17, 1);
35658 MI.addOperand(MCOperand::createImm(tmp));
35659 tmp = fieldFromInstruction(insn, 12, 1);
35660 MI.addOperand(MCOperand::createImm(tmp));
35663 tmp = fieldFromInstruction(insn, 56, 8);
35664 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35665 tmp = fieldFromInstruction(insn, 32, 8);
35666 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35667 tmp = fieldFromInstruction(insn, 0, 12);
35668 MI.addOperand(MCOperand::createImm(tmp));
35669 tmp = fieldFromInstruction(insn, 16, 1);
35670 MI.addOperand(MCOperand::createImm(tmp));
35671 tmp = fieldFromInstruction(insn, 17, 1);
35672 MI.addOperand(MCOperand::createImm(tmp));
35673 tmp = fieldFromInstruction(insn, 12, 1);
35674 MI.addOperand(MCOperand::createImm(tmp));
35677 tmp = fieldFromInstruction(insn, 56, 8);
35678 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35679 tmp = fieldFromInstruction(insn, 48, 7);
35680 if (DecodeSReg_32_XEXEC_HIRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35681 tmp = fieldFromInstruction(insn, 0, 12);
35682 MI.addOperand(MCOperand::createImm(tmp));
35683 tmp = fieldFromInstruction(insn, 16, 1);
35684 MI.addOperand(MCOperand::createImm(tmp));
35685 tmp = fieldFromInstruction(insn, 17, 1);
35686 MI.addOperand(MCOperand::createImm(tmp));
35687 tmp = fieldFromInstruction(insn, 12, 1);
35688 MI.addOperand(MCOperand::createImm(tmp));
35691 tmp = fieldFromInstruction(insn, 56, 8);
35692 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35693 tmp = fieldFromInstruction(insn, 32, 8);
35694 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35695 tmp = fieldFromInstruction(insn, 48, 7);
35696 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35697 tmp = fieldFromInstruction(insn, 0, 12);
35698 MI.addOperand(MCOperand::createImm(tmp));
35699 tmp = fieldFromInstruction(insn, 16, 1);
35700 MI.addOperand(MCOperand::createImm(tmp));
35701 tmp = fieldFromInstruction(insn, 17, 1);
35702 MI.addOperand(MCOperand::createImm(tmp));
35703 tmp = fieldFromInstruction(insn, 12, 1);
35704 MI.addOperand(MCOperand::createImm(tmp));
35707 tmp = fieldFromInstruction(insn, 56, 8);
35708 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35709 tmp = fieldFromInstruction(insn, 32, 8);
35710 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35711 tmp = fieldFromInstruction(insn, 0, 12);
35712 MI.addOperand(MCOperand::createImm(tmp));
35713 tmp = fieldFromInstruction(insn, 16, 1);
35714 MI.addOperand(MCOperand::createImm(tmp));
35715 tmp = fieldFromInstruction(insn, 17, 1);
35716 MI.addOperand(MCOperand::createImm(tmp));
35717 tmp = fieldFromInstruction(insn, 12, 1);
35718 MI.addOperand(MCOperand::createImm(tmp));
35721 tmp = fieldFromInstruction(insn, 56, 8);
35722 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35723 tmp = fieldFromInstruction(insn, 32, 8);
35724 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35725 tmp = fieldFromInstruction(insn, 0, 12);
35726 MI.addOperand(MCOperand::createImm(tmp));
35727 tmp = fieldFromInstruction(insn, 16, 1);
35728 MI.addOperand(MCOperand::createImm(tmp));
35729 tmp = fieldFromInstruction(insn, 17, 1);
35730 MI.addOperand(MCOperand::createImm(tmp));
35731 tmp = fieldFromInstruction(insn, 12, 1);
35732 MI.addOperand(MCOperand::createImm(tmp));
35735 tmp = fieldFromInstruction(insn, 56, 8);
35736 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35737 tmp = fieldFromInstruction(insn, 48, 7);
35738 if (DecodeSReg_32_XEXEC_HIRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35739 tmp = fieldFromInstruction(insn, 0, 12);
35740 MI.addOperand(MCOperand::createImm(tmp));
35741 tmp = fieldFromInstruction(insn, 16, 1);
35742 MI.addOperand(MCOperand::createImm(tmp));
35743 tmp = fieldFromInstruction(insn, 17, 1);
35744 MI.addOperand(MCOperand::createImm(tmp));
35745 tmp = fieldFromInstruction(insn, 12, 1);
35746 MI.addOperand(MCOperand::createImm(tmp));
35749 tmp = fieldFromInstruction(insn, 56, 8);
35750 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35751 tmp = fieldFromInstruction(insn, 32, 8);
35752 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35753 tmp = fieldFromInstruction(insn, 48, 7);
35754 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35755 tmp = fieldFromInstruction(insn, 0, 12);
35756 MI.addOperand(MCOperand::createImm(tmp));
35757 tmp = fieldFromInstruction(insn, 16, 1);
35758 MI.addOperand(MCOperand::createImm(tmp));
35759 tmp = fieldFromInstruction(insn, 17, 1);
35760 MI.addOperand(MCOperand::createImm(tmp));
35761 tmp = fieldFromInstruction(insn, 12, 1);
35762 MI.addOperand(MCOperand::createImm(tmp));
35765 tmp = fieldFromInstruction(insn, 56, 8);
35766 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35767 tmp = fieldFromInstruction(insn, 32, 8);
35768 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35769 tmp = fieldFromInstruction(insn, 0, 12);
35770 MI.addOperand(MCOperand::createImm(tmp));
35771 tmp = fieldFromInstruction(insn, 16, 1);
35772 MI.addOperand(MCOperand::createImm(tmp));
35773 tmp = fieldFromInstruction(insn, 17, 1);
35774 MI.addOperand(MCOperand::createImm(tmp));
35775 tmp = fieldFromInstruction(insn, 12, 1);
35776 MI.addOperand(MCOperand::createImm(tmp));
35779 tmp = fieldFromInstruction(insn, 56, 8);
35780 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35781 tmp = fieldFromInstruction(insn, 32, 8);
35782 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35783 tmp = fieldFromInstruction(insn, 0, 12);
35784 MI.addOperand(MCOperand::createImm(tmp));
35785 tmp = fieldFromInstruction(insn, 16, 1);
35786 MI.addOperand(MCOperand::createImm(tmp));
35787 tmp = fieldFromInstruction(insn, 17, 1);
35788 MI.addOperand(MCOperand::createImm(tmp));
35789 tmp = fieldFromInstruction(insn, 12, 1);
35790 MI.addOperand(MCOperand::createImm(tmp));
35793 tmp = fieldFromInstruction(insn, 56, 8);
35794 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35795 tmp = fieldFromInstruction(insn, 48, 7);
35796 if (DecodeSReg_32_XEXEC_HIRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35797 tmp = fieldFromInstruction(insn, 0, 12);
35798 MI.addOperand(MCOperand::createImm(tmp));
35799 tmp = fieldFromInstruction(insn, 16, 1);
35800 MI.addOperand(MCOperand::createImm(tmp));
35801 tmp = fieldFromInstruction(insn, 17, 1);
35802 MI.addOperand(MCOperand::createImm(tmp));
35803 tmp = fieldFromInstruction(insn, 12, 1);
35804 MI.addOperand(MCOperand::createImm(tmp));
35807 tmp = fieldFromInstruction(insn, 56, 8);
35808 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35809 tmp = fieldFromInstruction(insn, 32, 8);
35810 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35811 tmp = fieldFromInstruction(insn, 48, 7);
35812 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35813 tmp = fieldFromInstruction(insn, 0, 12);
35814 MI.addOperand(MCOperand::createImm(tmp));
35815 tmp = fieldFromInstruction(insn, 16, 1);
35816 MI.addOperand(MCOperand::createImm(tmp));
35817 tmp = fieldFromInstruction(insn, 17, 1);
35818 MI.addOperand(MCOperand::createImm(tmp));
35819 tmp = fieldFromInstruction(insn, 12, 1);
35820 MI.addOperand(MCOperand::createImm(tmp));
35823 tmp = fieldFromInstruction(insn, 32, 8);
35824 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35825 tmp = fieldFromInstruction(insn, 40, 8);
35826 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35827 tmp = fieldFromInstruction(insn, 0, 12);
35828 MI.addOperand(MCOperand::createImm(tmp));
35829 tmp = fieldFromInstruction(insn, 16, 1);
35830 MI.addOperand(MCOperand::createImm(tmp));
35831 tmp = fieldFromInstruction(insn, 17, 1);
35832 MI.addOperand(MCOperand::createImm(tmp));
35833 tmp = fieldFromInstruction(insn, 12, 1);
35834 MI.addOperand(MCOperand::createImm(tmp));
35837 tmp = fieldFromInstruction(insn, 40, 8);
35838 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35839 tmp = fieldFromInstruction(insn, 32, 8);
35840 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35841 tmp = fieldFromInstruction(insn, 0, 12);
35842 MI.addOperand(MCOperand::createImm(tmp));
35843 tmp = fieldFromInstruction(insn, 16, 1);
35844 MI.addOperand(MCOperand::createImm(tmp));
35845 tmp = fieldFromInstruction(insn, 17, 1);
35846 MI.addOperand(MCOperand::createImm(tmp));
35847 tmp = fieldFromInstruction(insn, 12, 1);
35848 MI.addOperand(MCOperand::createImm(tmp));
35851 tmp = fieldFromInstruction(insn, 40, 8);
35852 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35853 tmp = fieldFromInstruction(insn, 48, 7);
35854 if (DecodeSReg_32_XEXEC_HIRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35855 tmp = fieldFromInstruction(insn, 0, 12);
35856 MI.addOperand(MCOperand::createImm(tmp));
35857 tmp = fieldFromInstruction(insn, 16, 1);
35858 MI.addOperand(MCOperand::createImm(tmp));
35859 tmp = fieldFromInstruction(insn, 17, 1);
35860 MI.addOperand(MCOperand::createImm(tmp));
35861 tmp = fieldFromInstruction(insn, 12, 1);
35862 MI.addOperand(MCOperand::createImm(tmp));
35865 tmp = fieldFromInstruction(insn, 32, 8);
35866 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35867 tmp = fieldFromInstruction(insn, 40, 8);
35868 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35869 tmp = fieldFromInstruction(insn, 48, 7);
35870 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35871 tmp = fieldFromInstruction(insn, 0, 12);
35872 MI.addOperand(MCOperand::createImm(tmp));
35873 tmp = fieldFromInstruction(insn, 16, 1);
35874 MI.addOperand(MCOperand::createImm(tmp));
35875 tmp = fieldFromInstruction(insn, 17, 1);
35876 MI.addOperand(MCOperand::createImm(tmp));
35877 tmp = fieldFromInstruction(insn, 12, 1);
35878 MI.addOperand(MCOperand::createImm(tmp));
35881 tmp = fieldFromInstruction(insn, 32, 8);
35882 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35883 tmp = fieldFromInstruction(insn, 40, 8);
35884 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35885 tmp = fieldFromInstruction(insn, 0, 12);
35886 MI.addOperand(MCOperand::createImm(tmp));
35887 tmp = fieldFromInstruction(insn, 16, 1);
35888 MI.addOperand(MCOperand::createImm(tmp));
35889 tmp = fieldFromInstruction(insn, 17, 1);
35890 MI.addOperand(MCOperand::createImm(tmp));
35891 tmp = fieldFromInstruction(insn, 12, 1);
35892 MI.addOperand(MCOperand::createImm(tmp));
35895 tmp = fieldFromInstruction(insn, 40, 8);
35896 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35897 tmp = fieldFromInstruction(insn, 32, 8);
35898 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35899 tmp = fieldFromInstruction(insn, 0, 12);
35900 MI.addOperand(MCOperand::createImm(tmp));
35901 tmp = fieldFromInstruction(insn, 16, 1);
35902 MI.addOperand(MCOperand::createImm(tmp));
35903 tmp = fieldFromInstruction(insn, 17, 1);
35904 MI.addOperand(MCOperand::createImm(tmp));
35905 tmp = fieldFromInstruction(insn, 12, 1);
35906 MI.addOperand(MCOperand::createImm(tmp));
35909 tmp = fieldFromInstruction(insn, 40, 8);
35910 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35911 tmp = fieldFromInstruction(insn, 48, 7);
35912 if (DecodeSReg_32_XEXEC_HIRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35913 tmp = fieldFromInstruction(insn, 0, 12);
35914 MI.addOperand(MCOperand::createImm(tmp));
35915 tmp = fieldFromInstruction(insn, 16, 1);
35916 MI.addOperand(MCOperand::createImm(tmp));
35917 tmp = fieldFromInstruction(insn, 17, 1);
35918 MI.addOperand(MCOperand::createImm(tmp));
35919 tmp = fieldFromInstruction(insn, 12, 1);
35920 MI.addOperand(MCOperand::createImm(tmp));
35923 tmp = fieldFromInstruction(insn, 32, 8);
35924 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35925 tmp = fieldFromInstruction(insn, 40, 8);
35926 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35927 tmp = fieldFromInstruction(insn, 48, 7);
35928 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35929 tmp = fieldFromInstruction(insn, 0, 12);
35930 MI.addOperand(MCOperand::createImm(tmp));
35931 tmp = fieldFromInstruction(insn, 16, 1);
35932 MI.addOperand(MCOperand::createImm(tmp));
35933 tmp = fieldFromInstruction(insn, 17, 1);
35934 MI.addOperand(MCOperand::createImm(tmp));
35935 tmp = fieldFromInstruction(insn, 12, 1);
35936 MI.addOperand(MCOperand::createImm(tmp));
35939 tmp = fieldFromInstruction(insn, 32, 8);
35940 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35941 tmp = fieldFromInstruction(insn, 40, 8);
35942 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35943 tmp = fieldFromInstruction(insn, 0, 12);
35944 MI.addOperand(MCOperand::createImm(tmp));
35945 tmp = fieldFromInstruction(insn, 16, 1);
35946 MI.addOperand(MCOperand::createImm(tmp));
35947 tmp = fieldFromInstruction(insn, 17, 1);
35948 MI.addOperand(MCOperand::createImm(tmp));
35949 tmp = fieldFromInstruction(insn, 12, 1);
35950 MI.addOperand(MCOperand::createImm(tmp));
35953 tmp = fieldFromInstruction(insn, 40, 8);
35954 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35955 tmp = fieldFromInstruction(insn, 32, 8);
35956 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35957 tmp = fieldFromInstruction(insn, 0, 12);
35958 MI.addOperand(MCOperand::createImm(tmp));
35959 tmp = fieldFromInstruction(insn, 16, 1);
35960 MI.addOperand(MCOperand::createImm(tmp));
35961 tmp = fieldFromInstruction(insn, 17, 1);
35962 MI.addOperand(MCOperand::createImm(tmp));
35963 tmp = fieldFromInstruction(insn, 12, 1);
35964 MI.addOperand(MCOperand::createImm(tmp));
35967 tmp = fieldFromInstruction(insn, 40, 8);
35968 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35969 tmp = fieldFromInstruction(insn, 48, 7);
35970 if (DecodeSReg_32_XEXEC_HIRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35971 tmp = fieldFromInstruction(insn, 0, 12);
35972 MI.addOperand(MCOperand::createImm(tmp));
35973 tmp = fieldFromInstruction(insn, 16, 1);
35974 MI.addOperand(MCOperand::createImm(tmp));
35975 tmp = fieldFromInstruction(insn, 17, 1);
35976 MI.addOperand(MCOperand::createImm(tmp));
35977 tmp = fieldFromInstruction(insn, 12, 1);
35978 MI.addOperand(MCOperand::createImm(tmp));
35981 tmp = fieldFromInstruction(insn, 32, 8);
35982 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35983 tmp = fieldFromInstruction(insn, 40, 8);
35984 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35985 tmp = fieldFromInstruction(insn, 48, 7);
35986 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35987 tmp = fieldFromInstruction(insn, 0, 12);
35988 MI.addOperand(MCOperand::createImm(tmp));
35989 tmp = fieldFromInstruction(insn, 16, 1);
35990 MI.addOperand(MCOperand::createImm(tmp));
35991 tmp = fieldFromInstruction(insn, 17, 1);
35992 MI.addOperand(MCOperand::createImm(tmp));
35993 tmp = fieldFromInstruction(insn, 12, 1);
35994 MI.addOperand(MCOperand::createImm(tmp));
35997 tmp = fieldFromInstruction(insn, 32, 8);
35998 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
35999 tmp = fieldFromInstruction(insn, 40, 8);
36000 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36001 tmp = fieldFromInstruction(insn, 0, 12);
36002 MI.addOperand(MCOperand::createImm(tmp));
36003 tmp = fieldFromInstruction(insn, 16, 1);
36004 MI.addOperand(MCOperand::createImm(tmp));
36005 tmp = fieldFromInstruction(insn, 17, 1);
36006 MI.addOperand(MCOperand::createImm(tmp));
36007 tmp = fieldFromInstruction(insn, 12, 1);
36008 MI.addOperand(MCOperand::createImm(tmp));
36011 tmp = fieldFromInstruction(insn, 40, 8);
36012 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36013 tmp = fieldFromInstruction(insn, 32, 8);
36014 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36015 tmp = fieldFromInstruction(insn, 0, 12);
36016 MI.addOperand(MCOperand::createImm(tmp));
36017 tmp = fieldFromInstruction(insn, 16, 1);
36018 MI.addOperand(MCOperand::createImm(tmp));
36019 tmp = fieldFromInstruction(insn, 17, 1);
36020 MI.addOperand(MCOperand::createImm(tmp));
36021 tmp = fieldFromInstruction(insn, 12, 1);
36022 MI.addOperand(MCOperand::createImm(tmp));
36025 tmp = fieldFromInstruction(insn, 40, 8);
36026 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36027 tmp = fieldFromInstruction(insn, 48, 7);
36028 if (DecodeSReg_32_XEXEC_HIRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36029 tmp = fieldFromInstruction(insn, 0, 12);
36030 MI.addOperand(MCOperand::createImm(tmp));
36031 tmp = fieldFromInstruction(insn, 16, 1);
36032 MI.addOperand(MCOperand::createImm(tmp));
36033 tmp = fieldFromInstruction(insn, 17, 1);
36034 MI.addOperand(MCOperand::createImm(tmp));
36035 tmp = fieldFromInstruction(insn, 12, 1);
36036 MI.addOperand(MCOperand::createImm(tmp));
36039 tmp = fieldFromInstruction(insn, 32, 8);
36040 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36041 tmp = fieldFromInstruction(insn, 40, 8);
36042 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36043 tmp = fieldFromInstruction(insn, 48, 7);
36044 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36045 tmp = fieldFromInstruction(insn, 0, 12);
36046 MI.addOperand(MCOperand::createImm(tmp));
36047 tmp = fieldFromInstruction(insn, 16, 1);
36048 MI.addOperand(MCOperand::createImm(tmp));
36049 tmp = fieldFromInstruction(insn, 17, 1);
36050 MI.addOperand(MCOperand::createImm(tmp));
36051 tmp = fieldFromInstruction(insn, 12, 1);
36052 MI.addOperand(MCOperand::createImm(tmp));
36055 tmp = fieldFromInstruction(insn, 32, 8);
36056 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36057 tmp = fieldFromInstruction(insn, 40, 8);
36058 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36059 tmp = fieldFromInstruction(insn, 0, 12);
36060 MI.addOperand(MCOperand::createImm(tmp));
36061 tmp = fieldFromInstruction(insn, 17, 1);
36062 MI.addOperand(MCOperand::createImm(tmp));
36065 tmp = fieldFromInstruction(insn, 32, 8);
36066 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36067 tmp = fieldFromInstruction(insn, 40, 8);
36068 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36069 tmp = fieldFromInstruction(insn, 48, 7);
36070 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36071 tmp = fieldFromInstruction(insn, 0, 12);
36072 MI.addOperand(MCOperand::createImm(tmp));
36073 tmp = fieldFromInstruction(insn, 17, 1);
36074 MI.addOperand(MCOperand::createImm(tmp));
36077 tmp = fieldFromInstruction(insn, 56, 8);
36078 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36079 tmp = fieldFromInstruction(insn, 32, 8);
36080 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36081 tmp = fieldFromInstruction(insn, 40, 8);
36082 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36083 tmp = fieldFromInstruction(insn, 0, 12);
36084 MI.addOperand(MCOperand::createImm(tmp));
36085 tmp = fieldFromInstruction(insn, 17, 1);
36086 MI.addOperand(MCOperand::createImm(tmp));
36089 tmp = fieldFromInstruction(insn, 56, 8);
36090 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36091 tmp = fieldFromInstruction(insn, 32, 8);
36092 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36093 tmp = fieldFromInstruction(insn, 40, 8);
36094 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36095 tmp = fieldFromInstruction(insn, 48, 7);
36096 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36097 tmp = fieldFromInstruction(insn, 0, 12);
36098 MI.addOperand(MCOperand::createImm(tmp));
36099 tmp = fieldFromInstruction(insn, 17, 1);
36100 MI.addOperand(MCOperand::createImm(tmp));
36103 tmp = fieldFromInstruction(insn, 32, 8);
36104 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36105 tmp = fieldFromInstruction(insn, 40, 8);
36106 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36107 tmp = fieldFromInstruction(insn, 0, 12);
36108 MI.addOperand(MCOperand::createImm(tmp));
36109 tmp = fieldFromInstruction(insn, 17, 1);
36110 MI.addOperand(MCOperand::createImm(tmp));
36113 tmp = fieldFromInstruction(insn, 32, 8);
36114 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36115 tmp = fieldFromInstruction(insn, 40, 8);
36116 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36117 tmp = fieldFromInstruction(insn, 48, 7);
36118 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36119 tmp = fieldFromInstruction(insn, 0, 12);
36120 MI.addOperand(MCOperand::createImm(tmp));
36121 tmp = fieldFromInstruction(insn, 17, 1);
36122 MI.addOperand(MCOperand::createImm(tmp));
36125 tmp = fieldFromInstruction(insn, 56, 8);
36126 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36127 tmp = fieldFromInstruction(insn, 32, 8);
36128 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36129 tmp = fieldFromInstruction(insn, 40, 8);
36130 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36131 tmp = fieldFromInstruction(insn, 0, 12);
36132 MI.addOperand(MCOperand::createImm(tmp));
36133 tmp = fieldFromInstruction(insn, 17, 1);
36134 MI.addOperand(MCOperand::createImm(tmp));
36137 tmp = fieldFromInstruction(insn, 56, 8);
36138 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36139 tmp = fieldFromInstruction(insn, 32, 8);
36140 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36141 tmp = fieldFromInstruction(insn, 40, 8);
36142 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36143 tmp = fieldFromInstruction(insn, 48, 7);
36144 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36145 tmp = fieldFromInstruction(insn, 0, 12);
36146 MI.addOperand(MCOperand::createImm(tmp));
36147 tmp = fieldFromInstruction(insn, 17, 1);
36148 MI.addOperand(MCOperand::createImm(tmp));
36151 tmp = fieldFromInstruction(insn, 56, 8);
36152 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36153 tmp = fieldFromInstruction(insn, 32, 8);
36154 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36155 tmp = fieldFromInstruction(insn, 40, 8);
36156 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36157 tmp = fieldFromInstruction(insn, 0, 12);
36158 MI.addOperand(MCOperand::createImm(tmp));
36159 tmp = fieldFromInstruction(insn, 17, 1);
36160 MI.addOperand(MCOperand::createImm(tmp));
36163 tmp = fieldFromInstruction(insn, 56, 8);
36164 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36165 tmp = fieldFromInstruction(insn, 32, 8);
36166 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36167 tmp = fieldFromInstruction(insn, 40, 8);
36168 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36169 tmp = fieldFromInstruction(insn, 48, 7);
36170 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36171 tmp = fieldFromInstruction(insn, 0, 12);
36172 MI.addOperand(MCOperand::createImm(tmp));
36173 tmp = fieldFromInstruction(insn, 17, 1);
36174 MI.addOperand(MCOperand::createImm(tmp));
36177 tmp = fieldFromInstruction(insn, 32, 8);
36178 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36179 tmp = fieldFromInstruction(insn, 40, 8);
36180 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36181 tmp = fieldFromInstruction(insn, 0, 12);
36182 MI.addOperand(MCOperand::createImm(tmp));
36183 tmp = fieldFromInstruction(insn, 17, 1);
36184 MI.addOperand(MCOperand::createImm(tmp));
36187 tmp = fieldFromInstruction(insn, 32, 8);
36188 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36189 tmp = fieldFromInstruction(insn, 40, 8);
36190 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36191 tmp = fieldFromInstruction(insn, 48, 7);
36192 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36193 tmp = fieldFromInstruction(insn, 0, 12);
36194 MI.addOperand(MCOperand::createImm(tmp));
36195 tmp = fieldFromInstruction(insn, 17, 1);
36196 MI.addOperand(MCOperand::createImm(tmp));
36199 tmp = fieldFromInstruction(insn, 56, 8);
36200 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36201 tmp = fieldFromInstruction(insn, 32, 8);
36202 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36203 tmp = fieldFromInstruction(insn, 40, 8);
36204 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36205 tmp = fieldFromInstruction(insn, 0, 12);
36206 MI.addOperand(MCOperand::createImm(tmp));
36207 tmp = fieldFromInstruction(insn, 17, 1);
36208 MI.addOperand(MCOperand::createImm(tmp));
36211 tmp = fieldFromInstruction(insn, 56, 8);
36212 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36213 tmp = fieldFromInstruction(insn, 32, 8);
36214 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36215 tmp = fieldFromInstruction(insn, 40, 8);
36216 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36217 tmp = fieldFromInstruction(insn, 48, 7);
36218 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36219 tmp = fieldFromInstruction(insn, 0, 12);
36220 MI.addOperand(MCOperand::createImm(tmp));
36221 tmp = fieldFromInstruction(insn, 17, 1);
36222 MI.addOperand(MCOperand::createImm(tmp));
36225 tmp = fieldFromInstruction(insn, 40, 8);
36226 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36227 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36228 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36229 tmp = fieldFromInstruction(insn, 56, 8);
36230 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36231 tmp = fieldFromInstruction(insn, 0, 12);
36232 MI.addOperand(MCOperand::createImm(tmp));
36233 tmp = fieldFromInstruction(insn, 14, 1);
36234 MI.addOperand(MCOperand::createImm(tmp));
36235 tmp = fieldFromInstruction(insn, 54, 1);
36236 MI.addOperand(MCOperand::createImm(tmp));
36237 tmp = fieldFromInstruction(insn, 55, 1);
36238 MI.addOperand(MCOperand::createImm(tmp));
36239 tmp = fieldFromInstruction(insn, 15, 1);
36240 MI.addOperand(MCOperand::createImm(tmp));
36243 tmp = fieldFromInstruction(insn, 40, 8);
36244 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36245 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36246 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36247 tmp = fieldFromInstruction(insn, 56, 8);
36248 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36249 tmp = fieldFromInstruction(insn, 0, 12);
36250 MI.addOperand(MCOperand::createImm(tmp));
36251 tmp = fieldFromInstruction(insn, 14, 1);
36252 MI.addOperand(MCOperand::createImm(tmp));
36253 tmp = fieldFromInstruction(insn, 54, 1);
36254 MI.addOperand(MCOperand::createImm(tmp));
36255 tmp = fieldFromInstruction(insn, 15, 1);
36256 MI.addOperand(MCOperand::createImm(tmp));
36259 tmp = fieldFromInstruction(insn, 40, 8);
36260 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36261 tmp = fieldFromInstruction(insn, 32, 8);
36262 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36263 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36264 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36265 tmp = fieldFromInstruction(insn, 56, 8);
36266 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36267 tmp = fieldFromInstruction(insn, 0, 12);
36268 MI.addOperand(MCOperand::createImm(tmp));
36269 tmp = fieldFromInstruction(insn, 14, 1);
36270 MI.addOperand(MCOperand::createImm(tmp));
36271 tmp = fieldFromInstruction(insn, 54, 1);
36272 MI.addOperand(MCOperand::createImm(tmp));
36273 tmp = fieldFromInstruction(insn, 55, 1);
36274 MI.addOperand(MCOperand::createImm(tmp));
36275 tmp = fieldFromInstruction(insn, 15, 1);
36276 MI.addOperand(MCOperand::createImm(tmp));
36279 tmp = fieldFromInstruction(insn, 40, 8);
36280 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36281 tmp = fieldFromInstruction(insn, 32, 8);
36282 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36283 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36284 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36285 tmp = fieldFromInstruction(insn, 56, 8);
36286 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36287 tmp = fieldFromInstruction(insn, 0, 12);
36288 MI.addOperand(MCOperand::createImm(tmp));
36289 tmp = fieldFromInstruction(insn, 14, 1);
36290 MI.addOperand(MCOperand::createImm(tmp));
36291 tmp = fieldFromInstruction(insn, 54, 1);
36292 MI.addOperand(MCOperand::createImm(tmp));
36293 tmp = fieldFromInstruction(insn, 15, 1);
36294 MI.addOperand(MCOperand::createImm(tmp));
36297 tmp = fieldFromInstruction(insn, 40, 8);
36298 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36299 tmp = fieldFromInstruction(insn, 32, 8);
36300 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36301 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36302 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36303 tmp = fieldFromInstruction(insn, 56, 8);
36304 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36305 tmp = fieldFromInstruction(insn, 0, 12);
36306 MI.addOperand(MCOperand::createImm(tmp));
36307 tmp = fieldFromInstruction(insn, 14, 1);
36308 MI.addOperand(MCOperand::createImm(tmp));
36309 tmp = fieldFromInstruction(insn, 54, 1);
36310 MI.addOperand(MCOperand::createImm(tmp));
36311 tmp = fieldFromInstruction(insn, 55, 1);
36312 MI.addOperand(MCOperand::createImm(tmp));
36313 tmp = fieldFromInstruction(insn, 15, 1);
36314 MI.addOperand(MCOperand::createImm(tmp));
36317 tmp = fieldFromInstruction(insn, 40, 8);
36318 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36319 tmp = fieldFromInstruction(insn, 32, 8);
36320 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36321 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36322 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36323 tmp = fieldFromInstruction(insn, 56, 8);
36324 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36325 tmp = fieldFromInstruction(insn, 0, 12);
36326 MI.addOperand(MCOperand::createImm(tmp));
36327 tmp = fieldFromInstruction(insn, 14, 1);
36328 MI.addOperand(MCOperand::createImm(tmp));
36329 tmp = fieldFromInstruction(insn, 54, 1);
36330 MI.addOperand(MCOperand::createImm(tmp));
36331 tmp = fieldFromInstruction(insn, 15, 1);
36332 MI.addOperand(MCOperand::createImm(tmp));
36335 tmp = fieldFromInstruction(insn, 40, 8);
36336 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36337 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36338 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36339 tmp = fieldFromInstruction(insn, 56, 8);
36340 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36341 tmp = fieldFromInstruction(insn, 0, 12);
36342 MI.addOperand(MCOperand::createImm(tmp));
36343 tmp = fieldFromInstruction(insn, 14, 1);
36344 MI.addOperand(MCOperand::createImm(tmp));
36345 tmp = fieldFromInstruction(insn, 54, 1);
36346 MI.addOperand(MCOperand::createImm(tmp));
36347 tmp = fieldFromInstruction(insn, 55, 1);
36348 MI.addOperand(MCOperand::createImm(tmp));
36349 tmp = fieldFromInstruction(insn, 15, 1);
36350 MI.addOperand(MCOperand::createImm(tmp));
36353 tmp = fieldFromInstruction(insn, 40, 8);
36354 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36355 tmp = fieldFromInstruction(insn, 32, 8);
36356 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36357 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36358 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36359 tmp = fieldFromInstruction(insn, 56, 8);
36360 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36361 tmp = fieldFromInstruction(insn, 0, 12);
36362 MI.addOperand(MCOperand::createImm(tmp));
36363 tmp = fieldFromInstruction(insn, 14, 1);
36364 MI.addOperand(MCOperand::createImm(tmp));
36365 tmp = fieldFromInstruction(insn, 54, 1);
36366 MI.addOperand(MCOperand::createImm(tmp));
36367 tmp = fieldFromInstruction(insn, 55, 1);
36368 MI.addOperand(MCOperand::createImm(tmp));
36369 tmp = fieldFromInstruction(insn, 15, 1);
36370 MI.addOperand(MCOperand::createImm(tmp));
36373 tmp = fieldFromInstruction(insn, 40, 8);
36374 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36375 tmp = fieldFromInstruction(insn, 32, 8);
36376 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36377 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36378 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36379 tmp = fieldFromInstruction(insn, 56, 8);
36380 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36381 tmp = fieldFromInstruction(insn, 0, 12);
36382 MI.addOperand(MCOperand::createImm(tmp));
36383 tmp = fieldFromInstruction(insn, 14, 1);
36384 MI.addOperand(MCOperand::createImm(tmp));
36385 tmp = fieldFromInstruction(insn, 54, 1);
36386 MI.addOperand(MCOperand::createImm(tmp));
36387 tmp = fieldFromInstruction(insn, 55, 1);
36388 MI.addOperand(MCOperand::createImm(tmp));
36389 tmp = fieldFromInstruction(insn, 15, 1);
36390 MI.addOperand(MCOperand::createImm(tmp));
36393 tmp = fieldFromInstruction(insn, 40, 8);
36394 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36395 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36396 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36397 tmp = fieldFromInstruction(insn, 56, 8);
36398 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36399 tmp = fieldFromInstruction(insn, 0, 12);
36400 MI.addOperand(MCOperand::createImm(tmp));
36401 tmp = fieldFromInstruction(insn, 14, 1);
36402 MI.addOperand(MCOperand::createImm(tmp));
36403 tmp = fieldFromInstruction(insn, 54, 1);
36404 MI.addOperand(MCOperand::createImm(tmp));
36405 tmp = fieldFromInstruction(insn, 55, 1);
36406 MI.addOperand(MCOperand::createImm(tmp));
36407 tmp = fieldFromInstruction(insn, 15, 1);
36408 MI.addOperand(MCOperand::createImm(tmp));
36411 tmp = fieldFromInstruction(insn, 40, 8);
36412 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36413 tmp = fieldFromInstruction(insn, 32, 8);
36414 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36415 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36416 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36417 tmp = fieldFromInstruction(insn, 56, 8);
36418 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36419 tmp = fieldFromInstruction(insn, 0, 12);
36420 MI.addOperand(MCOperand::createImm(tmp));
36421 tmp = fieldFromInstruction(insn, 14, 1);
36422 MI.addOperand(MCOperand::createImm(tmp));
36423 tmp = fieldFromInstruction(insn, 54, 1);
36424 MI.addOperand(MCOperand::createImm(tmp));
36425 tmp = fieldFromInstruction(insn, 55, 1);
36426 MI.addOperand(MCOperand::createImm(tmp));
36427 tmp = fieldFromInstruction(insn, 15, 1);
36428 MI.addOperand(MCOperand::createImm(tmp));
36431 tmp = fieldFromInstruction(insn, 40, 8);
36432 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36433 tmp = fieldFromInstruction(insn, 32, 8);
36434 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36435 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36436 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36437 tmp = fieldFromInstruction(insn, 56, 8);
36438 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36439 tmp = fieldFromInstruction(insn, 0, 12);
36440 MI.addOperand(MCOperand::createImm(tmp));
36441 tmp = fieldFromInstruction(insn, 14, 1);
36442 MI.addOperand(MCOperand::createImm(tmp));
36443 tmp = fieldFromInstruction(insn, 54, 1);
36444 MI.addOperand(MCOperand::createImm(tmp));
36445 tmp = fieldFromInstruction(insn, 55, 1);
36446 MI.addOperand(MCOperand::createImm(tmp));
36447 tmp = fieldFromInstruction(insn, 15, 1);
36448 MI.addOperand(MCOperand::createImm(tmp));
36451 tmp = fieldFromInstruction(insn, 40, 8);
36452 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36453 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36454 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36455 tmp = fieldFromInstruction(insn, 56, 8);
36456 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36457 tmp = fieldFromInstruction(insn, 0, 12);
36458 MI.addOperand(MCOperand::createImm(tmp));
36459 tmp = fieldFromInstruction(insn, 14, 1);
36460 MI.addOperand(MCOperand::createImm(tmp));
36461 tmp = fieldFromInstruction(insn, 54, 1);
36462 MI.addOperand(MCOperand::createImm(tmp));
36463 tmp = fieldFromInstruction(insn, 55, 1);
36464 MI.addOperand(MCOperand::createImm(tmp));
36465 tmp = fieldFromInstruction(insn, 15, 1);
36466 MI.addOperand(MCOperand::createImm(tmp));
36469 tmp = fieldFromInstruction(insn, 40, 8);
36470 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36471 tmp = fieldFromInstruction(insn, 32, 8);
36472 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36473 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36474 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36475 tmp = fieldFromInstruction(insn, 56, 8);
36476 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36477 tmp = fieldFromInstruction(insn, 0, 12);
36478 MI.addOperand(MCOperand::createImm(tmp));
36479 tmp = fieldFromInstruction(insn, 14, 1);
36480 MI.addOperand(MCOperand::createImm(tmp));
36481 tmp = fieldFromInstruction(insn, 54, 1);
36482 MI.addOperand(MCOperand::createImm(tmp));
36483 tmp = fieldFromInstruction(insn, 55, 1);
36484 MI.addOperand(MCOperand::createImm(tmp));
36485 tmp = fieldFromInstruction(insn, 15, 1);
36486 MI.addOperand(MCOperand::createImm(tmp));
36489 tmp = fieldFromInstruction(insn, 40, 8);
36490 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36491 tmp = fieldFromInstruction(insn, 32, 8);
36492 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36493 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36494 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36495 tmp = fieldFromInstruction(insn, 56, 8);
36496 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36497 tmp = fieldFromInstruction(insn, 0, 12);
36498 MI.addOperand(MCOperand::createImm(tmp));
36499 tmp = fieldFromInstruction(insn, 14, 1);
36500 MI.addOperand(MCOperand::createImm(tmp));
36501 tmp = fieldFromInstruction(insn, 54, 1);
36502 MI.addOperand(MCOperand::createImm(tmp));
36503 tmp = fieldFromInstruction(insn, 55, 1);
36504 MI.addOperand(MCOperand::createImm(tmp));
36505 tmp = fieldFromInstruction(insn, 15, 1);
36506 MI.addOperand(MCOperand::createImm(tmp));
36509 tmp = fieldFromInstruction(insn, 40, 8);
36510 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36511 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36512 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36513 tmp = fieldFromInstruction(insn, 56, 8);
36514 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36515 tmp = fieldFromInstruction(insn, 0, 12);
36516 MI.addOperand(MCOperand::createImm(tmp));
36517 tmp = fieldFromInstruction(insn, 14, 1);
36518 MI.addOperand(MCOperand::createImm(tmp));
36519 tmp = fieldFromInstruction(insn, 54, 1);
36520 MI.addOperand(MCOperand::createImm(tmp));
36521 tmp = fieldFromInstruction(insn, 55, 1);
36522 MI.addOperand(MCOperand::createImm(tmp));
36523 tmp = fieldFromInstruction(insn, 15, 1);
36524 MI.addOperand(MCOperand::createImm(tmp));
36525 tmp = fieldFromInstruction(insn, 40, 8);
36526 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36529 tmp = fieldFromInstruction(insn, 40, 8);
36530 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36531 tmp = fieldFromInstruction(insn, 32, 8);
36532 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36533 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36534 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36535 tmp = fieldFromInstruction(insn, 56, 8);
36536 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36537 tmp = fieldFromInstruction(insn, 0, 12);
36538 MI.addOperand(MCOperand::createImm(tmp));
36539 tmp = fieldFromInstruction(insn, 14, 1);
36540 MI.addOperand(MCOperand::createImm(tmp));
36541 tmp = fieldFromInstruction(insn, 54, 1);
36542 MI.addOperand(MCOperand::createImm(tmp));
36543 tmp = fieldFromInstruction(insn, 55, 1);
36544 MI.addOperand(MCOperand::createImm(tmp));
36545 tmp = fieldFromInstruction(insn, 15, 1);
36546 MI.addOperand(MCOperand::createImm(tmp));
36547 tmp = fieldFromInstruction(insn, 40, 8);
36548 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36551 tmp = fieldFromInstruction(insn, 40, 8);
36552 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36553 tmp = fieldFromInstruction(insn, 32, 8);
36554 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36555 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36556 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36557 tmp = fieldFromInstruction(insn, 56, 8);
36558 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36559 tmp = fieldFromInstruction(insn, 0, 12);
36560 MI.addOperand(MCOperand::createImm(tmp));
36561 tmp = fieldFromInstruction(insn, 14, 1);
36562 MI.addOperand(MCOperand::createImm(tmp));
36563 tmp = fieldFromInstruction(insn, 54, 1);
36564 MI.addOperand(MCOperand::createImm(tmp));
36565 tmp = fieldFromInstruction(insn, 55, 1);
36566 MI.addOperand(MCOperand::createImm(tmp));
36567 tmp = fieldFromInstruction(insn, 15, 1);
36568 MI.addOperand(MCOperand::createImm(tmp));
36569 tmp = fieldFromInstruction(insn, 40, 8);
36570 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36573 tmp = fieldFromInstruction(insn, 40, 8);
36574 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36575 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36576 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36577 tmp = fieldFromInstruction(insn, 56, 8);
36578 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36579 tmp = fieldFromInstruction(insn, 0, 12);
36580 MI.addOperand(MCOperand::createImm(tmp));
36581 tmp = fieldFromInstruction(insn, 54, 1);
36582 MI.addOperand(MCOperand::createImm(tmp));
36585 tmp = fieldFromInstruction(insn, 40, 8);
36586 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36587 tmp = fieldFromInstruction(insn, 32, 8);
36588 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36589 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36590 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36591 tmp = fieldFromInstruction(insn, 56, 8);
36592 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36593 tmp = fieldFromInstruction(insn, 0, 12);
36594 MI.addOperand(MCOperand::createImm(tmp));
36595 tmp = fieldFromInstruction(insn, 54, 1);
36596 MI.addOperand(MCOperand::createImm(tmp));
36599 tmp = fieldFromInstruction(insn, 40, 8);
36600 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36601 tmp = fieldFromInstruction(insn, 32, 8);
36602 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36603 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36604 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36605 tmp = fieldFromInstruction(insn, 56, 8);
36606 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36607 tmp = fieldFromInstruction(insn, 0, 12);
36608 MI.addOperand(MCOperand::createImm(tmp));
36609 tmp = fieldFromInstruction(insn, 54, 1);
36610 MI.addOperand(MCOperand::createImm(tmp));
36613 tmp = fieldFromInstruction(insn, 40, 8);
36614 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36615 tmp = fieldFromInstruction(insn, 40, 8);
36616 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36617 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36618 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36619 tmp = fieldFromInstruction(insn, 56, 8);
36620 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36621 tmp = fieldFromInstruction(insn, 0, 12);
36622 MI.addOperand(MCOperand::createImm(tmp));
36623 tmp = fieldFromInstruction(insn, 54, 1);
36624 MI.addOperand(MCOperand::createImm(tmp));
36627 tmp = fieldFromInstruction(insn, 40, 8);
36628 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36629 tmp = fieldFromInstruction(insn, 40, 8);
36630 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36631 tmp = fieldFromInstruction(insn, 32, 8);
36632 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36633 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36634 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36635 tmp = fieldFromInstruction(insn, 56, 8);
36636 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36637 tmp = fieldFromInstruction(insn, 0, 12);
36638 MI.addOperand(MCOperand::createImm(tmp));
36639 tmp = fieldFromInstruction(insn, 54, 1);
36640 MI.addOperand(MCOperand::createImm(tmp));
36643 tmp = fieldFromInstruction(insn, 40, 8);
36644 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36645 tmp = fieldFromInstruction(insn, 40, 8);
36646 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36647 tmp = fieldFromInstruction(insn, 32, 8);
36648 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36649 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36650 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36651 tmp = fieldFromInstruction(insn, 56, 8);
36652 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36653 tmp = fieldFromInstruction(insn, 0, 12);
36654 MI.addOperand(MCOperand::createImm(tmp));
36655 tmp = fieldFromInstruction(insn, 54, 1);
36656 MI.addOperand(MCOperand::createImm(tmp));
36659 tmp = fieldFromInstruction(insn, 40, 8);
36660 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36661 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36662 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36663 tmp = fieldFromInstruction(insn, 56, 8);
36664 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36665 tmp = fieldFromInstruction(insn, 0, 12);
36666 MI.addOperand(MCOperand::createImm(tmp));
36667 tmp = fieldFromInstruction(insn, 54, 1);
36668 MI.addOperand(MCOperand::createImm(tmp));
36671 tmp = fieldFromInstruction(insn, 40, 8);
36672 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36673 tmp = fieldFromInstruction(insn, 32, 8);
36674 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36675 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36676 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36677 tmp = fieldFromInstruction(insn, 56, 8);
36678 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36679 tmp = fieldFromInstruction(insn, 0, 12);
36680 MI.addOperand(MCOperand::createImm(tmp));
36681 tmp = fieldFromInstruction(insn, 54, 1);
36682 MI.addOperand(MCOperand::createImm(tmp));
36685 tmp = fieldFromInstruction(insn, 40, 8);
36686 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36687 tmp = fieldFromInstruction(insn, 32, 8);
36688 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36689 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36690 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36691 tmp = fieldFromInstruction(insn, 56, 8);
36692 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36693 tmp = fieldFromInstruction(insn, 0, 12);
36694 MI.addOperand(MCOperand::createImm(tmp));
36695 tmp = fieldFromInstruction(insn, 54, 1);
36696 MI.addOperand(MCOperand::createImm(tmp));
36699 tmp = fieldFromInstruction(insn, 40, 8);
36700 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36701 tmp = fieldFromInstruction(insn, 40, 8);
36702 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36703 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36704 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36705 tmp = fieldFromInstruction(insn, 56, 8);
36706 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36707 tmp = fieldFromInstruction(insn, 0, 12);
36708 MI.addOperand(MCOperand::createImm(tmp));
36709 tmp = fieldFromInstruction(insn, 54, 1);
36710 MI.addOperand(MCOperand::createImm(tmp));
36713 tmp = fieldFromInstruction(insn, 40, 8);
36714 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36715 tmp = fieldFromInstruction(insn, 40, 8);
36716 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36717 tmp = fieldFromInstruction(insn, 32, 8);
36718 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36719 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36720 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36721 tmp = fieldFromInstruction(insn, 56, 8);
36722 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36723 tmp = fieldFromInstruction(insn, 0, 12);
36724 MI.addOperand(MCOperand::createImm(tmp));
36725 tmp = fieldFromInstruction(insn, 54, 1);
36726 MI.addOperand(MCOperand::createImm(tmp));
36729 tmp = fieldFromInstruction(insn, 40, 8);
36730 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36731 tmp = fieldFromInstruction(insn, 40, 8);
36732 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36733 tmp = fieldFromInstruction(insn, 32, 8);
36734 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36735 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36736 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36737 tmp = fieldFromInstruction(insn, 56, 8);
36738 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36739 tmp = fieldFromInstruction(insn, 0, 12);
36740 MI.addOperand(MCOperand::createImm(tmp));
36741 tmp = fieldFromInstruction(insn, 54, 1);
36742 MI.addOperand(MCOperand::createImm(tmp));
36745 tmp = fieldFromInstruction(insn, 40, 8);
36746 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36747 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36748 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36749 tmp = fieldFromInstruction(insn, 56, 8);
36750 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36751 tmp = fieldFromInstruction(insn, 0, 12);
36752 MI.addOperand(MCOperand::createImm(tmp));
36753 tmp = fieldFromInstruction(insn, 54, 1);
36754 MI.addOperand(MCOperand::createImm(tmp));
36757 tmp = fieldFromInstruction(insn, 40, 8);
36758 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36759 tmp = fieldFromInstruction(insn, 32, 8);
36760 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36761 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36762 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36763 tmp = fieldFromInstruction(insn, 56, 8);
36764 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36765 tmp = fieldFromInstruction(insn, 0, 12);
36766 MI.addOperand(MCOperand::createImm(tmp));
36767 tmp = fieldFromInstruction(insn, 54, 1);
36768 MI.addOperand(MCOperand::createImm(tmp));
36771 tmp = fieldFromInstruction(insn, 40, 8);
36772 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36773 tmp = fieldFromInstruction(insn, 32, 8);
36774 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36775 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36776 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36777 tmp = fieldFromInstruction(insn, 56, 8);
36778 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36779 tmp = fieldFromInstruction(insn, 0, 12);
36780 MI.addOperand(MCOperand::createImm(tmp));
36781 tmp = fieldFromInstruction(insn, 54, 1);
36782 MI.addOperand(MCOperand::createImm(tmp));
36785 tmp = fieldFromInstruction(insn, 40, 8);
36786 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36787 tmp = fieldFromInstruction(insn, 40, 8);
36788 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36789 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36790 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36791 tmp = fieldFromInstruction(insn, 56, 8);
36792 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36793 tmp = fieldFromInstruction(insn, 0, 12);
36794 MI.addOperand(MCOperand::createImm(tmp));
36795 tmp = fieldFromInstruction(insn, 54, 1);
36796 MI.addOperand(MCOperand::createImm(tmp));
36799 tmp = fieldFromInstruction(insn, 40, 8);
36800 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36801 tmp = fieldFromInstruction(insn, 40, 8);
36802 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36803 tmp = fieldFromInstruction(insn, 32, 8);
36804 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36805 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36806 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36807 tmp = fieldFromInstruction(insn, 56, 8);
36808 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36809 tmp = fieldFromInstruction(insn, 0, 12);
36810 MI.addOperand(MCOperand::createImm(tmp));
36811 tmp = fieldFromInstruction(insn, 54, 1);
36812 MI.addOperand(MCOperand::createImm(tmp));
36815 tmp = fieldFromInstruction(insn, 40, 8);
36816 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36817 tmp = fieldFromInstruction(insn, 40, 8);
36818 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36819 tmp = fieldFromInstruction(insn, 32, 8);
36820 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36821 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36822 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36823 tmp = fieldFromInstruction(insn, 56, 8);
36824 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36825 tmp = fieldFromInstruction(insn, 0, 12);
36826 MI.addOperand(MCOperand::createImm(tmp));
36827 tmp = fieldFromInstruction(insn, 54, 1);
36828 MI.addOperand(MCOperand::createImm(tmp));
36831 tmp = fieldFromInstruction(insn, 40, 8);
36832 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36833 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36834 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36835 tmp = fieldFromInstruction(insn, 56, 8);
36836 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36837 tmp = fieldFromInstruction(insn, 0, 12);
36838 MI.addOperand(MCOperand::createImm(tmp));
36839 tmp = fieldFromInstruction(insn, 19, 7);
36840 MI.addOperand(MCOperand::createImm(tmp));
36841 tmp = fieldFromInstruction(insn, 14, 1);
36842 MI.addOperand(MCOperand::createImm(tmp));
36843 tmp = fieldFromInstruction(insn, 54, 1);
36844 MI.addOperand(MCOperand::createImm(tmp));
36845 tmp = fieldFromInstruction(insn, 55, 1);
36846 MI.addOperand(MCOperand::createImm(tmp));
36847 tmp = fieldFromInstruction(insn, 15, 1);
36848 MI.addOperand(MCOperand::createImm(tmp));
36851 tmp = fieldFromInstruction(insn, 40, 8);
36852 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36853 tmp = fieldFromInstruction(insn, 32, 8);
36854 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36855 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36856 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36857 tmp = fieldFromInstruction(insn, 56, 8);
36858 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36859 tmp = fieldFromInstruction(insn, 0, 12);
36860 MI.addOperand(MCOperand::createImm(tmp));
36861 tmp = fieldFromInstruction(insn, 19, 7);
36862 MI.addOperand(MCOperand::createImm(tmp));
36863 tmp = fieldFromInstruction(insn, 14, 1);
36864 MI.addOperand(MCOperand::createImm(tmp));
36865 tmp = fieldFromInstruction(insn, 54, 1);
36866 MI.addOperand(MCOperand::createImm(tmp));
36867 tmp = fieldFromInstruction(insn, 55, 1);
36868 MI.addOperand(MCOperand::createImm(tmp));
36869 tmp = fieldFromInstruction(insn, 15, 1);
36870 MI.addOperand(MCOperand::createImm(tmp));
36873 tmp = fieldFromInstruction(insn, 40, 8);
36874 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36875 tmp = fieldFromInstruction(insn, 32, 8);
36876 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36877 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36878 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36879 tmp = fieldFromInstruction(insn, 56, 8);
36880 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36881 tmp = fieldFromInstruction(insn, 0, 12);
36882 MI.addOperand(MCOperand::createImm(tmp));
36883 tmp = fieldFromInstruction(insn, 19, 7);
36884 MI.addOperand(MCOperand::createImm(tmp));
36885 tmp = fieldFromInstruction(insn, 14, 1);
36886 MI.addOperand(MCOperand::createImm(tmp));
36887 tmp = fieldFromInstruction(insn, 54, 1);
36888 MI.addOperand(MCOperand::createImm(tmp));
36889 tmp = fieldFromInstruction(insn, 55, 1);
36890 MI.addOperand(MCOperand::createImm(tmp));
36891 tmp = fieldFromInstruction(insn, 15, 1);
36892 MI.addOperand(MCOperand::createImm(tmp));
36895 tmp = fieldFromInstruction(insn, 40, 8);
36896 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36897 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36898 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36899 tmp = fieldFromInstruction(insn, 56, 8);
36900 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36901 tmp = fieldFromInstruction(insn, 0, 12);
36902 MI.addOperand(MCOperand::createImm(tmp));
36903 tmp = fieldFromInstruction(insn, 19, 7);
36904 MI.addOperand(MCOperand::createImm(tmp));
36905 tmp = fieldFromInstruction(insn, 14, 1);
36906 MI.addOperand(MCOperand::createImm(tmp));
36907 tmp = fieldFromInstruction(insn, 54, 1);
36908 MI.addOperand(MCOperand::createImm(tmp));
36909 tmp = fieldFromInstruction(insn, 55, 1);
36910 MI.addOperand(MCOperand::createImm(tmp));
36911 tmp = fieldFromInstruction(insn, 15, 1);
36912 MI.addOperand(MCOperand::createImm(tmp));
36915 tmp = fieldFromInstruction(insn, 40, 8);
36916 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36917 tmp = fieldFromInstruction(insn, 32, 8);
36918 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36919 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36920 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36921 tmp = fieldFromInstruction(insn, 56, 8);
36922 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36923 tmp = fieldFromInstruction(insn, 0, 12);
36924 MI.addOperand(MCOperand::createImm(tmp));
36925 tmp = fieldFromInstruction(insn, 19, 7);
36926 MI.addOperand(MCOperand::createImm(tmp));
36927 tmp = fieldFromInstruction(insn, 14, 1);
36928 MI.addOperand(MCOperand::createImm(tmp));
36929 tmp = fieldFromInstruction(insn, 54, 1);
36930 MI.addOperand(MCOperand::createImm(tmp));
36931 tmp = fieldFromInstruction(insn, 55, 1);
36932 MI.addOperand(MCOperand::createImm(tmp));
36933 tmp = fieldFromInstruction(insn, 15, 1);
36934 MI.addOperand(MCOperand::createImm(tmp));
36937 tmp = fieldFromInstruction(insn, 40, 8);
36938 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36939 tmp = fieldFromInstruction(insn, 32, 8);
36940 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36941 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36942 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36943 tmp = fieldFromInstruction(insn, 56, 8);
36944 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36945 tmp = fieldFromInstruction(insn, 0, 12);
36946 MI.addOperand(MCOperand::createImm(tmp));
36947 tmp = fieldFromInstruction(insn, 19, 7);
36948 MI.addOperand(MCOperand::createImm(tmp));
36949 tmp = fieldFromInstruction(insn, 14, 1);
36950 MI.addOperand(MCOperand::createImm(tmp));
36951 tmp = fieldFromInstruction(insn, 54, 1);
36952 MI.addOperand(MCOperand::createImm(tmp));
36953 tmp = fieldFromInstruction(insn, 55, 1);
36954 MI.addOperand(MCOperand::createImm(tmp));
36955 tmp = fieldFromInstruction(insn, 15, 1);
36956 MI.addOperand(MCOperand::createImm(tmp));
36959 tmp = fieldFromInstruction(insn, 40, 8);
36960 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36961 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36962 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36963 tmp = fieldFromInstruction(insn, 56, 8);
36964 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36965 tmp = fieldFromInstruction(insn, 0, 12);
36966 MI.addOperand(MCOperand::createImm(tmp));
36967 tmp = fieldFromInstruction(insn, 19, 7);
36968 MI.addOperand(MCOperand::createImm(tmp));
36969 tmp = fieldFromInstruction(insn, 14, 1);
36970 MI.addOperand(MCOperand::createImm(tmp));
36971 tmp = fieldFromInstruction(insn, 54, 1);
36972 MI.addOperand(MCOperand::createImm(tmp));
36973 tmp = fieldFromInstruction(insn, 55, 1);
36974 MI.addOperand(MCOperand::createImm(tmp));
36975 tmp = fieldFromInstruction(insn, 15, 1);
36976 MI.addOperand(MCOperand::createImm(tmp));
36979 tmp = fieldFromInstruction(insn, 40, 8);
36980 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36981 tmp = fieldFromInstruction(insn, 32, 8);
36982 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36983 tmp = fieldFromInstruction(insn, 48, 5) << 2;
36984 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36985 tmp = fieldFromInstruction(insn, 56, 8);
36986 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
36987 tmp = fieldFromInstruction(insn, 0, 12);
36988 MI.addOperand(MCOperand::createImm(tmp));
36989 tmp = fieldFromInstruction(insn, 19, 7);
36990 MI.addOperand(MCOperand::createImm(tmp));
36991 tmp = fieldFromInstruction(insn, 14, 1);
36992 MI.addOperand(MCOperand::createImm(tmp));
36993 tmp = fieldFromInstruction(insn, 54, 1);
36994 MI.addOperand(MCOperand::createImm(tmp));
36995 tmp = fieldFromInstruction(insn, 55, 1);
36996 MI.addOperand(MCOperand::createImm(tmp));
36997 tmp = fieldFromInstruction(insn, 15, 1);
36998 MI.addOperand(MCOperand::createImm(tmp));
37001 tmp = fieldFromInstruction(insn, 40, 8);
37002 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37003 tmp = fieldFromInstruction(insn, 32, 8);
37004 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37005 tmp = fieldFromInstruction(insn, 48, 5) << 2;
37006 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37007 tmp = fieldFromInstruction(insn, 56, 8);
37008 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37009 tmp = fieldFromInstruction(insn, 0, 12);
37010 MI.addOperand(MCOperand::createImm(tmp));
37011 tmp = fieldFromInstruction(insn, 19, 7);
37012 MI.addOperand(MCOperand::createImm(tmp));
37013 tmp = fieldFromInstruction(insn, 14, 1);
37014 MI.addOperand(MCOperand::createImm(tmp));
37015 tmp = fieldFromInstruction(insn, 54, 1);
37016 MI.addOperand(MCOperand::createImm(tmp));
37017 tmp = fieldFromInstruction(insn, 55, 1);
37018 MI.addOperand(MCOperand::createImm(tmp));
37019 tmp = fieldFromInstruction(insn, 15, 1);
37020 MI.addOperand(MCOperand::createImm(tmp));
37023 tmp = fieldFromInstruction(insn, 40, 8);
37024 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37025 tmp = fieldFromInstruction(insn, 48, 5) << 2;
37026 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37027 tmp = fieldFromInstruction(insn, 56, 8);
37028 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37029 tmp = fieldFromInstruction(insn, 0, 12);
37030 MI.addOperand(MCOperand::createImm(tmp));
37031 tmp = fieldFromInstruction(insn, 19, 7);
37032 MI.addOperand(MCOperand::createImm(tmp));
37033 tmp = fieldFromInstruction(insn, 14, 1);
37034 MI.addOperand(MCOperand::createImm(tmp));
37035 tmp = fieldFromInstruction(insn, 54, 1);
37036 MI.addOperand(MCOperand::createImm(tmp));
37037 tmp = fieldFromInstruction(insn, 55, 1);
37038 MI.addOperand(MCOperand::createImm(tmp));
37039 tmp = fieldFromInstruction(insn, 15, 1);
37040 MI.addOperand(MCOperand::createImm(tmp));
37043 tmp = fieldFromInstruction(insn, 40, 8);
37044 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37045 tmp = fieldFromInstruction(insn, 32, 8);
37046 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37047 tmp = fieldFromInstruction(insn, 48, 5) << 2;
37048 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37049 tmp = fieldFromInstruction(insn, 56, 8);
37050 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37051 tmp = fieldFromInstruction(insn, 0, 12);
37052 MI.addOperand(MCOperand::createImm(tmp));
37053 tmp = fieldFromInstruction(insn, 19, 7);
37054 MI.addOperand(MCOperand::createImm(tmp));
37055 tmp = fieldFromInstruction(insn, 14, 1);
37056 MI.addOperand(MCOperand::createImm(tmp));
37057 tmp = fieldFromInstruction(insn, 54, 1);
37058 MI.addOperand(MCOperand::createImm(tmp));
37059 tmp = fieldFromInstruction(insn, 55, 1);
37060 MI.addOperand(MCOperand::createImm(tmp));
37061 tmp = fieldFromInstruction(insn, 15, 1);
37062 MI.addOperand(MCOperand::createImm(tmp));
37065 tmp = fieldFromInstruction(insn, 40, 8);
37066 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37067 tmp = fieldFromInstruction(insn, 32, 8);
37068 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37069 tmp = fieldFromInstruction(insn, 48, 5) << 2;
37070 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37071 tmp = fieldFromInstruction(insn, 56, 8);
37072 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37073 tmp = fieldFromInstruction(insn, 0, 12);
37074 MI.addOperand(MCOperand::createImm(tmp));
37075 tmp = fieldFromInstruction(insn, 19, 7);
37076 MI.addOperand(MCOperand::createImm(tmp));
37077 tmp = fieldFromInstruction(insn, 14, 1);
37078 MI.addOperand(MCOperand::createImm(tmp));
37079 tmp = fieldFromInstruction(insn, 54, 1);
37080 MI.addOperand(MCOperand::createImm(tmp));
37081 tmp = fieldFromInstruction(insn, 55, 1);
37082 MI.addOperand(MCOperand::createImm(tmp));
37083 tmp = fieldFromInstruction(insn, 15, 1);
37084 MI.addOperand(MCOperand::createImm(tmp));
37087 tmp = fieldFromInstruction(insn, 6, 7);
37088 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37089 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37090 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37091 tmp = fieldFromInstruction(insn, 32, 20);
37092 MI.addOperand(MCOperand::createImm(tmp));
37093 tmp = fieldFromInstruction(insn, 16, 1);
37094 MI.addOperand(MCOperand::createImm(tmp));
37095 tmp = fieldFromInstruction(insn, 14, 1);
37096 MI.addOperand(MCOperand::createImm(tmp));
37099 tmp = fieldFromInstruction(insn, 6, 7);
37100 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37101 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37102 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37103 tmp = fieldFromInstruction(insn, 57, 7);
37104 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37105 tmp = fieldFromInstruction(insn, 16, 1);
37106 MI.addOperand(MCOperand::createImm(tmp));
37107 tmp = fieldFromInstruction(insn, 14, 1);
37108 MI.addOperand(MCOperand::createImm(tmp));
37111 tmp = fieldFromInstruction(insn, 6, 7);
37112 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37113 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37114 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37115 tmp = fieldFromInstruction(insn, 32, 20);
37116 MI.addOperand(MCOperand::createImm(tmp));
37117 tmp = fieldFromInstruction(insn, 16, 1);
37118 MI.addOperand(MCOperand::createImm(tmp));
37119 tmp = fieldFromInstruction(insn, 14, 1);
37120 MI.addOperand(MCOperand::createImm(tmp));
37123 tmp = fieldFromInstruction(insn, 6, 7);
37124 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37125 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37126 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37127 tmp = fieldFromInstruction(insn, 57, 7);
37128 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37129 tmp = fieldFromInstruction(insn, 16, 1);
37130 MI.addOperand(MCOperand::createImm(tmp));
37131 tmp = fieldFromInstruction(insn, 14, 1);
37132 MI.addOperand(MCOperand::createImm(tmp));
37135 tmp = fieldFromInstruction(insn, 6, 7);
37136 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37137 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37138 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37139 tmp = fieldFromInstruction(insn, 32, 20);
37140 MI.addOperand(MCOperand::createImm(tmp));
37141 tmp = fieldFromInstruction(insn, 16, 1);
37142 MI.addOperand(MCOperand::createImm(tmp));
37143 tmp = fieldFromInstruction(insn, 14, 1);
37144 MI.addOperand(MCOperand::createImm(tmp));
37147 tmp = fieldFromInstruction(insn, 6, 7);
37148 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37149 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37150 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37151 tmp = fieldFromInstruction(insn, 57, 7);
37152 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37153 tmp = fieldFromInstruction(insn, 16, 1);
37154 MI.addOperand(MCOperand::createImm(tmp));
37155 tmp = fieldFromInstruction(insn, 14, 1);
37156 MI.addOperand(MCOperand::createImm(tmp));
37159 tmp = fieldFromInstruction(insn, 6, 7);
37160 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37161 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37162 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37163 tmp = fieldFromInstruction(insn, 32, 20);
37164 MI.addOperand(MCOperand::createImm(tmp));
37165 tmp = fieldFromInstruction(insn, 16, 1);
37166 MI.addOperand(MCOperand::createImm(tmp));
37167 tmp = fieldFromInstruction(insn, 14, 1);
37168 MI.addOperand(MCOperand::createImm(tmp));
37171 tmp = fieldFromInstruction(insn, 6, 7);
37172 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37173 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37174 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37175 tmp = fieldFromInstruction(insn, 57, 7);
37176 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37177 tmp = fieldFromInstruction(insn, 16, 1);
37178 MI.addOperand(MCOperand::createImm(tmp));
37179 tmp = fieldFromInstruction(insn, 14, 1);
37180 MI.addOperand(MCOperand::createImm(tmp));
37183 tmp = fieldFromInstruction(insn, 6, 7);
37184 if (DecodeSReg_512RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37185 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37186 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37187 tmp = fieldFromInstruction(insn, 32, 20);
37188 MI.addOperand(MCOperand::createImm(tmp));
37189 tmp = fieldFromInstruction(insn, 16, 1);
37190 MI.addOperand(MCOperand::createImm(tmp));
37191 tmp = fieldFromInstruction(insn, 14, 1);
37192 MI.addOperand(MCOperand::createImm(tmp));
37195 tmp = fieldFromInstruction(insn, 6, 7);
37196 if (DecodeSReg_512RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37197 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37198 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37199 tmp = fieldFromInstruction(insn, 57, 7);
37200 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37201 tmp = fieldFromInstruction(insn, 16, 1);
37202 MI.addOperand(MCOperand::createImm(tmp));
37203 tmp = fieldFromInstruction(insn, 14, 1);
37204 MI.addOperand(MCOperand::createImm(tmp));
37207 tmp = fieldFromInstruction(insn, 6, 7);
37208 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37209 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37210 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37211 tmp = fieldFromInstruction(insn, 32, 20);
37212 MI.addOperand(MCOperand::createImm(tmp));
37213 tmp = fieldFromInstruction(insn, 16, 1);
37214 MI.addOperand(MCOperand::createImm(tmp));
37215 tmp = fieldFromInstruction(insn, 14, 1);
37216 MI.addOperand(MCOperand::createImm(tmp));
37219 tmp = fieldFromInstruction(insn, 6, 7);
37220 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37221 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37222 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37223 tmp = fieldFromInstruction(insn, 57, 7);
37224 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37225 tmp = fieldFromInstruction(insn, 16, 1);
37226 MI.addOperand(MCOperand::createImm(tmp));
37227 tmp = fieldFromInstruction(insn, 14, 1);
37228 MI.addOperand(MCOperand::createImm(tmp));
37231 tmp = fieldFromInstruction(insn, 6, 7);
37232 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37233 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37234 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37235 tmp = fieldFromInstruction(insn, 32, 20);
37236 MI.addOperand(MCOperand::createImm(tmp));
37237 tmp = fieldFromInstruction(insn, 16, 1);
37238 MI.addOperand(MCOperand::createImm(tmp));
37239 tmp = fieldFromInstruction(insn, 14, 1);
37240 MI.addOperand(MCOperand::createImm(tmp));
37243 tmp = fieldFromInstruction(insn, 6, 7);
37244 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37245 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37246 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37247 tmp = fieldFromInstruction(insn, 57, 7);
37248 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37249 tmp = fieldFromInstruction(insn, 16, 1);
37250 MI.addOperand(MCOperand::createImm(tmp));
37251 tmp = fieldFromInstruction(insn, 14, 1);
37252 MI.addOperand(MCOperand::createImm(tmp));
37255 tmp = fieldFromInstruction(insn, 6, 7);
37256 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37257 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37258 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37259 tmp = fieldFromInstruction(insn, 32, 20);
37260 MI.addOperand(MCOperand::createImm(tmp));
37261 tmp = fieldFromInstruction(insn, 16, 1);
37262 MI.addOperand(MCOperand::createImm(tmp));
37263 tmp = fieldFromInstruction(insn, 14, 1);
37264 MI.addOperand(MCOperand::createImm(tmp));
37267 tmp = fieldFromInstruction(insn, 6, 7);
37268 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37269 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37270 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37271 tmp = fieldFromInstruction(insn, 57, 7);
37272 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37273 tmp = fieldFromInstruction(insn, 16, 1);
37274 MI.addOperand(MCOperand::createImm(tmp));
37275 tmp = fieldFromInstruction(insn, 14, 1);
37276 MI.addOperand(MCOperand::createImm(tmp));
37279 tmp = fieldFromInstruction(insn, 6, 7);
37280 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37281 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37282 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37283 tmp = fieldFromInstruction(insn, 32, 20);
37284 MI.addOperand(MCOperand::createImm(tmp));
37285 tmp = fieldFromInstruction(insn, 16, 1);
37286 MI.addOperand(MCOperand::createImm(tmp));
37287 tmp = fieldFromInstruction(insn, 14, 1);
37288 MI.addOperand(MCOperand::createImm(tmp));
37291 tmp = fieldFromInstruction(insn, 6, 7);
37292 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37293 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37294 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37295 tmp = fieldFromInstruction(insn, 57, 7);
37296 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37297 tmp = fieldFromInstruction(insn, 16, 1);
37298 MI.addOperand(MCOperand::createImm(tmp));
37299 tmp = fieldFromInstruction(insn, 14, 1);
37300 MI.addOperand(MCOperand::createImm(tmp));
37303 tmp = fieldFromInstruction(insn, 6, 7);
37304 if (DecodeSReg_512RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37305 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37306 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37307 tmp = fieldFromInstruction(insn, 32, 20);
37308 MI.addOperand(MCOperand::createImm(tmp));
37309 tmp = fieldFromInstruction(insn, 16, 1);
37310 MI.addOperand(MCOperand::createImm(tmp));
37311 tmp = fieldFromInstruction(insn, 14, 1);
37312 MI.addOperand(MCOperand::createImm(tmp));
37315 tmp = fieldFromInstruction(insn, 6, 7);
37316 if (DecodeSReg_512RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37317 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37318 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37319 tmp = fieldFromInstruction(insn, 57, 7);
37320 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37321 tmp = fieldFromInstruction(insn, 16, 1);
37322 MI.addOperand(MCOperand::createImm(tmp));
37323 tmp = fieldFromInstruction(insn, 14, 1);
37324 MI.addOperand(MCOperand::createImm(tmp));
37327 tmp = fieldFromInstruction(insn, 6, 7);
37328 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37331 tmp = fieldFromInstruction(insn, 6, 7);
37332 MI.addOperand(MCOperand::createImm(tmp));
37333 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37334 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37335 tmp = fieldFromInstruction(insn, 32, 20);
37336 MI.addOperand(MCOperand::createImm(tmp));
37339 tmp = fieldFromInstruction(insn, 6, 7);
37340 MI.addOperand(MCOperand::createImm(tmp));
37341 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37342 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37343 tmp = fieldFromInstruction(insn, 57, 7);
37344 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37347 tmp = fieldFromInstruction(insn, 6, 7);
37348 MI.addOperand(MCOperand::createImm(tmp));
37349 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37350 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37351 tmp = fieldFromInstruction(insn, 32, 20);
37352 MI.addOperand(MCOperand::createImm(tmp));
37355 tmp = fieldFromInstruction(insn, 6, 7);
37356 MI.addOperand(MCOperand::createImm(tmp));
37357 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37358 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37359 tmp = fieldFromInstruction(insn, 57, 7);
37360 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37363 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37364 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37365 tmp = fieldFromInstruction(insn, 32, 20);
37366 MI.addOperand(MCOperand::createImm(tmp));
37369 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37370 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37371 tmp = fieldFromInstruction(insn, 57, 7);
37372 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37375 tmp = fieldFromInstruction(insn, 6, 7);
37376 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37379 tmp = fieldFromInstruction(insn, 6, 7);
37380 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37381 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37382 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37383 tmp = fieldFromInstruction(insn, 32, 20);
37384 MI.addOperand(MCOperand::createImm(tmp));
37385 tmp = fieldFromInstruction(insn, 14, 1);
37386 MI.addOperand(MCOperand::createImm(tmp));
37389 tmp = fieldFromInstruction(insn, 6, 7);
37390 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37391 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37392 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37393 tmp = fieldFromInstruction(insn, 57, 7);
37394 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37395 tmp = fieldFromInstruction(insn, 14, 1);
37396 MI.addOperand(MCOperand::createImm(tmp));
37399 tmp = fieldFromInstruction(insn, 6, 7);
37400 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37401 tmp = fieldFromInstruction(insn, 6, 7);
37402 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37403 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37404 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37405 tmp = fieldFromInstruction(insn, 32, 20);
37406 MI.addOperand(MCOperand::createImm(tmp));
37407 tmp = fieldFromInstruction(insn, 14, 1);
37408 MI.addOperand(MCOperand::createImm(tmp));
37411 tmp = fieldFromInstruction(insn, 6, 7);
37412 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37413 tmp = fieldFromInstruction(insn, 6, 7);
37414 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37415 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37416 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37417 tmp = fieldFromInstruction(insn, 57, 7);
37418 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37419 tmp = fieldFromInstruction(insn, 14, 1);
37420 MI.addOperand(MCOperand::createImm(tmp));
37423 tmp = fieldFromInstruction(insn, 6, 7);
37424 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37425 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37426 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37427 tmp = fieldFromInstruction(insn, 32, 20);
37428 MI.addOperand(MCOperand::createImm(tmp));
37429 tmp = fieldFromInstruction(insn, 14, 1);
37430 MI.addOperand(MCOperand::createImm(tmp));
37433 tmp = fieldFromInstruction(insn, 6, 7);
37434 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37435 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37436 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37437 tmp = fieldFromInstruction(insn, 57, 7);
37438 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37439 tmp = fieldFromInstruction(insn, 14, 1);
37440 MI.addOperand(MCOperand::createImm(tmp));
37443 tmp = fieldFromInstruction(insn, 6, 7);
37444 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37445 tmp = fieldFromInstruction(insn, 6, 7);
37446 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37447 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37448 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37449 tmp = fieldFromInstruction(insn, 32, 20);
37450 MI.addOperand(MCOperand::createImm(tmp));
37451 tmp = fieldFromInstruction(insn, 14, 1);
37452 MI.addOperand(MCOperand::createImm(tmp));
37455 tmp = fieldFromInstruction(insn, 6, 7);
37456 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37457 tmp = fieldFromInstruction(insn, 6, 7);
37458 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37459 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37460 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37461 tmp = fieldFromInstruction(insn, 57, 7);
37462 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37463 tmp = fieldFromInstruction(insn, 14, 1);
37464 MI.addOperand(MCOperand::createImm(tmp));
37467 tmp = fieldFromInstruction(insn, 6, 7);
37468 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37469 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37470 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37471 tmp = fieldFromInstruction(insn, 32, 20);
37472 MI.addOperand(MCOperand::createImm(tmp));
37473 tmp = fieldFromInstruction(insn, 14, 1);
37474 MI.addOperand(MCOperand::createImm(tmp));
37477 tmp = fieldFromInstruction(insn, 6, 7);
37478 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37479 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37480 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37481 tmp = fieldFromInstruction(insn, 57, 7);
37482 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37483 tmp = fieldFromInstruction(insn, 14, 1);
37484 MI.addOperand(MCOperand::createImm(tmp));
37487 tmp = fieldFromInstruction(insn, 6, 7);
37488 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37489 tmp = fieldFromInstruction(insn, 6, 7);
37490 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37491 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37492 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37493 tmp = fieldFromInstruction(insn, 32, 20);
37494 MI.addOperand(MCOperand::createImm(tmp));
37495 tmp = fieldFromInstruction(insn, 14, 1);
37496 MI.addOperand(MCOperand::createImm(tmp));
37499 tmp = fieldFromInstruction(insn, 6, 7);
37500 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37501 tmp = fieldFromInstruction(insn, 6, 7);
37502 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37503 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37504 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37505 tmp = fieldFromInstruction(insn, 57, 7);
37506 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37507 tmp = fieldFromInstruction(insn, 14, 1);
37508 MI.addOperand(MCOperand::createImm(tmp));
37511 tmp = fieldFromInstruction(insn, 6, 7);
37512 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37513 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37514 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37515 tmp = fieldFromInstruction(insn, 32, 20);
37516 MI.addOperand(MCOperand::createImm(tmp));
37517 tmp = fieldFromInstruction(insn, 14, 1);
37518 MI.addOperand(MCOperand::createImm(tmp));
37521 tmp = fieldFromInstruction(insn, 6, 7);
37522 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37523 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37524 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37525 tmp = fieldFromInstruction(insn, 57, 7);
37526 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37527 tmp = fieldFromInstruction(insn, 14, 1);
37528 MI.addOperand(MCOperand::createImm(tmp));
37531 tmp = fieldFromInstruction(insn, 6, 7);
37532 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37533 tmp = fieldFromInstruction(insn, 6, 7);
37534 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37535 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37536 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37537 tmp = fieldFromInstruction(insn, 32, 20);
37538 MI.addOperand(MCOperand::createImm(tmp));
37539 tmp = fieldFromInstruction(insn, 14, 1);
37540 MI.addOperand(MCOperand::createImm(tmp));
37543 tmp = fieldFromInstruction(insn, 6, 7);
37544 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37545 tmp = fieldFromInstruction(insn, 6, 7);
37546 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37547 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37548 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37549 tmp = fieldFromInstruction(insn, 57, 7);
37550 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37551 tmp = fieldFromInstruction(insn, 14, 1);
37552 MI.addOperand(MCOperand::createImm(tmp));
37555 tmp = fieldFromInstruction(insn, 6, 7);
37556 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37557 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37558 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37559 tmp = fieldFromInstruction(insn, 32, 20);
37560 MI.addOperand(MCOperand::createImm(tmp));
37561 tmp = fieldFromInstruction(insn, 14, 1);
37562 MI.addOperand(MCOperand::createImm(tmp));
37565 tmp = fieldFromInstruction(insn, 6, 7);
37566 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37567 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37568 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37569 tmp = fieldFromInstruction(insn, 57, 7);
37570 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37571 tmp = fieldFromInstruction(insn, 14, 1);
37572 MI.addOperand(MCOperand::createImm(tmp));
37575 tmp = fieldFromInstruction(insn, 6, 7);
37576 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37577 tmp = fieldFromInstruction(insn, 6, 7);
37578 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37579 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37580 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37581 tmp = fieldFromInstruction(insn, 32, 20);
37582 MI.addOperand(MCOperand::createImm(tmp));
37583 tmp = fieldFromInstruction(insn, 14, 1);
37584 MI.addOperand(MCOperand::createImm(tmp));
37587 tmp = fieldFromInstruction(insn, 6, 7);
37588 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37589 tmp = fieldFromInstruction(insn, 6, 7);
37590 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37591 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37592 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37593 tmp = fieldFromInstruction(insn, 57, 7);
37594 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37595 tmp = fieldFromInstruction(insn, 14, 1);
37596 MI.addOperand(MCOperand::createImm(tmp));
37599 tmp = fieldFromInstruction(insn, 6, 7);
37600 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37601 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37602 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37603 tmp = fieldFromInstruction(insn, 32, 20);
37604 MI.addOperand(MCOperand::createImm(tmp));
37605 tmp = fieldFromInstruction(insn, 14, 1);
37606 MI.addOperand(MCOperand::createImm(tmp));
37609 tmp = fieldFromInstruction(insn, 6, 7);
37610 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37611 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37612 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37613 tmp = fieldFromInstruction(insn, 57, 7);
37614 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37615 tmp = fieldFromInstruction(insn, 14, 1);
37616 MI.addOperand(MCOperand::createImm(tmp));
37619 tmp = fieldFromInstruction(insn, 6, 7);
37620 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37621 tmp = fieldFromInstruction(insn, 6, 7);
37622 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37623 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37624 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37625 tmp = fieldFromInstruction(insn, 32, 20);
37626 MI.addOperand(MCOperand::createImm(tmp));
37627 tmp = fieldFromInstruction(insn, 14, 1);
37628 MI.addOperand(MCOperand::createImm(tmp));
37631 tmp = fieldFromInstruction(insn, 6, 7);
37632 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37633 tmp = fieldFromInstruction(insn, 6, 7);
37634 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37635 tmp = fieldFromInstruction(insn, 0, 6) << 1;
37636 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37637 tmp = fieldFromInstruction(insn, 57, 7);
37638 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37639 tmp = fieldFromInstruction(insn, 14, 1);
37640 MI.addOperand(MCOperand::createImm(tmp));
37643 tmp = fieldFromInstruction(insn, 4, 6);
37644 MI.addOperand(MCOperand::createImm(tmp));
37645 tmp = fieldFromInstruction(insn, 32, 8);
37646 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37647 tmp = fieldFromInstruction(insn, 40, 8);
37648 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37649 tmp = fieldFromInstruction(insn, 48, 8);
37650 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37651 tmp = fieldFromInstruction(insn, 56, 8);
37652 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37653 tmp = fieldFromInstruction(insn, 12, 1);
37654 MI.addOperand(MCOperand::createImm(tmp));
37655 tmp = fieldFromInstruction(insn, 10, 1);
37656 MI.addOperand(MCOperand::createImm(tmp));
37657 tmp = fieldFromInstruction(insn, 0, 4);
37658 MI.addOperand(MCOperand::createImm(tmp));
37661 tmp = fieldFromInstruction(insn, 17, 8);
37662 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37663 tmp = fieldFromInstruction(insn, 0, 9);
37664 if (DecodeVRegOrLds_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37665 tmp = fieldFromInstruction(insn, 9, 8);
37666 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37669 tmp = fieldFromInstruction(insn, 17, 8);
37670 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37671 tmp = fieldFromInstruction(insn, 0, 9);
37672 if (DecodeSRegOrLds_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37673 tmp = fieldFromInstruction(insn, 9, 8);
37674 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37675 tmp = fieldFromInstruction(insn, 17, 8);
37676 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37679 tmp = fieldFromInstruction(insn, 0, 8);
37680 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37683 tmp = fieldFromInstruction(insn, 15, 7);
37684 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37685 tmp = fieldFromInstruction(insn, 9, 6) << 1;
37686 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37687 tmp = fieldFromInstruction(insn, 0, 8);
37688 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37691 tmp = fieldFromInstruction(insn, 15, 7);
37692 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37693 tmp = fieldFromInstruction(insn, 9, 6) << 1;
37694 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37695 tmp = fieldFromInstruction(insn, 0, 8);
37696 MI.addOperand(MCOperand::createImm(tmp));
37699 tmp = fieldFromInstruction(insn, 15, 7);
37700 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37701 tmp = fieldFromInstruction(insn, 9, 6) << 1;
37702 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37703 tmp = fieldFromInstruction(insn, 0, 8);
37704 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37707 tmp = fieldFromInstruction(insn, 15, 7);
37708 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37709 tmp = fieldFromInstruction(insn, 9, 6) << 1;
37710 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37711 tmp = fieldFromInstruction(insn, 0, 8);
37712 MI.addOperand(MCOperand::createImm(tmp));
37715 tmp = fieldFromInstruction(insn, 15, 7);
37716 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37717 tmp = fieldFromInstruction(insn, 9, 6) << 1;
37718 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37719 tmp = fieldFromInstruction(insn, 0, 8);
37720 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37723 tmp = fieldFromInstruction(insn, 15, 7);
37724 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37725 tmp = fieldFromInstruction(insn, 9, 6) << 1;
37726 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37727 tmp = fieldFromInstruction(insn, 0, 8);
37728 MI.addOperand(MCOperand::createImm(tmp));
37731 tmp = fieldFromInstruction(insn, 15, 7);
37732 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37733 tmp = fieldFromInstruction(insn, 9, 6) << 1;
37734 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37735 tmp = fieldFromInstruction(insn, 0, 8);
37736 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37739 tmp = fieldFromInstruction(insn, 15, 7);
37740 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37741 tmp = fieldFromInstruction(insn, 9, 6) << 1;
37742 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37743 tmp = fieldFromInstruction(insn, 0, 8);
37744 MI.addOperand(MCOperand::createImm(tmp));
37747 tmp = fieldFromInstruction(insn, 15, 7);
37748 if (DecodeSReg_512RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37749 tmp = fieldFromInstruction(insn, 9, 6) << 1;
37750 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37751 tmp = fieldFromInstruction(insn, 0, 8);
37752 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37755 tmp = fieldFromInstruction(insn, 15, 7);
37756 if (DecodeSReg_512RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37757 tmp = fieldFromInstruction(insn, 9, 6) << 1;
37758 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37759 tmp = fieldFromInstruction(insn, 0, 8);
37760 MI.addOperand(MCOperand::createImm(tmp));
37763 tmp = fieldFromInstruction(insn, 15, 7);
37764 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37765 tmp = fieldFromInstruction(insn, 9, 6) << 1;
37766 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37767 tmp = fieldFromInstruction(insn, 0, 8);
37768 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37771 tmp = fieldFromInstruction(insn, 15, 7);
37772 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37773 tmp = fieldFromInstruction(insn, 9, 6) << 1;
37774 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37775 tmp = fieldFromInstruction(insn, 0, 8);
37776 MI.addOperand(MCOperand::createImm(tmp));
37779 tmp = fieldFromInstruction(insn, 15, 7);
37780 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37781 tmp = fieldFromInstruction(insn, 9, 6) << 1;
37782 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37783 tmp = fieldFromInstruction(insn, 0, 8);
37784 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37787 tmp = fieldFromInstruction(insn, 15, 7);
37788 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37789 tmp = fieldFromInstruction(insn, 9, 6) << 1;
37790 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37791 tmp = fieldFromInstruction(insn, 0, 8);
37792 MI.addOperand(MCOperand::createImm(tmp));
37795 tmp = fieldFromInstruction(insn, 15, 7);
37796 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37797 tmp = fieldFromInstruction(insn, 9, 6) << 1;
37798 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37799 tmp = fieldFromInstruction(insn, 0, 8);
37800 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37803 tmp = fieldFromInstruction(insn, 15, 7);
37804 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37805 tmp = fieldFromInstruction(insn, 9, 6) << 1;
37806 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37807 tmp = fieldFromInstruction(insn, 0, 8);
37808 MI.addOperand(MCOperand::createImm(tmp));
37811 tmp = fieldFromInstruction(insn, 15, 7);
37812 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37813 tmp = fieldFromInstruction(insn, 9, 6) << 1;
37814 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37815 tmp = fieldFromInstruction(insn, 0, 8);
37816 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37819 tmp = fieldFromInstruction(insn, 15, 7);
37820 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37821 tmp = fieldFromInstruction(insn, 9, 6) << 1;
37822 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37823 tmp = fieldFromInstruction(insn, 0, 8);
37824 MI.addOperand(MCOperand::createImm(tmp));
37827 tmp = fieldFromInstruction(insn, 15, 7);
37828 if (DecodeSReg_512RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37829 tmp = fieldFromInstruction(insn, 9, 6) << 1;
37830 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37831 tmp = fieldFromInstruction(insn, 0, 8);
37832 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37835 tmp = fieldFromInstruction(insn, 15, 7);
37836 if (DecodeSReg_512RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37837 tmp = fieldFromInstruction(insn, 9, 6) << 1;
37838 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37839 tmp = fieldFromInstruction(insn, 0, 8);
37840 MI.addOperand(MCOperand::createImm(tmp));
37843 tmp = fieldFromInstruction(insn, 15, 7);
37844 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37847 tmp = fieldFromInstruction(insn, 0, 8);
37848 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37849 tmp = 0x0;
37850 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
37851 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
37852 MI.addOperand(MCOperand::createImm(tmp));
37853 tmp = fieldFromInstruction(insn, 32, 9);
37854 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37855 tmp = 0x0;
37856 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
37857 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
37858 MI.addOperand(MCOperand::createImm(tmp));
37859 tmp = fieldFromInstruction(insn, 41, 9);
37860 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37861 tmp = fieldFromInstruction(insn, 11, 1);
37862 MI.addOperand(MCOperand::createImm(tmp));
37865 tmp = fieldFromInstruction(insn, 0, 8);
37866 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37867 tmp = 0x0;
37868 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
37869 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
37870 MI.addOperand(MCOperand::createImm(tmp));
37871 tmp = fieldFromInstruction(insn, 32, 9);
37872 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37873 tmp = 0x0;
37874 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
37875 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
37876 MI.addOperand(MCOperand::createImm(tmp));
37877 tmp = fieldFromInstruction(insn, 41, 9);
37878 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37879 tmp = fieldFromInstruction(insn, 11, 1);
37880 MI.addOperand(MCOperand::createImm(tmp));
37883 tmp = fieldFromInstruction(insn, 0, 8);
37884 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37885 tmp = 0x0;
37886 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
37887 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
37888 MI.addOperand(MCOperand::createImm(tmp));
37889 tmp = fieldFromInstruction(insn, 32, 9);
37890 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37891 tmp = 0x0;
37892 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
37893 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
37894 MI.addOperand(MCOperand::createImm(tmp));
37895 tmp = fieldFromInstruction(insn, 41, 9);
37896 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37897 tmp = fieldFromInstruction(insn, 11, 1);
37898 MI.addOperand(MCOperand::createImm(tmp));
37899 tmp = fieldFromInstruction(insn, 59, 2);
37900 MI.addOperand(MCOperand::createImm(tmp));
37903 tmp = fieldFromInstruction(insn, 0, 8);
37904 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37905 tmp = 0x0;
37906 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
37907 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
37908 MI.addOperand(MCOperand::createImm(tmp));
37909 tmp = fieldFromInstruction(insn, 32, 9);
37910 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37911 tmp = 0x0;
37912 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
37913 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
37914 MI.addOperand(MCOperand::createImm(tmp));
37915 tmp = fieldFromInstruction(insn, 41, 9);
37916 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37917 tmp = fieldFromInstruction(insn, 0, 8);
37918 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37919 tmp = fieldFromInstruction(insn, 11, 1);
37920 MI.addOperand(MCOperand::createImm(tmp));
37921 tmp = fieldFromInstruction(insn, 59, 2);
37922 MI.addOperand(MCOperand::createImm(tmp));
37925 tmp = fieldFromInstruction(insn, 0, 8);
37926 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37927 tmp = fieldFromInstruction(insn, 8, 7);
37928 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37929 tmp = fieldFromInstruction(insn, 32, 9);
37930 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37931 tmp = fieldFromInstruction(insn, 41, 9);
37932 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37935 tmp = fieldFromInstruction(insn, 0, 8);
37936 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37937 tmp = fieldFromInstruction(insn, 8, 7);
37938 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37939 tmp = fieldFromInstruction(insn, 32, 9);
37940 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37941 tmp = fieldFromInstruction(insn, 41, 9);
37942 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37943 tmp = fieldFromInstruction(insn, 50, 9);
37944 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37947 tmp = fieldFromInstruction(insn, 0, 8);
37948 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37949 tmp = 0x0;
37950 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
37951 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
37952 MI.addOperand(MCOperand::createImm(tmp));
37953 tmp = fieldFromInstruction(insn, 32, 9);
37954 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37955 tmp = 0x0;
37956 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
37957 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
37958 MI.addOperand(MCOperand::createImm(tmp));
37959 tmp = fieldFromInstruction(insn, 41, 9);
37960 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37961 tmp = fieldFromInstruction(insn, 11, 1);
37962 MI.addOperand(MCOperand::createImm(tmp));
37965 tmp = fieldFromInstruction(insn, 0, 8);
37966 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37967 tmp = 0x0;
37968 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
37969 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
37970 MI.addOperand(MCOperand::createImm(tmp));
37971 tmp = fieldFromInstruction(insn, 32, 9);
37972 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37973 tmp = 0x0;
37974 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
37975 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
37976 MI.addOperand(MCOperand::createImm(tmp));
37977 tmp = fieldFromInstruction(insn, 41, 9);
37978 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37979 tmp = 0x0;
37980 tmp |= fieldFromInstruction(insn, 10, 1) << 1;
37981 tmp |= fieldFromInstruction(insn, 63, 1) << 0;
37982 MI.addOperand(MCOperand::createImm(tmp));
37983 tmp = fieldFromInstruction(insn, 50, 9);
37984 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37985 tmp = fieldFromInstruction(insn, 11, 1);
37986 MI.addOperand(MCOperand::createImm(tmp));
37987 tmp = fieldFromInstruction(insn, 59, 2);
37988 MI.addOperand(MCOperand::createImm(tmp));
37991 tmp = fieldFromInstruction(insn, 0, 8);
37992 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37993 tmp = fieldFromInstruction(insn, 32, 9);
37994 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37995 tmp = fieldFromInstruction(insn, 41, 9);
37996 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37997 tmp = fieldFromInstruction(insn, 50, 9);
37998 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
37999 tmp = fieldFromInstruction(insn, 11, 1);
38000 MI.addOperand(MCOperand::createImm(tmp));
38003 tmp = fieldFromInstruction(insn, 0, 8);
38004 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38005 tmp = 0x0;
38006 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
38007 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
38008 MI.addOperand(MCOperand::createImm(tmp));
38009 tmp = fieldFromInstruction(insn, 32, 9);
38010 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38011 tmp = 0x0;
38012 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
38013 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
38014 MI.addOperand(MCOperand::createImm(tmp));
38015 tmp = fieldFromInstruction(insn, 41, 9);
38016 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38017 tmp = 0x0;
38018 tmp |= fieldFromInstruction(insn, 10, 1) << 1;
38019 tmp |= fieldFromInstruction(insn, 63, 1) << 0;
38020 MI.addOperand(MCOperand::createImm(tmp));
38021 tmp = fieldFromInstruction(insn, 50, 9);
38022 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38023 tmp = fieldFromInstruction(insn, 11, 1);
38024 MI.addOperand(MCOperand::createImm(tmp));
38025 tmp = fieldFromInstruction(insn, 59, 2);
38026 MI.addOperand(MCOperand::createImm(tmp));
38029 tmp = fieldFromInstruction(insn, 0, 8);
38030 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38031 tmp = 0x0;
38032 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
38033 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
38034 MI.addOperand(MCOperand::createImm(tmp));
38035 tmp = fieldFromInstruction(insn, 32, 9);
38036 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38037 tmp = 0x0;
38038 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
38039 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
38040 MI.addOperand(MCOperand::createImm(tmp));
38041 tmp = fieldFromInstruction(insn, 41, 9);
38042 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38043 tmp = 0x0;
38044 tmp |= fieldFromInstruction(insn, 10, 1) << 1;
38045 tmp |= fieldFromInstruction(insn, 63, 1) << 0;
38046 MI.addOperand(MCOperand::createImm(tmp));
38047 tmp = fieldFromInstruction(insn, 50, 9);
38048 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38049 tmp = fieldFromInstruction(insn, 11, 1);
38050 MI.addOperand(MCOperand::createImm(tmp));
38053 tmp = fieldFromInstruction(insn, 0, 8);
38054 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38055 tmp = fieldFromInstruction(insn, 32, 9);
38056 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38057 tmp = fieldFromInstruction(insn, 41, 9);
38058 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38061 tmp = fieldFromInstruction(insn, 0, 8);
38062 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38063 tmp = 0x0;
38064 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
38065 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
38066 MI.addOperand(MCOperand::createImm(tmp));
38067 tmp = fieldFromInstruction(insn, 32, 9);
38068 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38069 tmp = 0x0;
38070 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
38071 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
38072 MI.addOperand(MCOperand::createImm(tmp));
38073 tmp = fieldFromInstruction(insn, 41, 9);
38074 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38075 tmp = fieldFromInstruction(insn, 11, 1);
38076 MI.addOperand(MCOperand::createImm(tmp));
38077 tmp = fieldFromInstruction(insn, 59, 2);
38078 MI.addOperand(MCOperand::createImm(tmp));
38081 tmp = fieldFromInstruction(insn, 0, 8);
38082 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38083 tmp = 0x0;
38084 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
38085 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
38086 MI.addOperand(MCOperand::createImm(tmp));
38087 tmp = fieldFromInstruction(insn, 32, 9);
38088 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38089 tmp = 0x0;
38090 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
38091 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
38092 MI.addOperand(MCOperand::createImm(tmp));
38093 tmp = fieldFromInstruction(insn, 41, 9);
38094 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38095 tmp = fieldFromInstruction(insn, 11, 1);
38096 MI.addOperand(MCOperand::createImm(tmp));
38097 tmp = fieldFromInstruction(insn, 59, 2);
38098 MI.addOperand(MCOperand::createImm(tmp));
38101 tmp = fieldFromInstruction(insn, 0, 8);
38102 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38103 tmp = fieldFromInstruction(insn, 32, 9);
38104 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38105 tmp = fieldFromInstruction(insn, 41, 9);
38106 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38107 tmp = fieldFromInstruction(insn, 50, 9);
38108 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38109 tmp = fieldFromInstruction(insn, 11, 1);
38110 MI.addOperand(MCOperand::createImm(tmp));
38113 tmp = fieldFromInstruction(insn, 0, 8);
38114 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38115 tmp = 0x0;
38116 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
38117 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
38118 MI.addOperand(MCOperand::createImm(tmp));
38119 tmp = fieldFromInstruction(insn, 32, 9);
38120 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38121 tmp = fieldFromInstruction(insn, 11, 1);
38122 MI.addOperand(MCOperand::createImm(tmp));
38125 tmp = fieldFromInstruction(insn, 0, 8);
38126 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38127 tmp = fieldFromInstruction(insn, 32, 9);
38128 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38129 tmp = fieldFromInstruction(insn, 11, 1);
38130 MI.addOperand(MCOperand::createImm(tmp));
38131 tmp = fieldFromInstruction(insn, 59, 2);
38132 MI.addOperand(MCOperand::createImm(tmp));
38135 tmp = fieldFromInstruction(insn, 0, 8);
38136 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38137 tmp = fieldFromInstruction(insn, 32, 9);
38138 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38139 tmp = fieldFromInstruction(insn, 11, 1);
38140 MI.addOperand(MCOperand::createImm(tmp));
38141 tmp = fieldFromInstruction(insn, 59, 2);
38142 MI.addOperand(MCOperand::createImm(tmp));
38145 tmp = fieldFromInstruction(insn, 0, 8);
38146 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38147 tmp = 0x0;
38148 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
38149 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
38150 MI.addOperand(MCOperand::createImm(tmp));
38151 tmp = fieldFromInstruction(insn, 32, 9);
38152 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38153 tmp = fieldFromInstruction(insn, 11, 1);
38154 MI.addOperand(MCOperand::createImm(tmp));
38157 tmp = fieldFromInstruction(insn, 0, 8);
38158 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38159 tmp = 0x0;
38160 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
38161 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
38162 MI.addOperand(MCOperand::createImm(tmp));
38163 tmp = fieldFromInstruction(insn, 32, 9);
38164 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38165 tmp = fieldFromInstruction(insn, 11, 1);
38166 MI.addOperand(MCOperand::createImm(tmp));
38167 tmp = fieldFromInstruction(insn, 59, 2);
38168 MI.addOperand(MCOperand::createImm(tmp));
38171 tmp = fieldFromInstruction(insn, 0, 8);
38172 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38173 tmp = 0x0;
38174 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
38175 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
38176 MI.addOperand(MCOperand::createImm(tmp));
38177 tmp = fieldFromInstruction(insn, 32, 9);
38178 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38179 tmp = fieldFromInstruction(insn, 11, 1);
38180 MI.addOperand(MCOperand::createImm(tmp));
38181 tmp = fieldFromInstruction(insn, 59, 2);
38182 MI.addOperand(MCOperand::createImm(tmp));
38185 tmp = fieldFromInstruction(insn, 0, 8);
38186 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38187 tmp = 0x0;
38188 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
38189 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
38190 MI.addOperand(MCOperand::createImm(tmp));
38191 tmp = fieldFromInstruction(insn, 32, 9);
38192 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38193 tmp = fieldFromInstruction(insn, 11, 1);
38194 MI.addOperand(MCOperand::createImm(tmp));
38195 tmp = fieldFromInstruction(insn, 59, 2);
38196 MI.addOperand(MCOperand::createImm(tmp));
38199 tmp = fieldFromInstruction(insn, 0, 8);
38200 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38201 tmp = 0x0;
38202 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
38203 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
38204 MI.addOperand(MCOperand::createImm(tmp));
38205 tmp = fieldFromInstruction(insn, 32, 9);
38206 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38207 tmp = fieldFromInstruction(insn, 11, 1);
38208 MI.addOperand(MCOperand::createImm(tmp));
38209 tmp = fieldFromInstruction(insn, 59, 2);
38210 MI.addOperand(MCOperand::createImm(tmp));
38213 tmp = fieldFromInstruction(insn, 0, 8);
38214 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38215 tmp = 0x0;
38216 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
38217 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
38218 MI.addOperand(MCOperand::createImm(tmp));
38219 tmp = fieldFromInstruction(insn, 32, 9);
38220 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38221 tmp = fieldFromInstruction(insn, 11, 1);
38222 MI.addOperand(MCOperand::createImm(tmp));
38223 tmp = fieldFromInstruction(insn, 59, 2);
38224 MI.addOperand(MCOperand::createImm(tmp));
38227 tmp = fieldFromInstruction(insn, 40, 8);
38228 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38229 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38230 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38231 tmp = fieldFromInstruction(insn, 56, 8);
38232 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38233 tmp = fieldFromInstruction(insn, 0, 12);
38234 MI.addOperand(MCOperand::createImm(tmp));
38235 tmp = fieldFromInstruction(insn, 14, 1);
38236 MI.addOperand(MCOperand::createImm(tmp));
38237 tmp = fieldFromInstruction(insn, 54, 1);
38238 MI.addOperand(MCOperand::createImm(tmp));
38239 tmp = fieldFromInstruction(insn, 55, 1);
38240 MI.addOperand(MCOperand::createImm(tmp));
38243 tmp = fieldFromInstruction(insn, 40, 8);
38244 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38245 tmp = fieldFromInstruction(insn, 32, 8);
38246 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38247 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38248 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38249 tmp = fieldFromInstruction(insn, 56, 8);
38250 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38251 tmp = fieldFromInstruction(insn, 0, 12);
38252 MI.addOperand(MCOperand::createImm(tmp));
38253 tmp = fieldFromInstruction(insn, 14, 1);
38254 MI.addOperand(MCOperand::createImm(tmp));
38255 tmp = fieldFromInstruction(insn, 54, 1);
38256 MI.addOperand(MCOperand::createImm(tmp));
38257 tmp = fieldFromInstruction(insn, 55, 1);
38258 MI.addOperand(MCOperand::createImm(tmp));
38261 tmp = fieldFromInstruction(insn, 40, 8);
38262 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38263 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38264 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38265 tmp = fieldFromInstruction(insn, 56, 8);
38266 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38267 tmp = fieldFromInstruction(insn, 0, 12);
38268 MI.addOperand(MCOperand::createImm(tmp));
38269 tmp = fieldFromInstruction(insn, 14, 1);
38270 MI.addOperand(MCOperand::createImm(tmp));
38271 tmp = fieldFromInstruction(insn, 54, 1);
38272 MI.addOperand(MCOperand::createImm(tmp));
38275 tmp = fieldFromInstruction(insn, 40, 8);
38276 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38277 tmp = fieldFromInstruction(insn, 32, 8);
38278 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38279 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38280 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38281 tmp = fieldFromInstruction(insn, 56, 8);
38282 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38283 tmp = fieldFromInstruction(insn, 0, 12);
38284 MI.addOperand(MCOperand::createImm(tmp));
38285 tmp = fieldFromInstruction(insn, 14, 1);
38286 MI.addOperand(MCOperand::createImm(tmp));
38287 tmp = fieldFromInstruction(insn, 54, 1);
38288 MI.addOperand(MCOperand::createImm(tmp));
38291 tmp = fieldFromInstruction(insn, 40, 8);
38292 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38293 tmp = fieldFromInstruction(insn, 32, 8);
38294 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38295 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38296 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38297 tmp = fieldFromInstruction(insn, 56, 8);
38298 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38299 tmp = fieldFromInstruction(insn, 0, 12);
38300 MI.addOperand(MCOperand::createImm(tmp));
38301 tmp = fieldFromInstruction(insn, 14, 1);
38302 MI.addOperand(MCOperand::createImm(tmp));
38303 tmp = fieldFromInstruction(insn, 54, 1);
38304 MI.addOperand(MCOperand::createImm(tmp));
38305 tmp = fieldFromInstruction(insn, 55, 1);
38306 MI.addOperand(MCOperand::createImm(tmp));
38309 tmp = fieldFromInstruction(insn, 40, 8);
38310 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38311 tmp = fieldFromInstruction(insn, 32, 8);
38312 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38313 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38314 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38315 tmp = fieldFromInstruction(insn, 56, 8);
38316 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38317 tmp = fieldFromInstruction(insn, 0, 12);
38318 MI.addOperand(MCOperand::createImm(tmp));
38319 tmp = fieldFromInstruction(insn, 14, 1);
38320 MI.addOperand(MCOperand::createImm(tmp));
38321 tmp = fieldFromInstruction(insn, 54, 1);
38322 MI.addOperand(MCOperand::createImm(tmp));
38325 tmp = fieldFromInstruction(insn, 40, 8);
38326 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38327 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38328 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38329 tmp = fieldFromInstruction(insn, 56, 8);
38330 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38331 tmp = fieldFromInstruction(insn, 0, 12);
38332 MI.addOperand(MCOperand::createImm(tmp));
38333 tmp = fieldFromInstruction(insn, 14, 1);
38334 MI.addOperand(MCOperand::createImm(tmp));
38335 tmp = fieldFromInstruction(insn, 54, 1);
38336 MI.addOperand(MCOperand::createImm(tmp));
38337 tmp = fieldFromInstruction(insn, 55, 1);
38338 MI.addOperand(MCOperand::createImm(tmp));
38341 tmp = fieldFromInstruction(insn, 40, 8);
38342 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38343 tmp = fieldFromInstruction(insn, 32, 8);
38344 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38345 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38346 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38347 tmp = fieldFromInstruction(insn, 56, 8);
38348 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38349 tmp = fieldFromInstruction(insn, 0, 12);
38350 MI.addOperand(MCOperand::createImm(tmp));
38351 tmp = fieldFromInstruction(insn, 14, 1);
38352 MI.addOperand(MCOperand::createImm(tmp));
38353 tmp = fieldFromInstruction(insn, 54, 1);
38354 MI.addOperand(MCOperand::createImm(tmp));
38355 tmp = fieldFromInstruction(insn, 55, 1);
38356 MI.addOperand(MCOperand::createImm(tmp));
38359 tmp = fieldFromInstruction(insn, 40, 8);
38360 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38361 tmp = fieldFromInstruction(insn, 32, 8);
38362 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38363 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38364 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38365 tmp = fieldFromInstruction(insn, 56, 8);
38366 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38367 tmp = fieldFromInstruction(insn, 0, 12);
38368 MI.addOperand(MCOperand::createImm(tmp));
38369 tmp = fieldFromInstruction(insn, 14, 1);
38370 MI.addOperand(MCOperand::createImm(tmp));
38371 tmp = fieldFromInstruction(insn, 54, 1);
38372 MI.addOperand(MCOperand::createImm(tmp));
38373 tmp = fieldFromInstruction(insn, 55, 1);
38374 MI.addOperand(MCOperand::createImm(tmp));
38377 tmp = fieldFromInstruction(insn, 40, 8);
38378 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38379 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38380 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38381 tmp = fieldFromInstruction(insn, 56, 8);
38382 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38383 tmp = fieldFromInstruction(insn, 0, 12);
38384 MI.addOperand(MCOperand::createImm(tmp));
38385 tmp = fieldFromInstruction(insn, 14, 1);
38386 MI.addOperand(MCOperand::createImm(tmp));
38387 tmp = fieldFromInstruction(insn, 54, 1);
38388 MI.addOperand(MCOperand::createImm(tmp));
38389 tmp = fieldFromInstruction(insn, 55, 1);
38390 MI.addOperand(MCOperand::createImm(tmp));
38393 tmp = fieldFromInstruction(insn, 40, 8);
38394 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38395 tmp = fieldFromInstruction(insn, 32, 8);
38396 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38397 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38398 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38399 tmp = fieldFromInstruction(insn, 56, 8);
38400 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38401 tmp = fieldFromInstruction(insn, 0, 12);
38402 MI.addOperand(MCOperand::createImm(tmp));
38403 tmp = fieldFromInstruction(insn, 14, 1);
38404 MI.addOperand(MCOperand::createImm(tmp));
38405 tmp = fieldFromInstruction(insn, 54, 1);
38406 MI.addOperand(MCOperand::createImm(tmp));
38407 tmp = fieldFromInstruction(insn, 55, 1);
38408 MI.addOperand(MCOperand::createImm(tmp));
38411 tmp = fieldFromInstruction(insn, 40, 8);
38412 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38413 tmp = fieldFromInstruction(insn, 32, 8);
38414 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38415 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38416 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38417 tmp = fieldFromInstruction(insn, 56, 8);
38418 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38419 tmp = fieldFromInstruction(insn, 0, 12);
38420 MI.addOperand(MCOperand::createImm(tmp));
38421 tmp = fieldFromInstruction(insn, 14, 1);
38422 MI.addOperand(MCOperand::createImm(tmp));
38423 tmp = fieldFromInstruction(insn, 54, 1);
38424 MI.addOperand(MCOperand::createImm(tmp));
38425 tmp = fieldFromInstruction(insn, 55, 1);
38426 MI.addOperand(MCOperand::createImm(tmp));
38429 tmp = fieldFromInstruction(insn, 40, 8);
38430 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38431 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38432 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38433 tmp = fieldFromInstruction(insn, 56, 8);
38434 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38435 tmp = fieldFromInstruction(insn, 0, 12);
38436 MI.addOperand(MCOperand::createImm(tmp));
38437 tmp = fieldFromInstruction(insn, 14, 1);
38438 MI.addOperand(MCOperand::createImm(tmp));
38439 tmp = fieldFromInstruction(insn, 54, 1);
38440 MI.addOperand(MCOperand::createImm(tmp));
38441 tmp = fieldFromInstruction(insn, 55, 1);
38442 MI.addOperand(MCOperand::createImm(tmp));
38445 tmp = fieldFromInstruction(insn, 40, 8);
38446 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38447 tmp = fieldFromInstruction(insn, 32, 8);
38448 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38449 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38450 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38451 tmp = fieldFromInstruction(insn, 56, 8);
38452 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38453 tmp = fieldFromInstruction(insn, 0, 12);
38454 MI.addOperand(MCOperand::createImm(tmp));
38455 tmp = fieldFromInstruction(insn, 14, 1);
38456 MI.addOperand(MCOperand::createImm(tmp));
38457 tmp = fieldFromInstruction(insn, 54, 1);
38458 MI.addOperand(MCOperand::createImm(tmp));
38459 tmp = fieldFromInstruction(insn, 55, 1);
38460 MI.addOperand(MCOperand::createImm(tmp));
38463 tmp = fieldFromInstruction(insn, 40, 8);
38464 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38465 tmp = fieldFromInstruction(insn, 32, 8);
38466 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38467 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38468 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38469 tmp = fieldFromInstruction(insn, 56, 8);
38470 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38471 tmp = fieldFromInstruction(insn, 0, 12);
38472 MI.addOperand(MCOperand::createImm(tmp));
38473 tmp = fieldFromInstruction(insn, 14, 1);
38474 MI.addOperand(MCOperand::createImm(tmp));
38475 tmp = fieldFromInstruction(insn, 54, 1);
38476 MI.addOperand(MCOperand::createImm(tmp));
38477 tmp = fieldFromInstruction(insn, 55, 1);
38478 MI.addOperand(MCOperand::createImm(tmp));
38481 tmp = fieldFromInstruction(insn, 40, 8);
38482 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38483 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38484 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38485 tmp = fieldFromInstruction(insn, 56, 8);
38486 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38487 tmp = fieldFromInstruction(insn, 0, 12);
38488 MI.addOperand(MCOperand::createImm(tmp));
38489 tmp = fieldFromInstruction(insn, 19, 7);
38490 MI.addOperand(MCOperand::createImm(tmp));
38491 tmp = fieldFromInstruction(insn, 14, 1);
38492 MI.addOperand(MCOperand::createImm(tmp));
38493 tmp = fieldFromInstruction(insn, 54, 1);
38494 MI.addOperand(MCOperand::createImm(tmp));
38495 tmp = fieldFromInstruction(insn, 55, 1);
38496 MI.addOperand(MCOperand::createImm(tmp));
38499 tmp = fieldFromInstruction(insn, 40, 8);
38500 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38501 tmp = fieldFromInstruction(insn, 32, 8);
38502 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38503 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38504 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38505 tmp = fieldFromInstruction(insn, 56, 8);
38506 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38507 tmp = fieldFromInstruction(insn, 0, 12);
38508 MI.addOperand(MCOperand::createImm(tmp));
38509 tmp = fieldFromInstruction(insn, 19, 7);
38510 MI.addOperand(MCOperand::createImm(tmp));
38511 tmp = fieldFromInstruction(insn, 14, 1);
38512 MI.addOperand(MCOperand::createImm(tmp));
38513 tmp = fieldFromInstruction(insn, 54, 1);
38514 MI.addOperand(MCOperand::createImm(tmp));
38515 tmp = fieldFromInstruction(insn, 55, 1);
38516 MI.addOperand(MCOperand::createImm(tmp));
38519 tmp = fieldFromInstruction(insn, 40, 8);
38520 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38521 tmp = fieldFromInstruction(insn, 32, 8);
38522 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38523 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38524 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38525 tmp = fieldFromInstruction(insn, 56, 8);
38526 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38527 tmp = fieldFromInstruction(insn, 0, 12);
38528 MI.addOperand(MCOperand::createImm(tmp));
38529 tmp = fieldFromInstruction(insn, 19, 7);
38530 MI.addOperand(MCOperand::createImm(tmp));
38531 tmp = fieldFromInstruction(insn, 14, 1);
38532 MI.addOperand(MCOperand::createImm(tmp));
38533 tmp = fieldFromInstruction(insn, 54, 1);
38534 MI.addOperand(MCOperand::createImm(tmp));
38535 tmp = fieldFromInstruction(insn, 55, 1);
38536 MI.addOperand(MCOperand::createImm(tmp));
38539 tmp = fieldFromInstruction(insn, 40, 8);
38540 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38541 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38542 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38543 tmp = fieldFromInstruction(insn, 56, 8);
38544 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38545 tmp = fieldFromInstruction(insn, 0, 12);
38546 MI.addOperand(MCOperand::createImm(tmp));
38547 tmp = fieldFromInstruction(insn, 19, 7);
38548 MI.addOperand(MCOperand::createImm(tmp));
38549 tmp = fieldFromInstruction(insn, 14, 1);
38550 MI.addOperand(MCOperand::createImm(tmp));
38551 tmp = fieldFromInstruction(insn, 54, 1);
38552 MI.addOperand(MCOperand::createImm(tmp));
38553 tmp = fieldFromInstruction(insn, 55, 1);
38554 MI.addOperand(MCOperand::createImm(tmp));
38557 tmp = fieldFromInstruction(insn, 40, 8);
38558 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38559 tmp = fieldFromInstruction(insn, 32, 8);
38560 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38561 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38562 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38563 tmp = fieldFromInstruction(insn, 56, 8);
38564 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38565 tmp = fieldFromInstruction(insn, 0, 12);
38566 MI.addOperand(MCOperand::createImm(tmp));
38567 tmp = fieldFromInstruction(insn, 19, 7);
38568 MI.addOperand(MCOperand::createImm(tmp));
38569 tmp = fieldFromInstruction(insn, 14, 1);
38570 MI.addOperand(MCOperand::createImm(tmp));
38571 tmp = fieldFromInstruction(insn, 54, 1);
38572 MI.addOperand(MCOperand::createImm(tmp));
38573 tmp = fieldFromInstruction(insn, 55, 1);
38574 MI.addOperand(MCOperand::createImm(tmp));
38577 tmp = fieldFromInstruction(insn, 40, 8);
38578 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38579 tmp = fieldFromInstruction(insn, 32, 8);
38580 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38581 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38582 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38583 tmp = fieldFromInstruction(insn, 56, 8);
38584 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38585 tmp = fieldFromInstruction(insn, 0, 12);
38586 MI.addOperand(MCOperand::createImm(tmp));
38587 tmp = fieldFromInstruction(insn, 19, 7);
38588 MI.addOperand(MCOperand::createImm(tmp));
38589 tmp = fieldFromInstruction(insn, 14, 1);
38590 MI.addOperand(MCOperand::createImm(tmp));
38591 tmp = fieldFromInstruction(insn, 54, 1);
38592 MI.addOperand(MCOperand::createImm(tmp));
38593 tmp = fieldFromInstruction(insn, 55, 1);
38594 MI.addOperand(MCOperand::createImm(tmp));
38597 tmp = fieldFromInstruction(insn, 40, 8);
38598 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38599 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38600 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38601 tmp = fieldFromInstruction(insn, 56, 8);
38602 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38603 tmp = fieldFromInstruction(insn, 0, 12);
38604 MI.addOperand(MCOperand::createImm(tmp));
38605 tmp = fieldFromInstruction(insn, 19, 7);
38606 MI.addOperand(MCOperand::createImm(tmp));
38607 tmp = fieldFromInstruction(insn, 14, 1);
38608 MI.addOperand(MCOperand::createImm(tmp));
38609 tmp = fieldFromInstruction(insn, 54, 1);
38610 MI.addOperand(MCOperand::createImm(tmp));
38611 tmp = fieldFromInstruction(insn, 55, 1);
38612 MI.addOperand(MCOperand::createImm(tmp));
38615 tmp = fieldFromInstruction(insn, 40, 8);
38616 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38617 tmp = fieldFromInstruction(insn, 32, 8);
38618 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38619 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38620 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38621 tmp = fieldFromInstruction(insn, 56, 8);
38622 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38623 tmp = fieldFromInstruction(insn, 0, 12);
38624 MI.addOperand(MCOperand::createImm(tmp));
38625 tmp = fieldFromInstruction(insn, 19, 7);
38626 MI.addOperand(MCOperand::createImm(tmp));
38627 tmp = fieldFromInstruction(insn, 14, 1);
38628 MI.addOperand(MCOperand::createImm(tmp));
38629 tmp = fieldFromInstruction(insn, 54, 1);
38630 MI.addOperand(MCOperand::createImm(tmp));
38631 tmp = fieldFromInstruction(insn, 55, 1);
38632 MI.addOperand(MCOperand::createImm(tmp));
38635 tmp = fieldFromInstruction(insn, 40, 8);
38636 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38637 tmp = fieldFromInstruction(insn, 32, 8);
38638 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38639 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38640 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38641 tmp = fieldFromInstruction(insn, 56, 8);
38642 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38643 tmp = fieldFromInstruction(insn, 0, 12);
38644 MI.addOperand(MCOperand::createImm(tmp));
38645 tmp = fieldFromInstruction(insn, 19, 7);
38646 MI.addOperand(MCOperand::createImm(tmp));
38647 tmp = fieldFromInstruction(insn, 14, 1);
38648 MI.addOperand(MCOperand::createImm(tmp));
38649 tmp = fieldFromInstruction(insn, 54, 1);
38650 MI.addOperand(MCOperand::createImm(tmp));
38651 tmp = fieldFromInstruction(insn, 55, 1);
38652 MI.addOperand(MCOperand::createImm(tmp));
38655 tmp = fieldFromInstruction(insn, 40, 8);
38656 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38657 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38658 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38659 tmp = fieldFromInstruction(insn, 56, 8);
38660 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38661 tmp = fieldFromInstruction(insn, 0, 12);
38662 MI.addOperand(MCOperand::createImm(tmp));
38663 tmp = fieldFromInstruction(insn, 19, 7);
38664 MI.addOperand(MCOperand::createImm(tmp));
38665 tmp = fieldFromInstruction(insn, 14, 1);
38666 MI.addOperand(MCOperand::createImm(tmp));
38667 tmp = fieldFromInstruction(insn, 54, 1);
38668 MI.addOperand(MCOperand::createImm(tmp));
38669 tmp = fieldFromInstruction(insn, 55, 1);
38670 MI.addOperand(MCOperand::createImm(tmp));
38673 tmp = fieldFromInstruction(insn, 40, 8);
38674 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38675 tmp = fieldFromInstruction(insn, 32, 8);
38676 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38677 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38678 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38679 tmp = fieldFromInstruction(insn, 56, 8);
38680 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38681 tmp = fieldFromInstruction(insn, 0, 12);
38682 MI.addOperand(MCOperand::createImm(tmp));
38683 tmp = fieldFromInstruction(insn, 19, 7);
38684 MI.addOperand(MCOperand::createImm(tmp));
38685 tmp = fieldFromInstruction(insn, 14, 1);
38686 MI.addOperand(MCOperand::createImm(tmp));
38687 tmp = fieldFromInstruction(insn, 54, 1);
38688 MI.addOperand(MCOperand::createImm(tmp));
38689 tmp = fieldFromInstruction(insn, 55, 1);
38690 MI.addOperand(MCOperand::createImm(tmp));
38693 tmp = fieldFromInstruction(insn, 40, 8);
38694 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38695 tmp = fieldFromInstruction(insn, 32, 8);
38696 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38697 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38698 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38699 tmp = fieldFromInstruction(insn, 56, 8);
38700 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38701 tmp = fieldFromInstruction(insn, 0, 12);
38702 MI.addOperand(MCOperand::createImm(tmp));
38703 tmp = fieldFromInstruction(insn, 19, 7);
38704 MI.addOperand(MCOperand::createImm(tmp));
38705 tmp = fieldFromInstruction(insn, 14, 1);
38706 MI.addOperand(MCOperand::createImm(tmp));
38707 tmp = fieldFromInstruction(insn, 54, 1);
38708 MI.addOperand(MCOperand::createImm(tmp));
38709 tmp = fieldFromInstruction(insn, 55, 1);
38710 MI.addOperand(MCOperand::createImm(tmp));
38713 tmp = fieldFromInstruction(insn, 40, 8);
38714 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38715 tmp = fieldFromInstruction(insn, 40, 8);
38716 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38717 tmp = fieldFromInstruction(insn, 32, 8);
38718 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38719 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38720 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38721 tmp = fieldFromInstruction(insn, 8, 4);
38722 MI.addOperand(MCOperand::createImm(tmp));
38723 tmp = fieldFromInstruction(insn, 12, 1);
38724 MI.addOperand(MCOperand::createImm(tmp));
38725 tmp = fieldFromInstruction(insn, 13, 1);
38726 MI.addOperand(MCOperand::createImm(tmp));
38727 tmp = fieldFromInstruction(insn, 25, 1);
38728 MI.addOperand(MCOperand::createImm(tmp));
38729 tmp = fieldFromInstruction(insn, 15, 1);
38730 MI.addOperand(MCOperand::createImm(tmp));
38731 tmp = fieldFromInstruction(insn, 16, 1);
38732 MI.addOperand(MCOperand::createImm(tmp));
38733 tmp = fieldFromInstruction(insn, 17, 1);
38734 MI.addOperand(MCOperand::createImm(tmp));
38735 tmp = fieldFromInstruction(insn, 14, 1);
38736 MI.addOperand(MCOperand::createImm(tmp));
38739 tmp = fieldFromInstruction(insn, 40, 8);
38740 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38741 tmp = fieldFromInstruction(insn, 40, 8);
38742 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38743 tmp = fieldFromInstruction(insn, 32, 8);
38744 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38745 tmp = fieldFromInstruction(insn, 48, 5) << 2;
38746 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38747 tmp = fieldFromInstruction(insn, 8, 4);
38748 MI.addOperand(MCOperand::createImm(tmp));
38749 tmp = fieldFromInstruction(insn, 12, 1);
38750 MI.addOperand(MCOperand::createImm(tmp));
38751 tmp = fieldFromInstruction(insn, 13, 1);
38752 MI.addOperand(MCOperand::createImm(tmp));
38753 tmp = fieldFromInstruction(insn, 25, 1);
38754 MI.addOperand(MCOperand::createImm(tmp));
38755 tmp = fieldFromInstruction(insn, 15, 1);
38756 MI.addOperand(MCOperand::createImm(tmp));
38757 tmp = fieldFromInstruction(insn, 16, 1);
38758 MI.addOperand(MCOperand::createImm(tmp));
38759 tmp = fieldFromInstruction(insn, 17, 1);
38760 MI.addOperand(MCOperand::createImm(tmp));
38761 tmp = fieldFromInstruction(insn, 14, 1);
38762 MI.addOperand(MCOperand::createImm(tmp));
38765 tmp = fieldFromInstruction(insn, 15, 7);
38766 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38767 tmp = fieldFromInstruction(insn, 9, 6) << 1;
38768 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38769 tmp = fieldFromInstruction(insn, 32, 32);
38770 MI.addOperand(MCOperand::createImm(tmp));
38773 tmp = fieldFromInstruction(insn, 15, 7);
38774 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38775 tmp = fieldFromInstruction(insn, 9, 6) << 1;
38776 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38777 tmp = fieldFromInstruction(insn, 32, 32);
38778 MI.addOperand(MCOperand::createImm(tmp));
38781 tmp = fieldFromInstruction(insn, 56, 8);
38782 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38783 tmp = fieldFromInstruction(insn, 32, 8);
38784 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38785 tmp = fieldFromInstruction(insn, 0, 13);
38786 MI.addOperand(MCOperand::createImm(tmp));
38787 tmp = fieldFromInstruction(insn, 16, 1);
38788 MI.addOperand(MCOperand::createImm(tmp));
38789 tmp = fieldFromInstruction(insn, 17, 1);
38790 MI.addOperand(MCOperand::createImm(tmp));
38793 tmp = fieldFromInstruction(insn, 56, 8);
38794 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38795 tmp = fieldFromInstruction(insn, 32, 8);
38796 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38797 tmp = fieldFromInstruction(insn, 0, 13);
38798 MI.addOperand(MCOperand::createImm(tmp));
38799 tmp = fieldFromInstruction(insn, 16, 1);
38800 MI.addOperand(MCOperand::createImm(tmp));
38801 tmp = fieldFromInstruction(insn, 17, 1);
38802 MI.addOperand(MCOperand::createImm(tmp));
38805 tmp = fieldFromInstruction(insn, 56, 8);
38806 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38807 tmp = fieldFromInstruction(insn, 32, 8);
38808 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38809 tmp = fieldFromInstruction(insn, 0, 13);
38810 MI.addOperand(MCOperand::createImm(tmp));
38811 tmp = fieldFromInstruction(insn, 16, 1);
38812 MI.addOperand(MCOperand::createImm(tmp));
38813 tmp = fieldFromInstruction(insn, 17, 1);
38814 MI.addOperand(MCOperand::createImm(tmp));
38817 tmp = fieldFromInstruction(insn, 56, 8);
38818 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38819 tmp = fieldFromInstruction(insn, 32, 8);
38820 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38821 tmp = fieldFromInstruction(insn, 0, 13);
38822 MI.addOperand(MCOperand::createImm(tmp));
38823 tmp = fieldFromInstruction(insn, 16, 1);
38824 MI.addOperand(MCOperand::createImm(tmp));
38825 tmp = fieldFromInstruction(insn, 17, 1);
38826 MI.addOperand(MCOperand::createImm(tmp));
38829 tmp = fieldFromInstruction(insn, 15, 7);
38830 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38831 tmp = fieldFromInstruction(insn, 9, 6) << 1;
38832 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38833 tmp = fieldFromInstruction(insn, 32, 32);
38834 MI.addOperand(MCOperand::createImm(tmp));
38837 tmp = fieldFromInstruction(insn, 15, 7);
38838 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38839 tmp = fieldFromInstruction(insn, 9, 6) << 1;
38840 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38841 tmp = fieldFromInstruction(insn, 32, 32);
38842 MI.addOperand(MCOperand::createImm(tmp));
38845 tmp = fieldFromInstruction(insn, 32, 8);
38846 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38847 tmp = fieldFromInstruction(insn, 40, 8);
38848 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38849 tmp = fieldFromInstruction(insn, 0, 13);
38850 MI.addOperand(MCOperand::createImm(tmp));
38851 tmp = fieldFromInstruction(insn, 16, 1);
38852 MI.addOperand(MCOperand::createImm(tmp));
38853 tmp = fieldFromInstruction(insn, 17, 1);
38854 MI.addOperand(MCOperand::createImm(tmp));
38857 tmp = fieldFromInstruction(insn, 32, 8);
38858 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38859 tmp = fieldFromInstruction(insn, 40, 8);
38860 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38861 tmp = fieldFromInstruction(insn, 0, 13);
38862 MI.addOperand(MCOperand::createImm(tmp));
38863 tmp = fieldFromInstruction(insn, 16, 1);
38864 MI.addOperand(MCOperand::createImm(tmp));
38865 tmp = fieldFromInstruction(insn, 17, 1);
38866 MI.addOperand(MCOperand::createImm(tmp));
38869 tmp = fieldFromInstruction(insn, 32, 8);
38870 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38871 tmp = fieldFromInstruction(insn, 40, 8);
38872 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38873 tmp = fieldFromInstruction(insn, 0, 13);
38874 MI.addOperand(MCOperand::createImm(tmp));
38875 tmp = fieldFromInstruction(insn, 16, 1);
38876 MI.addOperand(MCOperand::createImm(tmp));
38877 tmp = fieldFromInstruction(insn, 17, 1);
38878 MI.addOperand(MCOperand::createImm(tmp));
38881 tmp = fieldFromInstruction(insn, 32, 8);
38882 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38883 tmp = fieldFromInstruction(insn, 40, 8);
38884 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38885 tmp = fieldFromInstruction(insn, 0, 13);
38886 MI.addOperand(MCOperand::createImm(tmp));
38887 tmp = fieldFromInstruction(insn, 16, 1);
38888 MI.addOperand(MCOperand::createImm(tmp));
38889 tmp = fieldFromInstruction(insn, 17, 1);
38890 MI.addOperand(MCOperand::createImm(tmp));
38893 tmp = fieldFromInstruction(insn, 15, 7);
38894 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38895 tmp = fieldFromInstruction(insn, 9, 6) << 1;
38896 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38897 tmp = fieldFromInstruction(insn, 32, 32);
38898 MI.addOperand(MCOperand::createImm(tmp));
38901 tmp = fieldFromInstruction(insn, 15, 7);
38902 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38903 tmp = fieldFromInstruction(insn, 9, 6) << 1;
38904 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38905 tmp = fieldFromInstruction(insn, 32, 32);
38906 MI.addOperand(MCOperand::createImm(tmp));
38909 tmp = fieldFromInstruction(insn, 15, 7);
38910 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38911 tmp = fieldFromInstruction(insn, 9, 6) << 1;
38912 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38913 tmp = fieldFromInstruction(insn, 32, 32);
38914 MI.addOperand(MCOperand::createImm(tmp));
38917 tmp = fieldFromInstruction(insn, 15, 7);
38918 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38919 tmp = fieldFromInstruction(insn, 9, 6) << 1;
38920 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38921 tmp = fieldFromInstruction(insn, 32, 32);
38922 MI.addOperand(MCOperand::createImm(tmp));
38925 tmp = fieldFromInstruction(insn, 0, 8);
38926 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38927 tmp = fieldFromInstruction(insn, 32, 9);
38928 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38929 tmp = fieldFromInstruction(insn, 41, 9);
38930 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38931 tmp = fieldFromInstruction(insn, 50, 9);
38932 if (DecodeVS_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38933 tmp = fieldFromInstruction(insn, 11, 1);
38934 MI.addOperand(MCOperand::createImm(tmp));
38937 tmp = fieldFromInstruction(insn, 0, 8);
38938 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38939 tmp = fieldFromInstruction(insn, 8, 7);
38940 if (decodeBoolReg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38941 tmp = fieldFromInstruction(insn, 32, 9);
38942 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38943 tmp = fieldFromInstruction(insn, 41, 9);
38944 if (decodeOperand_VS_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38945 tmp = fieldFromInstruction(insn, 50, 9);
38946 if (DecodeVS_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38949 tmp = fieldFromInstruction(insn, 32, 8);
38950 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38951 tmp = fieldFromInstruction(insn, 40, 8);
38952 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38953 tmp = fieldFromInstruction(insn, 0, 13);
38954 MI.addOperand(MCOperand::createImm(tmp));
38955 tmp = fieldFromInstruction(insn, 17, 1);
38956 MI.addOperand(MCOperand::createImm(tmp));
38959 tmp = fieldFromInstruction(insn, 56, 8);
38960 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38961 tmp = fieldFromInstruction(insn, 32, 8);
38962 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38963 tmp = fieldFromInstruction(insn, 40, 8);
38964 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38965 tmp = fieldFromInstruction(insn, 0, 13);
38966 MI.addOperand(MCOperand::createImm(tmp));
38967 tmp = fieldFromInstruction(insn, 17, 1);
38968 MI.addOperand(MCOperand::createImm(tmp));
38971 tmp = fieldFromInstruction(insn, 32, 8);
38972 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38973 tmp = fieldFromInstruction(insn, 40, 8);
38974 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38975 tmp = fieldFromInstruction(insn, 0, 13);
38976 MI.addOperand(MCOperand::createImm(tmp));
38977 tmp = fieldFromInstruction(insn, 17, 1);
38978 MI.addOperand(MCOperand::createImm(tmp));
38981 tmp = fieldFromInstruction(insn, 56, 8);
38982 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38983 tmp = fieldFromInstruction(insn, 32, 8);
38984 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38985 tmp = fieldFromInstruction(insn, 40, 8);
38986 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38987 tmp = fieldFromInstruction(insn, 0, 13);
38988 MI.addOperand(MCOperand::createImm(tmp));
38989 tmp = fieldFromInstruction(insn, 17, 1);
38990 MI.addOperand(MCOperand::createImm(tmp));
38993 tmp = fieldFromInstruction(insn, 15, 7);
38994 if (DecodeSReg_512RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38995 tmp = fieldFromInstruction(insn, 9, 6) << 1;
38996 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
38997 tmp = fieldFromInstruction(insn, 32, 32);
38998 MI.addOperand(MCOperand::createImm(tmp));
39001 tmp = fieldFromInstruction(insn, 15, 7);
39002 if (DecodeSReg_512RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39003 tmp = fieldFromInstruction(insn, 9, 6) << 1;
39004 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39005 tmp = fieldFromInstruction(insn, 32, 32);
39006 MI.addOperand(MCOperand::createImm(tmp));
39009 tmp = fieldFromInstruction(insn, 56, 8);
39010 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39011 tmp = fieldFromInstruction(insn, 32, 8);
39012 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39013 tmp = fieldFromInstruction(insn, 40, 8);
39014 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39015 tmp = fieldFromInstruction(insn, 0, 13);
39016 MI.addOperand(MCOperand::createImm(tmp));
39017 tmp = fieldFromInstruction(insn, 17, 1);
39018 MI.addOperand(MCOperand::createImm(tmp));
39021 tmp = fieldFromInstruction(insn, 32, 8);
39022 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39023 tmp = fieldFromInstruction(insn, 40, 8);
39024 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39025 tmp = fieldFromInstruction(insn, 0, 13);
39026 MI.addOperand(MCOperand::createImm(tmp));
39027 tmp = fieldFromInstruction(insn, 17, 1);
39028 MI.addOperand(MCOperand::createImm(tmp));
39031 tmp = fieldFromInstruction(insn, 56, 8);
39032 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39033 tmp = fieldFromInstruction(insn, 32, 8);
39034 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39035 tmp = fieldFromInstruction(insn, 40, 8);
39036 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39037 tmp = fieldFromInstruction(insn, 0, 13);
39038 MI.addOperand(MCOperand::createImm(tmp));
39039 tmp = fieldFromInstruction(insn, 17, 1);
39040 MI.addOperand(MCOperand::createImm(tmp));
39043 tmp = fieldFromInstruction(insn, 17, 8);
39044 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39045 tmp = fieldFromInstruction(insn, 0, 9);
39046 if (decodeOperand_VSrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39047 tmp = fieldFromInstruction(insn, 9, 8);
39048 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39051 tmp = fieldFromInstruction(insn, 0, 8);
39052 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39055 tmp = fieldFromInstruction(insn, 6, 7);
39056 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39057 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39058 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39059 tmp = fieldFromInstruction(insn, 32, 20);
39060 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39061 tmp = fieldFromInstruction(insn, 16, 1);
39062 MI.addOperand(MCOperand::createImm(tmp));
39065 tmp = fieldFromInstruction(insn, 6, 7);
39066 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39067 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39068 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39069 tmp = fieldFromInstruction(insn, 32, 20);
39070 MI.addOperand(MCOperand::createImm(tmp));
39071 tmp = fieldFromInstruction(insn, 16, 1);
39072 MI.addOperand(MCOperand::createImm(tmp));
39075 tmp = fieldFromInstruction(insn, 6, 7);
39076 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39077 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39078 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39079 tmp = fieldFromInstruction(insn, 32, 20);
39080 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39081 tmp = fieldFromInstruction(insn, 16, 1);
39082 MI.addOperand(MCOperand::createImm(tmp));
39085 tmp = fieldFromInstruction(insn, 6, 7);
39086 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39087 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39088 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39089 tmp = fieldFromInstruction(insn, 32, 20);
39090 MI.addOperand(MCOperand::createImm(tmp));
39091 tmp = fieldFromInstruction(insn, 16, 1);
39092 MI.addOperand(MCOperand::createImm(tmp));
39095 tmp = fieldFromInstruction(insn, 6, 7);
39096 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39097 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39098 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39099 tmp = fieldFromInstruction(insn, 32, 20);
39100 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39101 tmp = fieldFromInstruction(insn, 16, 1);
39102 MI.addOperand(MCOperand::createImm(tmp));
39105 tmp = fieldFromInstruction(insn, 6, 7);
39106 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39107 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39108 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39109 tmp = fieldFromInstruction(insn, 32, 20);
39110 MI.addOperand(MCOperand::createImm(tmp));
39111 tmp = fieldFromInstruction(insn, 16, 1);
39112 MI.addOperand(MCOperand::createImm(tmp));
39115 tmp = fieldFromInstruction(insn, 6, 7);
39116 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39117 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39118 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39119 tmp = fieldFromInstruction(insn, 32, 20);
39120 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39121 tmp = fieldFromInstruction(insn, 16, 1);
39122 MI.addOperand(MCOperand::createImm(tmp));
39125 tmp = fieldFromInstruction(insn, 6, 7);
39126 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39127 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39128 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39129 tmp = fieldFromInstruction(insn, 32, 20);
39130 MI.addOperand(MCOperand::createImm(tmp));
39131 tmp = fieldFromInstruction(insn, 16, 1);
39132 MI.addOperand(MCOperand::createImm(tmp));
39135 tmp = fieldFromInstruction(insn, 6, 7);
39136 if (DecodeSReg_512RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39137 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39138 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39139 tmp = fieldFromInstruction(insn, 32, 20);
39140 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39141 tmp = fieldFromInstruction(insn, 16, 1);
39142 MI.addOperand(MCOperand::createImm(tmp));
39145 tmp = fieldFromInstruction(insn, 6, 7);
39146 if (DecodeSReg_512RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39147 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39148 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39149 tmp = fieldFromInstruction(insn, 32, 20);
39150 MI.addOperand(MCOperand::createImm(tmp));
39151 tmp = fieldFromInstruction(insn, 16, 1);
39152 MI.addOperand(MCOperand::createImm(tmp));
39155 tmp = fieldFromInstruction(insn, 6, 7);
39156 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39157 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39158 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39159 tmp = fieldFromInstruction(insn, 32, 20);
39160 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39161 tmp = fieldFromInstruction(insn, 16, 1);
39162 MI.addOperand(MCOperand::createImm(tmp));
39165 tmp = fieldFromInstruction(insn, 6, 7);
39166 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39167 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39168 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39169 tmp = fieldFromInstruction(insn, 32, 20);
39170 MI.addOperand(MCOperand::createImm(tmp));
39171 tmp = fieldFromInstruction(insn, 16, 1);
39172 MI.addOperand(MCOperand::createImm(tmp));
39175 tmp = fieldFromInstruction(insn, 6, 7);
39176 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39177 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39178 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39179 tmp = fieldFromInstruction(insn, 32, 20);
39180 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39181 tmp = fieldFromInstruction(insn, 16, 1);
39182 MI.addOperand(MCOperand::createImm(tmp));
39185 tmp = fieldFromInstruction(insn, 6, 7);
39186 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39187 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39188 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39189 tmp = fieldFromInstruction(insn, 32, 20);
39190 MI.addOperand(MCOperand::createImm(tmp));
39191 tmp = fieldFromInstruction(insn, 16, 1);
39192 MI.addOperand(MCOperand::createImm(tmp));
39195 tmp = fieldFromInstruction(insn, 6, 7);
39196 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39197 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39198 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39199 tmp = fieldFromInstruction(insn, 32, 20);
39200 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39201 tmp = fieldFromInstruction(insn, 16, 1);
39202 MI.addOperand(MCOperand::createImm(tmp));
39205 tmp = fieldFromInstruction(insn, 6, 7);
39206 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39207 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39208 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39209 tmp = fieldFromInstruction(insn, 32, 20);
39210 MI.addOperand(MCOperand::createImm(tmp));
39211 tmp = fieldFromInstruction(insn, 16, 1);
39212 MI.addOperand(MCOperand::createImm(tmp));
39215 tmp = fieldFromInstruction(insn, 6, 7);
39216 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39217 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39218 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39219 tmp = fieldFromInstruction(insn, 32, 20);
39220 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39221 tmp = fieldFromInstruction(insn, 16, 1);
39222 MI.addOperand(MCOperand::createImm(tmp));
39225 tmp = fieldFromInstruction(insn, 6, 7);
39226 if (DecodeSReg_256RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39227 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39228 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39229 tmp = fieldFromInstruction(insn, 32, 20);
39230 MI.addOperand(MCOperand::createImm(tmp));
39231 tmp = fieldFromInstruction(insn, 16, 1);
39232 MI.addOperand(MCOperand::createImm(tmp));
39235 tmp = fieldFromInstruction(insn, 6, 7);
39236 if (DecodeSReg_512RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39237 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39238 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39239 tmp = fieldFromInstruction(insn, 32, 20);
39240 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39241 tmp = fieldFromInstruction(insn, 16, 1);
39242 MI.addOperand(MCOperand::createImm(tmp));
39245 tmp = fieldFromInstruction(insn, 6, 7);
39246 if (DecodeSReg_512RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39247 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39248 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39249 tmp = fieldFromInstruction(insn, 32, 20);
39250 MI.addOperand(MCOperand::createImm(tmp));
39251 tmp = fieldFromInstruction(insn, 16, 1);
39252 MI.addOperand(MCOperand::createImm(tmp));
39255 tmp = fieldFromInstruction(insn, 6, 7);
39256 MI.addOperand(MCOperand::createImm(tmp));
39257 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39258 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39259 tmp = fieldFromInstruction(insn, 32, 20);
39260 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39263 tmp = fieldFromInstruction(insn, 6, 7);
39264 MI.addOperand(MCOperand::createImm(tmp));
39265 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39266 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39267 tmp = fieldFromInstruction(insn, 32, 20);
39268 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39271 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39272 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39273 tmp = fieldFromInstruction(insn, 32, 20);
39274 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39277 tmp = fieldFromInstruction(insn, 6, 7);
39278 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39279 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39280 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39281 tmp = fieldFromInstruction(insn, 32, 20);
39282 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39285 tmp = fieldFromInstruction(insn, 6, 7);
39286 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39287 tmp = fieldFromInstruction(insn, 6, 7);
39288 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39289 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39290 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39291 tmp = fieldFromInstruction(insn, 32, 20);
39292 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39295 tmp = fieldFromInstruction(insn, 6, 7);
39296 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39297 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39298 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39299 tmp = fieldFromInstruction(insn, 32, 20);
39300 MI.addOperand(MCOperand::createImm(tmp));
39303 tmp = fieldFromInstruction(insn, 6, 7);
39304 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39305 tmp = fieldFromInstruction(insn, 6, 7);
39306 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39307 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39308 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39309 tmp = fieldFromInstruction(insn, 32, 20);
39310 MI.addOperand(MCOperand::createImm(tmp));
39313 tmp = fieldFromInstruction(insn, 6, 7);
39314 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39315 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39316 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39317 tmp = fieldFromInstruction(insn, 32, 20);
39318 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39321 tmp = fieldFromInstruction(insn, 6, 7);
39322 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39323 tmp = fieldFromInstruction(insn, 6, 7);
39324 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39325 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39326 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39327 tmp = fieldFromInstruction(insn, 32, 20);
39328 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39331 tmp = fieldFromInstruction(insn, 6, 7);
39332 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39333 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39334 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39335 tmp = fieldFromInstruction(insn, 32, 20);
39336 MI.addOperand(MCOperand::createImm(tmp));
39339 tmp = fieldFromInstruction(insn, 6, 7);
39340 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39341 tmp = fieldFromInstruction(insn, 6, 7);
39342 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39343 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39344 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39345 tmp = fieldFromInstruction(insn, 32, 20);
39346 MI.addOperand(MCOperand::createImm(tmp));
39349 tmp = fieldFromInstruction(insn, 6, 7);
39350 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39351 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39352 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39353 tmp = fieldFromInstruction(insn, 32, 20);
39354 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39357 tmp = fieldFromInstruction(insn, 6, 7);
39358 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39359 tmp = fieldFromInstruction(insn, 6, 7);
39360 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39361 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39362 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39363 tmp = fieldFromInstruction(insn, 32, 20);
39364 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39367 tmp = fieldFromInstruction(insn, 6, 7);
39368 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39369 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39370 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39371 tmp = fieldFromInstruction(insn, 32, 20);
39372 MI.addOperand(MCOperand::createImm(tmp));
39375 tmp = fieldFromInstruction(insn, 6, 7);
39376 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39377 tmp = fieldFromInstruction(insn, 6, 7);
39378 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39379 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39380 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39381 tmp = fieldFromInstruction(insn, 32, 20);
39382 MI.addOperand(MCOperand::createImm(tmp));
39385 tmp = fieldFromInstruction(insn, 6, 7);
39386 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39387 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39388 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39389 tmp = fieldFromInstruction(insn, 32, 20);
39390 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39393 tmp = fieldFromInstruction(insn, 6, 7);
39394 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39395 tmp = fieldFromInstruction(insn, 6, 7);
39396 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39397 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39398 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39399 tmp = fieldFromInstruction(insn, 32, 20);
39400 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39403 tmp = fieldFromInstruction(insn, 6, 7);
39404 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39405 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39406 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39407 tmp = fieldFromInstruction(insn, 32, 20);
39408 MI.addOperand(MCOperand::createImm(tmp));
39411 tmp = fieldFromInstruction(insn, 6, 7);
39412 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39413 tmp = fieldFromInstruction(insn, 6, 7);
39414 if (DecodeSReg_32_XM0_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39415 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39416 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39417 tmp = fieldFromInstruction(insn, 32, 20);
39418 MI.addOperand(MCOperand::createImm(tmp));
39421 tmp = fieldFromInstruction(insn, 6, 7);
39422 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39423 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39424 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39425 tmp = fieldFromInstruction(insn, 32, 20);
39426 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39429 tmp = fieldFromInstruction(insn, 6, 7);
39430 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39431 tmp = fieldFromInstruction(insn, 6, 7);
39432 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39433 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39434 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39435 tmp = fieldFromInstruction(insn, 32, 20);
39436 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39439 tmp = fieldFromInstruction(insn, 6, 7);
39440 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39441 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39442 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39443 tmp = fieldFromInstruction(insn, 32, 20);
39444 MI.addOperand(MCOperand::createImm(tmp));
39447 tmp = fieldFromInstruction(insn, 6, 7);
39448 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39449 tmp = fieldFromInstruction(insn, 6, 7);
39450 if (DecodeSReg_64_XEXECRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39451 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39452 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39453 tmp = fieldFromInstruction(insn, 32, 20);
39454 MI.addOperand(MCOperand::createImm(tmp));
39457 tmp = fieldFromInstruction(insn, 6, 7);
39458 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39459 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39460 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39461 tmp = fieldFromInstruction(insn, 32, 20);
39462 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39465 tmp = fieldFromInstruction(insn, 6, 7);
39466 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39467 tmp = fieldFromInstruction(insn, 6, 7);
39468 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39469 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39470 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39471 tmp = fieldFromInstruction(insn, 32, 20);
39472 if (DecodeSReg_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39475 tmp = fieldFromInstruction(insn, 6, 7);
39476 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39477 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39478 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39479 tmp = fieldFromInstruction(insn, 32, 20);
39480 MI.addOperand(MCOperand::createImm(tmp));
39483 tmp = fieldFromInstruction(insn, 6, 7);
39484 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39485 tmp = fieldFromInstruction(insn, 6, 7);
39486 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39487 tmp = fieldFromInstruction(insn, 0, 6) << 1;
39488 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39489 tmp = fieldFromInstruction(insn, 32, 20);
39490 MI.addOperand(MCOperand::createImm(tmp));
39493 tmp = fieldFromInstruction(insn, 0, 8);
39494 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39495 tmp = 0x0;
39496 tmp |= fieldFromInstruction(insn, 8, 1) << 1;
39497 tmp |= fieldFromInstruction(insn, 61, 1) << 0;
39498 MI.addOperand(MCOperand::createImm(tmp));
39499 tmp = fieldFromInstruction(insn, 32, 9);
39500 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39501 tmp = 0x0;
39502 tmp |= fieldFromInstruction(insn, 9, 1) << 1;
39503 tmp |= fieldFromInstruction(insn, 62, 1) << 0;
39504 MI.addOperand(MCOperand::createImm(tmp));
39505 tmp = fieldFromInstruction(insn, 41, 9);
39506 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39507 tmp = 0x0;
39508 tmp |= fieldFromInstruction(insn, 10, 1) << 1;
39509 tmp |= fieldFromInstruction(insn, 63, 1) << 0;
39510 MI.addOperand(MCOperand::createImm(tmp));
39511 tmp = fieldFromInstruction(insn, 50, 9);
39512 if (decodeOperand_VS_16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39513 tmp = fieldFromInstruction(insn, 15, 1);
39514 MI.addOperand(MCOperand::createImm(tmp));
39515 tmp = fieldFromInstruction(insn, 59, 2);
39516 MI.addOperand(MCOperand::createImm(tmp));
39519 tmp = fieldFromInstruction(insn, 0, 8);
39520 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39521 tmp = fieldFromInstruction(insn, 32, 9);
39522 if (decodeOperand_VSrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39523 tmp = fieldFromInstruction(insn, 41, 9);
39524 if (decodeOperand_VSrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39525 tmp = fieldFromInstruction(insn, 50, 9);
39526 if (decodeOperand_VSrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39527 tmp = fieldFromInstruction(insn, 15, 1);
39528 MI.addOperand(MCOperand::createImm(tmp));
39531 tmp = fieldFromInstruction(insn, 0, 8);
39532 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39533 tmp = fieldFromInstruction(insn, 32, 9);
39534 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39535 tmp = fieldFromInstruction(insn, 41, 9);
39536 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39537 tmp = fieldFromInstruction(insn, 0, 8);
39538 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39541 tmp = fieldFromInstruction(insn, 0, 8);
39542 if (DecodeAReg_1024RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39543 tmp = 0x0;
39544 tmp |= fieldFromInstruction(insn, 32, 9) << 0;
39545 tmp |= fieldFromInstruction(insn, 59, 1) << 9;
39546 if (DecodeAV_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39547 tmp = 0x0;
39548 tmp |= fieldFromInstruction(insn, 41, 9) << 0;
39549 tmp |= fieldFromInstruction(insn, 60, 1) << 9;
39550 if (DecodeAV_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39551 tmp = fieldFromInstruction(insn, 50, 9);
39552 if (decodeOperand_AReg_1024(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39553 tmp = fieldFromInstruction(insn, 8, 3);
39554 MI.addOperand(MCOperand::createImm(tmp));
39555 tmp = fieldFromInstruction(insn, 11, 4);
39556 MI.addOperand(MCOperand::createImm(tmp));
39557 tmp = fieldFromInstruction(insn, 61, 3);
39558 MI.addOperand(MCOperand::createImm(tmp));
39561 tmp = fieldFromInstruction(insn, 0, 8);
39562 if (DecodeAReg_512RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39563 tmp = 0x0;
39564 tmp |= fieldFromInstruction(insn, 32, 9) << 0;
39565 tmp |= fieldFromInstruction(insn, 59, 1) << 9;
39566 if (DecodeAV_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39567 tmp = 0x0;
39568 tmp |= fieldFromInstruction(insn, 41, 9) << 0;
39569 tmp |= fieldFromInstruction(insn, 60, 1) << 9;
39570 if (DecodeAV_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39571 tmp = fieldFromInstruction(insn, 50, 9);
39572 if (decodeOperand_AReg_512(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39573 tmp = fieldFromInstruction(insn, 8, 3);
39574 MI.addOperand(MCOperand::createImm(tmp));
39575 tmp = fieldFromInstruction(insn, 11, 4);
39576 MI.addOperand(MCOperand::createImm(tmp));
39577 tmp = fieldFromInstruction(insn, 61, 3);
39578 MI.addOperand(MCOperand::createImm(tmp));
39581 tmp = fieldFromInstruction(insn, 0, 8);
39582 if (DecodeAReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39583 tmp = 0x0;
39584 tmp |= fieldFromInstruction(insn, 32, 9) << 0;
39585 tmp |= fieldFromInstruction(insn, 59, 1) << 9;
39586 if (DecodeAV_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39587 tmp = 0x0;
39588 tmp |= fieldFromInstruction(insn, 41, 9) << 0;
39589 tmp |= fieldFromInstruction(insn, 60, 1) << 9;
39590 if (DecodeAV_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39591 tmp = fieldFromInstruction(insn, 50, 9);
39592 if (decodeOperand_AReg_128(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39593 tmp = fieldFromInstruction(insn, 8, 3);
39594 MI.addOperand(MCOperand::createImm(tmp));
39595 tmp = fieldFromInstruction(insn, 11, 4);
39596 MI.addOperand(MCOperand::createImm(tmp));
39597 tmp = fieldFromInstruction(insn, 61, 3);
39598 MI.addOperand(MCOperand::createImm(tmp));
39601 tmp = fieldFromInstruction(insn, 0, 8);
39602 if (DecodeAReg_1024RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39603 tmp = 0x0;
39604 tmp |= fieldFromInstruction(insn, 32, 9) << 0;
39605 tmp |= fieldFromInstruction(insn, 59, 1) << 9;
39606 if (DecodeAV_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39607 tmp = 0x0;
39608 tmp |= fieldFromInstruction(insn, 41, 9) << 0;
39609 tmp |= fieldFromInstruction(insn, 60, 1) << 9;
39610 if (DecodeAV_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39611 tmp = fieldFromInstruction(insn, 50, 9);
39612 if (decodeOperand_AReg_1024(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39613 tmp = fieldFromInstruction(insn, 8, 3);
39614 MI.addOperand(MCOperand::createImm(tmp));
39615 tmp = fieldFromInstruction(insn, 11, 4);
39616 MI.addOperand(MCOperand::createImm(tmp));
39617 tmp = fieldFromInstruction(insn, 61, 3);
39618 MI.addOperand(MCOperand::createImm(tmp));
39621 tmp = fieldFromInstruction(insn, 0, 8);
39622 if (DecodeAReg_512RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39623 tmp = 0x0;
39624 tmp |= fieldFromInstruction(insn, 32, 9) << 0;
39625 tmp |= fieldFromInstruction(insn, 59, 1) << 9;
39626 if (DecodeAV_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39627 tmp = 0x0;
39628 tmp |= fieldFromInstruction(insn, 41, 9) << 0;
39629 tmp |= fieldFromInstruction(insn, 60, 1) << 9;
39630 if (DecodeAV_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39631 tmp = fieldFromInstruction(insn, 50, 9);
39632 if (decodeOperand_AReg_512(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39633 tmp = fieldFromInstruction(insn, 8, 3);
39634 MI.addOperand(MCOperand::createImm(tmp));
39635 tmp = fieldFromInstruction(insn, 11, 4);
39636 MI.addOperand(MCOperand::createImm(tmp));
39637 tmp = fieldFromInstruction(insn, 61, 3);
39638 MI.addOperand(MCOperand::createImm(tmp));
39641 tmp = fieldFromInstruction(insn, 0, 8);
39642 if (DecodeAReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39643 tmp = 0x0;
39644 tmp |= fieldFromInstruction(insn, 32, 9) << 0;
39645 tmp |= fieldFromInstruction(insn, 59, 1) << 9;
39646 if (DecodeAV_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39647 tmp = 0x0;
39648 tmp |= fieldFromInstruction(insn, 41, 9) << 0;
39649 tmp |= fieldFromInstruction(insn, 60, 1) << 9;
39650 if (DecodeAV_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39651 tmp = fieldFromInstruction(insn, 50, 9);
39652 if (decodeOperand_AReg_128(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39653 tmp = fieldFromInstruction(insn, 8, 3);
39654 MI.addOperand(MCOperand::createImm(tmp));
39655 tmp = fieldFromInstruction(insn, 11, 4);
39656 MI.addOperand(MCOperand::createImm(tmp));
39657 tmp = fieldFromInstruction(insn, 61, 3);
39658 MI.addOperand(MCOperand::createImm(tmp));
39661 tmp = fieldFromInstruction(insn, 0, 8);
39662 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39663 tmp = 0x0;
39664 tmp |= fieldFromInstruction(insn, 32, 9) << 0;
39665 tmp |= fieldFromInstruction(insn, 59, 1) << 9;
39666 if (DecodeAGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39669 tmp = fieldFromInstruction(insn, 0, 8);
39670 if (DecodeAGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39671 tmp = 0x0;
39672 tmp |= fieldFromInstruction(insn, 32, 9) << 0;
39673 tmp |= fieldFromInstruction(insn, 59, 1) << 9;
39674 if (decodeOperand_VGPR_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39677 tmp = fieldFromInstruction(insn, 32, 8);
39678 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39679 tmp = fieldFromInstruction(insn, 40, 8);
39680 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39681 tmp = fieldFromInstruction(insn, 0, 16);
39682 MI.addOperand(MCOperand::createImm(tmp));
39683 tmp = fieldFromInstruction(insn, 16, 1);
39684 MI.addOperand(MCOperand::createImm(tmp));
39687 tmp = fieldFromInstruction(insn, 32, 8);
39688 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39689 tmp = fieldFromInstruction(insn, 40, 8);
39690 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39691 tmp = fieldFromInstruction(insn, 48, 8);
39692 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39693 tmp = fieldFromInstruction(insn, 0, 16);
39694 MI.addOperand(MCOperand::createImm(tmp));
39695 tmp = fieldFromInstruction(insn, 16, 1);
39696 MI.addOperand(MCOperand::createImm(tmp));
39699 tmp = fieldFromInstruction(insn, 32, 8);
39700 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39701 tmp = fieldFromInstruction(insn, 40, 8);
39702 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39703 tmp = fieldFromInstruction(insn, 48, 8);
39704 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39705 tmp = fieldFromInstruction(insn, 0, 8);
39706 MI.addOperand(MCOperand::createImm(tmp));
39707 tmp = fieldFromInstruction(insn, 8, 8);
39708 MI.addOperand(MCOperand::createImm(tmp));
39709 tmp = fieldFromInstruction(insn, 16, 1);
39710 MI.addOperand(MCOperand::createImm(tmp));
39713 tmp = fieldFromInstruction(insn, 40, 8);
39714 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39715 tmp = fieldFromInstruction(insn, 0, 16);
39716 MI.addOperand(MCOperand::createImm(tmp));
39717 tmp = fieldFromInstruction(insn, 16, 1);
39718 MI.addOperand(MCOperand::createImm(tmp));
39721 tmp = fieldFromInstruction(insn, 56, 8);
39722 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39723 tmp = fieldFromInstruction(insn, 32, 8);
39724 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39725 tmp = fieldFromInstruction(insn, 40, 8);
39726 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39727 tmp = fieldFromInstruction(insn, 0, 16);
39728 MI.addOperand(MCOperand::createImm(tmp));
39729 tmp = fieldFromInstruction(insn, 16, 1);
39730 MI.addOperand(MCOperand::createImm(tmp));
39733 tmp = fieldFromInstruction(insn, 56, 8);
39734 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39735 tmp = fieldFromInstruction(insn, 32, 8);
39736 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39737 tmp = fieldFromInstruction(insn, 40, 8);
39738 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39739 tmp = fieldFromInstruction(insn, 48, 8);
39740 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39741 tmp = fieldFromInstruction(insn, 0, 16);
39742 MI.addOperand(MCOperand::createImm(tmp));
39743 tmp = fieldFromInstruction(insn, 16, 1);
39744 MI.addOperand(MCOperand::createImm(tmp));
39747 tmp = fieldFromInstruction(insn, 56, 8);
39748 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39749 tmp = fieldFromInstruction(insn, 32, 8);
39750 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39751 tmp = fieldFromInstruction(insn, 40, 8);
39752 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39753 tmp = fieldFromInstruction(insn, 48, 8);
39754 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39755 tmp = fieldFromInstruction(insn, 0, 8);
39756 MI.addOperand(MCOperand::createImm(tmp));
39757 tmp = fieldFromInstruction(insn, 8, 8);
39758 MI.addOperand(MCOperand::createImm(tmp));
39759 tmp = fieldFromInstruction(insn, 16, 1);
39760 MI.addOperand(MCOperand::createImm(tmp));
39763 tmp = fieldFromInstruction(insn, 56, 8);
39764 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39765 tmp = fieldFromInstruction(insn, 32, 8);
39766 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39767 tmp = fieldFromInstruction(insn, 0, 16);
39768 MI.addOperand(MCOperand::createImm(tmp));
39769 tmp = fieldFromInstruction(insn, 16, 1);
39770 MI.addOperand(MCOperand::createImm(tmp));
39773 tmp = fieldFromInstruction(insn, 56, 8);
39774 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39775 tmp = fieldFromInstruction(insn, 32, 8);
39776 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39777 tmp = fieldFromInstruction(insn, 0, 8);
39778 MI.addOperand(MCOperand::createImm(tmp));
39779 tmp = fieldFromInstruction(insn, 8, 8);
39780 MI.addOperand(MCOperand::createImm(tmp));
39781 tmp = fieldFromInstruction(insn, 16, 1);
39782 MI.addOperand(MCOperand::createImm(tmp));
39785 tmp = fieldFromInstruction(insn, 32, 8);
39786 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39787 tmp = fieldFromInstruction(insn, 40, 8);
39788 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39789 tmp = fieldFromInstruction(insn, 0, 16);
39790 MI.addOperand(MCOperand::createImm(tmp));
39791 tmp = fieldFromInstruction(insn, 16, 1);
39792 MI.addOperand(MCOperand::createImm(tmp));
39795 tmp = fieldFromInstruction(insn, 32, 8);
39796 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39797 tmp = fieldFromInstruction(insn, 40, 8);
39798 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39799 tmp = fieldFromInstruction(insn, 48, 8);
39800 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39801 tmp = fieldFromInstruction(insn, 0, 16);
39802 MI.addOperand(MCOperand::createImm(tmp));
39803 tmp = fieldFromInstruction(insn, 16, 1);
39804 MI.addOperand(MCOperand::createImm(tmp));
39807 tmp = fieldFromInstruction(insn, 32, 8);
39808 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39809 tmp = fieldFromInstruction(insn, 40, 8);
39810 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39811 tmp = fieldFromInstruction(insn, 48, 8);
39812 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39813 tmp = fieldFromInstruction(insn, 0, 8);
39814 MI.addOperand(MCOperand::createImm(tmp));
39815 tmp = fieldFromInstruction(insn, 8, 8);
39816 MI.addOperand(MCOperand::createImm(tmp));
39817 tmp = fieldFromInstruction(insn, 16, 1);
39818 MI.addOperand(MCOperand::createImm(tmp));
39821 tmp = fieldFromInstruction(insn, 56, 8);
39822 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39823 tmp = fieldFromInstruction(insn, 32, 8);
39824 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39825 tmp = fieldFromInstruction(insn, 40, 8);
39826 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39827 tmp = fieldFromInstruction(insn, 0, 16);
39828 MI.addOperand(MCOperand::createImm(tmp));
39829 tmp = fieldFromInstruction(insn, 16, 1);
39830 MI.addOperand(MCOperand::createImm(tmp));
39833 tmp = fieldFromInstruction(insn, 56, 8);
39834 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39835 tmp = fieldFromInstruction(insn, 32, 8);
39836 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39837 tmp = fieldFromInstruction(insn, 40, 8);
39838 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39839 tmp = fieldFromInstruction(insn, 48, 8);
39840 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39841 tmp = fieldFromInstruction(insn, 0, 16);
39842 MI.addOperand(MCOperand::createImm(tmp));
39843 tmp = fieldFromInstruction(insn, 16, 1);
39844 MI.addOperand(MCOperand::createImm(tmp));
39847 tmp = fieldFromInstruction(insn, 56, 8);
39848 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39849 tmp = fieldFromInstruction(insn, 32, 8);
39850 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39851 tmp = fieldFromInstruction(insn, 40, 8);
39852 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39853 tmp = fieldFromInstruction(insn, 48, 8);
39854 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39855 tmp = fieldFromInstruction(insn, 0, 8);
39856 MI.addOperand(MCOperand::createImm(tmp));
39857 tmp = fieldFromInstruction(insn, 8, 8);
39858 MI.addOperand(MCOperand::createImm(tmp));
39859 tmp = fieldFromInstruction(insn, 16, 1);
39860 MI.addOperand(MCOperand::createImm(tmp));
39863 tmp = fieldFromInstruction(insn, 56, 8);
39864 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39865 tmp = fieldFromInstruction(insn, 32, 8);
39866 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39867 tmp = fieldFromInstruction(insn, 0, 16);
39868 MI.addOperand(MCOperand::createImm(tmp));
39869 tmp = fieldFromInstruction(insn, 16, 1);
39870 MI.addOperand(MCOperand::createImm(tmp));
39873 tmp = fieldFromInstruction(insn, 56, 8);
39874 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39875 tmp = fieldFromInstruction(insn, 32, 8);
39876 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39877 tmp = fieldFromInstruction(insn, 0, 8);
39878 MI.addOperand(MCOperand::createImm(tmp));
39879 tmp = fieldFromInstruction(insn, 8, 8);
39880 MI.addOperand(MCOperand::createImm(tmp));
39881 tmp = fieldFromInstruction(insn, 16, 1);
39882 MI.addOperand(MCOperand::createImm(tmp));
39885 tmp = fieldFromInstruction(insn, 32, 8);
39886 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39887 tmp = fieldFromInstruction(insn, 0, 16);
39888 MI.addOperand(MCOperand::createImm(tmp));
39889 tmp = fieldFromInstruction(insn, 16, 1);
39890 MI.addOperand(MCOperand::createImm(tmp));
39893 tmp = fieldFromInstruction(insn, 56, 8);
39894 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39895 tmp = fieldFromInstruction(insn, 0, 16);
39896 MI.addOperand(MCOperand::createImm(tmp));
39897 tmp = fieldFromInstruction(insn, 16, 1);
39898 MI.addOperand(MCOperand::createImm(tmp));
39901 tmp = fieldFromInstruction(insn, 32, 8);
39902 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39903 tmp = fieldFromInstruction(insn, 40, 8);
39904 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39905 tmp = fieldFromInstruction(insn, 0, 16);
39906 MI.addOperand(MCOperand::createImm(tmp));
39907 tmp = fieldFromInstruction(insn, 16, 1);
39908 MI.addOperand(MCOperand::createImm(tmp));
39911 tmp = fieldFromInstruction(insn, 32, 8);
39912 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39913 tmp = fieldFromInstruction(insn, 40, 8);
39914 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39915 tmp = fieldFromInstruction(insn, 0, 16);
39916 MI.addOperand(MCOperand::createImm(tmp));
39917 tmp = fieldFromInstruction(insn, 16, 1);
39918 MI.addOperand(MCOperand::createImm(tmp));
39921 tmp = fieldFromInstruction(insn, 56, 8);
39922 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39923 tmp = fieldFromInstruction(insn, 32, 8);
39924 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39925 tmp = fieldFromInstruction(insn, 0, 16);
39926 MI.addOperand(MCOperand::createImm(tmp));
39927 tmp = fieldFromInstruction(insn, 16, 1);
39928 MI.addOperand(MCOperand::createImm(tmp));
39931 tmp = fieldFromInstruction(insn, 56, 8);
39932 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39933 tmp = fieldFromInstruction(insn, 32, 8);
39934 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39935 tmp = fieldFromInstruction(insn, 0, 16);
39936 MI.addOperand(MCOperand::createImm(tmp));
39937 tmp = fieldFromInstruction(insn, 16, 1);
39938 MI.addOperand(MCOperand::createImm(tmp));
39941 tmp = fieldFromInstruction(insn, 56, 8);
39942 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39943 tmp = fieldFromInstruction(insn, 32, 8);
39944 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39945 tmp = fieldFromInstruction(insn, 0, 13);
39946 MI.addOperand(MCOperand::createImm(tmp));
39947 tmp = fieldFromInstruction(insn, 16, 1);
39948 MI.addOperand(MCOperand::createImm(tmp));
39949 tmp = fieldFromInstruction(insn, 17, 1);
39950 MI.addOperand(MCOperand::createImm(tmp));
39953 tmp = fieldFromInstruction(insn, 56, 8);
39954 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39955 tmp = fieldFromInstruction(insn, 48, 7);
39956 if (DecodeSReg_32_XEXEC_HIRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39957 tmp = fieldFromInstruction(insn, 0, 13);
39958 MI.addOperand(MCOperand::createImm(tmp));
39959 tmp = fieldFromInstruction(insn, 16, 1);
39960 MI.addOperand(MCOperand::createImm(tmp));
39961 tmp = fieldFromInstruction(insn, 17, 1);
39962 MI.addOperand(MCOperand::createImm(tmp));
39965 tmp = fieldFromInstruction(insn, 56, 8);
39966 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39967 tmp = fieldFromInstruction(insn, 32, 8);
39968 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39969 tmp = fieldFromInstruction(insn, 48, 7);
39970 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39971 tmp = fieldFromInstruction(insn, 0, 13);
39972 MI.addOperand(MCOperand::createImm(tmp));
39973 tmp = fieldFromInstruction(insn, 16, 1);
39974 MI.addOperand(MCOperand::createImm(tmp));
39975 tmp = fieldFromInstruction(insn, 17, 1);
39976 MI.addOperand(MCOperand::createImm(tmp));
39979 tmp = fieldFromInstruction(insn, 56, 8);
39980 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39981 tmp = fieldFromInstruction(insn, 32, 8);
39982 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39983 tmp = fieldFromInstruction(insn, 0, 13);
39984 MI.addOperand(MCOperand::createImm(tmp));
39985 tmp = fieldFromInstruction(insn, 16, 1);
39986 MI.addOperand(MCOperand::createImm(tmp));
39987 tmp = fieldFromInstruction(insn, 17, 1);
39988 MI.addOperand(MCOperand::createImm(tmp));
39991 tmp = fieldFromInstruction(insn, 56, 8);
39992 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39993 tmp = fieldFromInstruction(insn, 48, 7);
39994 if (DecodeSReg_32_XEXEC_HIRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
39995 tmp = fieldFromInstruction(insn, 0, 13);
39996 MI.addOperand(MCOperand::createImm(tmp));
39997 tmp = fieldFromInstruction(insn, 16, 1);
39998 MI.addOperand(MCOperand::createImm(tmp));
39999 tmp = fieldFromInstruction(insn, 17, 1);
40000 MI.addOperand(MCOperand::createImm(tmp));
40003 tmp = fieldFromInstruction(insn, 56, 8);
40004 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40005 tmp = fieldFromInstruction(insn, 32, 8);
40006 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40007 tmp = fieldFromInstruction(insn, 48, 7);
40008 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40009 tmp = fieldFromInstruction(insn, 0, 13);
40010 MI.addOperand(MCOperand::createImm(tmp));
40011 tmp = fieldFromInstruction(insn, 16, 1);
40012 MI.addOperand(MCOperand::createImm(tmp));
40013 tmp = fieldFromInstruction(insn, 17, 1);
40014 MI.addOperand(MCOperand::createImm(tmp));
40017 tmp = fieldFromInstruction(insn, 56, 8);
40018 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40019 tmp = fieldFromInstruction(insn, 32, 8);
40020 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40021 tmp = fieldFromInstruction(insn, 0, 13);
40022 MI.addOperand(MCOperand::createImm(tmp));
40023 tmp = fieldFromInstruction(insn, 16, 1);
40024 MI.addOperand(MCOperand::createImm(tmp));
40025 tmp = fieldFromInstruction(insn, 17, 1);
40026 MI.addOperand(MCOperand::createImm(tmp));
40029 tmp = fieldFromInstruction(insn, 56, 8);
40030 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40031 tmp = fieldFromInstruction(insn, 48, 7);
40032 if (DecodeSReg_32_XEXEC_HIRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40033 tmp = fieldFromInstruction(insn, 0, 13);
40034 MI.addOperand(MCOperand::createImm(tmp));
40035 tmp = fieldFromInstruction(insn, 16, 1);
40036 MI.addOperand(MCOperand::createImm(tmp));
40037 tmp = fieldFromInstruction(insn, 17, 1);
40038 MI.addOperand(MCOperand::createImm(tmp));
40041 tmp = fieldFromInstruction(insn, 56, 8);
40042 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40043 tmp = fieldFromInstruction(insn, 32, 8);
40044 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40045 tmp = fieldFromInstruction(insn, 48, 7);
40046 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40047 tmp = fieldFromInstruction(insn, 0, 13);
40048 MI.addOperand(MCOperand::createImm(tmp));
40049 tmp = fieldFromInstruction(insn, 16, 1);
40050 MI.addOperand(MCOperand::createImm(tmp));
40051 tmp = fieldFromInstruction(insn, 17, 1);
40052 MI.addOperand(MCOperand::createImm(tmp));
40055 tmp = fieldFromInstruction(insn, 56, 8);
40056 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40057 tmp = fieldFromInstruction(insn, 32, 8);
40058 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40059 tmp = fieldFromInstruction(insn, 0, 13);
40060 MI.addOperand(MCOperand::createImm(tmp));
40061 tmp = fieldFromInstruction(insn, 16, 1);
40062 MI.addOperand(MCOperand::createImm(tmp));
40063 tmp = fieldFromInstruction(insn, 17, 1);
40064 MI.addOperand(MCOperand::createImm(tmp));
40067 tmp = fieldFromInstruction(insn, 56, 8);
40068 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40069 tmp = fieldFromInstruction(insn, 48, 7);
40070 if (DecodeSReg_32_XEXEC_HIRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40071 tmp = fieldFromInstruction(insn, 0, 13);
40072 MI.addOperand(MCOperand::createImm(tmp));
40073 tmp = fieldFromInstruction(insn, 16, 1);
40074 MI.addOperand(MCOperand::createImm(tmp));
40075 tmp = fieldFromInstruction(insn, 17, 1);
40076 MI.addOperand(MCOperand::createImm(tmp));
40079 tmp = fieldFromInstruction(insn, 56, 8);
40080 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40081 tmp = fieldFromInstruction(insn, 32, 8);
40082 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40083 tmp = fieldFromInstruction(insn, 48, 7);
40084 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40085 tmp = fieldFromInstruction(insn, 0, 13);
40086 MI.addOperand(MCOperand::createImm(tmp));
40087 tmp = fieldFromInstruction(insn, 16, 1);
40088 MI.addOperand(MCOperand::createImm(tmp));
40089 tmp = fieldFromInstruction(insn, 17, 1);
40090 MI.addOperand(MCOperand::createImm(tmp));
40093 tmp = fieldFromInstruction(insn, 40, 8);
40094 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40095 tmp = fieldFromInstruction(insn, 32, 8);
40096 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40097 tmp = fieldFromInstruction(insn, 0, 13);
40098 MI.addOperand(MCOperand::createImm(tmp));
40099 tmp = fieldFromInstruction(insn, 16, 1);
40100 MI.addOperand(MCOperand::createImm(tmp));
40101 tmp = fieldFromInstruction(insn, 17, 1);
40102 MI.addOperand(MCOperand::createImm(tmp));
40105 tmp = fieldFromInstruction(insn, 40, 8);
40106 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40107 tmp = fieldFromInstruction(insn, 48, 7);
40108 if (DecodeSReg_32_XEXEC_HIRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40109 tmp = fieldFromInstruction(insn, 0, 13);
40110 MI.addOperand(MCOperand::createImm(tmp));
40111 tmp = fieldFromInstruction(insn, 16, 1);
40112 MI.addOperand(MCOperand::createImm(tmp));
40113 tmp = fieldFromInstruction(insn, 17, 1);
40114 MI.addOperand(MCOperand::createImm(tmp));
40117 tmp = fieldFromInstruction(insn, 32, 8);
40118 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40119 tmp = fieldFromInstruction(insn, 40, 8);
40120 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40121 tmp = fieldFromInstruction(insn, 48, 7);
40122 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40123 tmp = fieldFromInstruction(insn, 0, 13);
40124 MI.addOperand(MCOperand::createImm(tmp));
40125 tmp = fieldFromInstruction(insn, 16, 1);
40126 MI.addOperand(MCOperand::createImm(tmp));
40127 tmp = fieldFromInstruction(insn, 17, 1);
40128 MI.addOperand(MCOperand::createImm(tmp));
40131 tmp = fieldFromInstruction(insn, 40, 8);
40132 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40133 tmp = fieldFromInstruction(insn, 32, 8);
40134 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40135 tmp = fieldFromInstruction(insn, 0, 13);
40136 MI.addOperand(MCOperand::createImm(tmp));
40137 tmp = fieldFromInstruction(insn, 16, 1);
40138 MI.addOperand(MCOperand::createImm(tmp));
40139 tmp = fieldFromInstruction(insn, 17, 1);
40140 MI.addOperand(MCOperand::createImm(tmp));
40143 tmp = fieldFromInstruction(insn, 40, 8);
40144 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40145 tmp = fieldFromInstruction(insn, 48, 7);
40146 if (DecodeSReg_32_XEXEC_HIRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40147 tmp = fieldFromInstruction(insn, 0, 13);
40148 MI.addOperand(MCOperand::createImm(tmp));
40149 tmp = fieldFromInstruction(insn, 16, 1);
40150 MI.addOperand(MCOperand::createImm(tmp));
40151 tmp = fieldFromInstruction(insn, 17, 1);
40152 MI.addOperand(MCOperand::createImm(tmp));
40155 tmp = fieldFromInstruction(insn, 32, 8);
40156 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40157 tmp = fieldFromInstruction(insn, 40, 8);
40158 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40159 tmp = fieldFromInstruction(insn, 48, 7);
40160 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40161 tmp = fieldFromInstruction(insn, 0, 13);
40162 MI.addOperand(MCOperand::createImm(tmp));
40163 tmp = fieldFromInstruction(insn, 16, 1);
40164 MI.addOperand(MCOperand::createImm(tmp));
40165 tmp = fieldFromInstruction(insn, 17, 1);
40166 MI.addOperand(MCOperand::createImm(tmp));
40169 tmp = fieldFromInstruction(insn, 40, 8);
40170 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40171 tmp = fieldFromInstruction(insn, 32, 8);
40172 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40173 tmp = fieldFromInstruction(insn, 0, 13);
40174 MI.addOperand(MCOperand::createImm(tmp));
40175 tmp = fieldFromInstruction(insn, 16, 1);
40176 MI.addOperand(MCOperand::createImm(tmp));
40177 tmp = fieldFromInstruction(insn, 17, 1);
40178 MI.addOperand(MCOperand::createImm(tmp));
40181 tmp = fieldFromInstruction(insn, 40, 8);
40182 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40183 tmp = fieldFromInstruction(insn, 48, 7);
40184 if (DecodeSReg_32_XEXEC_HIRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40185 tmp = fieldFromInstruction(insn, 0, 13);
40186 MI.addOperand(MCOperand::createImm(tmp));
40187 tmp = fieldFromInstruction(insn, 16, 1);
40188 MI.addOperand(MCOperand::createImm(tmp));
40189 tmp = fieldFromInstruction(insn, 17, 1);
40190 MI.addOperand(MCOperand::createImm(tmp));
40193 tmp = fieldFromInstruction(insn, 32, 8);
40194 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40195 tmp = fieldFromInstruction(insn, 40, 8);
40196 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40197 tmp = fieldFromInstruction(insn, 48, 7);
40198 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40199 tmp = fieldFromInstruction(insn, 0, 13);
40200 MI.addOperand(MCOperand::createImm(tmp));
40201 tmp = fieldFromInstruction(insn, 16, 1);
40202 MI.addOperand(MCOperand::createImm(tmp));
40203 tmp = fieldFromInstruction(insn, 17, 1);
40204 MI.addOperand(MCOperand::createImm(tmp));
40207 tmp = fieldFromInstruction(insn, 40, 8);
40208 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40209 tmp = fieldFromInstruction(insn, 32, 8);
40210 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40211 tmp = fieldFromInstruction(insn, 0, 13);
40212 MI.addOperand(MCOperand::createImm(tmp));
40213 tmp = fieldFromInstruction(insn, 16, 1);
40214 MI.addOperand(MCOperand::createImm(tmp));
40215 tmp = fieldFromInstruction(insn, 17, 1);
40216 MI.addOperand(MCOperand::createImm(tmp));
40219 tmp = fieldFromInstruction(insn, 40, 8);
40220 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40221 tmp = fieldFromInstruction(insn, 48, 7);
40222 if (DecodeSReg_32_XEXEC_HIRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40223 tmp = fieldFromInstruction(insn, 0, 13);
40224 MI.addOperand(MCOperand::createImm(tmp));
40225 tmp = fieldFromInstruction(insn, 16, 1);
40226 MI.addOperand(MCOperand::createImm(tmp));
40227 tmp = fieldFromInstruction(insn, 17, 1);
40228 MI.addOperand(MCOperand::createImm(tmp));
40231 tmp = fieldFromInstruction(insn, 32, 8);
40232 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40233 tmp = fieldFromInstruction(insn, 40, 8);
40234 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40235 tmp = fieldFromInstruction(insn, 48, 7);
40236 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40237 tmp = fieldFromInstruction(insn, 0, 13);
40238 MI.addOperand(MCOperand::createImm(tmp));
40239 tmp = fieldFromInstruction(insn, 16, 1);
40240 MI.addOperand(MCOperand::createImm(tmp));
40241 tmp = fieldFromInstruction(insn, 17, 1);
40242 MI.addOperand(MCOperand::createImm(tmp));
40245 tmp = fieldFromInstruction(insn, 32, 8);
40246 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40247 tmp = fieldFromInstruction(insn, 40, 8);
40248 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40249 tmp = fieldFromInstruction(insn, 48, 7);
40250 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40251 tmp = fieldFromInstruction(insn, 0, 13);
40252 MI.addOperand(MCOperand::createImm(tmp));
40253 tmp = fieldFromInstruction(insn, 17, 1);
40254 MI.addOperand(MCOperand::createImm(tmp));
40257 tmp = fieldFromInstruction(insn, 56, 8);
40258 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40259 tmp = fieldFromInstruction(insn, 32, 8);
40260 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40261 tmp = fieldFromInstruction(insn, 40, 8);
40262 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40263 tmp = fieldFromInstruction(insn, 48, 7);
40264 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40265 tmp = fieldFromInstruction(insn, 0, 13);
40266 MI.addOperand(MCOperand::createImm(tmp));
40267 tmp = fieldFromInstruction(insn, 17, 1);
40268 MI.addOperand(MCOperand::createImm(tmp));
40271 tmp = fieldFromInstruction(insn, 32, 8);
40272 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40273 tmp = fieldFromInstruction(insn, 40, 8);
40274 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40275 tmp = fieldFromInstruction(insn, 48, 7);
40276 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40277 tmp = fieldFromInstruction(insn, 0, 13);
40278 MI.addOperand(MCOperand::createImm(tmp));
40279 tmp = fieldFromInstruction(insn, 17, 1);
40280 MI.addOperand(MCOperand::createImm(tmp));
40283 tmp = fieldFromInstruction(insn, 56, 8);
40284 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40285 tmp = fieldFromInstruction(insn, 32, 8);
40286 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40287 tmp = fieldFromInstruction(insn, 40, 8);
40288 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40289 tmp = fieldFromInstruction(insn, 48, 7);
40290 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40291 tmp = fieldFromInstruction(insn, 0, 13);
40292 MI.addOperand(MCOperand::createImm(tmp));
40293 tmp = fieldFromInstruction(insn, 17, 1);
40294 MI.addOperand(MCOperand::createImm(tmp));
40297 tmp = fieldFromInstruction(insn, 56, 8);
40298 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40299 tmp = fieldFromInstruction(insn, 32, 8);
40300 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40301 tmp = fieldFromInstruction(insn, 40, 8);
40302 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40303 tmp = fieldFromInstruction(insn, 48, 7);
40304 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40305 tmp = fieldFromInstruction(insn, 0, 13);
40306 MI.addOperand(MCOperand::createImm(tmp));
40307 tmp = fieldFromInstruction(insn, 17, 1);
40308 MI.addOperand(MCOperand::createImm(tmp));
40311 tmp = fieldFromInstruction(insn, 32, 8);
40312 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40313 tmp = fieldFromInstruction(insn, 40, 8);
40314 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40315 tmp = fieldFromInstruction(insn, 48, 7);
40316 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40317 tmp = fieldFromInstruction(insn, 0, 13);
40318 MI.addOperand(MCOperand::createImm(tmp));
40319 tmp = fieldFromInstruction(insn, 17, 1);
40320 MI.addOperand(MCOperand::createImm(tmp));
40323 tmp = fieldFromInstruction(insn, 56, 8);
40324 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40325 tmp = fieldFromInstruction(insn, 32, 8);
40326 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40327 tmp = fieldFromInstruction(insn, 40, 8);
40328 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40329 tmp = fieldFromInstruction(insn, 48, 7);
40330 if (DecodeSReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40331 tmp = fieldFromInstruction(insn, 0, 13);
40332 MI.addOperand(MCOperand::createImm(tmp));
40333 tmp = fieldFromInstruction(insn, 17, 1);
40334 MI.addOperand(MCOperand::createImm(tmp));
40337 tmp = fieldFromInstruction(insn, 40, 8);
40338 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40339 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40340 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40341 tmp = fieldFromInstruction(insn, 56, 8);
40342 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40343 tmp = fieldFromInstruction(insn, 0, 12);
40344 MI.addOperand(MCOperand::createImm(tmp));
40345 tmp = fieldFromInstruction(insn, 14, 1);
40346 MI.addOperand(MCOperand::createImm(tmp));
40347 tmp = fieldFromInstruction(insn, 17, 1);
40348 MI.addOperand(MCOperand::createImm(tmp));
40349 tmp = fieldFromInstruction(insn, 55, 1);
40350 MI.addOperand(MCOperand::createImm(tmp));
40353 tmp = fieldFromInstruction(insn, 40, 8);
40354 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40355 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40356 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40357 tmp = fieldFromInstruction(insn, 56, 8);
40358 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40359 tmp = fieldFromInstruction(insn, 0, 12);
40360 MI.addOperand(MCOperand::createImm(tmp));
40361 tmp = fieldFromInstruction(insn, 14, 1);
40362 MI.addOperand(MCOperand::createImm(tmp));
40363 tmp = fieldFromInstruction(insn, 17, 1);
40364 MI.addOperand(MCOperand::createImm(tmp));
40367 tmp = fieldFromInstruction(insn, 40, 8);
40368 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40369 tmp = fieldFromInstruction(insn, 32, 8);
40370 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40371 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40372 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40373 tmp = fieldFromInstruction(insn, 56, 8);
40374 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40375 tmp = fieldFromInstruction(insn, 0, 12);
40376 MI.addOperand(MCOperand::createImm(tmp));
40377 tmp = fieldFromInstruction(insn, 14, 1);
40378 MI.addOperand(MCOperand::createImm(tmp));
40379 tmp = fieldFromInstruction(insn, 17, 1);
40380 MI.addOperand(MCOperand::createImm(tmp));
40381 tmp = fieldFromInstruction(insn, 55, 1);
40382 MI.addOperand(MCOperand::createImm(tmp));
40385 tmp = fieldFromInstruction(insn, 40, 8);
40386 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40387 tmp = fieldFromInstruction(insn, 32, 8);
40388 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40389 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40390 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40391 tmp = fieldFromInstruction(insn, 56, 8);
40392 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40393 tmp = fieldFromInstruction(insn, 0, 12);
40394 MI.addOperand(MCOperand::createImm(tmp));
40395 tmp = fieldFromInstruction(insn, 14, 1);
40396 MI.addOperand(MCOperand::createImm(tmp));
40397 tmp = fieldFromInstruction(insn, 17, 1);
40398 MI.addOperand(MCOperand::createImm(tmp));
40401 tmp = fieldFromInstruction(insn, 40, 8);
40402 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40403 tmp = fieldFromInstruction(insn, 32, 8);
40404 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40405 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40406 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40407 tmp = fieldFromInstruction(insn, 56, 8);
40408 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40409 tmp = fieldFromInstruction(insn, 0, 12);
40410 MI.addOperand(MCOperand::createImm(tmp));
40411 tmp = fieldFromInstruction(insn, 14, 1);
40412 MI.addOperand(MCOperand::createImm(tmp));
40413 tmp = fieldFromInstruction(insn, 17, 1);
40414 MI.addOperand(MCOperand::createImm(tmp));
40415 tmp = fieldFromInstruction(insn, 55, 1);
40416 MI.addOperand(MCOperand::createImm(tmp));
40419 tmp = fieldFromInstruction(insn, 40, 8);
40420 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40421 tmp = fieldFromInstruction(insn, 32, 8);
40422 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40423 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40424 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40425 tmp = fieldFromInstruction(insn, 56, 8);
40426 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40427 tmp = fieldFromInstruction(insn, 0, 12);
40428 MI.addOperand(MCOperand::createImm(tmp));
40429 tmp = fieldFromInstruction(insn, 14, 1);
40430 MI.addOperand(MCOperand::createImm(tmp));
40431 tmp = fieldFromInstruction(insn, 17, 1);
40432 MI.addOperand(MCOperand::createImm(tmp));
40435 tmp = fieldFromInstruction(insn, 40, 8);
40436 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40437 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40438 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40439 tmp = fieldFromInstruction(insn, 56, 8);
40440 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40441 tmp = fieldFromInstruction(insn, 0, 12);
40442 MI.addOperand(MCOperand::createImm(tmp));
40443 tmp = fieldFromInstruction(insn, 14, 1);
40444 MI.addOperand(MCOperand::createImm(tmp));
40445 tmp = fieldFromInstruction(insn, 17, 1);
40446 MI.addOperand(MCOperand::createImm(tmp));
40447 tmp = fieldFromInstruction(insn, 55, 1);
40448 MI.addOperand(MCOperand::createImm(tmp));
40451 tmp = fieldFromInstruction(insn, 40, 8);
40452 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40453 tmp = fieldFromInstruction(insn, 32, 8);
40454 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40455 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40456 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40457 tmp = fieldFromInstruction(insn, 56, 8);
40458 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40459 tmp = fieldFromInstruction(insn, 0, 12);
40460 MI.addOperand(MCOperand::createImm(tmp));
40461 tmp = fieldFromInstruction(insn, 14, 1);
40462 MI.addOperand(MCOperand::createImm(tmp));
40463 tmp = fieldFromInstruction(insn, 17, 1);
40464 MI.addOperand(MCOperand::createImm(tmp));
40465 tmp = fieldFromInstruction(insn, 55, 1);
40466 MI.addOperand(MCOperand::createImm(tmp));
40469 tmp = fieldFromInstruction(insn, 40, 8);
40470 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40471 tmp = fieldFromInstruction(insn, 32, 8);
40472 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40473 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40474 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40475 tmp = fieldFromInstruction(insn, 56, 8);
40476 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40477 tmp = fieldFromInstruction(insn, 0, 12);
40478 MI.addOperand(MCOperand::createImm(tmp));
40479 tmp = fieldFromInstruction(insn, 14, 1);
40480 MI.addOperand(MCOperand::createImm(tmp));
40481 tmp = fieldFromInstruction(insn, 17, 1);
40482 MI.addOperand(MCOperand::createImm(tmp));
40483 tmp = fieldFromInstruction(insn, 55, 1);
40484 MI.addOperand(MCOperand::createImm(tmp));
40487 tmp = fieldFromInstruction(insn, 40, 8);
40488 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40489 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40490 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40491 tmp = fieldFromInstruction(insn, 56, 8);
40492 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40493 tmp = fieldFromInstruction(insn, 0, 12);
40494 MI.addOperand(MCOperand::createImm(tmp));
40495 tmp = fieldFromInstruction(insn, 14, 1);
40496 MI.addOperand(MCOperand::createImm(tmp));
40497 tmp = fieldFromInstruction(insn, 17, 1);
40498 MI.addOperand(MCOperand::createImm(tmp));
40499 tmp = fieldFromInstruction(insn, 55, 1);
40500 MI.addOperand(MCOperand::createImm(tmp));
40503 tmp = fieldFromInstruction(insn, 40, 8);
40504 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40505 tmp = fieldFromInstruction(insn, 32, 8);
40506 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40507 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40508 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40509 tmp = fieldFromInstruction(insn, 56, 8);
40510 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40511 tmp = fieldFromInstruction(insn, 0, 12);
40512 MI.addOperand(MCOperand::createImm(tmp));
40513 tmp = fieldFromInstruction(insn, 14, 1);
40514 MI.addOperand(MCOperand::createImm(tmp));
40515 tmp = fieldFromInstruction(insn, 17, 1);
40516 MI.addOperand(MCOperand::createImm(tmp));
40517 tmp = fieldFromInstruction(insn, 55, 1);
40518 MI.addOperand(MCOperand::createImm(tmp));
40521 tmp = fieldFromInstruction(insn, 40, 8);
40522 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40523 tmp = fieldFromInstruction(insn, 32, 8);
40524 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40525 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40526 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40527 tmp = fieldFromInstruction(insn, 56, 8);
40528 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40529 tmp = fieldFromInstruction(insn, 0, 12);
40530 MI.addOperand(MCOperand::createImm(tmp));
40531 tmp = fieldFromInstruction(insn, 14, 1);
40532 MI.addOperand(MCOperand::createImm(tmp));
40533 tmp = fieldFromInstruction(insn, 17, 1);
40534 MI.addOperand(MCOperand::createImm(tmp));
40535 tmp = fieldFromInstruction(insn, 55, 1);
40536 MI.addOperand(MCOperand::createImm(tmp));
40539 tmp = fieldFromInstruction(insn, 40, 8);
40540 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40541 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40542 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40543 tmp = fieldFromInstruction(insn, 56, 8);
40544 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40545 tmp = fieldFromInstruction(insn, 0, 12);
40546 MI.addOperand(MCOperand::createImm(tmp));
40547 tmp = fieldFromInstruction(insn, 14, 1);
40548 MI.addOperand(MCOperand::createImm(tmp));
40549 tmp = fieldFromInstruction(insn, 17, 1);
40550 MI.addOperand(MCOperand::createImm(tmp));
40551 tmp = fieldFromInstruction(insn, 55, 1);
40552 MI.addOperand(MCOperand::createImm(tmp));
40555 tmp = fieldFromInstruction(insn, 40, 8);
40556 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40557 tmp = fieldFromInstruction(insn, 32, 8);
40558 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40559 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40560 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40561 tmp = fieldFromInstruction(insn, 56, 8);
40562 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40563 tmp = fieldFromInstruction(insn, 0, 12);
40564 MI.addOperand(MCOperand::createImm(tmp));
40565 tmp = fieldFromInstruction(insn, 14, 1);
40566 MI.addOperand(MCOperand::createImm(tmp));
40567 tmp = fieldFromInstruction(insn, 17, 1);
40568 MI.addOperand(MCOperand::createImm(tmp));
40569 tmp = fieldFromInstruction(insn, 55, 1);
40570 MI.addOperand(MCOperand::createImm(tmp));
40573 tmp = fieldFromInstruction(insn, 40, 8);
40574 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40575 tmp = fieldFromInstruction(insn, 32, 8);
40576 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40577 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40578 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40579 tmp = fieldFromInstruction(insn, 56, 8);
40580 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40581 tmp = fieldFromInstruction(insn, 0, 12);
40582 MI.addOperand(MCOperand::createImm(tmp));
40583 tmp = fieldFromInstruction(insn, 14, 1);
40584 MI.addOperand(MCOperand::createImm(tmp));
40585 tmp = fieldFromInstruction(insn, 17, 1);
40586 MI.addOperand(MCOperand::createImm(tmp));
40587 tmp = fieldFromInstruction(insn, 55, 1);
40588 MI.addOperand(MCOperand::createImm(tmp));
40591 tmp = fieldFromInstruction(insn, 40, 8);
40592 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40593 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40594 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40595 tmp = fieldFromInstruction(insn, 56, 8);
40596 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40597 tmp = fieldFromInstruction(insn, 0, 12);
40598 MI.addOperand(MCOperand::createImm(tmp));
40599 tmp = fieldFromInstruction(insn, 14, 1);
40600 MI.addOperand(MCOperand::createImm(tmp));
40601 tmp = fieldFromInstruction(insn, 17, 1);
40602 MI.addOperand(MCOperand::createImm(tmp));
40605 tmp = fieldFromInstruction(insn, 40, 8);
40606 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40607 tmp = fieldFromInstruction(insn, 32, 8);
40608 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40609 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40610 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40611 tmp = fieldFromInstruction(insn, 56, 8);
40612 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40613 tmp = fieldFromInstruction(insn, 0, 12);
40614 MI.addOperand(MCOperand::createImm(tmp));
40615 tmp = fieldFromInstruction(insn, 14, 1);
40616 MI.addOperand(MCOperand::createImm(tmp));
40617 tmp = fieldFromInstruction(insn, 17, 1);
40618 MI.addOperand(MCOperand::createImm(tmp));
40621 tmp = fieldFromInstruction(insn, 40, 8);
40622 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40623 tmp = fieldFromInstruction(insn, 32, 8);
40624 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40625 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40626 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40627 tmp = fieldFromInstruction(insn, 56, 8);
40628 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40629 tmp = fieldFromInstruction(insn, 0, 12);
40630 MI.addOperand(MCOperand::createImm(tmp));
40631 tmp = fieldFromInstruction(insn, 14, 1);
40632 MI.addOperand(MCOperand::createImm(tmp));
40633 tmp = fieldFromInstruction(insn, 17, 1);
40634 MI.addOperand(MCOperand::createImm(tmp));
40637 tmp = fieldFromInstruction(insn, 40, 8);
40638 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40639 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40640 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40641 tmp = fieldFromInstruction(insn, 56, 8);
40642 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40643 tmp = fieldFromInstruction(insn, 0, 12);
40644 MI.addOperand(MCOperand::createImm(tmp));
40645 tmp = fieldFromInstruction(insn, 14, 1);
40646 MI.addOperand(MCOperand::createImm(tmp));
40647 tmp = fieldFromInstruction(insn, 17, 1);
40648 MI.addOperand(MCOperand::createImm(tmp));
40651 tmp = fieldFromInstruction(insn, 40, 8);
40652 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40653 tmp = fieldFromInstruction(insn, 32, 8);
40654 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40655 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40656 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40657 tmp = fieldFromInstruction(insn, 56, 8);
40658 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40659 tmp = fieldFromInstruction(insn, 0, 12);
40660 MI.addOperand(MCOperand::createImm(tmp));
40661 tmp = fieldFromInstruction(insn, 14, 1);
40662 MI.addOperand(MCOperand::createImm(tmp));
40663 tmp = fieldFromInstruction(insn, 17, 1);
40664 MI.addOperand(MCOperand::createImm(tmp));
40667 tmp = fieldFromInstruction(insn, 40, 8);
40668 if (DecodeVReg_96RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40669 tmp = fieldFromInstruction(insn, 32, 8);
40670 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40671 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40672 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40673 tmp = fieldFromInstruction(insn, 56, 8);
40674 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40675 tmp = fieldFromInstruction(insn, 0, 12);
40676 MI.addOperand(MCOperand::createImm(tmp));
40677 tmp = fieldFromInstruction(insn, 14, 1);
40678 MI.addOperand(MCOperand::createImm(tmp));
40679 tmp = fieldFromInstruction(insn, 17, 1);
40680 MI.addOperand(MCOperand::createImm(tmp));
40683 tmp = fieldFromInstruction(insn, 40, 8);
40684 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40685 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40686 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40687 tmp = fieldFromInstruction(insn, 56, 8);
40688 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40689 tmp = fieldFromInstruction(insn, 0, 12);
40690 MI.addOperand(MCOperand::createImm(tmp));
40691 tmp = fieldFromInstruction(insn, 14, 1);
40692 MI.addOperand(MCOperand::createImm(tmp));
40693 tmp = fieldFromInstruction(insn, 17, 1);
40694 MI.addOperand(MCOperand::createImm(tmp));
40697 tmp = fieldFromInstruction(insn, 40, 8);
40698 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40699 tmp = fieldFromInstruction(insn, 32, 8);
40700 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40701 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40702 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40703 tmp = fieldFromInstruction(insn, 56, 8);
40704 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40705 tmp = fieldFromInstruction(insn, 0, 12);
40706 MI.addOperand(MCOperand::createImm(tmp));
40707 tmp = fieldFromInstruction(insn, 14, 1);
40708 MI.addOperand(MCOperand::createImm(tmp));
40709 tmp = fieldFromInstruction(insn, 17, 1);
40710 MI.addOperand(MCOperand::createImm(tmp));
40713 tmp = fieldFromInstruction(insn, 40, 8);
40714 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40715 tmp = fieldFromInstruction(insn, 32, 8);
40716 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40717 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40718 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40719 tmp = fieldFromInstruction(insn, 56, 8);
40720 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40721 tmp = fieldFromInstruction(insn, 0, 12);
40722 MI.addOperand(MCOperand::createImm(tmp));
40723 tmp = fieldFromInstruction(insn, 14, 1);
40724 MI.addOperand(MCOperand::createImm(tmp));
40725 tmp = fieldFromInstruction(insn, 17, 1);
40726 MI.addOperand(MCOperand::createImm(tmp));
40729 tmp = fieldFromInstruction(insn, 40, 8);
40730 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40731 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40732 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40733 tmp = fieldFromInstruction(insn, 56, 8);
40734 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40735 tmp = fieldFromInstruction(insn, 0, 12);
40736 MI.addOperand(MCOperand::createImm(tmp));
40737 tmp = fieldFromInstruction(insn, 14, 1);
40738 MI.addOperand(MCOperand::createImm(tmp));
40739 tmp = fieldFromInstruction(insn, 17, 1);
40740 MI.addOperand(MCOperand::createImm(tmp));
40741 tmp = fieldFromInstruction(insn, 55, 1);
40742 MI.addOperand(MCOperand::createImm(tmp));
40743 tmp = fieldFromInstruction(insn, 40, 8);
40744 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40747 tmp = fieldFromInstruction(insn, 40, 8);
40748 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40749 tmp = fieldFromInstruction(insn, 32, 8);
40750 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40751 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40752 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40753 tmp = fieldFromInstruction(insn, 56, 8);
40754 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40755 tmp = fieldFromInstruction(insn, 0, 12);
40756 MI.addOperand(MCOperand::createImm(tmp));
40757 tmp = fieldFromInstruction(insn, 14, 1);
40758 MI.addOperand(MCOperand::createImm(tmp));
40759 tmp = fieldFromInstruction(insn, 17, 1);
40760 MI.addOperand(MCOperand::createImm(tmp));
40761 tmp = fieldFromInstruction(insn, 55, 1);
40762 MI.addOperand(MCOperand::createImm(tmp));
40763 tmp = fieldFromInstruction(insn, 40, 8);
40764 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40767 tmp = fieldFromInstruction(insn, 40, 8);
40768 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40769 tmp = fieldFromInstruction(insn, 32, 8);
40770 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40771 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40772 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40773 tmp = fieldFromInstruction(insn, 56, 8);
40774 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40775 tmp = fieldFromInstruction(insn, 0, 12);
40776 MI.addOperand(MCOperand::createImm(tmp));
40777 tmp = fieldFromInstruction(insn, 14, 1);
40778 MI.addOperand(MCOperand::createImm(tmp));
40779 tmp = fieldFromInstruction(insn, 17, 1);
40780 MI.addOperand(MCOperand::createImm(tmp));
40781 tmp = fieldFromInstruction(insn, 55, 1);
40782 MI.addOperand(MCOperand::createImm(tmp));
40783 tmp = fieldFromInstruction(insn, 40, 8);
40784 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40787 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40788 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40789 tmp = fieldFromInstruction(insn, 56, 8);
40790 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40791 tmp = fieldFromInstruction(insn, 0, 12);
40792 MI.addOperand(MCOperand::createImm(tmp));
40793 tmp = fieldFromInstruction(insn, 14, 1);
40794 MI.addOperand(MCOperand::createImm(tmp));
40795 tmp = fieldFromInstruction(insn, 17, 1);
40796 MI.addOperand(MCOperand::createImm(tmp));
40799 tmp = fieldFromInstruction(insn, 40, 8);
40800 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40801 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40802 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40803 tmp = fieldFromInstruction(insn, 56, 8);
40804 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40805 tmp = fieldFromInstruction(insn, 0, 12);
40806 MI.addOperand(MCOperand::createImm(tmp));
40807 tmp = fieldFromInstruction(insn, 17, 1);
40808 MI.addOperand(MCOperand::createImm(tmp));
40811 tmp = fieldFromInstruction(insn, 40, 8);
40812 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40813 tmp = fieldFromInstruction(insn, 32, 8);
40814 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40815 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40816 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40817 tmp = fieldFromInstruction(insn, 56, 8);
40818 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40819 tmp = fieldFromInstruction(insn, 0, 12);
40820 MI.addOperand(MCOperand::createImm(tmp));
40821 tmp = fieldFromInstruction(insn, 17, 1);
40822 MI.addOperand(MCOperand::createImm(tmp));
40825 tmp = fieldFromInstruction(insn, 40, 8);
40826 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40827 tmp = fieldFromInstruction(insn, 32, 8);
40828 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40829 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40830 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40831 tmp = fieldFromInstruction(insn, 56, 8);
40832 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40833 tmp = fieldFromInstruction(insn, 0, 12);
40834 MI.addOperand(MCOperand::createImm(tmp));
40835 tmp = fieldFromInstruction(insn, 17, 1);
40836 MI.addOperand(MCOperand::createImm(tmp));
40839 tmp = fieldFromInstruction(insn, 40, 8);
40840 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40841 tmp = fieldFromInstruction(insn, 40, 8);
40842 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40843 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40844 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40845 tmp = fieldFromInstruction(insn, 56, 8);
40846 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40847 tmp = fieldFromInstruction(insn, 0, 12);
40848 MI.addOperand(MCOperand::createImm(tmp));
40849 tmp = fieldFromInstruction(insn, 17, 1);
40850 MI.addOperand(MCOperand::createImm(tmp));
40853 tmp = fieldFromInstruction(insn, 40, 8);
40854 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40855 tmp = fieldFromInstruction(insn, 40, 8);
40856 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40857 tmp = fieldFromInstruction(insn, 32, 8);
40858 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40859 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40860 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40861 tmp = fieldFromInstruction(insn, 56, 8);
40862 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40863 tmp = fieldFromInstruction(insn, 0, 12);
40864 MI.addOperand(MCOperand::createImm(tmp));
40865 tmp = fieldFromInstruction(insn, 17, 1);
40866 MI.addOperand(MCOperand::createImm(tmp));
40869 tmp = fieldFromInstruction(insn, 40, 8);
40870 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40871 tmp = fieldFromInstruction(insn, 40, 8);
40872 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40873 tmp = fieldFromInstruction(insn, 32, 8);
40874 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40875 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40876 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40877 tmp = fieldFromInstruction(insn, 56, 8);
40878 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40879 tmp = fieldFromInstruction(insn, 0, 12);
40880 MI.addOperand(MCOperand::createImm(tmp));
40881 tmp = fieldFromInstruction(insn, 17, 1);
40882 MI.addOperand(MCOperand::createImm(tmp));
40885 tmp = fieldFromInstruction(insn, 40, 8);
40886 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40887 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40888 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40889 tmp = fieldFromInstruction(insn, 56, 8);
40890 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40891 tmp = fieldFromInstruction(insn, 0, 12);
40892 MI.addOperand(MCOperand::createImm(tmp));
40893 tmp = fieldFromInstruction(insn, 17, 1);
40894 MI.addOperand(MCOperand::createImm(tmp));
40897 tmp = fieldFromInstruction(insn, 40, 8);
40898 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40899 tmp = fieldFromInstruction(insn, 32, 8);
40900 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40901 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40902 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40903 tmp = fieldFromInstruction(insn, 56, 8);
40904 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40905 tmp = fieldFromInstruction(insn, 0, 12);
40906 MI.addOperand(MCOperand::createImm(tmp));
40907 tmp = fieldFromInstruction(insn, 17, 1);
40908 MI.addOperand(MCOperand::createImm(tmp));
40911 tmp = fieldFromInstruction(insn, 40, 8);
40912 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40913 tmp = fieldFromInstruction(insn, 32, 8);
40914 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40915 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40916 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40917 tmp = fieldFromInstruction(insn, 56, 8);
40918 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40919 tmp = fieldFromInstruction(insn, 0, 12);
40920 MI.addOperand(MCOperand::createImm(tmp));
40921 tmp = fieldFromInstruction(insn, 17, 1);
40922 MI.addOperand(MCOperand::createImm(tmp));
40925 tmp = fieldFromInstruction(insn, 40, 8);
40926 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40927 tmp = fieldFromInstruction(insn, 40, 8);
40928 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40929 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40930 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40931 tmp = fieldFromInstruction(insn, 56, 8);
40932 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40933 tmp = fieldFromInstruction(insn, 0, 12);
40934 MI.addOperand(MCOperand::createImm(tmp));
40935 tmp = fieldFromInstruction(insn, 17, 1);
40936 MI.addOperand(MCOperand::createImm(tmp));
40939 tmp = fieldFromInstruction(insn, 40, 8);
40940 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40941 tmp = fieldFromInstruction(insn, 40, 8);
40942 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40943 tmp = fieldFromInstruction(insn, 32, 8);
40944 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40945 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40946 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40947 tmp = fieldFromInstruction(insn, 56, 8);
40948 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40949 tmp = fieldFromInstruction(insn, 0, 12);
40950 MI.addOperand(MCOperand::createImm(tmp));
40951 tmp = fieldFromInstruction(insn, 17, 1);
40952 MI.addOperand(MCOperand::createImm(tmp));
40955 tmp = fieldFromInstruction(insn, 40, 8);
40956 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40957 tmp = fieldFromInstruction(insn, 40, 8);
40958 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40959 tmp = fieldFromInstruction(insn, 32, 8);
40960 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40961 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40962 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40963 tmp = fieldFromInstruction(insn, 56, 8);
40964 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40965 tmp = fieldFromInstruction(insn, 0, 12);
40966 MI.addOperand(MCOperand::createImm(tmp));
40967 tmp = fieldFromInstruction(insn, 17, 1);
40968 MI.addOperand(MCOperand::createImm(tmp));
40971 tmp = fieldFromInstruction(insn, 40, 8);
40972 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40973 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40974 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40975 tmp = fieldFromInstruction(insn, 56, 8);
40976 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40977 tmp = fieldFromInstruction(insn, 0, 12);
40978 MI.addOperand(MCOperand::createImm(tmp));
40979 tmp = fieldFromInstruction(insn, 17, 1);
40980 MI.addOperand(MCOperand::createImm(tmp));
40983 tmp = fieldFromInstruction(insn, 40, 8);
40984 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40985 tmp = fieldFromInstruction(insn, 32, 8);
40986 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40987 tmp = fieldFromInstruction(insn, 48, 5) << 2;
40988 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40989 tmp = fieldFromInstruction(insn, 56, 8);
40990 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40991 tmp = fieldFromInstruction(insn, 0, 12);
40992 MI.addOperand(MCOperand::createImm(tmp));
40993 tmp = fieldFromInstruction(insn, 17, 1);
40994 MI.addOperand(MCOperand::createImm(tmp));
40997 tmp = fieldFromInstruction(insn, 40, 8);
40998 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
40999 tmp = fieldFromInstruction(insn, 32, 8);
41000 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41001 tmp = fieldFromInstruction(insn, 48, 5) << 2;
41002 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41003 tmp = fieldFromInstruction(insn, 56, 8);
41004 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41005 tmp = fieldFromInstruction(insn, 0, 12);
41006 MI.addOperand(MCOperand::createImm(tmp));
41007 tmp = fieldFromInstruction(insn, 17, 1);
41008 MI.addOperand(MCOperand::createImm(tmp));
41011 tmp = fieldFromInstruction(insn, 40, 8);
41012 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41013 tmp = fieldFromInstruction(insn, 40, 8);
41014 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41015 tmp = fieldFromInstruction(insn, 48, 5) << 2;
41016 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41017 tmp = fieldFromInstruction(insn, 56, 8);
41018 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41019 tmp = fieldFromInstruction(insn, 0, 12);
41020 MI.addOperand(MCOperand::createImm(tmp));
41021 tmp = fieldFromInstruction(insn, 17, 1);
41022 MI.addOperand(MCOperand::createImm(tmp));
41025 tmp = fieldFromInstruction(insn, 40, 8);
41026 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41027 tmp = fieldFromInstruction(insn, 40, 8);
41028 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41029 tmp = fieldFromInstruction(insn, 32, 8);
41030 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41031 tmp = fieldFromInstruction(insn, 48, 5) << 2;
41032 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41033 tmp = fieldFromInstruction(insn, 56, 8);
41034 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41035 tmp = fieldFromInstruction(insn, 0, 12);
41036 MI.addOperand(MCOperand::createImm(tmp));
41037 tmp = fieldFromInstruction(insn, 17, 1);
41038 MI.addOperand(MCOperand::createImm(tmp));
41041 tmp = fieldFromInstruction(insn, 40, 8);
41042 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41043 tmp = fieldFromInstruction(insn, 40, 8);
41044 if (DecodeVReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41045 tmp = fieldFromInstruction(insn, 32, 8);
41046 if (DecodeVReg_64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41047 tmp = fieldFromInstruction(insn, 48, 5) << 2;
41048 if (DecodeSReg_128RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41049 tmp = fieldFromInstruction(insn, 56, 8);
41050 if (decodeOperand_SReg_32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41051 tmp = fieldFromInstruction(insn, 0, 12);
41052 MI.addOperand(MCOperand::createImm(tmp));
41053 tmp = fieldFromInstruction(insn, 17, 1);
41054 MI.addOperand(MCOperand::createImm(tmp));
41057 tmp = fieldFromInstruction(insn, 17, 8);
41058 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41059 tmp = fieldFromInstruction(insn, 51, 1);
41060 MI.addOperand(MCOperand::createImm(tmp));
41061 tmp = fieldFromInstruction(insn, 32, 8);
41062 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41063 tmp = fieldFromInstruction(insn, 59, 1);
41064 MI.addOperand(MCOperand::createImm(tmp));
41065 tmp = fieldFromInstruction(insn, 9, 8);
41066 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41067 tmp = fieldFromInstruction(insn, 45, 1);
41068 MI.addOperand(MCOperand::createImm(tmp));
41069 tmp = fieldFromInstruction(insn, 40, 3);
41070 MI.addOperand(MCOperand::createImm(tmp));
41071 tmp = fieldFromInstruction(insn, 43, 2);
41072 MI.addOperand(MCOperand::createImm(tmp));
41073 tmp = fieldFromInstruction(insn, 48, 3);
41074 MI.addOperand(MCOperand::createImm(tmp));
41075 tmp = fieldFromInstruction(insn, 56, 3);
41076 MI.addOperand(MCOperand::createImm(tmp));
41079 tmp = fieldFromInstruction(insn, 17, 8);
41080 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41081 tmp = fieldFromInstruction(insn, 52, 2);
41082 MI.addOperand(MCOperand::createImm(tmp));
41083 tmp = fieldFromInstruction(insn, 32, 8);
41084 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41085 tmp = fieldFromInstruction(insn, 60, 2);
41086 MI.addOperand(MCOperand::createImm(tmp));
41087 tmp = fieldFromInstruction(insn, 9, 8);
41088 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41089 tmp = fieldFromInstruction(insn, 45, 1);
41090 MI.addOperand(MCOperand::createImm(tmp));
41091 tmp = fieldFromInstruction(insn, 40, 3);
41092 MI.addOperand(MCOperand::createImm(tmp));
41093 tmp = fieldFromInstruction(insn, 43, 2);
41094 MI.addOperand(MCOperand::createImm(tmp));
41095 tmp = fieldFromInstruction(insn, 48, 3);
41096 MI.addOperand(MCOperand::createImm(tmp));
41097 tmp = fieldFromInstruction(insn, 56, 3);
41098 MI.addOperand(MCOperand::createImm(tmp));
41101 tmp = fieldFromInstruction(insn, 17, 8);
41102 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41103 tmp = fieldFromInstruction(insn, 52, 2);
41104 MI.addOperand(MCOperand::createImm(tmp));
41105 tmp = fieldFromInstruction(insn, 32, 8);
41106 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41107 tmp = fieldFromInstruction(insn, 60, 2);
41108 MI.addOperand(MCOperand::createImm(tmp));
41109 tmp = fieldFromInstruction(insn, 9, 8);
41110 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41111 tmp = fieldFromInstruction(insn, 17, 8);
41112 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41113 tmp = fieldFromInstruction(insn, 45, 1);
41114 MI.addOperand(MCOperand::createImm(tmp));
41115 tmp = fieldFromInstruction(insn, 40, 3);
41116 MI.addOperand(MCOperand::createImm(tmp));
41117 tmp = fieldFromInstruction(insn, 43, 2);
41118 MI.addOperand(MCOperand::createImm(tmp));
41119 tmp = fieldFromInstruction(insn, 48, 3);
41120 MI.addOperand(MCOperand::createImm(tmp));
41121 tmp = fieldFromInstruction(insn, 56, 3);
41122 MI.addOperand(MCOperand::createImm(tmp));
41125 tmp = fieldFromInstruction(insn, 17, 8);
41126 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41127 tmp = fieldFromInstruction(insn, 52, 2);
41128 MI.addOperand(MCOperand::createImm(tmp));
41129 tmp = fieldFromInstruction(insn, 32, 8);
41130 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41131 tmp = fieldFromInstruction(insn, 60, 2);
41132 MI.addOperand(MCOperand::createImm(tmp));
41133 tmp = fieldFromInstruction(insn, 9, 8);
41134 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41135 tmp = fieldFromInstruction(insn, 45, 1);
41136 MI.addOperand(MCOperand::createImm(tmp));
41137 tmp = fieldFromInstruction(insn, 40, 3);
41138 MI.addOperand(MCOperand::createImm(tmp));
41139 tmp = fieldFromInstruction(insn, 43, 2);
41140 MI.addOperand(MCOperand::createImm(tmp));
41141 tmp = fieldFromInstruction(insn, 48, 3);
41142 MI.addOperand(MCOperand::createImm(tmp));
41143 tmp = fieldFromInstruction(insn, 56, 3);
41144 MI.addOperand(MCOperand::createImm(tmp));
41147 tmp = fieldFromInstruction(insn, 17, 8);
41148 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41149 tmp = fieldFromInstruction(insn, 52, 2);
41150 MI.addOperand(MCOperand::createImm(tmp));
41151 tmp = fieldFromInstruction(insn, 32, 8);
41152 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41153 tmp = fieldFromInstruction(insn, 60, 2);
41154 MI.addOperand(MCOperand::createImm(tmp));
41155 tmp = fieldFromInstruction(insn, 9, 8);
41156 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41157 tmp = fieldFromInstruction(insn, 17, 8);
41158 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41159 tmp = fieldFromInstruction(insn, 45, 1);
41160 MI.addOperand(MCOperand::createImm(tmp));
41161 tmp = fieldFromInstruction(insn, 40, 3);
41162 MI.addOperand(MCOperand::createImm(tmp));
41163 tmp = fieldFromInstruction(insn, 43, 2);
41164 MI.addOperand(MCOperand::createImm(tmp));
41165 tmp = fieldFromInstruction(insn, 48, 3);
41166 MI.addOperand(MCOperand::createImm(tmp));
41167 tmp = fieldFromInstruction(insn, 56, 3);
41168 MI.addOperand(MCOperand::createImm(tmp));
41171 tmp = fieldFromInstruction(insn, 17, 8);
41172 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41173 tmp = fieldFromInstruction(insn, 51, 1);
41174 MI.addOperand(MCOperand::createImm(tmp));
41175 tmp = fieldFromInstruction(insn, 32, 8);
41176 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41177 tmp = fieldFromInstruction(insn, 59, 1);
41178 MI.addOperand(MCOperand::createImm(tmp));
41179 tmp = fieldFromInstruction(insn, 9, 8);
41180 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41181 tmp = fieldFromInstruction(insn, 45, 1);
41182 MI.addOperand(MCOperand::createImm(tmp));
41183 tmp = fieldFromInstruction(insn, 40, 3);
41184 MI.addOperand(MCOperand::createImm(tmp));
41185 tmp = fieldFromInstruction(insn, 43, 2);
41186 MI.addOperand(MCOperand::createImm(tmp));
41187 tmp = fieldFromInstruction(insn, 48, 3);
41188 MI.addOperand(MCOperand::createImm(tmp));
41189 tmp = fieldFromInstruction(insn, 56, 3);
41190 MI.addOperand(MCOperand::createImm(tmp));
41193 tmp = fieldFromInstruction(insn, 17, 8);
41194 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41195 tmp = fieldFromInstruction(insn, 52, 2);
41196 MI.addOperand(MCOperand::createImm(tmp));
41197 tmp = fieldFromInstruction(insn, 32, 8);
41198 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41199 tmp = fieldFromInstruction(insn, 59, 1);
41200 MI.addOperand(MCOperand::createImm(tmp));
41201 tmp = fieldFromInstruction(insn, 9, 8);
41202 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41203 tmp = fieldFromInstruction(insn, 45, 1);
41204 MI.addOperand(MCOperand::createImm(tmp));
41205 tmp = fieldFromInstruction(insn, 40, 3);
41206 MI.addOperand(MCOperand::createImm(tmp));
41207 tmp = fieldFromInstruction(insn, 43, 2);
41208 MI.addOperand(MCOperand::createImm(tmp));
41209 tmp = fieldFromInstruction(insn, 48, 3);
41210 MI.addOperand(MCOperand::createImm(tmp));
41211 tmp = fieldFromInstruction(insn, 56, 3);
41212 MI.addOperand(MCOperand::createImm(tmp));
41215 tmp = fieldFromInstruction(insn, 52, 2);
41216 MI.addOperand(MCOperand::createImm(tmp));
41217 tmp = fieldFromInstruction(insn, 32, 8);
41218 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41219 tmp = fieldFromInstruction(insn, 59, 1);
41220 MI.addOperand(MCOperand::createImm(tmp));
41221 tmp = fieldFromInstruction(insn, 9, 8);
41222 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41223 tmp = fieldFromInstruction(insn, 45, 1);
41224 MI.addOperand(MCOperand::createImm(tmp));
41225 tmp = fieldFromInstruction(insn, 48, 3);
41226 MI.addOperand(MCOperand::createImm(tmp));
41227 tmp = fieldFromInstruction(insn, 56, 3);
41228 MI.addOperand(MCOperand::createImm(tmp));
41231 tmp = fieldFromInstruction(insn, 52, 2);
41232 MI.addOperand(MCOperand::createImm(tmp));
41233 tmp = fieldFromInstruction(insn, 32, 8);
41234 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41235 tmp = fieldFromInstruction(insn, 59, 1);
41236 MI.addOperand(MCOperand::createImm(tmp));
41237 tmp = fieldFromInstruction(insn, 9, 8);
41238 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41239 tmp = fieldFromInstruction(insn, 45, 1);
41240 MI.addOperand(MCOperand::createImm(tmp));
41241 tmp = fieldFromInstruction(insn, 48, 3);
41242 MI.addOperand(MCOperand::createImm(tmp));
41243 tmp = fieldFromInstruction(insn, 56, 3);
41244 MI.addOperand(MCOperand::createImm(tmp));
41247 tmp = fieldFromInstruction(insn, 52, 2);
41248 MI.addOperand(MCOperand::createImm(tmp));
41249 tmp = fieldFromInstruction(insn, 32, 8);
41250 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41251 tmp = fieldFromInstruction(insn, 60, 2);
41252 MI.addOperand(MCOperand::createImm(tmp));
41253 tmp = fieldFromInstruction(insn, 9, 8);
41254 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41255 tmp = fieldFromInstruction(insn, 45, 1);
41256 MI.addOperand(MCOperand::createImm(tmp));
41257 tmp = fieldFromInstruction(insn, 48, 3);
41258 MI.addOperand(MCOperand::createImm(tmp));
41259 tmp = fieldFromInstruction(insn, 56, 3);
41260 MI.addOperand(MCOperand::createImm(tmp));
41263 tmp = fieldFromInstruction(insn, 52, 2);
41264 MI.addOperand(MCOperand::createImm(tmp));
41265 tmp = fieldFromInstruction(insn, 32, 8);
41266 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41267 tmp = fieldFromInstruction(insn, 60, 2);
41268 MI.addOperand(MCOperand::createImm(tmp));
41269 tmp = fieldFromInstruction(insn, 9, 8);
41270 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41271 tmp = fieldFromInstruction(insn, 45, 1);
41272 MI.addOperand(MCOperand::createImm(tmp));
41273 tmp = fieldFromInstruction(insn, 48, 3);
41274 MI.addOperand(MCOperand::createImm(tmp));
41275 tmp = fieldFromInstruction(insn, 56, 3);
41276 MI.addOperand(MCOperand::createImm(tmp));
41279 tmp = fieldFromInstruction(insn, 51, 1);
41280 MI.addOperand(MCOperand::createImm(tmp));
41281 tmp = fieldFromInstruction(insn, 32, 8);
41282 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41283 tmp = fieldFromInstruction(insn, 59, 1);
41284 MI.addOperand(MCOperand::createImm(tmp));
41285 tmp = fieldFromInstruction(insn, 9, 8);
41286 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41287 tmp = fieldFromInstruction(insn, 45, 1);
41288 MI.addOperand(MCOperand::createImm(tmp));
41289 tmp = fieldFromInstruction(insn, 48, 3);
41290 MI.addOperand(MCOperand::createImm(tmp));
41291 tmp = fieldFromInstruction(insn, 56, 3);
41292 MI.addOperand(MCOperand::createImm(tmp));
41295 tmp = fieldFromInstruction(insn, 51, 1);
41296 MI.addOperand(MCOperand::createImm(tmp));
41297 tmp = fieldFromInstruction(insn, 32, 8);
41298 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41299 tmp = fieldFromInstruction(insn, 59, 1);
41300 MI.addOperand(MCOperand::createImm(tmp));
41301 tmp = fieldFromInstruction(insn, 9, 8);
41302 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41303 tmp = fieldFromInstruction(insn, 45, 1);
41304 MI.addOperand(MCOperand::createImm(tmp));
41305 tmp = fieldFromInstruction(insn, 48, 3);
41306 MI.addOperand(MCOperand::createImm(tmp));
41307 tmp = fieldFromInstruction(insn, 56, 3);
41308 MI.addOperand(MCOperand::createImm(tmp));
41311 tmp = fieldFromInstruction(insn, 17, 8);
41312 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41313 tmp = fieldFromInstruction(insn, 51, 1);
41314 MI.addOperand(MCOperand::createImm(tmp));
41315 tmp = fieldFromInstruction(insn, 32, 8);
41316 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41317 tmp = fieldFromInstruction(insn, 45, 1);
41318 MI.addOperand(MCOperand::createImm(tmp));
41319 tmp = fieldFromInstruction(insn, 40, 3);
41320 MI.addOperand(MCOperand::createImm(tmp));
41321 tmp = fieldFromInstruction(insn, 43, 2);
41322 MI.addOperand(MCOperand::createImm(tmp));
41323 tmp = fieldFromInstruction(insn, 48, 3);
41324 MI.addOperand(MCOperand::createImm(tmp));
41327 tmp = fieldFromInstruction(insn, 17, 8);
41328 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41329 tmp = fieldFromInstruction(insn, 52, 2);
41330 MI.addOperand(MCOperand::createImm(tmp));
41331 tmp = fieldFromInstruction(insn, 32, 8);
41332 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41333 tmp = fieldFromInstruction(insn, 45, 1);
41334 MI.addOperand(MCOperand::createImm(tmp));
41335 tmp = fieldFromInstruction(insn, 40, 3);
41336 MI.addOperand(MCOperand::createImm(tmp));
41337 tmp = fieldFromInstruction(insn, 43, 2);
41338 MI.addOperand(MCOperand::createImm(tmp));
41339 tmp = fieldFromInstruction(insn, 48, 3);
41340 MI.addOperand(MCOperand::createImm(tmp));
41343 tmp = fieldFromInstruction(insn, 17, 8);
41344 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41345 tmp = fieldFromInstruction(insn, 52, 2);
41346 MI.addOperand(MCOperand::createImm(tmp));
41347 tmp = fieldFromInstruction(insn, 32, 8);
41348 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41349 tmp = fieldFromInstruction(insn, 45, 1);
41350 MI.addOperand(MCOperand::createImm(tmp));
41351 tmp = fieldFromInstruction(insn, 40, 3);
41352 MI.addOperand(MCOperand::createImm(tmp));
41353 tmp = fieldFromInstruction(insn, 43, 2);
41354 MI.addOperand(MCOperand::createImm(tmp));
41355 tmp = fieldFromInstruction(insn, 48, 3);
41356 MI.addOperand(MCOperand::createImm(tmp));
41359 tmp = fieldFromInstruction(insn, 17, 8);
41360 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41361 tmp = fieldFromInstruction(insn, 51, 1);
41362 MI.addOperand(MCOperand::createImm(tmp));
41363 tmp = fieldFromInstruction(insn, 32, 8);
41364 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41365 tmp = fieldFromInstruction(insn, 45, 1);
41366 MI.addOperand(MCOperand::createImm(tmp));
41367 tmp = fieldFromInstruction(insn, 40, 3);
41368 MI.addOperand(MCOperand::createImm(tmp));
41369 tmp = fieldFromInstruction(insn, 43, 2);
41370 MI.addOperand(MCOperand::createImm(tmp));
41371 tmp = fieldFromInstruction(insn, 48, 3);
41372 MI.addOperand(MCOperand::createImm(tmp));
41375 tmp = fieldFromInstruction(insn, 17, 8);
41376 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41377 tmp = fieldFromInstruction(insn, 51, 1);
41378 MI.addOperand(MCOperand::createImm(tmp));
41379 tmp = 0x0;
41380 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41381 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41382 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41383 tmp = fieldFromInstruction(insn, 59, 1);
41384 MI.addOperand(MCOperand::createImm(tmp));
41385 tmp = 0x0;
41386 tmp |= fieldFromInstruction(insn, 9, 8) << 0;
41387 tmp |= fieldFromInstruction(insn, 63, 1) << 8;
41388 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41389 tmp = fieldFromInstruction(insn, 45, 1);
41390 MI.addOperand(MCOperand::createImm(tmp));
41391 tmp = fieldFromInstruction(insn, 40, 3);
41392 MI.addOperand(MCOperand::createImm(tmp));
41393 tmp = fieldFromInstruction(insn, 43, 2);
41394 MI.addOperand(MCOperand::createImm(tmp));
41395 tmp = fieldFromInstruction(insn, 48, 3);
41396 MI.addOperand(MCOperand::createImm(tmp));
41397 tmp = fieldFromInstruction(insn, 56, 3);
41398 MI.addOperand(MCOperand::createImm(tmp));
41401 tmp = fieldFromInstruction(insn, 17, 8);
41402 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41403 tmp = fieldFromInstruction(insn, 17, 8);
41404 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41405 tmp = fieldFromInstruction(insn, 52, 2);
41406 MI.addOperand(MCOperand::createImm(tmp));
41407 tmp = fieldFromInstruction(insn, 32, 8);
41408 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41409 tmp = fieldFromInstruction(insn, 54, 2);
41410 MI.addOperand(MCOperand::createImm(tmp));
41411 tmp = fieldFromInstruction(insn, 9, 8);
41412 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41413 tmp = fieldFromInstruction(insn, 40, 9);
41414 MI.addOperand(MCOperand::createImm(tmp));
41415 tmp = fieldFromInstruction(insn, 60, 4);
41416 MI.addOperand(MCOperand::createImm(tmp));
41417 tmp = fieldFromInstruction(insn, 56, 4);
41418 MI.addOperand(MCOperand::createImm(tmp));
41419 tmp = fieldFromInstruction(insn, 51, 1);
41420 MI.addOperand(MCOperand::createImm(tmp));
41421 tmp = fieldFromInstruction(insn, 50, 1);
41422 MI.addOperand(MCOperand::createImm(tmp));
41425 tmp = fieldFromInstruction(insn, 17, 8);
41426 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41427 tmp = fieldFromInstruction(insn, 52, 2);
41428 MI.addOperand(MCOperand::createImm(tmp));
41429 tmp = fieldFromInstruction(insn, 32, 8);
41430 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41431 tmp = fieldFromInstruction(insn, 54, 2);
41432 MI.addOperand(MCOperand::createImm(tmp));
41433 tmp = fieldFromInstruction(insn, 9, 8);
41434 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41435 tmp = fieldFromInstruction(insn, 17, 8);
41436 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41437 tmp = fieldFromInstruction(insn, 40, 9);
41438 MI.addOperand(MCOperand::createImm(tmp));
41439 tmp = fieldFromInstruction(insn, 60, 4);
41440 MI.addOperand(MCOperand::createImm(tmp));
41441 tmp = fieldFromInstruction(insn, 56, 4);
41442 MI.addOperand(MCOperand::createImm(tmp));
41443 tmp = fieldFromInstruction(insn, 51, 1);
41444 MI.addOperand(MCOperand::createImm(tmp));
41445 tmp = fieldFromInstruction(insn, 50, 1);
41446 MI.addOperand(MCOperand::createImm(tmp));
41449 tmp = fieldFromInstruction(insn, 17, 8);
41450 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41451 tmp = fieldFromInstruction(insn, 52, 2);
41452 MI.addOperand(MCOperand::createImm(tmp));
41453 tmp = 0x0;
41454 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41455 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41456 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41457 tmp = fieldFromInstruction(insn, 60, 2);
41458 MI.addOperand(MCOperand::createImm(tmp));
41459 tmp = 0x0;
41460 tmp |= fieldFromInstruction(insn, 9, 8) << 0;
41461 tmp |= fieldFromInstruction(insn, 63, 1) << 8;
41462 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41463 tmp = fieldFromInstruction(insn, 45, 1);
41464 MI.addOperand(MCOperand::createImm(tmp));
41465 tmp = fieldFromInstruction(insn, 46, 2);
41466 MI.addOperand(MCOperand::createImm(tmp));
41467 tmp = fieldFromInstruction(insn, 40, 3);
41468 MI.addOperand(MCOperand::createImm(tmp));
41469 tmp = fieldFromInstruction(insn, 43, 2);
41470 MI.addOperand(MCOperand::createImm(tmp));
41471 tmp = fieldFromInstruction(insn, 48, 3);
41472 MI.addOperand(MCOperand::createImm(tmp));
41473 tmp = fieldFromInstruction(insn, 56, 3);
41474 MI.addOperand(MCOperand::createImm(tmp));
41477 tmp = fieldFromInstruction(insn, 17, 8);
41478 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41479 tmp = fieldFromInstruction(insn, 17, 8);
41480 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41481 tmp = fieldFromInstruction(insn, 32, 8);
41482 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41483 tmp = fieldFromInstruction(insn, 9, 8);
41484 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41485 tmp = fieldFromInstruction(insn, 40, 9);
41486 MI.addOperand(MCOperand::createImm(tmp));
41487 tmp = fieldFromInstruction(insn, 60, 4);
41488 MI.addOperand(MCOperand::createImm(tmp));
41489 tmp = fieldFromInstruction(insn, 56, 4);
41490 MI.addOperand(MCOperand::createImm(tmp));
41491 tmp = fieldFromInstruction(insn, 51, 1);
41492 MI.addOperand(MCOperand::createImm(tmp));
41493 tmp = fieldFromInstruction(insn, 50, 1);
41494 MI.addOperand(MCOperand::createImm(tmp));
41497 tmp = fieldFromInstruction(insn, 17, 8);
41498 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41499 tmp = fieldFromInstruction(insn, 52, 2);
41500 MI.addOperand(MCOperand::createImm(tmp));
41501 tmp = 0x0;
41502 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41503 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41504 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41505 tmp = fieldFromInstruction(insn, 60, 2);
41506 MI.addOperand(MCOperand::createImm(tmp));
41507 tmp = 0x0;
41508 tmp |= fieldFromInstruction(insn, 9, 8) << 0;
41509 tmp |= fieldFromInstruction(insn, 63, 1) << 8;
41510 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41511 tmp = fieldFromInstruction(insn, 45, 1);
41512 MI.addOperand(MCOperand::createImm(tmp));
41513 tmp = fieldFromInstruction(insn, 46, 2);
41514 MI.addOperand(MCOperand::createImm(tmp));
41515 tmp = fieldFromInstruction(insn, 40, 3);
41516 MI.addOperand(MCOperand::createImm(tmp));
41517 tmp = fieldFromInstruction(insn, 43, 2);
41518 MI.addOperand(MCOperand::createImm(tmp));
41519 tmp = fieldFromInstruction(insn, 48, 3);
41520 MI.addOperand(MCOperand::createImm(tmp));
41521 tmp = fieldFromInstruction(insn, 56, 3);
41522 MI.addOperand(MCOperand::createImm(tmp));
41525 tmp = fieldFromInstruction(insn, 17, 8);
41526 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41527 tmp = fieldFromInstruction(insn, 52, 2);
41528 MI.addOperand(MCOperand::createImm(tmp));
41529 tmp = 0x0;
41530 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41531 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41532 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41533 tmp = fieldFromInstruction(insn, 59, 1);
41534 MI.addOperand(MCOperand::createImm(tmp));
41535 tmp = 0x0;
41536 tmp |= fieldFromInstruction(insn, 9, 8) << 0;
41537 tmp |= fieldFromInstruction(insn, 63, 1) << 8;
41538 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41539 tmp = fieldFromInstruction(insn, 45, 1);
41540 MI.addOperand(MCOperand::createImm(tmp));
41541 tmp = fieldFromInstruction(insn, 46, 2);
41542 MI.addOperand(MCOperand::createImm(tmp));
41543 tmp = fieldFromInstruction(insn, 40, 3);
41544 MI.addOperand(MCOperand::createImm(tmp));
41545 tmp = fieldFromInstruction(insn, 43, 2);
41546 MI.addOperand(MCOperand::createImm(tmp));
41547 tmp = fieldFromInstruction(insn, 48, 3);
41548 MI.addOperand(MCOperand::createImm(tmp));
41549 tmp = fieldFromInstruction(insn, 56, 3);
41550 MI.addOperand(MCOperand::createImm(tmp));
41553 tmp = fieldFromInstruction(insn, 40, 8);
41554 if (decodeSDWAVopcDst(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41555 tmp = fieldFromInstruction(insn, 52, 2);
41556 MI.addOperand(MCOperand::createImm(tmp));
41557 tmp = 0x0;
41558 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41559 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41560 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41561 tmp = fieldFromInstruction(insn, 60, 2);
41562 MI.addOperand(MCOperand::createImm(tmp));
41563 tmp = 0x0;
41564 tmp |= fieldFromInstruction(insn, 9, 8) << 0;
41565 tmp |= fieldFromInstruction(insn, 63, 1) << 8;
41566 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41567 tmp = fieldFromInstruction(insn, 48, 3);
41568 MI.addOperand(MCOperand::createImm(tmp));
41569 tmp = fieldFromInstruction(insn, 56, 3);
41570 MI.addOperand(MCOperand::createImm(tmp));
41573 tmp = fieldFromInstruction(insn, 52, 2);
41574 MI.addOperand(MCOperand::createImm(tmp));
41575 tmp = 0x0;
41576 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41577 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41578 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41579 tmp = fieldFromInstruction(insn, 60, 2);
41580 MI.addOperand(MCOperand::createImm(tmp));
41581 tmp = 0x0;
41582 tmp |= fieldFromInstruction(insn, 9, 8) << 0;
41583 tmp |= fieldFromInstruction(insn, 63, 1) << 8;
41584 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41585 tmp = fieldFromInstruction(insn, 48, 3);
41586 MI.addOperand(MCOperand::createImm(tmp));
41587 tmp = fieldFromInstruction(insn, 56, 3);
41588 MI.addOperand(MCOperand::createImm(tmp));
41591 tmp = fieldFromInstruction(insn, 40, 8);
41592 if (decodeSDWAVopcDst(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41593 tmp = fieldFromInstruction(insn, 51, 1);
41594 MI.addOperand(MCOperand::createImm(tmp));
41595 tmp = 0x0;
41596 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41597 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41598 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41599 tmp = fieldFromInstruction(insn, 59, 1);
41600 MI.addOperand(MCOperand::createImm(tmp));
41601 tmp = 0x0;
41602 tmp |= fieldFromInstruction(insn, 9, 8) << 0;
41603 tmp |= fieldFromInstruction(insn, 63, 1) << 8;
41604 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41605 tmp = fieldFromInstruction(insn, 48, 3);
41606 MI.addOperand(MCOperand::createImm(tmp));
41607 tmp = fieldFromInstruction(insn, 56, 3);
41608 MI.addOperand(MCOperand::createImm(tmp));
41611 tmp = fieldFromInstruction(insn, 40, 8);
41612 if (decodeSDWAVopcDst(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41613 tmp = fieldFromInstruction(insn, 52, 2);
41614 MI.addOperand(MCOperand::createImm(tmp));
41615 tmp = 0x0;
41616 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41617 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41618 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41619 tmp = fieldFromInstruction(insn, 59, 1);
41620 MI.addOperand(MCOperand::createImm(tmp));
41621 tmp = 0x0;
41622 tmp |= fieldFromInstruction(insn, 9, 8) << 0;
41623 tmp |= fieldFromInstruction(insn, 63, 1) << 8;
41624 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41625 tmp = fieldFromInstruction(insn, 48, 3);
41626 MI.addOperand(MCOperand::createImm(tmp));
41627 tmp = fieldFromInstruction(insn, 56, 3);
41628 MI.addOperand(MCOperand::createImm(tmp));
41631 tmp = fieldFromInstruction(insn, 40, 8);
41632 if (decodeSDWAVopcDst(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41633 tmp = fieldFromInstruction(insn, 51, 1);
41634 MI.addOperand(MCOperand::createImm(tmp));
41635 tmp = 0x0;
41636 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41637 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41638 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41639 tmp = fieldFromInstruction(insn, 59, 1);
41640 MI.addOperand(MCOperand::createImm(tmp));
41641 tmp = 0x0;
41642 tmp |= fieldFromInstruction(insn, 9, 8) << 0;
41643 tmp |= fieldFromInstruction(insn, 63, 1) << 8;
41644 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41645 tmp = fieldFromInstruction(insn, 48, 3);
41646 MI.addOperand(MCOperand::createImm(tmp));
41647 tmp = fieldFromInstruction(insn, 56, 3);
41648 MI.addOperand(MCOperand::createImm(tmp));
41651 tmp = fieldFromInstruction(insn, 40, 8);
41652 if (decodeSDWAVopcDst(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41653 tmp = fieldFromInstruction(insn, 52, 2);
41654 MI.addOperand(MCOperand::createImm(tmp));
41655 tmp = 0x0;
41656 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41657 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41658 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41659 tmp = fieldFromInstruction(insn, 59, 1);
41660 MI.addOperand(MCOperand::createImm(tmp));
41661 tmp = 0x0;
41662 tmp |= fieldFromInstruction(insn, 9, 8) << 0;
41663 tmp |= fieldFromInstruction(insn, 63, 1) << 8;
41664 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41665 tmp = fieldFromInstruction(insn, 48, 3);
41666 MI.addOperand(MCOperand::createImm(tmp));
41667 tmp = fieldFromInstruction(insn, 56, 3);
41668 MI.addOperand(MCOperand::createImm(tmp));
41671 tmp = fieldFromInstruction(insn, 51, 1);
41672 MI.addOperand(MCOperand::createImm(tmp));
41673 tmp = 0x0;
41674 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41675 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41676 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41677 tmp = fieldFromInstruction(insn, 59, 1);
41678 MI.addOperand(MCOperand::createImm(tmp));
41679 tmp = 0x0;
41680 tmp |= fieldFromInstruction(insn, 9, 8) << 0;
41681 tmp |= fieldFromInstruction(insn, 63, 1) << 8;
41682 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41683 tmp = fieldFromInstruction(insn, 48, 3);
41684 MI.addOperand(MCOperand::createImm(tmp));
41685 tmp = fieldFromInstruction(insn, 56, 3);
41686 MI.addOperand(MCOperand::createImm(tmp));
41689 tmp = fieldFromInstruction(insn, 52, 2);
41690 MI.addOperand(MCOperand::createImm(tmp));
41691 tmp = 0x0;
41692 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41693 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41694 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41695 tmp = fieldFromInstruction(insn, 59, 1);
41696 MI.addOperand(MCOperand::createImm(tmp));
41697 tmp = 0x0;
41698 tmp |= fieldFromInstruction(insn, 9, 8) << 0;
41699 tmp |= fieldFromInstruction(insn, 63, 1) << 8;
41700 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41701 tmp = fieldFromInstruction(insn, 48, 3);
41702 MI.addOperand(MCOperand::createImm(tmp));
41703 tmp = fieldFromInstruction(insn, 56, 3);
41704 MI.addOperand(MCOperand::createImm(tmp));
41707 tmp = fieldFromInstruction(insn, 51, 1);
41708 MI.addOperand(MCOperand::createImm(tmp));
41709 tmp = 0x0;
41710 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41711 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41712 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41713 tmp = fieldFromInstruction(insn, 59, 1);
41714 MI.addOperand(MCOperand::createImm(tmp));
41715 tmp = 0x0;
41716 tmp |= fieldFromInstruction(insn, 9, 8) << 0;
41717 tmp |= fieldFromInstruction(insn, 63, 1) << 8;
41718 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41719 tmp = fieldFromInstruction(insn, 48, 3);
41720 MI.addOperand(MCOperand::createImm(tmp));
41721 tmp = fieldFromInstruction(insn, 56, 3);
41722 MI.addOperand(MCOperand::createImm(tmp));
41725 tmp = fieldFromInstruction(insn, 52, 2);
41726 MI.addOperand(MCOperand::createImm(tmp));
41727 tmp = 0x0;
41728 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41729 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41730 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41731 tmp = fieldFromInstruction(insn, 59, 1);
41732 MI.addOperand(MCOperand::createImm(tmp));
41733 tmp = 0x0;
41734 tmp |= fieldFromInstruction(insn, 9, 8) << 0;
41735 tmp |= fieldFromInstruction(insn, 63, 1) << 8;
41736 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41737 tmp = fieldFromInstruction(insn, 48, 3);
41738 MI.addOperand(MCOperand::createImm(tmp));
41739 tmp = fieldFromInstruction(insn, 56, 3);
41740 MI.addOperand(MCOperand::createImm(tmp));
41743 tmp = fieldFromInstruction(insn, 40, 8);
41744 if (decodeSDWAVopcDst(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41745 tmp = fieldFromInstruction(insn, 52, 2);
41746 MI.addOperand(MCOperand::createImm(tmp));
41747 tmp = 0x0;
41748 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41749 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41750 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41751 tmp = fieldFromInstruction(insn, 60, 2);
41752 MI.addOperand(MCOperand::createImm(tmp));
41753 tmp = 0x0;
41754 tmp |= fieldFromInstruction(insn, 9, 8) << 0;
41755 tmp |= fieldFromInstruction(insn, 63, 1) << 8;
41756 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41757 tmp = fieldFromInstruction(insn, 48, 3);
41758 MI.addOperand(MCOperand::createImm(tmp));
41759 tmp = fieldFromInstruction(insn, 56, 3);
41760 MI.addOperand(MCOperand::createImm(tmp));
41763 tmp = fieldFromInstruction(insn, 52, 2);
41764 MI.addOperand(MCOperand::createImm(tmp));
41765 tmp = 0x0;
41766 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41767 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41768 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41769 tmp = fieldFromInstruction(insn, 60, 2);
41770 MI.addOperand(MCOperand::createImm(tmp));
41771 tmp = 0x0;
41772 tmp |= fieldFromInstruction(insn, 9, 8) << 0;
41773 tmp |= fieldFromInstruction(insn, 63, 1) << 8;
41774 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41775 tmp = fieldFromInstruction(insn, 48, 3);
41776 MI.addOperand(MCOperand::createImm(tmp));
41777 tmp = fieldFromInstruction(insn, 56, 3);
41778 MI.addOperand(MCOperand::createImm(tmp));
41781 tmp = fieldFromInstruction(insn, 17, 8);
41782 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41783 tmp = fieldFromInstruction(insn, 51, 1);
41784 MI.addOperand(MCOperand::createImm(tmp));
41785 tmp = 0x0;
41786 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41787 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41788 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41789 tmp = fieldFromInstruction(insn, 45, 1);
41790 MI.addOperand(MCOperand::createImm(tmp));
41791 tmp = fieldFromInstruction(insn, 40, 3);
41792 MI.addOperand(MCOperand::createImm(tmp));
41793 tmp = fieldFromInstruction(insn, 43, 2);
41794 MI.addOperand(MCOperand::createImm(tmp));
41795 tmp = fieldFromInstruction(insn, 48, 3);
41796 MI.addOperand(MCOperand::createImm(tmp));
41799 tmp = fieldFromInstruction(insn, 17, 8);
41800 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41801 tmp = fieldFromInstruction(insn, 17, 8);
41802 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41803 tmp = fieldFromInstruction(insn, 32, 8);
41804 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41805 tmp = fieldFromInstruction(insn, 40, 9);
41806 MI.addOperand(MCOperand::createImm(tmp));
41807 tmp = fieldFromInstruction(insn, 60, 4);
41808 MI.addOperand(MCOperand::createImm(tmp));
41809 tmp = fieldFromInstruction(insn, 56, 4);
41810 MI.addOperand(MCOperand::createImm(tmp));
41811 tmp = fieldFromInstruction(insn, 51, 1);
41812 MI.addOperand(MCOperand::createImm(tmp));
41813 tmp = fieldFromInstruction(insn, 50, 1);
41814 MI.addOperand(MCOperand::createImm(tmp));
41817 tmp = fieldFromInstruction(insn, 17, 8);
41818 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41819 tmp = fieldFromInstruction(insn, 51, 1);
41820 MI.addOperand(MCOperand::createImm(tmp));
41821 tmp = 0x0;
41822 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41823 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41824 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41825 tmp = fieldFromInstruction(insn, 45, 1);
41826 MI.addOperand(MCOperand::createImm(tmp));
41827 tmp = fieldFromInstruction(insn, 46, 2);
41828 MI.addOperand(MCOperand::createImm(tmp));
41829 tmp = fieldFromInstruction(insn, 40, 3);
41830 MI.addOperand(MCOperand::createImm(tmp));
41831 tmp = fieldFromInstruction(insn, 43, 2);
41832 MI.addOperand(MCOperand::createImm(tmp));
41833 tmp = fieldFromInstruction(insn, 48, 3);
41834 MI.addOperand(MCOperand::createImm(tmp));
41837 tmp = fieldFromInstruction(insn, 17, 8);
41838 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41839 tmp = fieldFromInstruction(insn, 52, 2);
41840 MI.addOperand(MCOperand::createImm(tmp));
41841 tmp = 0x0;
41842 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41843 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41844 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41845 tmp = fieldFromInstruction(insn, 45, 1);
41846 MI.addOperand(MCOperand::createImm(tmp));
41847 tmp = fieldFromInstruction(insn, 40, 3);
41848 MI.addOperand(MCOperand::createImm(tmp));
41849 tmp = fieldFromInstruction(insn, 43, 2);
41850 MI.addOperand(MCOperand::createImm(tmp));
41851 tmp = fieldFromInstruction(insn, 48, 3);
41852 MI.addOperand(MCOperand::createImm(tmp));
41855 tmp = fieldFromInstruction(insn, 17, 8);
41856 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41857 tmp = fieldFromInstruction(insn, 17, 8);
41858 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41859 tmp = fieldFromInstruction(insn, 52, 2);
41860 MI.addOperand(MCOperand::createImm(tmp));
41861 tmp = fieldFromInstruction(insn, 32, 8);
41862 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41863 tmp = fieldFromInstruction(insn, 40, 9);
41864 MI.addOperand(MCOperand::createImm(tmp));
41865 tmp = fieldFromInstruction(insn, 60, 4);
41866 MI.addOperand(MCOperand::createImm(tmp));
41867 tmp = fieldFromInstruction(insn, 56, 4);
41868 MI.addOperand(MCOperand::createImm(tmp));
41869 tmp = fieldFromInstruction(insn, 51, 1);
41870 MI.addOperand(MCOperand::createImm(tmp));
41871 tmp = fieldFromInstruction(insn, 50, 1);
41872 MI.addOperand(MCOperand::createImm(tmp));
41875 tmp = fieldFromInstruction(insn, 17, 8);
41876 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41877 tmp = fieldFromInstruction(insn, 52, 2);
41878 MI.addOperand(MCOperand::createImm(tmp));
41879 tmp = 0x0;
41880 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41881 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41882 if (decodeSDWASrc32(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41883 tmp = fieldFromInstruction(insn, 45, 1);
41884 MI.addOperand(MCOperand::createImm(tmp));
41885 tmp = fieldFromInstruction(insn, 46, 2);
41886 MI.addOperand(MCOperand::createImm(tmp));
41887 tmp = fieldFromInstruction(insn, 40, 3);
41888 MI.addOperand(MCOperand::createImm(tmp));
41889 tmp = fieldFromInstruction(insn, 43, 2);
41890 MI.addOperand(MCOperand::createImm(tmp));
41891 tmp = fieldFromInstruction(insn, 48, 3);
41892 MI.addOperand(MCOperand::createImm(tmp));
41895 tmp = fieldFromInstruction(insn, 17, 8);
41896 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41897 tmp = fieldFromInstruction(insn, 52, 2);
41898 MI.addOperand(MCOperand::createImm(tmp));
41899 tmp = 0x0;
41900 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41901 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41902 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41903 tmp = fieldFromInstruction(insn, 45, 1);
41904 MI.addOperand(MCOperand::createImm(tmp));
41905 tmp = fieldFromInstruction(insn, 46, 2);
41906 MI.addOperand(MCOperand::createImm(tmp));
41907 tmp = fieldFromInstruction(insn, 40, 3);
41908 MI.addOperand(MCOperand::createImm(tmp));
41909 tmp = fieldFromInstruction(insn, 43, 2);
41910 MI.addOperand(MCOperand::createImm(tmp));
41911 tmp = fieldFromInstruction(insn, 48, 3);
41912 MI.addOperand(MCOperand::createImm(tmp));
41915 tmp = fieldFromInstruction(insn, 17, 8);
41916 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41917 tmp = fieldFromInstruction(insn, 51, 1);
41918 MI.addOperand(MCOperand::createImm(tmp));
41919 tmp = 0x0;
41920 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41921 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41922 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41923 tmp = fieldFromInstruction(insn, 45, 1);
41924 MI.addOperand(MCOperand::createImm(tmp));
41925 tmp = fieldFromInstruction(insn, 46, 2);
41926 MI.addOperand(MCOperand::createImm(tmp));
41927 tmp = fieldFromInstruction(insn, 40, 3);
41928 MI.addOperand(MCOperand::createImm(tmp));
41929 tmp = fieldFromInstruction(insn, 43, 2);
41930 MI.addOperand(MCOperand::createImm(tmp));
41931 tmp = fieldFromInstruction(insn, 48, 3);
41932 MI.addOperand(MCOperand::createImm(tmp));
41935 tmp = fieldFromInstruction(insn, 17, 8);
41936 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41937 tmp = fieldFromInstruction(insn, 52, 2);
41938 MI.addOperand(MCOperand::createImm(tmp));
41939 tmp = 0x0;
41940 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41941 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41942 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41943 tmp = fieldFromInstruction(insn, 45, 1);
41944 MI.addOperand(MCOperand::createImm(tmp));
41945 tmp = fieldFromInstruction(insn, 40, 3);
41946 MI.addOperand(MCOperand::createImm(tmp));
41947 tmp = fieldFromInstruction(insn, 43, 2);
41948 MI.addOperand(MCOperand::createImm(tmp));
41949 tmp = fieldFromInstruction(insn, 48, 3);
41950 MI.addOperand(MCOperand::createImm(tmp));
41953 tmp = fieldFromInstruction(insn, 17, 8);
41954 if (DecodeVGPR_32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41955 tmp = fieldFromInstruction(insn, 51, 1);
41956 MI.addOperand(MCOperand::createImm(tmp));
41957 tmp = 0x0;
41958 tmp |= fieldFromInstruction(insn, 32, 8) << 0;
41959 tmp |= fieldFromInstruction(insn, 55, 1) << 8;
41960 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41961 tmp = fieldFromInstruction(insn, 59, 1);
41962 MI.addOperand(MCOperand::createImm(tmp));
41963 tmp = 0x0;
41964 tmp |= fieldFromInstruction(insn, 9, 8) << 0;
41965 tmp |= fieldFromInstruction(insn, 63, 1) << 8;
41966 if (decodeSDWASrc16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
41967 tmp = fieldFromInstruction(insn, 45, 1);
41968 MI.addOperand(MCOperand::createImm(tmp));
41969 tmp = fieldFromInstruction(insn, 40, 3);
41970 MI.addOperand(MCOperand::createImm(tmp));
41971 tmp = fieldFromInstruction(insn, 43, 2);
41972 MI.addOperand(MCOperand::createImm(tmp));
41973 tmp = fieldFromInstruction(insn, 48, 3);
41974 MI.addOperand(MCOperand::createImm(tmp));
41975 tmp = fieldFromInstruction(insn, 56, 3);
41976 MI.addOperand(MCOperand::createImm(tmp));