|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 4478 return MCK_addr64; // "addr64"
9927 case MCK_addr64: return "MCK_addr64";
11083 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11090 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11113 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11120 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11139 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11146 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11165 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11172 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11191 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11198 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11217 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11224 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11243 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11250 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11269 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11276 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11293 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11298 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11311 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11316 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11329 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11334 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11347 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11352 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11365 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11370 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11383 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11388 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11403 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11410 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11429 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11436 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11455 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11462 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11481 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11488 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11511 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11518 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11537 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11544 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11563 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11570 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11589 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11596 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11615 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11622 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11641 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11648 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11667 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11674 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11693 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11700 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11719 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11726 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11745 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11752 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11771 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11778 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11797 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11804 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11823 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11830 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11849 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11856 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11877 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11878 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11901 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11918 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11935 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12006 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12007 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12029 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12042 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12055 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12071 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12072 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12129 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12130 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12155 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12156 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12197 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12198 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12220 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12241 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12254 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12267 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12280 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12345 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12358 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12371 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12384 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12398 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18702 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18715 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18728 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18741 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18802 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18815 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18828 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18841 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 6963 case MCK_addr64: