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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 5693 case MCK_VSrcV2F16: {
10098 case MCK_VSrcV2F16: return "MCK_VSrcV2F16";
21132 { 22781 /* v_dot2c_f32_f16 */, AMDGPU::V_DOT2C_F32_F16_e32_gfx10, Convert__Reg1_0__VSrcV2F161_1__Reg1_2__Tie0_1_1, AMFBS_HasDot5Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VGPR_32 }, },
21133 { 22781 /* v_dot2c_f32_f16 */, AMDGPU::V_DOT2C_F32_F16_e32_vi, Convert__Reg1_0__VSrcV2F161_1__Reg1_2__Tie0_1_1, AMFBS_HasDot5Insts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VGPR_32 }, },
21317 { 25353 /* v_pk_fmac_f16 */, AMDGPU::V_PK_FMAC_F16_e32_gfx10, Convert__Reg1_0__VSrcV2F161_1__Reg1_2, AMFBS_HasPkFmacF16Inst_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VGPR_32 }, },
21318 { 25353 /* v_pk_fmac_f16 */, AMDGPU::V_PK_FMAC_F16_e32_vi, Convert__Reg1_0__VSrcV2F161_1__Reg1_2, AMFBS_HasPkFmacF16Inst_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VGPR_32 }, },
22250 { 22736 /* v_dot2_f32_f16 */, AMDGPU::V_DOT2_F32_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_VSrcF32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22250 { 22736 /* v_dot2_f32_f16 */, AMDGPU::V_DOT2_F32_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_VSrcF32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22251 { 22736 /* v_dot2_f32_f16 */, AMDGPU::V_DOT2_F32_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_VSrcF32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22251 { 22736 /* v_dot2_f32_f16 */, AMDGPU::V_DOT2_F32_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_VSrcF32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22620 { 25284 /* v_pk_add_f16 */, AMDGPU::V_PK_ADD_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22620 { 25284 /* v_pk_add_f16 */, AMDGPU::V_PK_ADD_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22621 { 25284 /* v_pk_add_f16 */, AMDGPU::V_PK_ADD_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22621 { 25284 /* v_pk_add_f16 */, AMDGPU::V_PK_ADD_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22628 { 25340 /* v_pk_fma_f16 */, AMDGPU::V_PK_FMA_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22628 { 25340 /* v_pk_fma_f16 */, AMDGPU::V_PK_FMA_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22628 { 25340 /* v_pk_fma_f16 */, AMDGPU::V_PK_FMA_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22629 { 25340 /* v_pk_fma_f16 */, AMDGPU::V_PK_FMA_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22629 { 25340 /* v_pk_fma_f16 */, AMDGPU::V_PK_FMA_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22629 { 25340 /* v_pk_fma_f16 */, AMDGPU::V_PK_FMA_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22638 { 25427 /* v_pk_max_f16 */, AMDGPU::V_PK_MAX_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22638 { 25427 /* v_pk_max_f16 */, AMDGPU::V_PK_MAX_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22639 { 25427 /* v_pk_max_f16 */, AMDGPU::V_PK_MAX_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22639 { 25427 /* v_pk_max_f16 */, AMDGPU::V_PK_MAX_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22644 { 25466 /* v_pk_min_f16 */, AMDGPU::V_PK_MIN_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22644 { 25466 /* v_pk_min_f16 */, AMDGPU::V_PK_MIN_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22645 { 25466 /* v_pk_min_f16 */, AMDGPU::V_PK_MIN_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22645 { 25466 /* v_pk_min_f16 */, AMDGPU::V_PK_MIN_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22650 { 25505 /* v_pk_mul_f16 */, AMDGPU::V_PK_MUL_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22650 { 25505 /* v_pk_mul_f16 */, AMDGPU::V_PK_MUL_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22651 { 25505 /* v_pk_mul_f16 */, AMDGPU::V_PK_MUL_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22651 { 25505 /* v_pk_mul_f16 */, AMDGPU::V_PK_MUL_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },