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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 5665 case MCK_VSrcF16: {
10094 case MCK_VSrcF16: return "MCK_VSrcF16";
18857 { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
18858 { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
18885 { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
18886 { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
18896 { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
18897 { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
18898 { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
18899 { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
18900 { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
18901 { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
18902 { 13657 /* v_cmp_class_f16_e32 */, AMDGPU::V_CMP_CLASS_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
18903 { 13657 /* v_cmp_class_f16_e32 */, AMDGPU::V_CMP_CLASS_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
18928 { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
18929 { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
18930 { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
18931 { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
18932 { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
18933 { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
18934 { 13762 /* v_cmp_eq_f16_e32 */, AMDGPU::V_CMP_EQ_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
18935 { 13762 /* v_cmp_eq_f16_e32 */, AMDGPU::V_CMP_EQ_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19024 { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19025 { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19026 { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19027 { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19028 { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19029 { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19030 { 14031 /* v_cmp_f_f16_e32 */, AMDGPU::V_CMP_F_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19031 { 14031 /* v_cmp_f_f16_e32 */, AMDGPU::V_CMP_F_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19112 { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19113 { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19114 { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19115 { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19116 { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19117 { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19118 { 14284 /* v_cmp_ge_f16_e32 */, AMDGPU::V_CMP_GE_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19119 { 14284 /* v_cmp_ge_f16_e32 */, AMDGPU::V_CMP_GE_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19208 { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19209 { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19210 { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19211 { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19212 { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19213 { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19214 { 14554 /* v_cmp_gt_f16_e32 */, AMDGPU::V_CMP_GT_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19215 { 14554 /* v_cmp_gt_f16_e32 */, AMDGPU::V_CMP_GT_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19304 { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19305 { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19306 { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19307 { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19308 { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19309 { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19310 { 14824 /* v_cmp_le_f16_e32 */, AMDGPU::V_CMP_LE_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19311 { 14824 /* v_cmp_le_f16_e32 */, AMDGPU::V_CMP_LE_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19400 { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19401 { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19402 { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19403 { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19404 { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19405 { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19406 { 15094 /* v_cmp_lg_f16_e32 */, AMDGPU::V_CMP_LG_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19407 { 15094 /* v_cmp_lg_f16_e32 */, AMDGPU::V_CMP_LG_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19432 { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19433 { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19434 { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19435 { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19436 { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19437 { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19438 { 15184 /* v_cmp_lt_f16_e32 */, AMDGPU::V_CMP_LT_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19439 { 15184 /* v_cmp_lt_f16_e32 */, AMDGPU::V_CMP_LT_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19592 { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19593 { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19594 { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19595 { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19596 { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19597 { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19598 { 15635 /* v_cmp_neq_f16_e32 */, AMDGPU::V_CMP_NEQ_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19599 { 15635 /* v_cmp_neq_f16_e32 */, AMDGPU::V_CMP_NEQ_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19624 { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19625 { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19626 { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19627 { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19628 { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19629 { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19630 { 15731 /* v_cmp_nge_f16_e32 */, AMDGPU::V_CMP_NGE_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19631 { 15731 /* v_cmp_nge_f16_e32 */, AMDGPU::V_CMP_NGE_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19656 { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19657 { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19658 { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19659 { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19660 { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19661 { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19662 { 15827 /* v_cmp_ngt_f16_e32 */, AMDGPU::V_CMP_NGT_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19663 { 15827 /* v_cmp_ngt_f16_e32 */, AMDGPU::V_CMP_NGT_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19688 { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19689 { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19690 { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19691 { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19692 { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19693 { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19694 { 15923 /* v_cmp_nle_f16_e32 */, AMDGPU::V_CMP_NLE_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19695 { 15923 /* v_cmp_nle_f16_e32 */, AMDGPU::V_CMP_NLE_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19720 { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19721 { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19722 { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19723 { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19724 { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19725 { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19726 { 16019 /* v_cmp_nlg_f16_e32 */, AMDGPU::V_CMP_NLG_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19727 { 16019 /* v_cmp_nlg_f16_e32 */, AMDGPU::V_CMP_NLG_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19752 { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19753 { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19754 { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19755 { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19756 { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19757 { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19758 { 16115 /* v_cmp_nlt_f16_e32 */, AMDGPU::V_CMP_NLT_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19759 { 16115 /* v_cmp_nlt_f16_e32 */, AMDGPU::V_CMP_NLT_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19784 { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19785 { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19786 { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19787 { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19788 { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19789 { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19790 { 16209 /* v_cmp_o_f16_e32 */, AMDGPU::V_CMP_O_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19791 { 16209 /* v_cmp_o_f16_e32 */, AMDGPU::V_CMP_O_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19872 { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19873 { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19874 { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19875 { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19876 { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19877 { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19878 { 16463 /* v_cmp_tru_f16_e32 */, AMDGPU::V_CMP_TRU_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19879 { 16463 /* v_cmp_tru_f16_e32 */, AMDGPU::V_CMP_TRU_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19904 { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19905 { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
19906 { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19907 { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19908 { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19909 { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19910 { 16557 /* v_cmp_u_f16_e32 */, AMDGPU::V_CMP_U_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
19911 { 16557 /* v_cmp_u_f16_e32 */, AMDGPU::V_CMP_U_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20192 { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20193 { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20194 { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20195 { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20196 { 18790 /* v_cmpx_class_f16_e32 */, AMDGPU::V_CMPX_CLASS_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20197 { 18790 /* v_cmpx_class_f16_e32 */, AMDGPU::V_CMPX_CLASS_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20218 { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20219 { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20220 { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20221 { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20222 { 18901 /* v_cmpx_eq_f16_e32 */, AMDGPU::V_CMPX_EQ_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20223 { 18901 /* v_cmpx_eq_f16_e32 */, AMDGPU::V_CMPX_EQ_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20296 { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20297 { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20298 { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20299 { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20300 { 19188 /* v_cmpx_f_f16_e32 */, AMDGPU::V_CMPX_F_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20301 { 19188 /* v_cmpx_f_f16_e32 */, AMDGPU::V_CMPX_F_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20370 { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20371 { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20372 { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20373 { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20374 { 19459 /* v_cmpx_ge_f16_e32 */, AMDGPU::V_CMPX_GE_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20375 { 19459 /* v_cmpx_ge_f16_e32 */, AMDGPU::V_CMPX_GE_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20448 { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20449 { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20450 { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20451 { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20452 { 19747 /* v_cmpx_gt_f16_e32 */, AMDGPU::V_CMPX_GT_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20453 { 19747 /* v_cmpx_gt_f16_e32 */, AMDGPU::V_CMPX_GT_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20526 { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20527 { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20528 { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20529 { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20530 { 20035 /* v_cmpx_le_f16_e32 */, AMDGPU::V_CMPX_LE_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20531 { 20035 /* v_cmpx_le_f16_e32 */, AMDGPU::V_CMPX_LE_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20604 { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20605 { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20606 { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20607 { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20608 { 20323 /* v_cmpx_lg_f16_e32 */, AMDGPU::V_CMPX_LG_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20609 { 20323 /* v_cmpx_lg_f16_e32 */, AMDGPU::V_CMPX_LG_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20630 { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20631 { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20632 { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20633 { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20634 { 20419 /* v_cmpx_lt_f16_e32 */, AMDGPU::V_CMPX_LT_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20635 { 20419 /* v_cmpx_lt_f16_e32 */, AMDGPU::V_CMPX_LT_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20760 { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20761 { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20762 { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20763 { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20764 { 20900 /* v_cmpx_neq_f16_e32 */, AMDGPU::V_CMPX_NEQ_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20765 { 20900 /* v_cmpx_neq_f16_e32 */, AMDGPU::V_CMPX_NEQ_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20786 { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20787 { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20788 { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20789 { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20790 { 21002 /* v_cmpx_nge_f16_e32 */, AMDGPU::V_CMPX_NGE_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20791 { 21002 /* v_cmpx_nge_f16_e32 */, AMDGPU::V_CMPX_NGE_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20812 { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20813 { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20814 { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20815 { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20816 { 21104 /* v_cmpx_ngt_f16_e32 */, AMDGPU::V_CMPX_NGT_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20817 { 21104 /* v_cmpx_ngt_f16_e32 */, AMDGPU::V_CMPX_NGT_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20838 { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20839 { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20840 { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20841 { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20842 { 21206 /* v_cmpx_nle_f16_e32 */, AMDGPU::V_CMPX_NLE_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20843 { 21206 /* v_cmpx_nle_f16_e32 */, AMDGPU::V_CMPX_NLE_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20864 { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20865 { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20866 { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20867 { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20868 { 21308 /* v_cmpx_nlg_f16_e32 */, AMDGPU::V_CMPX_NLG_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20869 { 21308 /* v_cmpx_nlg_f16_e32 */, AMDGPU::V_CMPX_NLG_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20890 { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20891 { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20892 { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20893 { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20894 { 21410 /* v_cmpx_nlt_f16_e32 */, AMDGPU::V_CMPX_NLT_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20895 { 21410 /* v_cmpx_nlt_f16_e32 */, AMDGPU::V_CMPX_NLT_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20916 { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20917 { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20918 { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20919 { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20920 { 21510 /* v_cmpx_o_f16_e32 */, AMDGPU::V_CMPX_O_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20921 { 21510 /* v_cmpx_o_f16_e32 */, AMDGPU::V_CMPX_O_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20990 { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20991 { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
20992 { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20993 { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20994 { 21782 /* v_cmpx_tru_f16_e32 */, AMDGPU::V_CMPX_TRU_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
20995 { 21782 /* v_cmpx_tru_f16_e32 */, AMDGPU::V_CMPX_TRU_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
21016 { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
21017 { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
21018 { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
21019 { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
21020 { 21882 /* v_cmpx_u_f16_e32 */, AMDGPU::V_CMPX_U_F16_e32_gfx10, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcF16, MCK_VGPR_32 }, },
21021 { 21882 /* v_cmpx_u_f16_e32 */, AMDGPU::V_CMPX_U_F16_e32_vi, Convert__VSrcF161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcF16, MCK_VGPR_32 }, },
21051 { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21052 { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
21063 { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21064 { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF16 }, },
21065 { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
21099 { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21100 { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
21107 { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21108 { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
21109 { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21110 { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
21124 { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21125 { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
21138 { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21139 { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
21154 { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21155 { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
21164 { 23122 /* v_fmac_f16 */, AMDGPU::V_FMAC_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1__Reg1_2__Tie0_1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
21169 { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21170 { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
21177 { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21178 { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
21185 { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21186 { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
21205 { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
21206 { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
21209 { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21210 { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
21226 { 23695 /* v_mac_f16 */, AMDGPU::V_MAC_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2__Tie0_1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
21240 { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
21241 { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
21256 { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
21257 { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
21286 { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
21287 { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
21321 { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21322 { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
21337 { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21338 { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
21347 { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21348 { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
21359 { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21360 { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
21364 { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21365 { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },
21378 { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
21379 { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
21404 { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
21405 { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
21417 { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, },
21418 { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },