reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

 5672   case MCK_VSrcB32: {
10095   case MCK_VSrcB32: return "MCK_VSrcB32";
18851   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18852   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
18853   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
18854   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
18855   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
18856   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
18862   { 13291 /* v_add_i32 */, AMDGPU::V_ADD_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
18863   { 13355 /* v_add_nc_u32 */, AMDGPU::V_ADD_NC_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_HasAddNoCarryInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18865   { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_HasAddNoCarryInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18866   { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_e32_vi, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
18867   { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
18868   { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
18869   { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
18870   { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
18871   { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e32_vi, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
18872   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18873   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18874   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18875   { 13467 /* v_ashr_i32 */, AMDGPU::V_ASHR_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18877   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18878   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18879   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18880   { 13531 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18881   { 13576 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18882   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
18883   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
18884   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
18968   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
18969   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
18970   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
18971   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
18972   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
18973   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
18974   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
18975   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
18976   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
18977   { 13882 /* v_cmp_eq_i32_e32 */, AMDGPU::V_CMP_EQ_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
18978   { 13882 /* v_cmp_eq_i32_e32 */, AMDGPU::V_CMP_EQ_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
18979   { 13882 /* v_cmp_eq_i32_e32 */, AMDGPU::V_CMP_EQ_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19000   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19001   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19002   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19003   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19004   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19005   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19006   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19007   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19008   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19009   { 13972 /* v_cmp_eq_u32_e32 */, AMDGPU::V_CMP_EQ_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19010   { 13972 /* v_cmp_eq_u32_e32 */, AMDGPU::V_CMP_EQ_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19011   { 13972 /* v_cmp_eq_u32_e32 */, AMDGPU::V_CMP_EQ_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19060   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19061   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19062   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19063   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19064   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19065   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19066   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19067   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19068   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19069   { 14143 /* v_cmp_f_i32_e32 */, AMDGPU::V_CMP_F_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19070   { 14143 /* v_cmp_f_i32_e32 */, AMDGPU::V_CMP_F_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19071   { 14143 /* v_cmp_f_i32_e32 */, AMDGPU::V_CMP_F_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19088   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19089   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19090   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19091   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19092   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19093   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19094   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19095   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19096   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19097   { 14227 /* v_cmp_f_u32_e32 */, AMDGPU::V_CMP_F_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19098   { 14227 /* v_cmp_f_u32_e32 */, AMDGPU::V_CMP_F_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19099   { 14227 /* v_cmp_f_u32_e32 */, AMDGPU::V_CMP_F_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19152   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19153   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19154   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19155   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19156   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19157   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19158   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19159   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19160   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19161   { 14404 /* v_cmp_ge_i32_e32 */, AMDGPU::V_CMP_GE_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19162   { 14404 /* v_cmp_ge_i32_e32 */, AMDGPU::V_CMP_GE_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19163   { 14404 /* v_cmp_ge_i32_e32 */, AMDGPU::V_CMP_GE_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19184   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19185   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19186   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19187   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19188   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19189   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19190   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19191   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19192   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19193   { 14494 /* v_cmp_ge_u32_e32 */, AMDGPU::V_CMP_GE_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19194   { 14494 /* v_cmp_ge_u32_e32 */, AMDGPU::V_CMP_GE_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19195   { 14494 /* v_cmp_ge_u32_e32 */, AMDGPU::V_CMP_GE_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19248   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19249   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19250   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19251   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19252   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19253   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19254   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19255   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19256   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19257   { 14674 /* v_cmp_gt_i32_e32 */, AMDGPU::V_CMP_GT_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19258   { 14674 /* v_cmp_gt_i32_e32 */, AMDGPU::V_CMP_GT_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19259   { 14674 /* v_cmp_gt_i32_e32 */, AMDGPU::V_CMP_GT_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19280   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19281   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19282   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19283   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19284   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19285   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19286   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19287   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19288   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19289   { 14764 /* v_cmp_gt_u32_e32 */, AMDGPU::V_CMP_GT_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19290   { 14764 /* v_cmp_gt_u32_e32 */, AMDGPU::V_CMP_GT_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19291   { 14764 /* v_cmp_gt_u32_e32 */, AMDGPU::V_CMP_GT_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19344   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19345   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19346   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19347   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19348   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19349   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19350   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19351   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19352   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19353   { 14944 /* v_cmp_le_i32_e32 */, AMDGPU::V_CMP_LE_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19354   { 14944 /* v_cmp_le_i32_e32 */, AMDGPU::V_CMP_LE_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19355   { 14944 /* v_cmp_le_i32_e32 */, AMDGPU::V_CMP_LE_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19376   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19377   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19378   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19379   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19380   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19381   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19382   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19383   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19384   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19385   { 15034 /* v_cmp_le_u32_e32 */, AMDGPU::V_CMP_LE_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19386   { 15034 /* v_cmp_le_u32_e32 */, AMDGPU::V_CMP_LE_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19387   { 15034 /* v_cmp_le_u32_e32 */, AMDGPU::V_CMP_LE_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19472   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19473   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19474   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19475   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19476   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19477   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19478   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19479   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19480   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19481   { 15304 /* v_cmp_lt_i32_e32 */, AMDGPU::V_CMP_LT_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19482   { 15304 /* v_cmp_lt_i32_e32 */, AMDGPU::V_CMP_LT_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19483   { 15304 /* v_cmp_lt_i32_e32 */, AMDGPU::V_CMP_LT_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19504   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19505   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19506   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19507   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19508   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19509   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19510   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19511   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19512   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19513   { 15394 /* v_cmp_lt_u32_e32 */, AMDGPU::V_CMP_LT_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19514   { 15394 /* v_cmp_lt_u32_e32 */, AMDGPU::V_CMP_LT_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19515   { 15394 /* v_cmp_lt_u32_e32 */, AMDGPU::V_CMP_LT_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19536   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19537   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19538   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19539   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19540   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19541   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19542   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19543   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19544   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19545   { 15484 /* v_cmp_ne_i32_e32 */, AMDGPU::V_CMP_NE_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19546   { 15484 /* v_cmp_ne_i32_e32 */, AMDGPU::V_CMP_NE_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19547   { 15484 /* v_cmp_ne_i32_e32 */, AMDGPU::V_CMP_NE_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19568   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19569   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19570   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19571   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19572   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19573   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19574   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19575   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19576   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19577   { 15574 /* v_cmp_ne_u32_e32 */, AMDGPU::V_CMP_NE_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19578   { 15574 /* v_cmp_ne_u32_e32 */, AMDGPU::V_CMP_NE_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19579   { 15574 /* v_cmp_ne_u32_e32 */, AMDGPU::V_CMP_NE_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19820   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19821   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19822   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19823   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19824   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19825   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19826   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19827   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19828   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19829   { 16321 /* v_cmp_t_i32_e32 */, AMDGPU::V_CMP_T_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19830   { 16321 /* v_cmp_t_i32_e32 */, AMDGPU::V_CMP_T_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19831   { 16321 /* v_cmp_t_i32_e32 */, AMDGPU::V_CMP_T_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19848   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19849   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19850   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
19851   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19852   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19853   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
19854   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19855   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19856   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19857   { 16405 /* v_cmp_t_u32_e32 */, AMDGPU::V_CMP_T_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
19858   { 16405 /* v_cmp_t_u32_e32 */, AMDGPU::V_CMP_T_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
19859   { 16405 /* v_cmp_t_u32_e32 */, AMDGPU::V_CMP_T_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20250   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20251   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20252   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20253   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20254   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20255   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20256   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20257   { 19029 /* v_cmpx_eq_i32_e32 */, AMDGPU::V_CMPX_EQ_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20258   { 19029 /* v_cmpx_eq_i32_e32 */, AMDGPU::V_CMPX_EQ_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20259   { 19029 /* v_cmpx_eq_i32_e32 */, AMDGPU::V_CMPX_EQ_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20276   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20277   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20278   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20279   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20280   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20281   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20282   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20283   { 19125 /* v_cmpx_eq_u32_e32 */, AMDGPU::V_CMPX_EQ_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20284   { 19125 /* v_cmpx_eq_u32_e32 */, AMDGPU::V_CMPX_EQ_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20285   { 19125 /* v_cmpx_eq_u32_e32 */, AMDGPU::V_CMPX_EQ_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20326   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20327   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20328   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20329   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20330   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20331   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20332   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20333   { 19308 /* v_cmpx_f_i32_e32 */, AMDGPU::V_CMPX_F_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20334   { 19308 /* v_cmpx_f_i32_e32 */, AMDGPU::V_CMPX_F_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20335   { 19308 /* v_cmpx_f_i32_e32 */, AMDGPU::V_CMPX_F_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20350   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20351   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20352   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20353   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20354   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20355   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20356   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20357   { 19398 /* v_cmpx_f_u32_e32 */, AMDGPU::V_CMPX_F_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20358   { 19398 /* v_cmpx_f_u32_e32 */, AMDGPU::V_CMPX_F_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20359   { 19398 /* v_cmpx_f_u32_e32 */, AMDGPU::V_CMPX_F_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20402   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20403   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20404   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20405   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20406   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20407   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20408   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20409   { 19587 /* v_cmpx_ge_i32_e32 */, AMDGPU::V_CMPX_GE_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20410   { 19587 /* v_cmpx_ge_i32_e32 */, AMDGPU::V_CMPX_GE_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20411   { 19587 /* v_cmpx_ge_i32_e32 */, AMDGPU::V_CMPX_GE_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20428   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20429   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20430   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20431   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20432   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20433   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20434   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20435   { 19683 /* v_cmpx_ge_u32_e32 */, AMDGPU::V_CMPX_GE_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20436   { 19683 /* v_cmpx_ge_u32_e32 */, AMDGPU::V_CMPX_GE_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20437   { 19683 /* v_cmpx_ge_u32_e32 */, AMDGPU::V_CMPX_GE_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20480   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20481   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20482   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20483   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20484   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20485   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20486   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20487   { 19875 /* v_cmpx_gt_i32_e32 */, AMDGPU::V_CMPX_GT_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20488   { 19875 /* v_cmpx_gt_i32_e32 */, AMDGPU::V_CMPX_GT_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20489   { 19875 /* v_cmpx_gt_i32_e32 */, AMDGPU::V_CMPX_GT_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20506   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20507   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20508   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20509   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20510   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20511   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20512   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20513   { 19971 /* v_cmpx_gt_u32_e32 */, AMDGPU::V_CMPX_GT_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20514   { 19971 /* v_cmpx_gt_u32_e32 */, AMDGPU::V_CMPX_GT_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20515   { 19971 /* v_cmpx_gt_u32_e32 */, AMDGPU::V_CMPX_GT_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20558   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20559   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20560   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20561   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20562   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20563   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20564   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20565   { 20163 /* v_cmpx_le_i32_e32 */, AMDGPU::V_CMPX_LE_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20566   { 20163 /* v_cmpx_le_i32_e32 */, AMDGPU::V_CMPX_LE_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20567   { 20163 /* v_cmpx_le_i32_e32 */, AMDGPU::V_CMPX_LE_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20584   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20585   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20586   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20587   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20588   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20589   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20590   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20591   { 20259 /* v_cmpx_le_u32_e32 */, AMDGPU::V_CMPX_LE_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20592   { 20259 /* v_cmpx_le_u32_e32 */, AMDGPU::V_CMPX_LE_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20593   { 20259 /* v_cmpx_le_u32_e32 */, AMDGPU::V_CMPX_LE_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20662   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20663   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20664   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20665   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20666   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20667   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20668   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20669   { 20547 /* v_cmpx_lt_i32_e32 */, AMDGPU::V_CMPX_LT_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20670   { 20547 /* v_cmpx_lt_i32_e32 */, AMDGPU::V_CMPX_LT_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20671   { 20547 /* v_cmpx_lt_i32_e32 */, AMDGPU::V_CMPX_LT_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20688   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20689   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20690   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20691   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20692   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20693   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20694   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20695   { 20643 /* v_cmpx_lt_u32_e32 */, AMDGPU::V_CMPX_LT_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20696   { 20643 /* v_cmpx_lt_u32_e32 */, AMDGPU::V_CMPX_LT_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20697   { 20643 /* v_cmpx_lt_u32_e32 */, AMDGPU::V_CMPX_LT_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20714   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20715   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20716   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20717   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20718   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20719   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20720   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20721   { 20739 /* v_cmpx_ne_i32_e32 */, AMDGPU::V_CMPX_NE_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20722   { 20739 /* v_cmpx_ne_i32_e32 */, AMDGPU::V_CMPX_NE_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20723   { 20739 /* v_cmpx_ne_i32_e32 */, AMDGPU::V_CMPX_NE_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20740   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20741   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20742   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20743   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20744   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20745   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20746   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20747   { 20835 /* v_cmpx_ne_u32_e32 */, AMDGPU::V_CMPX_NE_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20748   { 20835 /* v_cmpx_ne_u32_e32 */, AMDGPU::V_CMPX_NE_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20749   { 20835 /* v_cmpx_ne_u32_e32 */, AMDGPU::V_CMPX_NE_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20946   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20947   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20948   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20949   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20950   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20951   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20952   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20953   { 21630 /* v_cmpx_t_i32_e32 */, AMDGPU::V_CMPX_T_I32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20954   { 21630 /* v_cmpx_t_i32_e32 */, AMDGPU::V_CMPX_T_I32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20955   { 21630 /* v_cmpx_t_i32_e32 */, AMDGPU::V_CMPX_T_I32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20970   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20971   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20972   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
20973   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20974   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
20975   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20976   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20977   { 21720 /* v_cmpx_t_u32_e32 */, AMDGPU::V_CMPX_T_U32_e32_gfx10, Convert__VSrcB321_0__Reg1_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VGPR_32 }, },
20978   { 21720 /* v_cmpx_t_u32_e32 */, AMDGPU::V_CMPX_T_U32_e32_gfx6_gfx7, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX6GFX7, { MCK_VSrcB32, MCK_VGPR_32 }, },
20979   { 21720 /* v_cmpx_t_u32_e32 */, AMDGPU::V_CMPX_T_U32_e32_vi, Convert__VSrcB321_0__Reg1_1, AMFBS_isGFX8GFX9, { MCK_VSrcB32, MCK_VGPR_32 }, },
21042   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21043   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21044   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21045   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21046   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21047   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21048   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21049   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21050   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21069   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21070   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21071   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21072   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21073   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21074   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21075   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21076   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21077   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21078   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21079   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21080   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21081   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21082   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21083   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21084   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21085   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21086   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21090   { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB32 }, },
21091   { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB32 }, },
21092   { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB32 }, },
21093   { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB32 }, },
21094   { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB32 }, },
21095   { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB32 }, },
21111   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21112   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21113   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21114   { 22368 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21115   { 22385 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21134   { 22797 /* v_dot2c_i32_i16 */, AMDGPU::V_DOT2C_I32_I16_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2__Tie0_1_1, AMFBS_HasDot4Insts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21135   { 22841 /* v_dot4c_i32_i8 */, AMDGPU::V_DOT4C_I32_I8_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2__Tie0_1_1, AMFBS_HasDot6Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21136   { 22841 /* v_dot4c_i32_i8 */, AMDGPU::V_DOT4C_I32_I8_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2__Tie0_1_1, AMFBS_HasDot6Insts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21137   { 22884 /* v_dot8c_i32_i4 */, AMDGPU::V_DOT8C_I32_I4_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2__Tie0_1_1, AMFBS_HasDot3Insts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21145   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21146   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21147   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21148   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21149   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21150   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21151   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21152   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21153   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21216   { 23553 /* v_lshl_b32 */, AMDGPU::V_LSHL_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21218   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21219   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21220   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21221   { 23631 /* v_lshr_b32 */, AMDGPU::V_LSHR_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21223   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21224   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21225   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21246   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21247   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21248   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21251   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21252   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21253   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21254   { 24171 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21255   { 24190 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21262   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21263   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21264   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21267   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21268   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21269   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21270   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21271   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21272   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21273   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21274   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21275   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21276   { 24886 /* v_movreld_b32 */, AMDGPU::V_MOVRELD_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21277   { 24886 /* v_movreld_b32 */, AMDGPU::V_MOVRELD_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21278   { 24886 /* v_movreld_b32 */, AMDGPU::V_MOVRELD_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21282   { 24914 /* v_movrelsd_2_b32 */, AMDGPU::V_MOVRELSD_2_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21283   { 24931 /* v_movrelsd_b32 */, AMDGPU::V_MOVRELSD_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21284   { 24931 /* v_movrelsd_b32 */, AMDGPU::V_MOVRELSD_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21285   { 24931 /* v_movrelsd_b32 */, AMDGPU::V_MOVRELSD_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21291   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21292   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21293   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21294   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21295   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21296   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21297   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21298   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21299   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21304   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21305   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21306   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21310   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21311   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21312   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21313   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21314   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21315   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21356   { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21357   { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21358   { 25879 /* v_screen_partition_4se_b32 */, AMDGPU::V_SCREEN_PARTITION_4SE_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX9Only_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32 }, },
21372   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21373   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21374   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21375   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
21376   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
21377   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
21383   { 26018 /* v_sub_i32 */, AMDGPU::V_SUB_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
21384   { 26067 /* v_sub_nc_u32 */, AMDGPU::V_SUB_NC_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_HasAddNoCarryInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21386   { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_HasAddNoCarryInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21387   { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_e32_vi, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
21388   { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21389   { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21390   { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21391   { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21392   { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e32_vi, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21393   { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21394   { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21395   { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21396   { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21397   { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e32_vi, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21398   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21399   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21400   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21401   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
21402   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
21403   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
21409   { 26217 /* v_subrev_i32 */, AMDGPU::V_SUBREV_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
21410   { 26230 /* v_subrev_nc_u32 */, AMDGPU::V_SUBREV_NC_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_HasAddNoCarryInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21412   { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_HasAddNoCarryInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21413   { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_e32_vi, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
21428   { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_HasDLInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21429   { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_HasDLInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21430   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21431   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21432   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21438   { 13211 /* v_add3_u32 */, AMDGPU::V_ADD3_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21438   { 13211 /* v_add3_u32 */, AMDGPU::V_ADD3_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21438   { 13211 /* v_add3_u32 */, AMDGPU::V_ADD3_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21439   { 13211 /* v_add3_u32 */, AMDGPU::V_ADD3_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21439   { 13211 /* v_add3_u32 */, AMDGPU::V_ADD3_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21439   { 13211 /* v_add3_u32 */, AMDGPU::V_ADD3_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21440   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21441   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21442   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
21442   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
21443   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
21444   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
21445   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21445   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21446   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21446   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21456   { 13291 /* v_add_i32 */, AMDGPU::V_ADD_I32_gfx9_gfx9, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX9Plus_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21456   { 13291 /* v_add_i32 */, AMDGPU::V_ADD_I32_gfx9_gfx9, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX9Plus_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21457   { 13291 /* v_add_i32 */, AMDGPU::V_ADD_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21457   { 13291 /* v_add_i32 */, AMDGPU::V_ADD_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21458   { 13301 /* v_add_lshl_u32 */, AMDGPU::V_ADD_LSHL_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21458   { 13301 /* v_add_lshl_u32 */, AMDGPU::V_ADD_LSHL_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21458   { 13301 /* v_add_lshl_u32 */, AMDGPU::V_ADD_LSHL_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21459   { 13301 /* v_add_lshl_u32 */, AMDGPU::V_ADD_LSHL_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21459   { 13301 /* v_add_lshl_u32 */, AMDGPU::V_ADD_LSHL_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21459   { 13301 /* v_add_lshl_u32 */, AMDGPU::V_ADD_LSHL_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21461   { 13329 /* v_add_nc_i32 */, AMDGPU::V_ADD_NC_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21461   { 13329 /* v_add_nc_i32 */, AMDGPU::V_ADD_NC_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21463   { 13355 /* v_add_nc_u32 */, AMDGPU::V_ADD_NC_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21463   { 13355 /* v_add_nc_u32 */, AMDGPU::V_ADD_NC_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21465   { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21465   { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21466   { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21466   { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21467   { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21468   { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21469   { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
21469   { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
21470   { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
21470   { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
21471   { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
21471   { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
21472   { 13413 /* v_alignbit_b32 */, AMDGPU::V_ALIGNBIT_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21472   { 13413 /* v_alignbit_b32 */, AMDGPU::V_ALIGNBIT_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21472   { 13413 /* v_alignbit_b32 */, AMDGPU::V_ALIGNBIT_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21473   { 13413 /* v_alignbit_b32 */, AMDGPU::V_ALIGNBIT_B32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21473   { 13413 /* v_alignbit_b32 */, AMDGPU::V_ALIGNBIT_B32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21473   { 13413 /* v_alignbit_b32 */, AMDGPU::V_ALIGNBIT_B32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21474   { 13413 /* v_alignbit_b32 */, AMDGPU::V_ALIGNBIT_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21474   { 13413 /* v_alignbit_b32 */, AMDGPU::V_ALIGNBIT_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21474   { 13413 /* v_alignbit_b32 */, AMDGPU::V_ALIGNBIT_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21475   { 13428 /* v_alignbyte_b32 */, AMDGPU::V_ALIGNBYTE_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21475   { 13428 /* v_alignbyte_b32 */, AMDGPU::V_ALIGNBYTE_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21475   { 13428 /* v_alignbyte_b32 */, AMDGPU::V_ALIGNBYTE_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21476   { 13428 /* v_alignbyte_b32 */, AMDGPU::V_ALIGNBYTE_B32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21476   { 13428 /* v_alignbyte_b32 */, AMDGPU::V_ALIGNBYTE_B32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21476   { 13428 /* v_alignbyte_b32 */, AMDGPU::V_ALIGNBYTE_B32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21477   { 13428 /* v_alignbyte_b32 */, AMDGPU::V_ALIGNBYTE_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21477   { 13428 /* v_alignbyte_b32 */, AMDGPU::V_ALIGNBYTE_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21477   { 13428 /* v_alignbyte_b32 */, AMDGPU::V_ALIGNBYTE_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21478   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21478   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21479   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21479   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21480   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21480   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21481   { 13454 /* v_and_or_b32 */, AMDGPU::V_AND_OR_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21481   { 13454 /* v_and_or_b32 */, AMDGPU::V_AND_OR_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21481   { 13454 /* v_and_or_b32 */, AMDGPU::V_AND_OR_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21482   { 13454 /* v_and_or_b32 */, AMDGPU::V_AND_OR_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21482   { 13454 /* v_and_or_b32 */, AMDGPU::V_AND_OR_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21482   { 13454 /* v_and_or_b32 */, AMDGPU::V_AND_OR_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21483   { 13467 /* v_ashr_i32 */, AMDGPU::V_ASHR_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21483   { 13467 /* v_ashr_i32 */, AMDGPU::V_ASHR_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21484   { 13478 /* v_ashr_i64 */, AMDGPU::V_ASHR_I64_gfx6_gfx7, Convert__Reg1_0__VSrcB641_1__VSrcB321_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32 }, },
21487   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21487   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21488   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21488   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21489   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21489   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21490   { 13517 /* v_ashrrev_i64 */, AMDGPU::V_ASHRREV_I64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB641_2, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB32, MCK_VSrcB64 }, },
21491   { 13517 /* v_ashrrev_i64 */, AMDGPU::V_ASHRREV_I64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB641_2, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB32, MCK_VSrcB64 }, },
21492   { 13531 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21492   { 13531 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21493   { 13531 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21493   { 13531 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21494   { 13531 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21494   { 13531 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21495   { 13546 /* v_bfe_i32 */, AMDGPU::V_BFE_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21495   { 13546 /* v_bfe_i32 */, AMDGPU::V_BFE_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21495   { 13546 /* v_bfe_i32 */, AMDGPU::V_BFE_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21496   { 13546 /* v_bfe_i32 */, AMDGPU::V_BFE_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21496   { 13546 /* v_bfe_i32 */, AMDGPU::V_BFE_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21496   { 13546 /* v_bfe_i32 */, AMDGPU::V_BFE_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21497   { 13546 /* v_bfe_i32 */, AMDGPU::V_BFE_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21497   { 13546 /* v_bfe_i32 */, AMDGPU::V_BFE_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21497   { 13546 /* v_bfe_i32 */, AMDGPU::V_BFE_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21498   { 13556 /* v_bfe_u32 */, AMDGPU::V_BFE_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21498   { 13556 /* v_bfe_u32 */, AMDGPU::V_BFE_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21498   { 13556 /* v_bfe_u32 */, AMDGPU::V_BFE_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21499   { 13556 /* v_bfe_u32 */, AMDGPU::V_BFE_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21499   { 13556 /* v_bfe_u32 */, AMDGPU::V_BFE_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21499   { 13556 /* v_bfe_u32 */, AMDGPU::V_BFE_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21500   { 13556 /* v_bfe_u32 */, AMDGPU::V_BFE_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21500   { 13556 /* v_bfe_u32 */, AMDGPU::V_BFE_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21500   { 13556 /* v_bfe_u32 */, AMDGPU::V_BFE_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21501   { 13566 /* v_bfi_b32 */, AMDGPU::V_BFI_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21501   { 13566 /* v_bfi_b32 */, AMDGPU::V_BFI_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21501   { 13566 /* v_bfi_b32 */, AMDGPU::V_BFI_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21502   { 13566 /* v_bfi_b32 */, AMDGPU::V_BFI_B32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21502   { 13566 /* v_bfi_b32 */, AMDGPU::V_BFI_B32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21502   { 13566 /* v_bfi_b32 */, AMDGPU::V_BFI_B32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21503   { 13566 /* v_bfi_b32 */, AMDGPU::V_BFI_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21503   { 13566 /* v_bfi_b32 */, AMDGPU::V_BFI_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21503   { 13566 /* v_bfi_b32 */, AMDGPU::V_BFI_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
21504   { 13576 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21504   { 13576 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21505   { 13576 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21505   { 13576 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21506   { 13576 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21506   { 13576 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21507   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21508   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21509   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21521   { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_VSrcB32 }, },
21522   { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_VSrcB32 }, },
21523   { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_VSrcB32 }, },
21524   { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_VSrcB32 }, },
21525   { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_VSrcB32 }, },
21526   { 13713 /* v_cmp_class_f64 */, AMDGPU::V_CMP_CLASS_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_VSrcB32 }, },
21527   { 13713 /* v_cmp_class_f64 */, AMDGPU::V_CMP_CLASS_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_VSrcB32 }, },
21528   { 13713 /* v_cmp_class_f64 */, AMDGPU::V_CMP_CLASS_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_VSrcB32 }, },
21539   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21539   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21540   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21540   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21541   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21541   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21547   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21547   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21548   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21548   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21549   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21549   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21562   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21562   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21563   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21563   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21564   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21564   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21569   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21569   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21570   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21570   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21571   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21571   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21585   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21585   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21586   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21586   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21587   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21587   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21593   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21593   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21594   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21594   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21595   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21595   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21609   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21609   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21610   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21610   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21611   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21611   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21617   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21617   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21618   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21618   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21619   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21619   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21633   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21633   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21634   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21634   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21635   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21635   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21641   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21641   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21642   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21642   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21643   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21643   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21665   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21665   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21666   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21666   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21667   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21667   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21673   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21673   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21674   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21674   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21675   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21675   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21681   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21681   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21682   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21682   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21683   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21683   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21689   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21689   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21690   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21690   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21691   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21691   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21752   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21752   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21753   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21753   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21754   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21754   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21759   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21759   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e64_gfx10, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21760   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21760   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21761   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21761   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21845   { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_VSrcB32 }, },
21846   { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_VSrcB32 }, },
21847   { 18811 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_VSrcB32 }, },
21848   { 18811 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_VSrcB32 }, },
21849   { 18811 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_VSrcB32 }, },
21850   { 18849 /* v_cmpx_class_f64 */, AMDGPU::V_CMPX_CLASS_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_VSrcB32 }, },
21851   { 18849 /* v_cmpx_class_f64 */, AMDGPU::V_CMPX_CLASS_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_VSrcB32 }, },
21852   { 18849 /* v_cmpx_class_f64 */, AMDGPU::V_CMPX_CLASS_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_VSrcB32 }, },
21863   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21863   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21864   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21864   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21865   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21865   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21871   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21871   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21872   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21872   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21873   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21873   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21886   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21886   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21887   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21887   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21888   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21888   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21893   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21893   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21894   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21894   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21895   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21895   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21909   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21909   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21910   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21910   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21911   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21911   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21917   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21917   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21918   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21918   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21919   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21919   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21933   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21933   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21934   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21934   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21935   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21935   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21941   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21941   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21942   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21942   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21943   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21943   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21957   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21957   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21958   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21958   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21959   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21959   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21965   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21965   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21966   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21966   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21967   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21967   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21989   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21989   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21990   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21990   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21991   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21991   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21997   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21997   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
21998   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21998   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21999   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
21999   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22005   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
22005   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
22006   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22006   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22007   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22007   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22013   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
22013   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
22014   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22014   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22015   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22015   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22076   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
22076   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
22077   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22077   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22078   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22078   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22083   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
22083   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e64_gfx10, Convert__VSrcB321_0__VSrcB321_1, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_VSrcB32, MCK_VSrcB32 }, },
22084   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22084   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e64_gfx6_gfx7, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22085   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22085   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e64_vi, Convert__BoolReg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32 }, },
22108   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22109   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22110   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22111   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22112   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22113   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22144   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22145   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22146   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22147   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22148   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22149   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22150   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22151   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22152   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22153   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22154   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22155   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22156   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22157   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22158   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22159   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22160   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22161   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22165   { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22166   { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22167   { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22168   { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22169   { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22170   { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22186   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22187   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22188   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22189   { 22368 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22189   { 22368 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22190   { 22368 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22190   { 22368 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22191   { 22368 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22191   { 22368 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22192   { 22385 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22192   { 22385 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22193   { 22385 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22193   { 22385 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22194   { 22385 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22194   { 22385 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22252   { 22751 /* v_dot2_i32_i16 */, AMDGPU::V_DOT2_I32_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22253   { 22751 /* v_dot2_i32_i16 */, AMDGPU::V_DOT2_I32_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22254   { 22766 /* v_dot2_u32_u16 */, AMDGPU::V_DOT2_U32_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22255   { 22766 /* v_dot2_u32_u16 */, AMDGPU::V_DOT2_U32_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22256   { 22813 /* v_dot4_i32_i8 */, AMDGPU::V_DOT4_I32_I8_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot1Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22256   { 22813 /* v_dot4_i32_i8 */, AMDGPU::V_DOT4_I32_I8_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot1Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22256   { 22813 /* v_dot4_i32_i8 */, AMDGPU::V_DOT4_I32_I8_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot1Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22257   { 22813 /* v_dot4_i32_i8 */, AMDGPU::V_DOT4_I32_I8_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot1Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22257   { 22813 /* v_dot4_i32_i8 */, AMDGPU::V_DOT4_I32_I8_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot1Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22257   { 22813 /* v_dot4_i32_i8 */, AMDGPU::V_DOT4_I32_I8_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot1Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22258   { 22827 /* v_dot4_u32_u8 */, AMDGPU::V_DOT4_U32_U8_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22258   { 22827 /* v_dot4_u32_u8 */, AMDGPU::V_DOT4_U32_U8_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22258   { 22827 /* v_dot4_u32_u8 */, AMDGPU::V_DOT4_U32_U8_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22259   { 22827 /* v_dot4_u32_u8 */, AMDGPU::V_DOT4_U32_U8_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22259   { 22827 /* v_dot4_u32_u8 */, AMDGPU::V_DOT4_U32_U8_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22259   { 22827 /* v_dot4_u32_u8 */, AMDGPU::V_DOT4_U32_U8_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22260   { 22856 /* v_dot8_i32_i4 */, AMDGPU::V_DOT8_I32_I4_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot1Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22260   { 22856 /* v_dot8_i32_i4 */, AMDGPU::V_DOT8_I32_I4_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot1Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22260   { 22856 /* v_dot8_i32_i4 */, AMDGPU::V_DOT8_I32_I4_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot1Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22261   { 22856 /* v_dot8_i32_i4 */, AMDGPU::V_DOT8_I32_I4_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot1Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22261   { 22856 /* v_dot8_i32_i4 */, AMDGPU::V_DOT8_I32_I4_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot1Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22261   { 22856 /* v_dot8_i32_i4 */, AMDGPU::V_DOT8_I32_I4_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot1Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22262   { 22870 /* v_dot8_u32_u4 */, AMDGPU::V_DOT8_U32_U4_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22262   { 22870 /* v_dot8_u32_u4 */, AMDGPU::V_DOT8_U32_U4_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22262   { 22870 /* v_dot8_u32_u4 */, AMDGPU::V_DOT8_U32_U4_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22263   { 22870 /* v_dot8_u32_u4 */, AMDGPU::V_DOT8_U32_U4_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22263   { 22870 /* v_dot8_u32_u4 */, AMDGPU::V_DOT8_U32_U4_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22263   { 22870 /* v_dot8_u32_u4 */, AMDGPU::V_DOT8_U32_U4_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22271   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22272   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22273   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22274   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22275   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22276   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22277   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22278   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22279   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22354   { 23475 /* v_lerp_u8 */, AMDGPU::V_LERP_U8_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22354   { 23475 /* v_lerp_u8 */, AMDGPU::V_LERP_U8_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22354   { 23475 /* v_lerp_u8 */, AMDGPU::V_LERP_U8_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22355   { 23475 /* v_lerp_u8 */, AMDGPU::V_LERP_U8_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22355   { 23475 /* v_lerp_u8 */, AMDGPU::V_LERP_U8_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22355   { 23475 /* v_lerp_u8 */, AMDGPU::V_LERP_U8_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22356   { 23475 /* v_lerp_u8 */, AMDGPU::V_LERP_U8_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22356   { 23475 /* v_lerp_u8 */, AMDGPU::V_LERP_U8_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22356   { 23475 /* v_lerp_u8 */, AMDGPU::V_LERP_U8_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22365   { 23538 /* v_lshl_add_u32 */, AMDGPU::V_LSHL_ADD_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22365   { 23538 /* v_lshl_add_u32 */, AMDGPU::V_LSHL_ADD_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22365   { 23538 /* v_lshl_add_u32 */, AMDGPU::V_LSHL_ADD_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22366   { 23538 /* v_lshl_add_u32 */, AMDGPU::V_LSHL_ADD_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22366   { 23538 /* v_lshl_add_u32 */, AMDGPU::V_LSHL_ADD_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22366   { 23538 /* v_lshl_add_u32 */, AMDGPU::V_LSHL_ADD_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22367   { 23553 /* v_lshl_b32 */, AMDGPU::V_LSHL_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22367   { 23553 /* v_lshl_b32 */, AMDGPU::V_LSHL_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22368   { 23564 /* v_lshl_b64 */, AMDGPU::V_LSHL_B64_gfx6_gfx7, Convert__Reg1_0__VSrcB641_1__VSrcB321_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32 }, },
22369   { 23575 /* v_lshl_or_b32 */, AMDGPU::V_LSHL_OR_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22369   { 23575 /* v_lshl_or_b32 */, AMDGPU::V_LSHL_OR_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22369   { 23575 /* v_lshl_or_b32 */, AMDGPU::V_LSHL_OR_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22370   { 23575 /* v_lshl_or_b32 */, AMDGPU::V_LSHL_OR_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22370   { 23575 /* v_lshl_or_b32 */, AMDGPU::V_LSHL_OR_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22370   { 23575 /* v_lshl_or_b32 */, AMDGPU::V_LSHL_OR_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22373   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22373   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22374   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22374   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22375   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22375   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22376   { 23617 /* v_lshlrev_b64 */, AMDGPU::V_LSHLREV_B64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB641_2, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB32, MCK_VSrcB64 }, },
22377   { 23617 /* v_lshlrev_b64 */, AMDGPU::V_LSHLREV_B64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB641_2, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB32, MCK_VSrcB64 }, },
22378   { 23631 /* v_lshr_b32 */, AMDGPU::V_LSHR_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22378   { 23631 /* v_lshr_b32 */, AMDGPU::V_LSHR_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22379   { 23642 /* v_lshr_b64 */, AMDGPU::V_LSHR_B64_gfx6_gfx7, Convert__Reg1_0__VSrcB641_1__VSrcB321_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32 }, },
22382   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22382   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22383   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22383   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22384   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22384   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22385   { 23681 /* v_lshrrev_b64 */, AMDGPU::V_LSHRREV_B64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB641_2, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB32, MCK_VSrcB64 }, },
22386   { 23681 /* v_lshrrev_b64 */, AMDGPU::V_LSHRREV_B64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB641_2, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB32, MCK_VSrcB64 }, },
22401   { 23762 /* v_mad_i32_i16 */, AMDGPU::V_MAD_I32_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmClampSI }, },
22402   { 23762 /* v_mad_i32_i16 */, AMDGPU::V_MAD_I32_I16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmClampSI }, },
22403   { 23776 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22403   { 23776 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22403   { 23776 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22404   { 23776 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22404   { 23776 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22404   { 23776 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22405   { 23776 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22405   { 23776 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22405   { 23776 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22406   { 23790 /* v_mad_i64_i32 */, AMDGPU::V_MAD_I64_I32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22406   { 23790 /* v_mad_i64_i32 */, AMDGPU::V_MAD_I64_I32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22407   { 23790 /* v_mad_i64_i32 */, AMDGPU::V_MAD_I64_I32_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22407   { 23790 /* v_mad_i64_i32 */, AMDGPU::V_MAD_I64_I32_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22408   { 23790 /* v_mad_i64_i32 */, AMDGPU::V_MAD_I64_I32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22408   { 23790 /* v_mad_i64_i32 */, AMDGPU::V_MAD_I64_I32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22421   { 23928 /* v_mad_u32_u16 */, AMDGPU::V_MAD_U32_U16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmClampSI }, },
22422   { 23928 /* v_mad_u32_u16 */, AMDGPU::V_MAD_U32_U16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmClampSI }, },
22423   { 23942 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22423   { 23942 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22423   { 23942 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22424   { 23942 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22424   { 23942 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22424   { 23942 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22425   { 23942 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22425   { 23942 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22425   { 23942 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22426   { 23956 /* v_mad_u64_u32 */, AMDGPU::V_MAD_U64_U32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22426   { 23956 /* v_mad_u64_u32 */, AMDGPU::V_MAD_U64_U32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22427   { 23956 /* v_mad_u64_u32 */, AMDGPU::V_MAD_U64_U32_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22427   { 23956 /* v_mad_u64_u32 */, AMDGPU::V_MAD_U64_U32_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22428   { 23956 /* v_mad_u64_u32 */, AMDGPU::V_MAD_U64_U32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22428   { 23956 /* v_mad_u64_u32 */, AMDGPU::V_MAD_U64_U32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22436   { 24051 /* v_max3_i32 */, AMDGPU::V_MAX3_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22436   { 24051 /* v_max3_i32 */, AMDGPU::V_MAX3_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22436   { 24051 /* v_max3_i32 */, AMDGPU::V_MAX3_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22437   { 24051 /* v_max3_i32 */, AMDGPU::V_MAX3_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22437   { 24051 /* v_max3_i32 */, AMDGPU::V_MAX3_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22437   { 24051 /* v_max3_i32 */, AMDGPU::V_MAX3_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22438   { 24051 /* v_max3_i32 */, AMDGPU::V_MAX3_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22438   { 24051 /* v_max3_i32 */, AMDGPU::V_MAX3_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22438   { 24051 /* v_max3_i32 */, AMDGPU::V_MAX3_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22441   { 24073 /* v_max3_u32 */, AMDGPU::V_MAX3_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22441   { 24073 /* v_max3_u32 */, AMDGPU::V_MAX3_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22441   { 24073 /* v_max3_u32 */, AMDGPU::V_MAX3_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22442   { 24073 /* v_max3_u32 */, AMDGPU::V_MAX3_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22442   { 24073 /* v_max3_u32 */, AMDGPU::V_MAX3_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22442   { 24073 /* v_max3_u32 */, AMDGPU::V_MAX3_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22443   { 24073 /* v_max3_u32 */, AMDGPU::V_MAX3_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22443   { 24073 /* v_max3_u32 */, AMDGPU::V_MAX3_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22443   { 24073 /* v_max3_u32 */, AMDGPU::V_MAX3_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22454   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22454   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22455   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22455   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22456   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22456   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22460   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22460   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22461   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22461   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22462   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22462   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22463   { 24171 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22463   { 24171 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22464   { 24171 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22464   { 24171 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22465   { 24171 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22465   { 24171 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22466   { 24190 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22466   { 24190 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22467   { 24190 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22467   { 24190 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22468   { 24190 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22468   { 24190 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22476   { 24242 /* v_med3_i32 */, AMDGPU::V_MED3_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22476   { 24242 /* v_med3_i32 */, AMDGPU::V_MED3_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22476   { 24242 /* v_med3_i32 */, AMDGPU::V_MED3_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22477   { 24242 /* v_med3_i32 */, AMDGPU::V_MED3_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22477   { 24242 /* v_med3_i32 */, AMDGPU::V_MED3_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22477   { 24242 /* v_med3_i32 */, AMDGPU::V_MED3_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22478   { 24242 /* v_med3_i32 */, AMDGPU::V_MED3_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22478   { 24242 /* v_med3_i32 */, AMDGPU::V_MED3_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22478   { 24242 /* v_med3_i32 */, AMDGPU::V_MED3_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22481   { 24264 /* v_med3_u32 */, AMDGPU::V_MED3_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22481   { 24264 /* v_med3_u32 */, AMDGPU::V_MED3_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22481   { 24264 /* v_med3_u32 */, AMDGPU::V_MED3_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22482   { 24264 /* v_med3_u32 */, AMDGPU::V_MED3_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22482   { 24264 /* v_med3_u32 */, AMDGPU::V_MED3_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22482   { 24264 /* v_med3_u32 */, AMDGPU::V_MED3_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22483   { 24264 /* v_med3_u32 */, AMDGPU::V_MED3_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22483   { 24264 /* v_med3_u32 */, AMDGPU::V_MED3_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22483   { 24264 /* v_med3_u32 */, AMDGPU::V_MED3_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22511   { 24742 /* v_min3_i32 */, AMDGPU::V_MIN3_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22511   { 24742 /* v_min3_i32 */, AMDGPU::V_MIN3_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22511   { 24742 /* v_min3_i32 */, AMDGPU::V_MIN3_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22512   { 24742 /* v_min3_i32 */, AMDGPU::V_MIN3_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22512   { 24742 /* v_min3_i32 */, AMDGPU::V_MIN3_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22512   { 24742 /* v_min3_i32 */, AMDGPU::V_MIN3_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22513   { 24742 /* v_min3_i32 */, AMDGPU::V_MIN3_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22513   { 24742 /* v_min3_i32 */, AMDGPU::V_MIN3_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22513   { 24742 /* v_min3_i32 */, AMDGPU::V_MIN3_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22516   { 24764 /* v_min3_u32 */, AMDGPU::V_MIN3_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22516   { 24764 /* v_min3_u32 */, AMDGPU::V_MIN3_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22516   { 24764 /* v_min3_u32 */, AMDGPU::V_MIN3_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22517   { 24764 /* v_min3_u32 */, AMDGPU::V_MIN3_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22517   { 24764 /* v_min3_u32 */, AMDGPU::V_MIN3_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22517   { 24764 /* v_min3_u32 */, AMDGPU::V_MIN3_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22518   { 24764 /* v_min3_u32 */, AMDGPU::V_MIN3_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22518   { 24764 /* v_min3_u32 */, AMDGPU::V_MIN3_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22518   { 24764 /* v_min3_u32 */, AMDGPU::V_MIN3_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22529   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22529   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22530   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22530   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22531   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22531   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22535   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22535   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22536   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22536   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22537   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22537   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22538   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22539   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22540   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22541   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22542   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22543   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22544   { 24886 /* v_movreld_b32 */, AMDGPU::V_MOVRELD_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22545   { 24886 /* v_movreld_b32 */, AMDGPU::V_MOVRELD_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22546   { 24886 /* v_movreld_b32 */, AMDGPU::V_MOVRELD_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22550   { 24914 /* v_movrelsd_2_b32 */, AMDGPU::V_MOVRELSD_2_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22551   { 24931 /* v_movrelsd_b32 */, AMDGPU::V_MOVRELSD_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22552   { 24931 /* v_movrelsd_b32 */, AMDGPU::V_MOVRELSD_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22553   { 24931 /* v_movrelsd_b32 */, AMDGPU::V_MOVRELSD_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22554   { 24946 /* v_mqsad_pk_u16_u8 */, AMDGPU::V_MQSAD_PK_U16_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22555   { 24946 /* v_mqsad_pk_u16_u8 */, AMDGPU::V_MQSAD_PK_U16_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22556   { 24946 /* v_mqsad_pk_u16_u8 */, AMDGPU::V_MQSAD_PK_U16_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22557   { 24964 /* v_mqsad_u32_u8 */, AMDGPU::V_MQSAD_U32_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_128, MCK_VSrcB64, MCK_VSrcB32, MCK_VReg_128, MCK_ImmClampSI }, },
22558   { 24964 /* v_mqsad_u32_u8 */, AMDGPU::V_MQSAD_U32_U8_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_128, MCK_VSrcB64, MCK_VSrcB32, MCK_VReg_128, MCK_ImmClampSI }, },
22559   { 24964 /* v_mqsad_u32_u8 */, AMDGPU::V_MQSAD_U32_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_128, MCK_VSrcB64, MCK_VSrcB32, MCK_VReg_128, MCK_ImmClampSI }, },
22560   { 24979 /* v_msad_u8 */, AMDGPU::V_MSAD_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22560   { 24979 /* v_msad_u8 */, AMDGPU::V_MSAD_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22560   { 24979 /* v_msad_u8 */, AMDGPU::V_MSAD_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22561   { 24979 /* v_msad_u8 */, AMDGPU::V_MSAD_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22561   { 24979 /* v_msad_u8 */, AMDGPU::V_MSAD_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22561   { 24979 /* v_msad_u8 */, AMDGPU::V_MSAD_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22562   { 24979 /* v_msad_u8 */, AMDGPU::V_MSAD_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22562   { 24979 /* v_msad_u8 */, AMDGPU::V_MSAD_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22562   { 24979 /* v_msad_u8 */, AMDGPU::V_MSAD_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22571   { 25019 /* v_mul_hi_i32 */, AMDGPU::V_MUL_HI_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22571   { 25019 /* v_mul_hi_i32 */, AMDGPU::V_MUL_HI_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22572   { 25019 /* v_mul_hi_i32 */, AMDGPU::V_MUL_HI_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22572   { 25019 /* v_mul_hi_i32 */, AMDGPU::V_MUL_HI_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22573   { 25019 /* v_mul_hi_i32 */, AMDGPU::V_MUL_HI_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22573   { 25019 /* v_mul_hi_i32 */, AMDGPU::V_MUL_HI_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22574   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22574   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22575   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22575   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22576   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22576   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22577   { 25049 /* v_mul_hi_u32 */, AMDGPU::V_MUL_HI_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22577   { 25049 /* v_mul_hi_u32 */, AMDGPU::V_MUL_HI_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22578   { 25049 /* v_mul_hi_u32 */, AMDGPU::V_MUL_HI_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22578   { 25049 /* v_mul_hi_u32 */, AMDGPU::V_MUL_HI_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22579   { 25049 /* v_mul_hi_u32 */, AMDGPU::V_MUL_HI_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22579   { 25049 /* v_mul_hi_u32 */, AMDGPU::V_MUL_HI_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22580   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22580   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22581   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22581   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22582   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22582   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22583   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22583   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22584   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22584   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22585   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22585   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22589   { 25110 /* v_mul_lo_i32 */, AMDGPU::V_MUL_LO_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22589   { 25110 /* v_mul_lo_i32 */, AMDGPU::V_MUL_LO_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22590   { 25110 /* v_mul_lo_i32 */, AMDGPU::V_MUL_LO_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22590   { 25110 /* v_mul_lo_i32 */, AMDGPU::V_MUL_LO_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22591   { 25110 /* v_mul_lo_i32 */, AMDGPU::V_MUL_LO_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22591   { 25110 /* v_mul_lo_i32 */, AMDGPU::V_MUL_LO_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22594   { 25136 /* v_mul_lo_u32 */, AMDGPU::V_MUL_LO_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22594   { 25136 /* v_mul_lo_u32 */, AMDGPU::V_MUL_LO_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22595   { 25136 /* v_mul_lo_u32 */, AMDGPU::V_MUL_LO_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22595   { 25136 /* v_mul_lo_u32 */, AMDGPU::V_MUL_LO_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22596   { 25136 /* v_mul_lo_u32 */, AMDGPU::V_MUL_LO_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22596   { 25136 /* v_mul_lo_u32 */, AMDGPU::V_MUL_LO_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22597   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22597   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22598   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22598   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22599   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22599   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22605   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22606   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22607   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22608   { 25192 /* v_or3_b32 */, AMDGPU::V_OR3_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22608   { 25192 /* v_or3_b32 */, AMDGPU::V_OR3_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22608   { 25192 /* v_or3_b32 */, AMDGPU::V_OR3_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22609   { 25192 /* v_or3_b32 */, AMDGPU::V_OR3_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22609   { 25192 /* v_or3_b32 */, AMDGPU::V_OR3_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22609   { 25192 /* v_or3_b32 */, AMDGPU::V_OR3_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22610   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22610   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22611   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22611   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22612   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22612   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22615   { 25226 /* v_perm_b32 */, AMDGPU::V_PERM_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22615   { 25226 /* v_perm_b32 */, AMDGPU::V_PERM_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22615   { 25226 /* v_perm_b32 */, AMDGPU::V_PERM_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22616   { 25226 /* v_perm_b32 */, AMDGPU::V_PERM_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22616   { 25226 /* v_perm_b32 */, AMDGPU::V_PERM_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22616   { 25226 /* v_perm_b32 */, AMDGPU::V_PERM_B32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22658   { 25560 /* v_qsad_pk_u16_u8 */, AMDGPU::V_QSAD_PK_U16_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22659   { 25560 /* v_qsad_pk_u16_u8 */, AMDGPU::V_QSAD_PK_U16_U8_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22660   { 25560 /* v_qsad_pk_u16_u8 */, AMDGPU::V_QSAD_PK_U16_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22694   { 25822 /* v_sad_hi_u8 */, AMDGPU::V_SAD_HI_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22694   { 25822 /* v_sad_hi_u8 */, AMDGPU::V_SAD_HI_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22694   { 25822 /* v_sad_hi_u8 */, AMDGPU::V_SAD_HI_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22695   { 25822 /* v_sad_hi_u8 */, AMDGPU::V_SAD_HI_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22695   { 25822 /* v_sad_hi_u8 */, AMDGPU::V_SAD_HI_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22695   { 25822 /* v_sad_hi_u8 */, AMDGPU::V_SAD_HI_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22696   { 25822 /* v_sad_hi_u8 */, AMDGPU::V_SAD_HI_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22696   { 25822 /* v_sad_hi_u8 */, AMDGPU::V_SAD_HI_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22696   { 25822 /* v_sad_hi_u8 */, AMDGPU::V_SAD_HI_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22697   { 25834 /* v_sad_u16 */, AMDGPU::V_SAD_U16_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22697   { 25834 /* v_sad_u16 */, AMDGPU::V_SAD_U16_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22697   { 25834 /* v_sad_u16 */, AMDGPU::V_SAD_U16_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22698   { 25834 /* v_sad_u16 */, AMDGPU::V_SAD_U16_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22698   { 25834 /* v_sad_u16 */, AMDGPU::V_SAD_U16_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22698   { 25834 /* v_sad_u16 */, AMDGPU::V_SAD_U16_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22699   { 25834 /* v_sad_u16 */, AMDGPU::V_SAD_U16_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22699   { 25834 /* v_sad_u16 */, AMDGPU::V_SAD_U16_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22699   { 25834 /* v_sad_u16 */, AMDGPU::V_SAD_U16_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22700   { 25844 /* v_sad_u32 */, AMDGPU::V_SAD_U32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22700   { 25844 /* v_sad_u32 */, AMDGPU::V_SAD_U32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22700   { 25844 /* v_sad_u32 */, AMDGPU::V_SAD_U32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22701   { 25844 /* v_sad_u32 */, AMDGPU::V_SAD_U32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22701   { 25844 /* v_sad_u32 */, AMDGPU::V_SAD_U32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22701   { 25844 /* v_sad_u32 */, AMDGPU::V_SAD_U32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22702   { 25844 /* v_sad_u32 */, AMDGPU::V_SAD_U32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22702   { 25844 /* v_sad_u32 */, AMDGPU::V_SAD_U32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22702   { 25844 /* v_sad_u32 */, AMDGPU::V_SAD_U32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22703   { 25854 /* v_sad_u8 */, AMDGPU::V_SAD_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22703   { 25854 /* v_sad_u8 */, AMDGPU::V_SAD_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22703   { 25854 /* v_sad_u8 */, AMDGPU::V_SAD_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22704   { 25854 /* v_sad_u8 */, AMDGPU::V_SAD_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22704   { 25854 /* v_sad_u8 */, AMDGPU::V_SAD_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22704   { 25854 /* v_sad_u8 */, AMDGPU::V_SAD_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22705   { 25854 /* v_sad_u8 */, AMDGPU::V_SAD_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22705   { 25854 /* v_sad_u8 */, AMDGPU::V_SAD_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22705   { 25854 /* v_sad_u8 */, AMDGPU::V_SAD_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22706   { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22707   { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22708   { 25879 /* v_screen_partition_4se_b32 */, AMDGPU::V_SCREEN_PARTITION_4SE_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX9Only_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32 }, },
22722   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22723   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22724   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22724   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22725   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
22726   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
22727   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22727   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22728   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22728   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22735   { 26018 /* v_sub_i32 */, AMDGPU::V_SUB_I32_gfx9_gfx9, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX9Plus_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22735   { 26018 /* v_sub_i32 */, AMDGPU::V_SUB_I32_gfx9_gfx9, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX9Plus_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22736   { 26018 /* v_sub_i32 */, AMDGPU::V_SUB_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22736   { 26018 /* v_sub_i32 */, AMDGPU::V_SUB_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22738   { 26041 /* v_sub_nc_i32 */, AMDGPU::V_SUB_NC_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22738   { 26041 /* v_sub_nc_i32 */, AMDGPU::V_SUB_NC_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22740   { 26067 /* v_sub_nc_u32 */, AMDGPU::V_SUB_NC_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22740   { 26067 /* v_sub_nc_u32 */, AMDGPU::V_SUB_NC_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22742   { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22742   { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22743   { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22743   { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22744   { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22745   { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22746   { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22746   { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22747   { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22747   { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22748   { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22748   { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22749   { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22750   { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22751   { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22751   { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22752   { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22752   { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22753   { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22753   { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22754   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22755   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22756   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22756   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22757   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
22758   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
22759   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22759   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22760   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22760   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22766   { 26217 /* v_subrev_i32 */, AMDGPU::V_SUBREV_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22766   { 26217 /* v_subrev_i32 */, AMDGPU::V_SUBREV_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22767   { 26230 /* v_subrev_nc_u32 */, AMDGPU::V_SUBREV_NC_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22767   { 26230 /* v_subrev_nc_u32 */, AMDGPU::V_SUBREV_NC_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22769   { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22769   { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22770   { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22770   { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22782   { 26366 /* v_xad_u32 */, AMDGPU::V_XAD_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22782   { 26366 /* v_xad_u32 */, AMDGPU::V_XAD_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22782   { 26366 /* v_xad_u32 */, AMDGPU::V_XAD_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22783   { 26366 /* v_xad_u32 */, AMDGPU::V_XAD_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22783   { 26366 /* v_xad_u32 */, AMDGPU::V_XAD_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22783   { 26366 /* v_xad_u32 */, AMDGPU::V_XAD_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22784   { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_HasDLInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22784   { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_HasDLInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22785   { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_HasDLInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22785   { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_HasDLInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22786   { 26387 /* v_xor3_b32 */, AMDGPU::V_XOR3_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22786   { 26387 /* v_xor3_b32 */, AMDGPU::V_XOR3_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22786   { 26387 /* v_xor3_b32 */, AMDGPU::V_XOR3_B32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2__VSrcB321_3, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32 }, },
22787   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22787   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22788   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22788   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22789   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22789   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22793   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22794   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22795   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
22796   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
22801   { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22802   { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22942   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22943   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22944   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22945   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22946   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22947   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23032   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23033   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23034   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
23035   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23040   { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23041   { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23043   { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23044   { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23046   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23047   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23048   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
23049   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23061   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23062   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23066   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
23067   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23076   { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23077   { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23346   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23347   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23348   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23349   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23350   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23351   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23510   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23511   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23515   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
23516   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23525   { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23526   { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23528   { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23529   { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23531   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23532   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23536   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
23537   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23557   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23558   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23565   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
23566   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23579   { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23580   { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23599   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23600   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23601   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23602   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23603   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23604   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23851   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23852   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23859   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
23860   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23873   { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23874   { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23877   { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23878   { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23881   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23882   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23889   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
23890   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },