|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 9159 case AMDGPU::VGPR0_VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15: OpKind = MCK_VReg_512; break;
9160 case AMDGPU::VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16: OpKind = MCK_VReg_512; break;
9161 case AMDGPU::VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17: OpKind = MCK_VReg_512; break;
9162 case AMDGPU::VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18: OpKind = MCK_VReg_512; break;
9163 case AMDGPU::VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19: OpKind = MCK_VReg_512; break;
9164 case AMDGPU::VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20: OpKind = MCK_VReg_512; break;
9165 case AMDGPU::VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21: OpKind = MCK_VReg_512; break;
9166 case AMDGPU::VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22: OpKind = MCK_VReg_512; break;
9167 case AMDGPU::VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23: OpKind = MCK_VReg_512; break;
9168 case AMDGPU::VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24: OpKind = MCK_VReg_512; break;
9169 case AMDGPU::VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25: OpKind = MCK_VReg_512; break;
9170 case AMDGPU::VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26: OpKind = MCK_VReg_512; break;
9171 case AMDGPU::VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27: OpKind = MCK_VReg_512; break;
9172 case AMDGPU::VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28: OpKind = MCK_VReg_512; break;
9173 case AMDGPU::VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29: OpKind = MCK_VReg_512; break;
9174 case AMDGPU::VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30: OpKind = MCK_VReg_512; break;
9175 case AMDGPU::VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31: OpKind = MCK_VReg_512; break;
9176 case AMDGPU::VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32: OpKind = MCK_VReg_512; break;
9177 case AMDGPU::VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33: OpKind = MCK_VReg_512; break;
9178 case AMDGPU::VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34: OpKind = MCK_VReg_512; break;
9179 case AMDGPU::VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35: OpKind = MCK_VReg_512; break;
9180 case AMDGPU::VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36: OpKind = MCK_VReg_512; break;
9181 case AMDGPU::VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37: OpKind = MCK_VReg_512; break;
9182 case AMDGPU::VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38: OpKind = MCK_VReg_512; break;
9183 case AMDGPU::VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39: OpKind = MCK_VReg_512; break;
9184 case AMDGPU::VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40: OpKind = MCK_VReg_512; break;
9185 case AMDGPU::VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41: OpKind = MCK_VReg_512; break;
9186 case AMDGPU::VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42: OpKind = MCK_VReg_512; break;
9187 case AMDGPU::VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43: OpKind = MCK_VReg_512; break;
9188 case AMDGPU::VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44: OpKind = MCK_VReg_512; break;
9189 case AMDGPU::VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45: OpKind = MCK_VReg_512; break;
9190 case AMDGPU::VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46: OpKind = MCK_VReg_512; break;
9191 case AMDGPU::VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47: OpKind = MCK_VReg_512; break;
9192 case AMDGPU::VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48: OpKind = MCK_VReg_512; break;
9193 case AMDGPU::VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49: OpKind = MCK_VReg_512; break;
9194 case AMDGPU::VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50: OpKind = MCK_VReg_512; break;
9195 case AMDGPU::VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51: OpKind = MCK_VReg_512; break;
9196 case AMDGPU::VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52: OpKind = MCK_VReg_512; break;
9197 case AMDGPU::VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53: OpKind = MCK_VReg_512; break;
9198 case AMDGPU::VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54: OpKind = MCK_VReg_512; break;
9199 case AMDGPU::VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55: OpKind = MCK_VReg_512; break;
9200 case AMDGPU::VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56: OpKind = MCK_VReg_512; break;
9201 case AMDGPU::VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57: OpKind = MCK_VReg_512; break;
9202 case AMDGPU::VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58: OpKind = MCK_VReg_512; break;
9203 case AMDGPU::VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59: OpKind = MCK_VReg_512; break;
9204 case AMDGPU::VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60: OpKind = MCK_VReg_512; break;
9205 case AMDGPU::VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61: OpKind = MCK_VReg_512; break;
9206 case AMDGPU::VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62: OpKind = MCK_VReg_512; break;
9207 case AMDGPU::VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63: OpKind = MCK_VReg_512; break;
9208 case AMDGPU::VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64: OpKind = MCK_VReg_512; break;
9209 case AMDGPU::VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65: OpKind = MCK_VReg_512; break;
9210 case AMDGPU::VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66: OpKind = MCK_VReg_512; break;
9211 case AMDGPU::VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67: OpKind = MCK_VReg_512; break;
9212 case AMDGPU::VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68: OpKind = MCK_VReg_512; break;
9213 case AMDGPU::VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69: OpKind = MCK_VReg_512; break;
9214 case AMDGPU::VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70: OpKind = MCK_VReg_512; break;
9215 case AMDGPU::VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71: OpKind = MCK_VReg_512; break;
9216 case AMDGPU::VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72: OpKind = MCK_VReg_512; break;
9217 case AMDGPU::VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73: OpKind = MCK_VReg_512; break;
9218 case AMDGPU::VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74: OpKind = MCK_VReg_512; break;
9219 case AMDGPU::VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75: OpKind = MCK_VReg_512; break;
9220 case AMDGPU::VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76: OpKind = MCK_VReg_512; break;
9221 case AMDGPU::VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77: OpKind = MCK_VReg_512; break;
9222 case AMDGPU::VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78: OpKind = MCK_VReg_512; break;
9223 case AMDGPU::VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79: OpKind = MCK_VReg_512; break;
9224 case AMDGPU::VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80: OpKind = MCK_VReg_512; break;
9225 case AMDGPU::VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81: OpKind = MCK_VReg_512; break;
9226 case AMDGPU::VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82: OpKind = MCK_VReg_512; break;
9227 case AMDGPU::VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83: OpKind = MCK_VReg_512; break;
9228 case AMDGPU::VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84: OpKind = MCK_VReg_512; break;
9229 case AMDGPU::VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85: OpKind = MCK_VReg_512; break;
9230 case AMDGPU::VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86: OpKind = MCK_VReg_512; break;
9231 case AMDGPU::VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87: OpKind = MCK_VReg_512; break;
9232 case AMDGPU::VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88: OpKind = MCK_VReg_512; break;
9233 case AMDGPU::VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89: OpKind = MCK_VReg_512; break;
9234 case AMDGPU::VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90: OpKind = MCK_VReg_512; break;
9235 case AMDGPU::VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91: OpKind = MCK_VReg_512; break;
9236 case AMDGPU::VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92: OpKind = MCK_VReg_512; break;
9237 case AMDGPU::VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93: OpKind = MCK_VReg_512; break;
9238 case AMDGPU::VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94: OpKind = MCK_VReg_512; break;
9239 case AMDGPU::VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95: OpKind = MCK_VReg_512; break;
9240 case AMDGPU::VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96: OpKind = MCK_VReg_512; break;
9241 case AMDGPU::VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97: OpKind = MCK_VReg_512; break;
9242 case AMDGPU::VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98: OpKind = MCK_VReg_512; break;
9243 case AMDGPU::VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99: OpKind = MCK_VReg_512; break;
9244 case AMDGPU::VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100: OpKind = MCK_VReg_512; break;
9245 case AMDGPU::VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101: OpKind = MCK_VReg_512; break;
9246 case AMDGPU::VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102: OpKind = MCK_VReg_512; break;
9247 case AMDGPU::VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103: OpKind = MCK_VReg_512; break;
9248 case AMDGPU::VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104: OpKind = MCK_VReg_512; break;
9249 case AMDGPU::VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105: OpKind = MCK_VReg_512; break;
9250 case AMDGPU::VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106: OpKind = MCK_VReg_512; break;
9251 case AMDGPU::VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107: OpKind = MCK_VReg_512; break;
9252 case AMDGPU::VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108: OpKind = MCK_VReg_512; break;
9253 case AMDGPU::VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109: OpKind = MCK_VReg_512; break;
9254 case AMDGPU::VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110: OpKind = MCK_VReg_512; break;
9255 case AMDGPU::VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111: OpKind = MCK_VReg_512; break;
9256 case AMDGPU::VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112: OpKind = MCK_VReg_512; break;
9257 case AMDGPU::VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113: OpKind = MCK_VReg_512; break;
9258 case AMDGPU::VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114: OpKind = MCK_VReg_512; break;
9259 case AMDGPU::VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115: OpKind = MCK_VReg_512; break;
9260 case AMDGPU::VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116: OpKind = MCK_VReg_512; break;
9261 case AMDGPU::VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117: OpKind = MCK_VReg_512; break;
9262 case AMDGPU::VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118: OpKind = MCK_VReg_512; break;
9263 case AMDGPU::VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119: OpKind = MCK_VReg_512; break;
9264 case AMDGPU::VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120: OpKind = MCK_VReg_512; break;
9265 case AMDGPU::VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121: OpKind = MCK_VReg_512; break;
9266 case AMDGPU::VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122: OpKind = MCK_VReg_512; break;
9267 case AMDGPU::VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123: OpKind = MCK_VReg_512; break;
9268 case AMDGPU::VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124: OpKind = MCK_VReg_512; break;
9269 case AMDGPU::VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125: OpKind = MCK_VReg_512; break;
9270 case AMDGPU::VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126: OpKind = MCK_VReg_512; break;
9271 case AMDGPU::VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127: OpKind = MCK_VReg_512; break;
9272 case AMDGPU::VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128: OpKind = MCK_VReg_512; break;
9273 case AMDGPU::VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129: OpKind = MCK_VReg_512; break;
9274 case AMDGPU::VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130: OpKind = MCK_VReg_512; break;
9275 case AMDGPU::VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131: OpKind = MCK_VReg_512; break;
9276 case AMDGPU::VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132: OpKind = MCK_VReg_512; break;
9277 case AMDGPU::VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133: OpKind = MCK_VReg_512; break;
9278 case AMDGPU::VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134: OpKind = MCK_VReg_512; break;
9279 case AMDGPU::VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135: OpKind = MCK_VReg_512; break;
9280 case AMDGPU::VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136: OpKind = MCK_VReg_512; break;
9281 case AMDGPU::VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137: OpKind = MCK_VReg_512; break;
9282 case AMDGPU::VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138: OpKind = MCK_VReg_512; break;
9283 case AMDGPU::VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139: OpKind = MCK_VReg_512; break;
9284 case AMDGPU::VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140: OpKind = MCK_VReg_512; break;
9285 case AMDGPU::VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141: OpKind = MCK_VReg_512; break;
9286 case AMDGPU::VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142: OpKind = MCK_VReg_512; break;
9287 case AMDGPU::VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143: OpKind = MCK_VReg_512; break;
9288 case AMDGPU::VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144: OpKind = MCK_VReg_512; break;
9289 case AMDGPU::VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145: OpKind = MCK_VReg_512; break;
9290 case AMDGPU::VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146: OpKind = MCK_VReg_512; break;
9291 case AMDGPU::VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147: OpKind = MCK_VReg_512; break;
9292 case AMDGPU::VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148: OpKind = MCK_VReg_512; break;
9293 case AMDGPU::VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149: OpKind = MCK_VReg_512; break;
9294 case AMDGPU::VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150: OpKind = MCK_VReg_512; break;
9295 case AMDGPU::VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151: OpKind = MCK_VReg_512; break;
9296 case AMDGPU::VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152: OpKind = MCK_VReg_512; break;
9297 case AMDGPU::VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153: OpKind = MCK_VReg_512; break;
9298 case AMDGPU::VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154: OpKind = MCK_VReg_512; break;
9299 case AMDGPU::VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155: OpKind = MCK_VReg_512; break;
9300 case AMDGPU::VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156: OpKind = MCK_VReg_512; break;
9301 case AMDGPU::VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157: OpKind = MCK_VReg_512; break;
9302 case AMDGPU::VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158: OpKind = MCK_VReg_512; break;
9303 case AMDGPU::VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159: OpKind = MCK_VReg_512; break;
9304 case AMDGPU::VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160: OpKind = MCK_VReg_512; break;
9305 case AMDGPU::VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161: OpKind = MCK_VReg_512; break;
9306 case AMDGPU::VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162: OpKind = MCK_VReg_512; break;
9307 case AMDGPU::VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163: OpKind = MCK_VReg_512; break;
9308 case AMDGPU::VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164: OpKind = MCK_VReg_512; break;
9309 case AMDGPU::VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165: OpKind = MCK_VReg_512; break;
9310 case AMDGPU::VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166: OpKind = MCK_VReg_512; break;
9311 case AMDGPU::VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167: OpKind = MCK_VReg_512; break;
9312 case AMDGPU::VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168: OpKind = MCK_VReg_512; break;
9313 case AMDGPU::VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169: OpKind = MCK_VReg_512; break;
9314 case AMDGPU::VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170: OpKind = MCK_VReg_512; break;
9315 case AMDGPU::VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171: OpKind = MCK_VReg_512; break;
9316 case AMDGPU::VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172: OpKind = MCK_VReg_512; break;
9317 case AMDGPU::VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173: OpKind = MCK_VReg_512; break;
9318 case AMDGPU::VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174: OpKind = MCK_VReg_512; break;
9319 case AMDGPU::VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175: OpKind = MCK_VReg_512; break;
9320 case AMDGPU::VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176: OpKind = MCK_VReg_512; break;
9321 case AMDGPU::VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177: OpKind = MCK_VReg_512; break;
9322 case AMDGPU::VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178: OpKind = MCK_VReg_512; break;
9323 case AMDGPU::VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179: OpKind = MCK_VReg_512; break;
9324 case AMDGPU::VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180: OpKind = MCK_VReg_512; break;
9325 case AMDGPU::VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181: OpKind = MCK_VReg_512; break;
9326 case AMDGPU::VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182: OpKind = MCK_VReg_512; break;
9327 case AMDGPU::VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183: OpKind = MCK_VReg_512; break;
9328 case AMDGPU::VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184: OpKind = MCK_VReg_512; break;
9329 case AMDGPU::VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185: OpKind = MCK_VReg_512; break;
9330 case AMDGPU::VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186: OpKind = MCK_VReg_512; break;
9331 case AMDGPU::VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187: OpKind = MCK_VReg_512; break;
9332 case AMDGPU::VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188: OpKind = MCK_VReg_512; break;
9333 case AMDGPU::VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189: OpKind = MCK_VReg_512; break;
9334 case AMDGPU::VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190: OpKind = MCK_VReg_512; break;
9335 case AMDGPU::VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191: OpKind = MCK_VReg_512; break;
9336 case AMDGPU::VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192: OpKind = MCK_VReg_512; break;
9337 case AMDGPU::VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193: OpKind = MCK_VReg_512; break;
9338 case AMDGPU::VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194: OpKind = MCK_VReg_512; break;
9339 case AMDGPU::VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195: OpKind = MCK_VReg_512; break;
9340 case AMDGPU::VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196: OpKind = MCK_VReg_512; break;
9341 case AMDGPU::VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197: OpKind = MCK_VReg_512; break;
9342 case AMDGPU::VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198: OpKind = MCK_VReg_512; break;
9343 case AMDGPU::VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199: OpKind = MCK_VReg_512; break;
9344 case AMDGPU::VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200: OpKind = MCK_VReg_512; break;
9345 case AMDGPU::VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201: OpKind = MCK_VReg_512; break;
9346 case AMDGPU::VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202: OpKind = MCK_VReg_512; break;
9347 case AMDGPU::VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203: OpKind = MCK_VReg_512; break;
9348 case AMDGPU::VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204: OpKind = MCK_VReg_512; break;
9349 case AMDGPU::VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205: OpKind = MCK_VReg_512; break;
9350 case AMDGPU::VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206: OpKind = MCK_VReg_512; break;
9351 case AMDGPU::VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207: OpKind = MCK_VReg_512; break;
9352 case AMDGPU::VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208: OpKind = MCK_VReg_512; break;
9353 case AMDGPU::VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209: OpKind = MCK_VReg_512; break;
9354 case AMDGPU::VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210: OpKind = MCK_VReg_512; break;
9355 case AMDGPU::VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211: OpKind = MCK_VReg_512; break;
9356 case AMDGPU::VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212: OpKind = MCK_VReg_512; break;
9357 case AMDGPU::VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213: OpKind = MCK_VReg_512; break;
9358 case AMDGPU::VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214: OpKind = MCK_VReg_512; break;
9359 case AMDGPU::VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215: OpKind = MCK_VReg_512; break;
9360 case AMDGPU::VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216: OpKind = MCK_VReg_512; break;
9361 case AMDGPU::VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217: OpKind = MCK_VReg_512; break;
9362 case AMDGPU::VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218: OpKind = MCK_VReg_512; break;
9363 case AMDGPU::VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219: OpKind = MCK_VReg_512; break;
9364 case AMDGPU::VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220: OpKind = MCK_VReg_512; break;
9365 case AMDGPU::VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221: OpKind = MCK_VReg_512; break;
9366 case AMDGPU::VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222: OpKind = MCK_VReg_512; break;
9367 case AMDGPU::VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223: OpKind = MCK_VReg_512; break;
9368 case AMDGPU::VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224: OpKind = MCK_VReg_512; break;
9369 case AMDGPU::VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225: OpKind = MCK_VReg_512; break;
9370 case AMDGPU::VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226: OpKind = MCK_VReg_512; break;
9371 case AMDGPU::VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227: OpKind = MCK_VReg_512; break;
9372 case AMDGPU::VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228: OpKind = MCK_VReg_512; break;
9373 case AMDGPU::VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229: OpKind = MCK_VReg_512; break;
9374 case AMDGPU::VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230: OpKind = MCK_VReg_512; break;
9375 case AMDGPU::VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231: OpKind = MCK_VReg_512; break;
9376 case AMDGPU::VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232: OpKind = MCK_VReg_512; break;
9377 case AMDGPU::VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233: OpKind = MCK_VReg_512; break;
9378 case AMDGPU::VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234: OpKind = MCK_VReg_512; break;
9379 case AMDGPU::VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235: OpKind = MCK_VReg_512; break;
9380 case AMDGPU::VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236: OpKind = MCK_VReg_512; break;
9381 case AMDGPU::VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237: OpKind = MCK_VReg_512; break;
9382 case AMDGPU::VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238: OpKind = MCK_VReg_512; break;
9383 case AMDGPU::VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239: OpKind = MCK_VReg_512; break;
9384 case AMDGPU::VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240: OpKind = MCK_VReg_512; break;
9385 case AMDGPU::VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241: OpKind = MCK_VReg_512; break;
9386 case AMDGPU::VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242: OpKind = MCK_VReg_512; break;
9387 case AMDGPU::VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243: OpKind = MCK_VReg_512; break;
9388 case AMDGPU::VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244: OpKind = MCK_VReg_512; break;
9389 case AMDGPU::VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245: OpKind = MCK_VReg_512; break;
9390 case AMDGPU::VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246: OpKind = MCK_VReg_512; break;
9391 case AMDGPU::VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247: OpKind = MCK_VReg_512; break;
9392 case AMDGPU::VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248: OpKind = MCK_VReg_512; break;
9393 case AMDGPU::VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249: OpKind = MCK_VReg_512; break;
9394 case AMDGPU::VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250: OpKind = MCK_VReg_512; break;
9395 case AMDGPU::VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251: OpKind = MCK_VReg_512; break;
9396 case AMDGPU::VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252: OpKind = MCK_VReg_512; break;
9397 case AMDGPU::VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253: OpKind = MCK_VReg_512; break;
9398 case AMDGPU::VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254: OpKind = MCK_VReg_512; break;
9399 case AMDGPU::VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254_VGPR255: OpKind = MCK_VReg_512; break;
10029 case MCK_VReg_512: return "MCK_VReg_512";
15440 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15444 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15448 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15452 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15456 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15460 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15464 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15468 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15472 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15476 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15515 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15519 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15523 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15527 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15531 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15535 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15539 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15543 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15547 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15551 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15590 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15593 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15596 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15599 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15602 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15605 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15608 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15611 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15614 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15617 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15655 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15658 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15661 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15664 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15667 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15670 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15673 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15676 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15679 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15682 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15830 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15834 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15838 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15842 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15846 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15850 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15854 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15858 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15862 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15866 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15905 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15909 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15913 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15917 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15921 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15925 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15929 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15933 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15937 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15941 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15980 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15983 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15986 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15989 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15992 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15995 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15998 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16001 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16004 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16007 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16045 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16048 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16051 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16054 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16057 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16060 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16063 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16066 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16069 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16072 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16355 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16360 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16365 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16370 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16375 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16380 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16385 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16390 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16395 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16400 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16440 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16445 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16450 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16455 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16460 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16465 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16470 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16475 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16480 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16485 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16525 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16529 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16533 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16537 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16541 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16545 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16549 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16553 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16557 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16561 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16600 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16604 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16608 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16612 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16616 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16620 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16624 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16628 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16632 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16636 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16790 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16795 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16800 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16805 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16810 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16815 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16820 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16825 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16830 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16835 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16875 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16880 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16885 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16890 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16895 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16900 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16905 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16910 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16915 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16920 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16960 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16964 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16968 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16972 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16976 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16980 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16984 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16988 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16992 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16996 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17035 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17039 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17043 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17047 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17051 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17055 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17059 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17063 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17067 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17071 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },