reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
5441 case MCK_VRegWithIntInputMods: { 10062 case MCK_VRegWithIntInputMods: return "MCK_VRegWithIntInputMods"; 23678 { 22797 /* v_dot2c_i32_i16 */, AMDGPU::V_DOT2C_I32_I16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDot4Insts_HasDPP, { MCK_VGPR_32, MCK_VRegWithIntInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23678 { 22797 /* v_dot2c_i32_i16 */, AMDGPU::V_DOT2C_I32_I16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDot4Insts_HasDPP, { MCK_VGPR_32, MCK_VRegWithIntInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23680 { 22841 /* v_dot4c_i32_i8 */, AMDGPU::V_DOT4C_I32_I8_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDot6Insts_HasDPP, { MCK_VGPR_32, MCK_VRegWithIntInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23680 { 22841 /* v_dot4c_i32_i8 */, AMDGPU::V_DOT4C_I32_I8_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDot6Insts_HasDPP, { MCK_VGPR_32, MCK_VRegWithIntInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23681 { 22841 /* v_dot4c_i32_i8 */, AMDGPU::V_DOT4C_I32_I8_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDot6Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithIntInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, }, 23681 { 22841 /* v_dot4c_i32_i8 */, AMDGPU::V_DOT4C_I32_I8_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDot6Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithIntInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, }, 23682 { 22884 /* v_dot8c_i32_i4 */, AMDGPU::V_DOT8C_I32_I4_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDot3Insts_HasDPP, { MCK_VGPR_32, MCK_VRegWithIntInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23682 { 22884 /* v_dot8c_i32_i4 */, AMDGPU::V_DOT8C_I32_I4_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDot3Insts_HasDPP, { MCK_VGPR_32, MCK_VRegWithIntInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23729 { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23730 { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, }, 76912 { 22797 /* v_dot2c_i32_i16 */, 6 /* 1, 2 */, MCK_VRegWithIntInputMods, AMFBS_HasDot4Insts_HasDPP }, 76939 { 22841 /* v_dot4c_i32_i8 */, 6 /* 1, 2 */, MCK_VRegWithIntInputMods, AMFBS_HasDot6Insts_HasDPP }, 76944 { 22841 /* v_dot4c_i32_i8 */, 6 /* 1, 2 */, MCK_VRegWithIntInputMods, AMFBS_HasDot6Insts_isGFX10Plus }, 76970 { 22884 /* v_dot8c_i32_i4 */, 6 /* 1, 2 */, MCK_VRegWithIntInputMods, AMFBS_HasDot3Insts_HasDPP }, 77656 { 23439 /* v_ldexp_f16 */, 4 /* 2 */, MCK_VRegWithIntInputMods, AMFBS_Has16BitInsts_HasDPP }, 77669 { 23439 /* v_ldexp_f16 */, 4 /* 2 */, MCK_VRegWithIntInputMods, AMFBS_HasDPP16_isGFX10Plus }, 80281 case MCK_VRegWithIntInputMods: