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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 5511 case MCK_VReg32OrOff: {
10072 case MCK_VReg32OrOff: return "MCK_VReg32OrOff";
12868 { 3979 /* exp */, AMDGPU::EXP_gfx10, ConvertCustom_cvtExp, AMFBS_isGFX10Plus, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12868 { 3979 /* exp */, AMDGPU::EXP_gfx10, ConvertCustom_cvtExp, AMFBS_isGFX10Plus, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12868 { 3979 /* exp */, AMDGPU::EXP_gfx10, ConvertCustom_cvtExp, AMFBS_isGFX10Plus, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12868 { 3979 /* exp */, AMDGPU::EXP_gfx10, ConvertCustom_cvtExp, AMFBS_isGFX10Plus, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12869 { 3979 /* exp */, AMDGPU::EXP_si, ConvertCustom_cvtExp, AMFBS_isGFX6GFX7, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12869 { 3979 /* exp */, AMDGPU::EXP_si, ConvertCustom_cvtExp, AMFBS_isGFX6GFX7, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12869 { 3979 /* exp */, AMDGPU::EXP_si, ConvertCustom_cvtExp, AMFBS_isGFX6GFX7, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12869 { 3979 /* exp */, AMDGPU::EXP_si, ConvertCustom_cvtExp, AMFBS_isGFX6GFX7, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12870 { 3979 /* exp */, AMDGPU::EXP_vi, ConvertCustom_cvtExp, AMFBS_isGFX8GFX9, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12870 { 3979 /* exp */, AMDGPU::EXP_vi, ConvertCustom_cvtExp, AMFBS_isGFX8GFX9, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12870 { 3979 /* exp */, AMDGPU::EXP_vi, ConvertCustom_cvtExp, AMFBS_isGFX8GFX9, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12870 { 3979 /* exp */, AMDGPU::EXP_vi, ConvertCustom_cvtExp, AMFBS_isGFX8GFX9, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12871 { 3979 /* exp */, AMDGPU::EXP_DONE_gfx10, ConvertCustom_cvtExp, AMFBS_isGFX10Plus, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_done, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12871 { 3979 /* exp */, AMDGPU::EXP_DONE_gfx10, ConvertCustom_cvtExp, AMFBS_isGFX10Plus, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_done, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12871 { 3979 /* exp */, AMDGPU::EXP_DONE_gfx10, ConvertCustom_cvtExp, AMFBS_isGFX10Plus, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_done, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12871 { 3979 /* exp */, AMDGPU::EXP_DONE_gfx10, ConvertCustom_cvtExp, AMFBS_isGFX10Plus, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_done, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12872 { 3979 /* exp */, AMDGPU::EXP_DONE_si, ConvertCustom_cvtExp, AMFBS_isGFX6GFX7, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_done, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12872 { 3979 /* exp */, AMDGPU::EXP_DONE_si, ConvertCustom_cvtExp, AMFBS_isGFX6GFX7, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_done, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12872 { 3979 /* exp */, AMDGPU::EXP_DONE_si, ConvertCustom_cvtExp, AMFBS_isGFX6GFX7, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_done, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12872 { 3979 /* exp */, AMDGPU::EXP_DONE_si, ConvertCustom_cvtExp, AMFBS_isGFX6GFX7, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_done, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12873 { 3979 /* exp */, AMDGPU::EXP_DONE_vi, ConvertCustom_cvtExp, AMFBS_isGFX8GFX9, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_done, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12873 { 3979 /* exp */, AMDGPU::EXP_DONE_vi, ConvertCustom_cvtExp, AMFBS_isGFX8GFX9, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_done, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12873 { 3979 /* exp */, AMDGPU::EXP_DONE_vi, ConvertCustom_cvtExp, AMFBS_isGFX8GFX9, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_done, MCK_ImmExpCompr, MCK_ImmExpVM }, },
12873 { 3979 /* exp */, AMDGPU::EXP_DONE_vi, ConvertCustom_cvtExp, AMFBS_isGFX8GFX9, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_done, MCK_ImmExpCompr, MCK_ImmExpVM }, },
29818 { 3979 /* exp */, 30 /* 1, 2, 3, 4 */, MCK_VReg32OrOff, AMFBS_isGFX10Plus },
29822 { 3979 /* exp */, 30 /* 1, 2, 3, 4 */, MCK_VReg32OrOff, AMFBS_isGFX6GFX7 },
29826 { 3979 /* exp */, 30 /* 1, 2, 3, 4 */, MCK_VReg32OrOff, AMFBS_isGFX8GFX9 },
29830 { 3979 /* exp */, 30 /* 1, 2, 3, 4 */, MCK_VReg32OrOff, AMFBS_isGFX10Plus },
29834 { 3979 /* exp */, 30 /* 1, 2, 3, 4 */, MCK_VReg32OrOff, AMFBS_isGFX6GFX7 },
29838 { 3979 /* exp */, 30 /* 1, 2, 3, 4 */, MCK_VReg32OrOff, AMFBS_isGFX8GFX9 },
80301 case MCK_VReg32OrOff:
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 6987 case MCK_VReg32OrOff: