reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
5735 case MCK_VCSrcF32: { 10104 case MCK_VCSrcF32: return "MCK_VCSrcF32"; 21163 { 23110 /* v_fmaak_f32 */, AMDGPU::V_FMAAK_F32_gfx10, Convert__Reg1_0__VCSrcF321_1__Reg1_2__KImmFP321_3, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VGPR_32, MCK_KImmFP32 }, }, 21167 { 23144 /* v_fmamk_f16 */, AMDGPU::V_FMAMK_F16_gfx10, Convert__Reg1_0__VCSrcF321_1__KImmFP161_2__Reg1_3, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VCSrcF32, MCK_KImmFP16, MCK_VGPR_32 }, }, 21168 { 23156 /* v_fmamk_f32 */, AMDGPU::V_FMAMK_F32_gfx10, Convert__Reg1_0__VCSrcF321_1__KImmFP321_2__Reg1_3, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VCSrcF32, MCK_KImmFP32, MCK_VGPR_32 }, }, 21233 { 23982 /* v_madak_f32 */, AMDGPU::V_MADAK_F32_gfx10, Convert__Reg1_0__VCSrcF321_1__Reg1_2__KImmFP321_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VGPR_32, MCK_KImmFP32 }, }, 21234 { 23982 /* v_madak_f32 */, AMDGPU::V_MADAK_F32_gfx6_gfx7, Convert__Reg1_0__VCSrcF321_1__Reg1_2__KImmFP321_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VGPR_32, MCK_KImmFP32 }, }, 21235 { 23982 /* v_madak_f32 */, AMDGPU::V_MADAK_F32_vi, Convert__Reg1_0__VCSrcF321_1__Reg1_2__KImmFP321_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VGPR_32, MCK_KImmFP32 }, }, 21236 { 23994 /* v_madmk_f16 */, AMDGPU::V_MADMK_F16_vi, Convert__Reg1_0__VCSrcF321_1__KImmFP161_2__Reg1_3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VCSrcF32, MCK_KImmFP16, MCK_VGPR_32 }, }, 21237 { 24006 /* v_madmk_f32 */, AMDGPU::V_MADMK_F32_gfx10, Convert__Reg1_0__VCSrcF321_1__KImmFP321_2__Reg1_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VCSrcF32, MCK_KImmFP32, MCK_VGPR_32 }, }, 21238 { 24006 /* v_madmk_f32 */, AMDGPU::V_MADMK_F32_gfx6_gfx7, Convert__Reg1_0__VCSrcF321_1__KImmFP321_2__Reg1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VCSrcF32, MCK_KImmFP32, MCK_VGPR_32 }, }, 21239 { 24006 /* v_madmk_f32 */, AMDGPU::V_MADMK_F32_vi, Convert__Reg1_0__VCSrcF321_1__KImmFP321_2__Reg1_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VCSrcF32, MCK_KImmFP32, MCK_VGPR_32 }, }, 22198 { 22418 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VCSrcF32 }, }, 22198 { 22418 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VCSrcF32 }, }, 22203 { 22460 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VCSrcF32 }, }, 22203 { 22460 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VCSrcF32 }, }, 22209 { 22502 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VCSrcF32 }, }, 22209 { 22502 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VCSrcF32 }, }, 22213 { 22523 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0__imm_95_0, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VCSrcF32 }, }, 22213 { 22523 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0__imm_95_0, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VCSrcF32 }, }, 22347 { 23451 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0__imm_95_0, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VCSrcF32 }, }, 22347 { 23451 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0__imm_95_0, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VCSrcF32 }, },