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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 4581 case MCK_VCC_LO:
6314 case AMDGPU::VCC_LO: OpKind = MCK_VCC_LO; break;
9945 case MCK_VCC_LO: return "MCK_VCC_LO";
18853 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
18853 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
18856 { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
18869 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
18869 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
18900 { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
18901 { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
18910 { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
18911 { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_e32_gfx10, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
18912 { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
18922 { 13713 /* v_cmp_class_f64 */, AMDGPU::V_CMP_CLASS_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VGPR_32 }, },
18923 { 13713 /* v_cmp_class_f64 */, AMDGPU::V_CMP_CLASS_F64_e32_gfx10, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VGPR_32 }, },
18924 { 13713 /* v_cmp_class_f64 */, AMDGPU::V_CMP_CLASS_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VGPR_32 }, },
18932 { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
18933 { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
18942 { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
18943 { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_e32_gfx10, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
18944 { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
18954 { 13809 /* v_cmp_eq_f64 */, AMDGPU::V_CMP_EQ_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
18955 { 13809 /* v_cmp_eq_f64 */, AMDGPU::V_CMP_EQ_F64_e32_gfx10, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
18956 { 13809 /* v_cmp_eq_f64 */, AMDGPU::V_CMP_EQ_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
18964 { 13839 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
18965 { 13839 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
18974 { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
18975 { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
18976 { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
18986 { 13899 /* v_cmp_eq_i64 */, AMDGPU::V_CMP_EQ_I64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
18987 { 13899 /* v_cmp_eq_i64 */, AMDGPU::V_CMP_EQ_I64_e32_gfx10, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
18988 { 13899 /* v_cmp_eq_i64 */, AMDGPU::V_CMP_EQ_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
18996 { 13929 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
18997 { 13929 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19006 { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19007 { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19008 { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19018 { 13989 /* v_cmp_eq_u64 */, AMDGPU::V_CMP_EQ_U64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19019 { 13989 /* v_cmp_eq_u64 */, AMDGPU::V_CMP_EQ_U64_e32_gfx10, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19020 { 13989 /* v_cmp_eq_u64 */, AMDGPU::V_CMP_EQ_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19028 { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19029 { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19038 { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19039 { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_e32_gfx10, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19040 { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19050 { 14075 /* v_cmp_f_f64 */, AMDGPU::V_CMP_F_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19051 { 14075 /* v_cmp_f_f64 */, AMDGPU::V_CMP_F_F64_e32_gfx10, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19052 { 14075 /* v_cmp_f_f64 */, AMDGPU::V_CMP_F_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19058 { 14103 /* v_cmp_f_i16 */, AMDGPU::V_CMP_F_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19066 { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19067 { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19068 { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19078 { 14159 /* v_cmp_f_i64 */, AMDGPU::V_CMP_F_I64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19079 { 14159 /* v_cmp_f_i64 */, AMDGPU::V_CMP_F_I64_e32_gfx10, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19080 { 14159 /* v_cmp_f_i64 */, AMDGPU::V_CMP_F_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19086 { 14187 /* v_cmp_f_u16 */, AMDGPU::V_CMP_F_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19094 { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19095 { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19096 { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19106 { 14243 /* v_cmp_f_u64 */, AMDGPU::V_CMP_F_U64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19107 { 14243 /* v_cmp_f_u64 */, AMDGPU::V_CMP_F_U64_e32_gfx10, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19108 { 14243 /* v_cmp_f_u64 */, AMDGPU::V_CMP_F_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19116 { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19117 { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19126 { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19127 { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_e32_gfx10, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19128 { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19138 { 14331 /* v_cmp_ge_f64 */, AMDGPU::V_CMP_GE_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19139 { 14331 /* v_cmp_ge_f64 */, AMDGPU::V_CMP_GE_F64_e32_gfx10, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19140 { 14331 /* v_cmp_ge_f64 */, AMDGPU::V_CMP_GE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19148 { 14361 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19149 { 14361 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19158 { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19159 { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19160 { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19170 { 14421 /* v_cmp_ge_i64 */, AMDGPU::V_CMP_GE_I64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19171 { 14421 /* v_cmp_ge_i64 */, AMDGPU::V_CMP_GE_I64_e32_gfx10, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19172 { 14421 /* v_cmp_ge_i64 */, AMDGPU::V_CMP_GE_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19180 { 14451 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19181 { 14451 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19190 { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19191 { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19192 { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19202 { 14511 /* v_cmp_ge_u64 */, AMDGPU::V_CMP_GE_U64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19203 { 14511 /* v_cmp_ge_u64 */, AMDGPU::V_CMP_GE_U64_e32_gfx10, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19204 { 14511 /* v_cmp_ge_u64 */, AMDGPU::V_CMP_GE_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19212 { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19213 { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19222 { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19223 { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_e32_gfx10, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19224 { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19234 { 14601 /* v_cmp_gt_f64 */, AMDGPU::V_CMP_GT_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19235 { 14601 /* v_cmp_gt_f64 */, AMDGPU::V_CMP_GT_F64_e32_gfx10, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19236 { 14601 /* v_cmp_gt_f64 */, AMDGPU::V_CMP_GT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19244 { 14631 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19245 { 14631 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19254 { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19255 { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19256 { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19266 { 14691 /* v_cmp_gt_i64 */, AMDGPU::V_CMP_GT_I64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19267 { 14691 /* v_cmp_gt_i64 */, AMDGPU::V_CMP_GT_I64_e32_gfx10, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19268 { 14691 /* v_cmp_gt_i64 */, AMDGPU::V_CMP_GT_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19276 { 14721 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19277 { 14721 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19286 { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19287 { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19288 { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19298 { 14781 /* v_cmp_gt_u64 */, AMDGPU::V_CMP_GT_U64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19299 { 14781 /* v_cmp_gt_u64 */, AMDGPU::V_CMP_GT_U64_e32_gfx10, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19300 { 14781 /* v_cmp_gt_u64 */, AMDGPU::V_CMP_GT_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19308 { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19309 { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19318 { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19319 { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_e32_gfx10, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19320 { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19330 { 14871 /* v_cmp_le_f64 */, AMDGPU::V_CMP_LE_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19331 { 14871 /* v_cmp_le_f64 */, AMDGPU::V_CMP_LE_F64_e32_gfx10, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19332 { 14871 /* v_cmp_le_f64 */, AMDGPU::V_CMP_LE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19340 { 14901 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19341 { 14901 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19350 { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19351 { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19352 { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19362 { 14961 /* v_cmp_le_i64 */, AMDGPU::V_CMP_LE_I64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19363 { 14961 /* v_cmp_le_i64 */, AMDGPU::V_CMP_LE_I64_e32_gfx10, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19364 { 14961 /* v_cmp_le_i64 */, AMDGPU::V_CMP_LE_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19372 { 14991 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19373 { 14991 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19382 { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19383 { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19384 { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19394 { 15051 /* v_cmp_le_u64 */, AMDGPU::V_CMP_LE_U64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19395 { 15051 /* v_cmp_le_u64 */, AMDGPU::V_CMP_LE_U64_e32_gfx10, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19396 { 15051 /* v_cmp_le_u64 */, AMDGPU::V_CMP_LE_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19404 { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19405 { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19414 { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19415 { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_e32_gfx10, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19416 { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19426 { 15141 /* v_cmp_lg_f64 */, AMDGPU::V_CMP_LG_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19427 { 15141 /* v_cmp_lg_f64 */, AMDGPU::V_CMP_LG_F64_e32_gfx10, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19428 { 15141 /* v_cmp_lg_f64 */, AMDGPU::V_CMP_LG_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19436 { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19437 { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19446 { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19447 { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_e32_gfx10, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19448 { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19458 { 15231 /* v_cmp_lt_f64 */, AMDGPU::V_CMP_LT_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19459 { 15231 /* v_cmp_lt_f64 */, AMDGPU::V_CMP_LT_F64_e32_gfx10, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19460 { 15231 /* v_cmp_lt_f64 */, AMDGPU::V_CMP_LT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19468 { 15261 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19469 { 15261 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19478 { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19479 { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19480 { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19490 { 15321 /* v_cmp_lt_i64 */, AMDGPU::V_CMP_LT_I64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19491 { 15321 /* v_cmp_lt_i64 */, AMDGPU::V_CMP_LT_I64_e32_gfx10, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19492 { 15321 /* v_cmp_lt_i64 */, AMDGPU::V_CMP_LT_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19500 { 15351 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19501 { 15351 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19510 { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19511 { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19512 { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19522 { 15411 /* v_cmp_lt_u64 */, AMDGPU::V_CMP_LT_U64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19523 { 15411 /* v_cmp_lt_u64 */, AMDGPU::V_CMP_LT_U64_e32_gfx10, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19524 { 15411 /* v_cmp_lt_u64 */, AMDGPU::V_CMP_LT_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19532 { 15441 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19533 { 15441 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19542 { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19543 { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19544 { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19554 { 15501 /* v_cmp_ne_i64 */, AMDGPU::V_CMP_NE_I64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19555 { 15501 /* v_cmp_ne_i64 */, AMDGPU::V_CMP_NE_I64_e32_gfx10, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19556 { 15501 /* v_cmp_ne_i64 */, AMDGPU::V_CMP_NE_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19564 { 15531 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19565 { 15531 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19574 { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19575 { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19576 { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19586 { 15591 /* v_cmp_ne_u64 */, AMDGPU::V_CMP_NE_U64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19587 { 15591 /* v_cmp_ne_u64 */, AMDGPU::V_CMP_NE_U64_e32_gfx10, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19588 { 15591 /* v_cmp_ne_u64 */, AMDGPU::V_CMP_NE_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19596 { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19597 { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19606 { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19607 { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_e32_gfx10, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19608 { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19618 { 15685 /* v_cmp_neq_f64 */, AMDGPU::V_CMP_NEQ_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19619 { 15685 /* v_cmp_neq_f64 */, AMDGPU::V_CMP_NEQ_F64_e32_gfx10, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19620 { 15685 /* v_cmp_neq_f64 */, AMDGPU::V_CMP_NEQ_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19628 { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19629 { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19638 { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19639 { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_e32_gfx10, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19640 { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19650 { 15781 /* v_cmp_nge_f64 */, AMDGPU::V_CMP_NGE_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19651 { 15781 /* v_cmp_nge_f64 */, AMDGPU::V_CMP_NGE_F64_e32_gfx10, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19652 { 15781 /* v_cmp_nge_f64 */, AMDGPU::V_CMP_NGE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19660 { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19661 { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19670 { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19671 { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_e32_gfx10, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19672 { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19682 { 15877 /* v_cmp_ngt_f64 */, AMDGPU::V_CMP_NGT_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19683 { 15877 /* v_cmp_ngt_f64 */, AMDGPU::V_CMP_NGT_F64_e32_gfx10, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19684 { 15877 /* v_cmp_ngt_f64 */, AMDGPU::V_CMP_NGT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19692 { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19693 { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19702 { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19703 { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_e32_gfx10, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19704 { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19714 { 15973 /* v_cmp_nle_f64 */, AMDGPU::V_CMP_NLE_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19715 { 15973 /* v_cmp_nle_f64 */, AMDGPU::V_CMP_NLE_F64_e32_gfx10, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19716 { 15973 /* v_cmp_nle_f64 */, AMDGPU::V_CMP_NLE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19724 { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19725 { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19734 { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19735 { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_e32_gfx10, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19736 { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19746 { 16069 /* v_cmp_nlg_f64 */, AMDGPU::V_CMP_NLG_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19747 { 16069 /* v_cmp_nlg_f64 */, AMDGPU::V_CMP_NLG_F64_e32_gfx10, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19748 { 16069 /* v_cmp_nlg_f64 */, AMDGPU::V_CMP_NLG_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19756 { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19757 { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19766 { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19767 { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_e32_gfx10, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19768 { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19778 { 16165 /* v_cmp_nlt_f64 */, AMDGPU::V_CMP_NLT_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19779 { 16165 /* v_cmp_nlt_f64 */, AMDGPU::V_CMP_NLT_F64_e32_gfx10, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19780 { 16165 /* v_cmp_nlt_f64 */, AMDGPU::V_CMP_NLT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19788 { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19789 { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19798 { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19799 { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_e32_gfx10, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19800 { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19810 { 16253 /* v_cmp_o_f64 */, AMDGPU::V_CMP_O_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19811 { 16253 /* v_cmp_o_f64 */, AMDGPU::V_CMP_O_F64_e32_gfx10, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19812 { 16253 /* v_cmp_o_f64 */, AMDGPU::V_CMP_O_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19818 { 16281 /* v_cmp_t_i16 */, AMDGPU::V_CMP_T_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19826 { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19827 { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19828 { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19838 { 16337 /* v_cmp_t_i64 */, AMDGPU::V_CMP_T_I64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19839 { 16337 /* v_cmp_t_i64 */, AMDGPU::V_CMP_T_I64_e32_gfx10, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19840 { 16337 /* v_cmp_t_i64 */, AMDGPU::V_CMP_T_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19846 { 16365 /* v_cmp_t_u16 */, AMDGPU::V_CMP_T_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19854 { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19855 { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e32_gfx10, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19856 { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
19866 { 16421 /* v_cmp_t_u64 */, AMDGPU::V_CMP_T_U64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19867 { 16421 /* v_cmp_t_u64 */, AMDGPU::V_CMP_T_U64_e32_gfx10, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19868 { 16421 /* v_cmp_t_u64 */, AMDGPU::V_CMP_T_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
19876 { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19877 { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19886 { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19887 { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_e32_gfx10, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19888 { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19898 { 16513 /* v_cmp_tru_f64 */, AMDGPU::V_CMP_TRU_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19899 { 16513 /* v_cmp_tru_f64 */, AMDGPU::V_CMP_TRU_F64_e32_gfx10, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19900 { 16513 /* v_cmp_tru_f64 */, AMDGPU::V_CMP_TRU_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19908 { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19909 { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19918 { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19919 { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_e32_gfx10, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19920 { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19930 { 16601 /* v_cmp_u_f64 */, AMDGPU::V_CMP_U_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19931 { 16601 /* v_cmp_u_f64 */, AMDGPU::V_CMP_U_F64_e32_gfx10, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19932 { 16601 /* v_cmp_u_f64 */, AMDGPU::V_CMP_U_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19938 { 16629 /* v_cmps_eq_f32 */, AMDGPU::V_CMPS_EQ_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19942 { 16661 /* v_cmps_eq_f64 */, AMDGPU::V_CMPS_EQ_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19946 { 16693 /* v_cmps_f_f32 */, AMDGPU::V_CMPS_F_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19950 { 16723 /* v_cmps_f_f64 */, AMDGPU::V_CMPS_F_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19954 { 16753 /* v_cmps_ge_f32 */, AMDGPU::V_CMPS_GE_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19958 { 16785 /* v_cmps_ge_f64 */, AMDGPU::V_CMPS_GE_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19962 { 16817 /* v_cmps_gt_f32 */, AMDGPU::V_CMPS_GT_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19966 { 16849 /* v_cmps_gt_f64 */, AMDGPU::V_CMPS_GT_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19970 { 16881 /* v_cmps_le_f32 */, AMDGPU::V_CMPS_LE_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19974 { 16913 /* v_cmps_le_f64 */, AMDGPU::V_CMPS_LE_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19978 { 16945 /* v_cmps_lg_f32 */, AMDGPU::V_CMPS_LG_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19982 { 16977 /* v_cmps_lg_f64 */, AMDGPU::V_CMPS_LG_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19986 { 17009 /* v_cmps_lt_f32 */, AMDGPU::V_CMPS_LT_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19990 { 17041 /* v_cmps_lt_f64 */, AMDGPU::V_CMPS_LT_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
19994 { 17073 /* v_cmps_neq_f32 */, AMDGPU::V_CMPS_NEQ_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
19998 { 17107 /* v_cmps_neq_f64 */, AMDGPU::V_CMPS_NEQ_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20002 { 17141 /* v_cmps_nge_f32 */, AMDGPU::V_CMPS_NGE_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20006 { 17175 /* v_cmps_nge_f64 */, AMDGPU::V_CMPS_NGE_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20010 { 17209 /* v_cmps_ngt_f32 */, AMDGPU::V_CMPS_NGT_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20014 { 17243 /* v_cmps_ngt_f64 */, AMDGPU::V_CMPS_NGT_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20018 { 17277 /* v_cmps_nle_f32 */, AMDGPU::V_CMPS_NLE_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20022 { 17311 /* v_cmps_nle_f64 */, AMDGPU::V_CMPS_NLE_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20026 { 17345 /* v_cmps_nlg_f32 */, AMDGPU::V_CMPS_NLG_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20030 { 17379 /* v_cmps_nlg_f64 */, AMDGPU::V_CMPS_NLG_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20034 { 17413 /* v_cmps_nlt_f32 */, AMDGPU::V_CMPS_NLT_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20038 { 17447 /* v_cmps_nlt_f64 */, AMDGPU::V_CMPS_NLT_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20042 { 17481 /* v_cmps_o_f32 */, AMDGPU::V_CMPS_O_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20046 { 17511 /* v_cmps_o_f64 */, AMDGPU::V_CMPS_O_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20050 { 17541 /* v_cmps_tru_f32 */, AMDGPU::V_CMPS_TRU_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20054 { 17575 /* v_cmps_tru_f64 */, AMDGPU::V_CMPS_TRU_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20058 { 17609 /* v_cmps_u_f32 */, AMDGPU::V_CMPS_U_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20062 { 17639 /* v_cmps_u_f64 */, AMDGPU::V_CMPS_U_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20066 { 17669 /* v_cmpsx_eq_f32 */, AMDGPU::V_CMPSX_EQ_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20070 { 17703 /* v_cmpsx_eq_f64 */, AMDGPU::V_CMPSX_EQ_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20074 { 17737 /* v_cmpsx_f_f32 */, AMDGPU::V_CMPSX_F_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20078 { 17769 /* v_cmpsx_f_f64 */, AMDGPU::V_CMPSX_F_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20082 { 17801 /* v_cmpsx_ge_f32 */, AMDGPU::V_CMPSX_GE_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20086 { 17835 /* v_cmpsx_ge_f64 */, AMDGPU::V_CMPSX_GE_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20090 { 17869 /* v_cmpsx_gt_f32 */, AMDGPU::V_CMPSX_GT_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20094 { 17903 /* v_cmpsx_gt_f64 */, AMDGPU::V_CMPSX_GT_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20098 { 17937 /* v_cmpsx_le_f32 */, AMDGPU::V_CMPSX_LE_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20102 { 17971 /* v_cmpsx_le_f64 */, AMDGPU::V_CMPSX_LE_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20106 { 18005 /* v_cmpsx_lg_f32 */, AMDGPU::V_CMPSX_LG_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20110 { 18039 /* v_cmpsx_lg_f64 */, AMDGPU::V_CMPSX_LG_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20114 { 18073 /* v_cmpsx_lt_f32 */, AMDGPU::V_CMPSX_LT_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20118 { 18107 /* v_cmpsx_lt_f64 */, AMDGPU::V_CMPSX_LT_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20122 { 18141 /* v_cmpsx_neq_f32 */, AMDGPU::V_CMPSX_NEQ_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20126 { 18177 /* v_cmpsx_neq_f64 */, AMDGPU::V_CMPSX_NEQ_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20130 { 18213 /* v_cmpsx_nge_f32 */, AMDGPU::V_CMPSX_NGE_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20134 { 18249 /* v_cmpsx_nge_f64 */, AMDGPU::V_CMPSX_NGE_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20138 { 18285 /* v_cmpsx_ngt_f32 */, AMDGPU::V_CMPSX_NGT_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20142 { 18321 /* v_cmpsx_ngt_f64 */, AMDGPU::V_CMPSX_NGT_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20146 { 18357 /* v_cmpsx_nle_f32 */, AMDGPU::V_CMPSX_NLE_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20150 { 18393 /* v_cmpsx_nle_f64 */, AMDGPU::V_CMPSX_NLE_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20154 { 18429 /* v_cmpsx_nlg_f32 */, AMDGPU::V_CMPSX_NLG_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20158 { 18465 /* v_cmpsx_nlg_f64 */, AMDGPU::V_CMPSX_NLG_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20162 { 18501 /* v_cmpsx_nlt_f32 */, AMDGPU::V_CMPSX_NLT_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20166 { 18537 /* v_cmpsx_nlt_f64 */, AMDGPU::V_CMPSX_NLT_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20170 { 18573 /* v_cmpsx_o_f32 */, AMDGPU::V_CMPSX_O_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20174 { 18605 /* v_cmpsx_o_f64 */, AMDGPU::V_CMPSX_O_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20178 { 18637 /* v_cmpsx_tru_f32 */, AMDGPU::V_CMPSX_TRU_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20182 { 18673 /* v_cmpsx_tru_f64 */, AMDGPU::V_CMPSX_TRU_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20186 { 18709 /* v_cmpsx_u_f32 */, AMDGPU::V_CMPSX_U_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20190 { 18741 /* v_cmpsx_u_f64 */, AMDGPU::V_CMPSX_U_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20195 { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20203 { 18811 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20204 { 18811 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20213 { 18849 /* v_cmpx_class_f64 */, AMDGPU::V_CMPX_CLASS_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VGPR_32 }, },
20214 { 18849 /* v_cmpx_class_f64 */, AMDGPU::V_CMPX_CLASS_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VGPR_32 }, },
20221 { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20229 { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20230 { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20239 { 18951 /* v_cmpx_eq_f64 */, AMDGPU::V_CMPX_EQ_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20240 { 18951 /* v_cmpx_eq_f64 */, AMDGPU::V_CMPX_EQ_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20247 { 18983 /* v_cmpx_eq_i16 */, AMDGPU::V_CMPX_EQ_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20255 { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20256 { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20265 { 19047 /* v_cmpx_eq_i64 */, AMDGPU::V_CMPX_EQ_I64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20266 { 19047 /* v_cmpx_eq_i64 */, AMDGPU::V_CMPX_EQ_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20273 { 19079 /* v_cmpx_eq_u16 */, AMDGPU::V_CMPX_EQ_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20281 { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20282 { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20291 { 19143 /* v_cmpx_eq_u64 */, AMDGPU::V_CMPX_EQ_U64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20292 { 19143 /* v_cmpx_eq_u64 */, AMDGPU::V_CMPX_EQ_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20299 { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20307 { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20308 { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20317 { 19235 /* v_cmpx_f_f64 */, AMDGPU::V_CMPX_F_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20318 { 19235 /* v_cmpx_f_f64 */, AMDGPU::V_CMPX_F_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20324 { 19265 /* v_cmpx_f_i16 */, AMDGPU::V_CMPX_F_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20331 { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20332 { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20341 { 19325 /* v_cmpx_f_i64 */, AMDGPU::V_CMPX_F_I64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20342 { 19325 /* v_cmpx_f_i64 */, AMDGPU::V_CMPX_F_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20348 { 19355 /* v_cmpx_f_u16 */, AMDGPU::V_CMPX_F_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20355 { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20356 { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20365 { 19415 /* v_cmpx_f_u64 */, AMDGPU::V_CMPX_F_U64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20366 { 19415 /* v_cmpx_f_u64 */, AMDGPU::V_CMPX_F_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20373 { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20381 { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20382 { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20391 { 19509 /* v_cmpx_ge_f64 */, AMDGPU::V_CMPX_GE_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20392 { 19509 /* v_cmpx_ge_f64 */, AMDGPU::V_CMPX_GE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20399 { 19541 /* v_cmpx_ge_i16 */, AMDGPU::V_CMPX_GE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20407 { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20408 { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20417 { 19605 /* v_cmpx_ge_i64 */, AMDGPU::V_CMPX_GE_I64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20418 { 19605 /* v_cmpx_ge_i64 */, AMDGPU::V_CMPX_GE_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20425 { 19637 /* v_cmpx_ge_u16 */, AMDGPU::V_CMPX_GE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20433 { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20434 { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20443 { 19701 /* v_cmpx_ge_u64 */, AMDGPU::V_CMPX_GE_U64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20444 { 19701 /* v_cmpx_ge_u64 */, AMDGPU::V_CMPX_GE_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20451 { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20459 { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20460 { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20469 { 19797 /* v_cmpx_gt_f64 */, AMDGPU::V_CMPX_GT_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20470 { 19797 /* v_cmpx_gt_f64 */, AMDGPU::V_CMPX_GT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20477 { 19829 /* v_cmpx_gt_i16 */, AMDGPU::V_CMPX_GT_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20485 { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20486 { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20495 { 19893 /* v_cmpx_gt_i64 */, AMDGPU::V_CMPX_GT_I64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20496 { 19893 /* v_cmpx_gt_i64 */, AMDGPU::V_CMPX_GT_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20503 { 19925 /* v_cmpx_gt_u16 */, AMDGPU::V_CMPX_GT_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20511 { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20512 { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20521 { 19989 /* v_cmpx_gt_u64 */, AMDGPU::V_CMPX_GT_U64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20522 { 19989 /* v_cmpx_gt_u64 */, AMDGPU::V_CMPX_GT_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20529 { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20537 { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20538 { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20547 { 20085 /* v_cmpx_le_f64 */, AMDGPU::V_CMPX_LE_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20548 { 20085 /* v_cmpx_le_f64 */, AMDGPU::V_CMPX_LE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20555 { 20117 /* v_cmpx_le_i16 */, AMDGPU::V_CMPX_LE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20563 { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20564 { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20573 { 20181 /* v_cmpx_le_i64 */, AMDGPU::V_CMPX_LE_I64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20574 { 20181 /* v_cmpx_le_i64 */, AMDGPU::V_CMPX_LE_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20581 { 20213 /* v_cmpx_le_u16 */, AMDGPU::V_CMPX_LE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20589 { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20590 { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20599 { 20277 /* v_cmpx_le_u64 */, AMDGPU::V_CMPX_LE_U64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20600 { 20277 /* v_cmpx_le_u64 */, AMDGPU::V_CMPX_LE_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20607 { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20615 { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20616 { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20625 { 20373 /* v_cmpx_lg_f64 */, AMDGPU::V_CMPX_LG_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20626 { 20373 /* v_cmpx_lg_f64 */, AMDGPU::V_CMPX_LG_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20633 { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20641 { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20642 { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20651 { 20469 /* v_cmpx_lt_f64 */, AMDGPU::V_CMPX_LT_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20652 { 20469 /* v_cmpx_lt_f64 */, AMDGPU::V_CMPX_LT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20659 { 20501 /* v_cmpx_lt_i16 */, AMDGPU::V_CMPX_LT_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20667 { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20668 { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20677 { 20565 /* v_cmpx_lt_i64 */, AMDGPU::V_CMPX_LT_I64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20678 { 20565 /* v_cmpx_lt_i64 */, AMDGPU::V_CMPX_LT_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20685 { 20597 /* v_cmpx_lt_u16 */, AMDGPU::V_CMPX_LT_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20693 { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20694 { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20703 { 20661 /* v_cmpx_lt_u64 */, AMDGPU::V_CMPX_LT_U64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20704 { 20661 /* v_cmpx_lt_u64 */, AMDGPU::V_CMPX_LT_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20711 { 20693 /* v_cmpx_ne_i16 */, AMDGPU::V_CMPX_NE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20719 { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20720 { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20729 { 20757 /* v_cmpx_ne_i64 */, AMDGPU::V_CMPX_NE_I64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20730 { 20757 /* v_cmpx_ne_i64 */, AMDGPU::V_CMPX_NE_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20737 { 20789 /* v_cmpx_ne_u16 */, AMDGPU::V_CMPX_NE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20745 { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20746 { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20755 { 20853 /* v_cmpx_ne_u64 */, AMDGPU::V_CMPX_NE_U64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20756 { 20853 /* v_cmpx_ne_u64 */, AMDGPU::V_CMPX_NE_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20763 { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20771 { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20772 { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20781 { 20953 /* v_cmpx_neq_f64 */, AMDGPU::V_CMPX_NEQ_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20782 { 20953 /* v_cmpx_neq_f64 */, AMDGPU::V_CMPX_NEQ_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20789 { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20797 { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20798 { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20807 { 21055 /* v_cmpx_nge_f64 */, AMDGPU::V_CMPX_NGE_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20808 { 21055 /* v_cmpx_nge_f64 */, AMDGPU::V_CMPX_NGE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20815 { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20823 { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20824 { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20833 { 21157 /* v_cmpx_ngt_f64 */, AMDGPU::V_CMPX_NGT_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20834 { 21157 /* v_cmpx_ngt_f64 */, AMDGPU::V_CMPX_NGT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20841 { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20849 { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20850 { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20859 { 21259 /* v_cmpx_nle_f64 */, AMDGPU::V_CMPX_NLE_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20860 { 21259 /* v_cmpx_nle_f64 */, AMDGPU::V_CMPX_NLE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20867 { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20875 { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20876 { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20885 { 21361 /* v_cmpx_nlg_f64 */, AMDGPU::V_CMPX_NLG_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20886 { 21361 /* v_cmpx_nlg_f64 */, AMDGPU::V_CMPX_NLG_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20893 { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20901 { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20902 { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20911 { 21463 /* v_cmpx_nlt_f64 */, AMDGPU::V_CMPX_NLT_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20912 { 21463 /* v_cmpx_nlt_f64 */, AMDGPU::V_CMPX_NLT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20919 { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20927 { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20928 { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
20937 { 21557 /* v_cmpx_o_f64 */, AMDGPU::V_CMPX_O_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20938 { 21557 /* v_cmpx_o_f64 */, AMDGPU::V_CMPX_O_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
20944 { 21587 /* v_cmpx_t_i16 */, AMDGPU::V_CMPX_T_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20951 { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20952 { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20961 { 21647 /* v_cmpx_t_i64 */, AMDGPU::V_CMPX_T_I64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20962 { 21647 /* v_cmpx_t_i64 */, AMDGPU::V_CMPX_T_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20968 { 21677 /* v_cmpx_t_u16 */, AMDGPU::V_CMPX_T_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20975 { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e32_gfx6_gfx7, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20976 { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
20985 { 21737 /* v_cmpx_t_u64 */, AMDGPU::V_CMPX_T_U64_e32_gfx6_gfx7, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20986 { 21737 /* v_cmpx_t_u64 */, AMDGPU::V_CMPX_T_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB64, MCK_VReg_64 }, },
20993 { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
21001 { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
21002 { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
21011 { 21835 /* v_cmpx_tru_f64 */, AMDGPU::V_CMPX_TRU_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
21012 { 21835 /* v_cmpx_tru_f64 */, AMDGPU::V_CMPX_TRU_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
21019 { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
21027 { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_e32_gfx6_gfx7, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
21028 { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF32, MCK_VGPR_32 }, },
21037 { 21929 /* v_cmpx_u_f64 */, AMDGPU::V_CMPX_U_F64_e32_gfx6_gfx7, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
21038 { 21929 /* v_cmpx_u_f64 */, AMDGPU::V_CMPX_U_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF64, MCK_VReg_64 }, },
21048 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21049 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21050 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21374 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21374 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21377 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
21390 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21390 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21395 { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21395 { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21400 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21400 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21403 { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
21441 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21441 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21444 { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
21468 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21468 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22111 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22112 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22113 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22723 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22723 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22726 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
22745 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22745 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22750 { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22750 { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22755 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22755 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22758 { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
22794 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22794 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22796 { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
22802 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22802 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22945 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22946 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22947 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23033 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23033 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23035 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23041 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23041 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23044 { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23044 { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23047 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23047 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23049 { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23062 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23062 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23065 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23065 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23067 { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23077 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23077 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23349 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23350 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23351 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23355 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2e, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23511 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23511 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23514 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23514 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23516 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23526 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23526 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23529 { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23529 { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23532 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23532 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23535 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23535 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23537 { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23558 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23558 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23561 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_dpp8_w32_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPP8, MCK_ImmFI }, },
23561 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_dpp8_w32_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPP8, MCK_ImmFI }, },
23564 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_dpp_w32_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23564 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_dpp_w32_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23566 { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23580 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23580 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23602 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23603 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23604 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23607 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp8_w32_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPP8, MCK_ImmFI }, },
23611 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp_w32_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23852 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23852 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23855 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_dpp8_w32_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPP8, MCK_ImmFI }, },
23855 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_dpp8_w32_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPP8, MCK_ImmFI }, },
23858 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_dpp_w32_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23858 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_dpp_w32_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23860 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23874 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23874 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23878 { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23878 { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23882 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23882 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23885 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_dpp8_w32_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPP8, MCK_ImmFI }, },
23885 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_dpp8_w32_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPP8, MCK_ImmFI }, },
23888 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_dpp_w32_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23888 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_dpp_w32_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23890 { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },