reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
6302 case MCK_U16Imm: { 10185 case MCK_U16Imm: return "MCK_U16Imm"; 18177 { 10039 /* s_cmpk_eq_u32 */, AMDGPU::S_CMPK_EQ_U32_gfx10, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_U16Imm }, }, 18178 { 10039 /* s_cmpk_eq_u32 */, AMDGPU::S_CMPK_EQ_U32_gfx6_gfx7, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_U16Imm }, }, 18179 { 10039 /* s_cmpk_eq_u32 */, AMDGPU::S_CMPK_EQ_U32_vi, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_U16Imm }, }, 18183 { 10067 /* s_cmpk_ge_u32 */, AMDGPU::S_CMPK_GE_U32_gfx10, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_U16Imm }, }, 18184 { 10067 /* s_cmpk_ge_u32 */, AMDGPU::S_CMPK_GE_U32_gfx6_gfx7, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_U16Imm }, }, 18185 { 10067 /* s_cmpk_ge_u32 */, AMDGPU::S_CMPK_GE_U32_vi, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_U16Imm }, }, 18189 { 10095 /* s_cmpk_gt_u32 */, AMDGPU::S_CMPK_GT_U32_gfx10, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_U16Imm }, }, 18190 { 10095 /* s_cmpk_gt_u32 */, AMDGPU::S_CMPK_GT_U32_gfx6_gfx7, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_U16Imm }, }, 18191 { 10095 /* s_cmpk_gt_u32 */, AMDGPU::S_CMPK_GT_U32_vi, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_U16Imm }, }, 18195 { 10123 /* s_cmpk_le_u32 */, AMDGPU::S_CMPK_LE_U32_gfx10, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_U16Imm }, }, 18196 { 10123 /* s_cmpk_le_u32 */, AMDGPU::S_CMPK_LE_U32_gfx6_gfx7, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_U16Imm }, }, 18197 { 10123 /* s_cmpk_le_u32 */, AMDGPU::S_CMPK_LE_U32_vi, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_U16Imm }, }, 18201 { 10151 /* s_cmpk_lg_u32 */, AMDGPU::S_CMPK_LG_U32_gfx10, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_U16Imm }, }, 18202 { 10151 /* s_cmpk_lg_u32 */, AMDGPU::S_CMPK_LG_U32_gfx6_gfx7, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_U16Imm }, }, 18203 { 10151 /* s_cmpk_lg_u32 */, AMDGPU::S_CMPK_LG_U32_vi, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_U16Imm }, }, 18207 { 10179 /* s_cmpk_lt_u32 */, AMDGPU::S_CMPK_LT_U32_gfx10, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_U16Imm }, }, 18208 { 10179 /* s_cmpk_lt_u32 */, AMDGPU::S_CMPK_LT_U32_gfx6_gfx7, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_U16Imm }, }, 18209 { 10179 /* s_cmpk_lt_u32 */, AMDGPU::S_CMPK_LT_U32_vi, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_U16Imm }, },