|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 5497 case MCK_SoppBrTarget: {
10070 case MCK_SoppBrTarget: return "MCK_SoppBrTarget";
17859 { 8774 /* s_branch */, AMDGPU::S_BRANCH, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
17860 { 8774 /* s_branch */, AMDGPU::S_BRANCH_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18122 { 9556 /* s_call_b64 */, AMDGPU::S_CALL_B64_gfx10, Convert__Reg1_0__SoppBrTarget1_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_64, MCK_SoppBrTarget }, },
18123 { 9556 /* s_call_b64 */, AMDGPU::S_CALL_B64_vi, Convert__Reg1_0__SoppBrTarget1_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_64, MCK_SoppBrTarget }, },
18124 { 9567 /* s_cbranch_cdbgsys */, AMDGPU::S_CBRANCH_CDBGSYS, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18125 { 9567 /* s_cbranch_cdbgsys */, AMDGPU::S_CBRANCH_CDBGSYS_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18126 { 9585 /* s_cbranch_cdbgsys_and_user */, AMDGPU::S_CBRANCH_CDBGSYS_AND_USER, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18127 { 9585 /* s_cbranch_cdbgsys_and_user */, AMDGPU::S_CBRANCH_CDBGSYS_AND_USER_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18128 { 9612 /* s_cbranch_cdbgsys_or_user */, AMDGPU::S_CBRANCH_CDBGSYS_OR_USER, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18129 { 9612 /* s_cbranch_cdbgsys_or_user */, AMDGPU::S_CBRANCH_CDBGSYS_OR_USER_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18130 { 9638 /* s_cbranch_cdbguser */, AMDGPU::S_CBRANCH_CDBGUSER, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18131 { 9638 /* s_cbranch_cdbguser */, AMDGPU::S_CBRANCH_CDBGUSER_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18132 { 9657 /* s_cbranch_execnz */, AMDGPU::S_CBRANCH_EXECNZ, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18133 { 9657 /* s_cbranch_execnz */, AMDGPU::S_CBRANCH_EXECNZ_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18134 { 9674 /* s_cbranch_execz */, AMDGPU::S_CBRANCH_EXECZ, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18135 { 9674 /* s_cbranch_execz */, AMDGPU::S_CBRANCH_EXECZ_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18138 { 9707 /* s_cbranch_i_fork */, AMDGPU::S_CBRANCH_I_FORK_gfx6_gfx7, Convert__Reg1_0__SoppBrTarget1_1, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_SReg_64, MCK_SoppBrTarget }, },
18139 { 9707 /* s_cbranch_i_fork */, AMDGPU::S_CBRANCH_I_FORK_vi, Convert__Reg1_0__SoppBrTarget1_1, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_SReg_64, MCK_SoppBrTarget }, },
18142 { 9739 /* s_cbranch_scc0 */, AMDGPU::S_CBRANCH_SCC0, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18143 { 9739 /* s_cbranch_scc0 */, AMDGPU::S_CBRANCH_SCC0_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18144 { 9754 /* s_cbranch_scc1 */, AMDGPU::S_CBRANCH_SCC1, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18145 { 9754 /* s_cbranch_scc1 */, AMDGPU::S_CBRANCH_SCC1_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18146 { 9769 /* s_cbranch_vccnz */, AMDGPU::S_CBRANCH_VCCNZ, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18147 { 9769 /* s_cbranch_vccnz */, AMDGPU::S_CBRANCH_VCCNZ_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18148 { 9785 /* s_cbranch_vccz */, AMDGPU::S_CBRANCH_VCCZ, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18149 { 9785 /* s_cbranch_vccz */, AMDGPU::S_CBRANCH_VCCZ_pad_s_nop, Convert__SoppBrTarget1_0, AMFBS_None, { MCK_SoppBrTarget }, },
18520 { 11912 /* s_subvector_loop_begin */, AMDGPU::S_SUBVECTOR_LOOP_BEGIN_gfx10, Convert__SoppBrTarget1_1__Reg1_0, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SoppBrTarget }, },
18521 { 11935 /* s_subvector_loop_end */, AMDGPU::S_SUBVECTOR_LOOP_END_gfx10, Convert__SoppBrTarget1_1__Reg1_0, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SoppBrTarget }, },
70437 { 8774 /* s_branch */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70438 { 8774 /* s_branch */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70871 { 9556 /* s_call_b64 */, 2 /* 1 */, MCK_SoppBrTarget, AMFBS_isGFX9Plus_isGFX10Plus },
70872 { 9556 /* s_call_b64 */, 2 /* 1 */, MCK_SoppBrTarget, AMFBS_isGFX9Plus_isGFX8GFX9 },
70873 { 9567 /* s_cbranch_cdbgsys */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70874 { 9567 /* s_cbranch_cdbgsys */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70875 { 9585 /* s_cbranch_cdbgsys_and_user */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70876 { 9585 /* s_cbranch_cdbgsys_and_user */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70877 { 9612 /* s_cbranch_cdbgsys_or_user */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70878 { 9612 /* s_cbranch_cdbgsys_or_user */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70879 { 9638 /* s_cbranch_cdbguser */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70880 { 9638 /* s_cbranch_cdbguser */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70881 { 9657 /* s_cbranch_execnz */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70882 { 9657 /* s_cbranch_execnz */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70883 { 9674 /* s_cbranch_execz */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70884 { 9674 /* s_cbranch_execz */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70885 { 9707 /* s_cbranch_i_fork */, 2 /* 1 */, MCK_SoppBrTarget, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
70886 { 9707 /* s_cbranch_i_fork */, 2 /* 1 */, MCK_SoppBrTarget, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
70887 { 9739 /* s_cbranch_scc0 */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70888 { 9739 /* s_cbranch_scc0 */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70889 { 9754 /* s_cbranch_scc1 */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70890 { 9754 /* s_cbranch_scc1 */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70891 { 9769 /* s_cbranch_vccnz */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70892 { 9769 /* s_cbranch_vccnz */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70893 { 9785 /* s_cbranch_vccz */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
70894 { 9785 /* s_cbranch_vccz */, 1 /* 0 */, MCK_SoppBrTarget, AMFBS_None },
71093 { 11912 /* s_subvector_loop_begin */, 2 /* 1 */, MCK_SoppBrTarget, AMFBS_isGFX10Plus_isGFX10Plus },
71094 { 11935 /* s_subvector_loop_end */, 2 /* 1 */, MCK_SoppBrTarget, AMFBS_isGFX10Plus_isGFX10Plus },
80297 case MCK_SoppBrTarget:
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 6985 case MCK_SoppBrTarget: