reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

 5553   case MCK_SSrcB32: {
10078   case MCK_SSrcB32: return "MCK_SSrcB32";
17541   { 7751 /* s_abs_i32 */, AMDGPU::S_ABS_I32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17542   { 7751 /* s_abs_i32 */, AMDGPU::S_ABS_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
17543   { 7751 /* s_abs_i32 */, AMDGPU::S_ABS_I32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
17544   { 7761 /* s_absdiff_i32 */, AMDGPU::S_ABSDIFF_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17544   { 7761 /* s_absdiff_i32 */, AMDGPU::S_ABSDIFF_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17545   { 7761 /* s_absdiff_i32 */, AMDGPU::S_ABSDIFF_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17545   { 7761 /* s_absdiff_i32 */, AMDGPU::S_ABSDIFF_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17546   { 7761 /* s_absdiff_i32 */, AMDGPU::S_ABSDIFF_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17546   { 7761 /* s_absdiff_i32 */, AMDGPU::S_ABSDIFF_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17547   { 7775 /* s_add_i32 */, AMDGPU::S_ADD_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17547   { 7775 /* s_add_i32 */, AMDGPU::S_ADD_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17548   { 7775 /* s_add_i32 */, AMDGPU::S_ADD_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17548   { 7775 /* s_add_i32 */, AMDGPU::S_ADD_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17549   { 7775 /* s_add_i32 */, AMDGPU::S_ADD_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17549   { 7775 /* s_add_i32 */, AMDGPU::S_ADD_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17550   { 7785 /* s_add_u32 */, AMDGPU::S_ADD_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17550   { 7785 /* s_add_u32 */, AMDGPU::S_ADD_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17551   { 7785 /* s_add_u32 */, AMDGPU::S_ADD_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17551   { 7785 /* s_add_u32 */, AMDGPU::S_ADD_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17552   { 7785 /* s_add_u32 */, AMDGPU::S_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17552   { 7785 /* s_add_u32 */, AMDGPU::S_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17553   { 7795 /* s_addc_u32 */, AMDGPU::S_ADDC_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17553   { 7795 /* s_addc_u32 */, AMDGPU::S_ADDC_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17554   { 7795 /* s_addc_u32 */, AMDGPU::S_ADDC_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17554   { 7795 /* s_addc_u32 */, AMDGPU::S_ADDC_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17555   { 7795 /* s_addc_u32 */, AMDGPU::S_ADDC_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17555   { 7795 /* s_addc_u32 */, AMDGPU::S_ADDC_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17559   { 7817 /* s_and_b32 */, AMDGPU::S_AND_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17559   { 7817 /* s_and_b32 */, AMDGPU::S_AND_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17560   { 7817 /* s_and_b32 */, AMDGPU::S_AND_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17560   { 7817 /* s_and_b32 */, AMDGPU::S_AND_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17561   { 7817 /* s_and_b32 */, AMDGPU::S_AND_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17561   { 7817 /* s_and_b32 */, AMDGPU::S_AND_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17565   { 7837 /* s_and_saveexec_b32 */, AMDGPU::S_AND_SAVEEXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17569   { 7875 /* s_andn1_saveexec_b32 */, AMDGPU::S_ANDN1_SAVEEXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17572   { 7917 /* s_andn1_wrexec_b32 */, AMDGPU::S_ANDN1_WREXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17575   { 7955 /* s_andn2_b32 */, AMDGPU::S_ANDN2_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17575   { 7955 /* s_andn2_b32 */, AMDGPU::S_ANDN2_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17576   { 7955 /* s_andn2_b32 */, AMDGPU::S_ANDN2_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17576   { 7955 /* s_andn2_b32 */, AMDGPU::S_ANDN2_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17577   { 7955 /* s_andn2_b32 */, AMDGPU::S_ANDN2_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17577   { 7955 /* s_andn2_b32 */, AMDGPU::S_ANDN2_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17581   { 7979 /* s_andn2_saveexec_b32 */, AMDGPU::S_ANDN2_SAVEEXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17585   { 8021 /* s_andn2_wrexec_b32 */, AMDGPU::S_ANDN2_WREXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17588   { 8059 /* s_ashr_i32 */, AMDGPU::S_ASHR_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17588   { 8059 /* s_ashr_i32 */, AMDGPU::S_ASHR_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17589   { 8059 /* s_ashr_i32 */, AMDGPU::S_ASHR_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17589   { 8059 /* s_ashr_i32 */, AMDGPU::S_ASHR_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17590   { 8059 /* s_ashr_i32 */, AMDGPU::S_ASHR_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17590   { 8059 /* s_ashr_i32 */, AMDGPU::S_ASHR_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17591   { 8070 /* s_ashr_i64 */, AMDGPU::S_ASHR_I64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17592   { 8070 /* s_ashr_i64 */, AMDGPU::S_ASHR_I64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17593   { 8070 /* s_ashr_i64 */, AMDGPU::S_ASHR_I64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17811   { 8515 /* s_bcnt0_i32_b32 */, AMDGPU::S_BCNT0_I32_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17812   { 8515 /* s_bcnt0_i32_b32 */, AMDGPU::S_BCNT0_I32_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
17813   { 8515 /* s_bcnt0_i32_b32 */, AMDGPU::S_BCNT0_I32_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
17817   { 8547 /* s_bcnt1_i32_b32 */, AMDGPU::S_BCNT1_I32_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17818   { 8547 /* s_bcnt1_i32_b32 */, AMDGPU::S_BCNT1_I32_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
17819   { 8547 /* s_bcnt1_i32_b32 */, AMDGPU::S_BCNT1_I32_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
17823   { 8579 /* s_bfe_i32 */, AMDGPU::S_BFE_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17823   { 8579 /* s_bfe_i32 */, AMDGPU::S_BFE_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17824   { 8579 /* s_bfe_i32 */, AMDGPU::S_BFE_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17824   { 8579 /* s_bfe_i32 */, AMDGPU::S_BFE_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17825   { 8579 /* s_bfe_i32 */, AMDGPU::S_BFE_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17825   { 8579 /* s_bfe_i32 */, AMDGPU::S_BFE_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17826   { 8589 /* s_bfe_i64 */, AMDGPU::S_BFE_I64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17827   { 8589 /* s_bfe_i64 */, AMDGPU::S_BFE_I64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17828   { 8589 /* s_bfe_i64 */, AMDGPU::S_BFE_I64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17829   { 8599 /* s_bfe_u32 */, AMDGPU::S_BFE_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17829   { 8599 /* s_bfe_u32 */, AMDGPU::S_BFE_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17830   { 8599 /* s_bfe_u32 */, AMDGPU::S_BFE_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17830   { 8599 /* s_bfe_u32 */, AMDGPU::S_BFE_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17831   { 8599 /* s_bfe_u32 */, AMDGPU::S_BFE_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17831   { 8599 /* s_bfe_u32 */, AMDGPU::S_BFE_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17832   { 8609 /* s_bfe_u64 */, AMDGPU::S_BFE_U64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17833   { 8609 /* s_bfe_u64 */, AMDGPU::S_BFE_U64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17834   { 8609 /* s_bfe_u64 */, AMDGPU::S_BFE_U64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17835   { 8619 /* s_bfm_b32 */, AMDGPU::S_BFM_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17835   { 8619 /* s_bfm_b32 */, AMDGPU::S_BFM_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17836   { 8619 /* s_bfm_b32 */, AMDGPU::S_BFM_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17836   { 8619 /* s_bfm_b32 */, AMDGPU::S_BFM_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17837   { 8619 /* s_bfm_b32 */, AMDGPU::S_BFM_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17837   { 8619 /* s_bfm_b32 */, AMDGPU::S_BFM_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17838   { 8629 /* s_bfm_b64 */, AMDGPU::S_BFM_B64_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB32, MCK_SSrcB32 }, },
17838   { 8629 /* s_bfm_b64 */, AMDGPU::S_BFM_B64_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB32, MCK_SSrcB32 }, },
17839   { 8629 /* s_bfm_b64 */, AMDGPU::S_BFM_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB32, MCK_SSrcB32 }, },
17839   { 8629 /* s_bfm_b64 */, AMDGPU::S_BFM_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB32, MCK_SSrcB32 }, },
17840   { 8629 /* s_bfm_b64 */, AMDGPU::S_BFM_B64_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB32, MCK_SSrcB32 }, },
17840   { 8629 /* s_bfm_b64 */, AMDGPU::S_BFM_B64_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB32, MCK_SSrcB32 }, },
17841   { 8639 /* s_bitcmp0_b32 */, AMDGPU::S_BITCMP0_B32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
17841   { 8639 /* s_bitcmp0_b32 */, AMDGPU::S_BITCMP0_B32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
17842   { 8653 /* s_bitcmp0_b64 */, AMDGPU::S_BITCMP0_B64, Convert__SSrcB641_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB64, MCK_SSrcB32 }, },
17843   { 8667 /* s_bitcmp1_b32 */, AMDGPU::S_BITCMP1_B32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
17843   { 8667 /* s_bitcmp1_b32 */, AMDGPU::S_BITCMP1_B32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
17844   { 8681 /* s_bitcmp1_b64 */, AMDGPU::S_BITCMP1_B64, Convert__SSrcB641_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB64, MCK_SSrcB32 }, },
17845   { 8695 /* s_bitreplicate_b64_b32 */, AMDGPU::S_BITREPLICATE_B64_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB32 }, },
17846   { 8695 /* s_bitreplicate_b64_b32 */, AMDGPU::S_BITREPLICATE_B64_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB32 }, },
17847   { 8718 /* s_bitset0_b32 */, AMDGPU::S_BITSET0_B32_gfx10, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17848   { 8718 /* s_bitset0_b32 */, AMDGPU::S_BITSET0_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
17849   { 8718 /* s_bitset0_b32 */, AMDGPU::S_BITSET0_B32_vi, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
17850   { 8732 /* s_bitset0_b64 */, AMDGPU::S_BITSET0_B64_gfx10, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB32 }, },
17851   { 8732 /* s_bitset0_b64 */, AMDGPU::S_BITSET0_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB32 }, },
17852   { 8732 /* s_bitset0_b64 */, AMDGPU::S_BITSET0_B64_vi, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB32 }, },
17853   { 8746 /* s_bitset1_b32 */, AMDGPU::S_BITSET1_B32_gfx10, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17854   { 8746 /* s_bitset1_b32 */, AMDGPU::S_BITSET1_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
17855   { 8746 /* s_bitset1_b32 */, AMDGPU::S_BITSET1_B32_vi, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
17856   { 8760 /* s_bitset1_b64 */, AMDGPU::S_BITSET1_B64_gfx10, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB32 }, },
17857   { 8760 /* s_bitset1_b64 */, AMDGPU::S_BITSET1_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB32 }, },
17858   { 8760 /* s_bitset1_b64 */, AMDGPU::S_BITSET1_B64_vi, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB32 }, },
17861   { 8783 /* s_brev_b32 */, AMDGPU::S_BREV_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17862   { 8783 /* s_brev_b32 */, AMDGPU::S_BREV_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
17863   { 8783 /* s_brev_b32 */, AMDGPU::S_BREV_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18151   { 9809 /* s_cmov_b32 */, AMDGPU::S_CMOV_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18152   { 9809 /* s_cmov_b32 */, AMDGPU::S_CMOV_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18153   { 9809 /* s_cmov_b32 */, AMDGPU::S_CMOV_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18160   { 9843 /* s_cmp_eq_i32 */, AMDGPU::S_CMP_EQ_I32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18160   { 9843 /* s_cmp_eq_i32 */, AMDGPU::S_CMP_EQ_I32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18161   { 9856 /* s_cmp_eq_u32 */, AMDGPU::S_CMP_EQ_U32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18161   { 9856 /* s_cmp_eq_u32 */, AMDGPU::S_CMP_EQ_U32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18163   { 9882 /* s_cmp_ge_i32 */, AMDGPU::S_CMP_GE_I32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18163   { 9882 /* s_cmp_ge_i32 */, AMDGPU::S_CMP_GE_I32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18164   { 9895 /* s_cmp_ge_u32 */, AMDGPU::S_CMP_GE_U32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18164   { 9895 /* s_cmp_ge_u32 */, AMDGPU::S_CMP_GE_U32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18165   { 9908 /* s_cmp_gt_i32 */, AMDGPU::S_CMP_GT_I32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18165   { 9908 /* s_cmp_gt_i32 */, AMDGPU::S_CMP_GT_I32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18166   { 9921 /* s_cmp_gt_u32 */, AMDGPU::S_CMP_GT_U32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18166   { 9921 /* s_cmp_gt_u32 */, AMDGPU::S_CMP_GT_U32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18167   { 9934 /* s_cmp_le_i32 */, AMDGPU::S_CMP_LE_I32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18167   { 9934 /* s_cmp_le_i32 */, AMDGPU::S_CMP_LE_I32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18168   { 9947 /* s_cmp_le_u32 */, AMDGPU::S_CMP_LE_U32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18168   { 9947 /* s_cmp_le_u32 */, AMDGPU::S_CMP_LE_U32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18169   { 9960 /* s_cmp_lg_i32 */, AMDGPU::S_CMP_LG_I32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18169   { 9960 /* s_cmp_lg_i32 */, AMDGPU::S_CMP_LG_I32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18170   { 9973 /* s_cmp_lg_u32 */, AMDGPU::S_CMP_LG_U32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18170   { 9973 /* s_cmp_lg_u32 */, AMDGPU::S_CMP_LG_U32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18172   { 9999 /* s_cmp_lt_i32 */, AMDGPU::S_CMP_LT_I32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18172   { 9999 /* s_cmp_lt_i32 */, AMDGPU::S_CMP_LT_I32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18173   { 10012 /* s_cmp_lt_u32 */, AMDGPU::S_CMP_LT_U32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18173   { 10012 /* s_cmp_lt_u32 */, AMDGPU::S_CMP_LT_U32, Convert__SSrcB321_0__SSrcB321_1, AMFBS_None, { MCK_SSrcB32, MCK_SSrcB32 }, },
18211   { 10204 /* s_cselect_b32 */, AMDGPU::S_CSELECT_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18211   { 10204 /* s_cselect_b32 */, AMDGPU::S_CSELECT_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18212   { 10204 /* s_cselect_b32 */, AMDGPU::S_CSELECT_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18212   { 10204 /* s_cselect_b32 */, AMDGPU::S_CSELECT_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18213   { 10204 /* s_cselect_b32 */, AMDGPU::S_CSELECT_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18213   { 10204 /* s_cselect_b32 */, AMDGPU::S_CSELECT_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18238   { 10405 /* s_ff0_i32_b32 */, AMDGPU::S_FF0_I32_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18239   { 10405 /* s_ff0_i32_b32 */, AMDGPU::S_FF0_I32_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18240   { 10405 /* s_ff0_i32_b32 */, AMDGPU::S_FF0_I32_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18244   { 10433 /* s_ff1_i32_b32 */, AMDGPU::S_FF1_I32_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18245   { 10433 /* s_ff1_i32_b32 */, AMDGPU::S_FF1_I32_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18246   { 10433 /* s_ff1_i32_b32 */, AMDGPU::S_FF1_I32_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18250   { 10461 /* s_flbit_i32 */, AMDGPU::S_FLBIT_I32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18251   { 10461 /* s_flbit_i32 */, AMDGPU::S_FLBIT_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18252   { 10461 /* s_flbit_i32 */, AMDGPU::S_FLBIT_I32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18253   { 10473 /* s_flbit_i32_b32 */, AMDGPU::S_FLBIT_I32_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18254   { 10473 /* s_flbit_i32_b32 */, AMDGPU::S_FLBIT_I32_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18255   { 10473 /* s_flbit_i32_b32 */, AMDGPU::S_FLBIT_I32_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18308   { 10700 /* s_lshl1_add_u32 */, AMDGPU::S_LSHL1_ADD_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18308   { 10700 /* s_lshl1_add_u32 */, AMDGPU::S_LSHL1_ADD_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18309   { 10700 /* s_lshl1_add_u32 */, AMDGPU::S_LSHL1_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18309   { 10700 /* s_lshl1_add_u32 */, AMDGPU::S_LSHL1_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18310   { 10716 /* s_lshl2_add_u32 */, AMDGPU::S_LSHL2_ADD_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18310   { 10716 /* s_lshl2_add_u32 */, AMDGPU::S_LSHL2_ADD_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18311   { 10716 /* s_lshl2_add_u32 */, AMDGPU::S_LSHL2_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18311   { 10716 /* s_lshl2_add_u32 */, AMDGPU::S_LSHL2_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18312   { 10732 /* s_lshl3_add_u32 */, AMDGPU::S_LSHL3_ADD_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18312   { 10732 /* s_lshl3_add_u32 */, AMDGPU::S_LSHL3_ADD_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18313   { 10732 /* s_lshl3_add_u32 */, AMDGPU::S_LSHL3_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18313   { 10732 /* s_lshl3_add_u32 */, AMDGPU::S_LSHL3_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18314   { 10748 /* s_lshl4_add_u32 */, AMDGPU::S_LSHL4_ADD_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18314   { 10748 /* s_lshl4_add_u32 */, AMDGPU::S_LSHL4_ADD_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18315   { 10748 /* s_lshl4_add_u32 */, AMDGPU::S_LSHL4_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18315   { 10748 /* s_lshl4_add_u32 */, AMDGPU::S_LSHL4_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18316   { 10764 /* s_lshl_b32 */, AMDGPU::S_LSHL_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18316   { 10764 /* s_lshl_b32 */, AMDGPU::S_LSHL_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18317   { 10764 /* s_lshl_b32 */, AMDGPU::S_LSHL_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18317   { 10764 /* s_lshl_b32 */, AMDGPU::S_LSHL_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18318   { 10764 /* s_lshl_b32 */, AMDGPU::S_LSHL_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18318   { 10764 /* s_lshl_b32 */, AMDGPU::S_LSHL_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18319   { 10775 /* s_lshl_b64 */, AMDGPU::S_LSHL_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
18320   { 10775 /* s_lshl_b64 */, AMDGPU::S_LSHL_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
18321   { 10775 /* s_lshl_b64 */, AMDGPU::S_LSHL_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
18322   { 10786 /* s_lshr_b32 */, AMDGPU::S_LSHR_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18322   { 10786 /* s_lshr_b32 */, AMDGPU::S_LSHR_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18323   { 10786 /* s_lshr_b32 */, AMDGPU::S_LSHR_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18323   { 10786 /* s_lshr_b32 */, AMDGPU::S_LSHR_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18324   { 10786 /* s_lshr_b32 */, AMDGPU::S_LSHR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18324   { 10786 /* s_lshr_b32 */, AMDGPU::S_LSHR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18325   { 10797 /* s_lshr_b64 */, AMDGPU::S_LSHR_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
18326   { 10797 /* s_lshr_b64 */, AMDGPU::S_LSHR_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
18327   { 10797 /* s_lshr_b64 */, AMDGPU::S_LSHR_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
18328   { 10808 /* s_max_i32 */, AMDGPU::S_MAX_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18328   { 10808 /* s_max_i32 */, AMDGPU::S_MAX_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18329   { 10808 /* s_max_i32 */, AMDGPU::S_MAX_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18329   { 10808 /* s_max_i32 */, AMDGPU::S_MAX_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18330   { 10808 /* s_max_i32 */, AMDGPU::S_MAX_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18330   { 10808 /* s_max_i32 */, AMDGPU::S_MAX_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18331   { 10818 /* s_max_u32 */, AMDGPU::S_MAX_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18331   { 10818 /* s_max_u32 */, AMDGPU::S_MAX_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18332   { 10818 /* s_max_u32 */, AMDGPU::S_MAX_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18332   { 10818 /* s_max_u32 */, AMDGPU::S_MAX_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18333   { 10818 /* s_max_u32 */, AMDGPU::S_MAX_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18333   { 10818 /* s_max_u32 */, AMDGPU::S_MAX_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18339   { 10852 /* s_min_i32 */, AMDGPU::S_MIN_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18339   { 10852 /* s_min_i32 */, AMDGPU::S_MIN_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18340   { 10852 /* s_min_i32 */, AMDGPU::S_MIN_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18340   { 10852 /* s_min_i32 */, AMDGPU::S_MIN_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18341   { 10852 /* s_min_i32 */, AMDGPU::S_MIN_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18341   { 10852 /* s_min_i32 */, AMDGPU::S_MIN_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18342   { 10862 /* s_min_u32 */, AMDGPU::S_MIN_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18342   { 10862 /* s_min_u32 */, AMDGPU::S_MIN_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18343   { 10862 /* s_min_u32 */, AMDGPU::S_MIN_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18343   { 10862 /* s_min_u32 */, AMDGPU::S_MIN_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18344   { 10862 /* s_min_u32 */, AMDGPU::S_MIN_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18344   { 10862 /* s_min_u32 */, AMDGPU::S_MIN_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18345   { 10872 /* s_mov_b32 */, AMDGPU::S_MOV_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18346   { 10872 /* s_mov_b32 */, AMDGPU::S_MOV_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18347   { 10872 /* s_mov_b32 */, AMDGPU::S_MOV_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18351   { 10892 /* s_mov_fed_b32 */, AMDGPU::S_MOV_FED_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18352   { 10892 /* s_mov_fed_b32 */, AMDGPU::S_MOV_FED_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18353   { 10892 /* s_mov_fed_b32 */, AMDGPU::S_MOV_FED_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18354   { 10906 /* s_mov_regrd_b32 */, AMDGPU::S_MOV_REGRD_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18355   { 10906 /* s_mov_regrd_b32 */, AMDGPU::S_MOV_REGRD_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18359   { 10933 /* s_movreld_b32 */, AMDGPU::S_MOVRELD_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18360   { 10933 /* s_movreld_b32 */, AMDGPU::S_MOVRELD_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18361   { 10933 /* s_movreld_b32 */, AMDGPU::S_MOVRELD_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18365   { 10961 /* s_movrels_b32 */, AMDGPU::S_MOVRELS_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18366   { 10961 /* s_movrels_b32 */, AMDGPU::S_MOVRELS_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18367   { 10961 /* s_movrels_b32 */, AMDGPU::S_MOVRELS_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18371   { 10989 /* s_movrelsd_2_b32 */, AMDGPU::S_MOVRELSD_2_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18372   { 11006 /* s_mul_hi_i32 */, AMDGPU::S_MUL_HI_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18372   { 11006 /* s_mul_hi_i32 */, AMDGPU::S_MUL_HI_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18373   { 11006 /* s_mul_hi_i32 */, AMDGPU::S_MUL_HI_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18373   { 11006 /* s_mul_hi_i32 */, AMDGPU::S_MUL_HI_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18374   { 11019 /* s_mul_hi_u32 */, AMDGPU::S_MUL_HI_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18374   { 11019 /* s_mul_hi_u32 */, AMDGPU::S_MUL_HI_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18375   { 11019 /* s_mul_hi_u32 */, AMDGPU::S_MUL_HI_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18375   { 11019 /* s_mul_hi_u32 */, AMDGPU::S_MUL_HI_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18376   { 11032 /* s_mul_i32 */, AMDGPU::S_MUL_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18376   { 11032 /* s_mul_i32 */, AMDGPU::S_MUL_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18377   { 11032 /* s_mul_i32 */, AMDGPU::S_MUL_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18377   { 11032 /* s_mul_i32 */, AMDGPU::S_MUL_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18378   { 11032 /* s_mul_i32 */, AMDGPU::S_MUL_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18378   { 11032 /* s_mul_i32 */, AMDGPU::S_MUL_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18382   { 11053 /* s_nand_b32 */, AMDGPU::S_NAND_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18382   { 11053 /* s_nand_b32 */, AMDGPU::S_NAND_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18383   { 11053 /* s_nand_b32 */, AMDGPU::S_NAND_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18383   { 11053 /* s_nand_b32 */, AMDGPU::S_NAND_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18384   { 11053 /* s_nand_b32 */, AMDGPU::S_NAND_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18384   { 11053 /* s_nand_b32 */, AMDGPU::S_NAND_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18388   { 11075 /* s_nand_saveexec_b32 */, AMDGPU::S_NAND_SAVEEXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18393   { 11121 /* s_nor_b32 */, AMDGPU::S_NOR_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18393   { 11121 /* s_nor_b32 */, AMDGPU::S_NOR_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18394   { 11121 /* s_nor_b32 */, AMDGPU::S_NOR_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18394   { 11121 /* s_nor_b32 */, AMDGPU::S_NOR_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18395   { 11121 /* s_nor_b32 */, AMDGPU::S_NOR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18395   { 11121 /* s_nor_b32 */, AMDGPU::S_NOR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18399   { 11141 /* s_nor_saveexec_b32 */, AMDGPU::S_NOR_SAVEEXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18403   { 11179 /* s_not_b32 */, AMDGPU::S_NOT_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18404   { 11179 /* s_not_b32 */, AMDGPU::S_NOT_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18405   { 11179 /* s_not_b32 */, AMDGPU::S_NOT_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18409   { 11199 /* s_or_b32 */, AMDGPU::S_OR_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18409   { 11199 /* s_or_b32 */, AMDGPU::S_OR_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18410   { 11199 /* s_or_b32 */, AMDGPU::S_OR_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18410   { 11199 /* s_or_b32 */, AMDGPU::S_OR_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18411   { 11199 /* s_or_b32 */, AMDGPU::S_OR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18411   { 11199 /* s_or_b32 */, AMDGPU::S_OR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18415   { 11217 /* s_or_saveexec_b32 */, AMDGPU::S_OR_SAVEEXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18419   { 11253 /* s_orn1_saveexec_b32 */, AMDGPU::S_ORN1_SAVEEXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18422   { 11293 /* s_orn2_b32 */, AMDGPU::S_ORN2_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18422   { 11293 /* s_orn2_b32 */, AMDGPU::S_ORN2_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18423   { 11293 /* s_orn2_b32 */, AMDGPU::S_ORN2_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18423   { 11293 /* s_orn2_b32 */, AMDGPU::S_ORN2_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18424   { 11293 /* s_orn2_b32 */, AMDGPU::S_ORN2_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18424   { 11293 /* s_orn2_b32 */, AMDGPU::S_ORN2_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18428   { 11315 /* s_orn2_saveexec_b32 */, AMDGPU::S_ORN2_SAVEEXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18432   { 11355 /* s_pack_hh_b32_b16 */, AMDGPU::S_PACK_HH_B32_B16_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18432   { 11355 /* s_pack_hh_b32_b16 */, AMDGPU::S_PACK_HH_B32_B16_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18433   { 11355 /* s_pack_hh_b32_b16 */, AMDGPU::S_PACK_HH_B32_B16_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18433   { 11355 /* s_pack_hh_b32_b16 */, AMDGPU::S_PACK_HH_B32_B16_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18434   { 11373 /* s_pack_lh_b32_b16 */, AMDGPU::S_PACK_LH_B32_B16_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18434   { 11373 /* s_pack_lh_b32_b16 */, AMDGPU::S_PACK_LH_B32_B16_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18435   { 11373 /* s_pack_lh_b32_b16 */, AMDGPU::S_PACK_LH_B32_B16_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18435   { 11373 /* s_pack_lh_b32_b16 */, AMDGPU::S_PACK_LH_B32_B16_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18436   { 11391 /* s_pack_ll_b32_b16 */, AMDGPU::S_PACK_LL_B32_B16_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18436   { 11391 /* s_pack_ll_b32_b16 */, AMDGPU::S_PACK_LL_B32_B16_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18437   { 11391 /* s_pack_ll_b32_b16 */, AMDGPU::S_PACK_LL_B32_B16_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18437   { 11391 /* s_pack_ll_b32_b16 */, AMDGPU::S_PACK_LL_B32_B16_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18438   { 11409 /* s_quadmask_b32 */, AMDGPU::S_QUADMASK_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18439   { 11409 /* s_quadmask_b32 */, AMDGPU::S_QUADMASK_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18440   { 11409 /* s_quadmask_b32 */, AMDGPU::S_QUADMASK_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18447   { 11449 /* s_rfe_restore_b64 */, AMDGPU::S_RFE_RESTORE_B64_vi, Convert__SSrcB641_0__SSrcB321_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_SSrcB64, MCK_SSrcB32 }, },
18475   { 11641 /* s_set_gpr_idx_idx */, AMDGPU::S_SET_GPR_IDX_IDX_vi, Convert__SSrcB321_0, AMFBS_HasVGPRIndexMode_isGFX8GFX9, { MCK_SSrcB32 }, },
18478   { 11696 /* s_set_gpr_idx_on */, AMDGPU::S_SET_GPR_IDX_ON, Convert__SSrcB321_0__GPRIdxMode1_1, AMFBS_HasVGPRIndexMode, { MCK_SSrcB32, MCK_GPRIdxMode }, },
18491   { 11787 /* s_setvskip */, AMDGPU::S_SETVSKIP, Convert__SSrcB321_0__SSrcB321_1, AMFBS_isGFX6GFX7GFX8GFX9, { MCK_SSrcB32, MCK_SSrcB32 }, },
18491   { 11787 /* s_setvskip */, AMDGPU::S_SETVSKIP, Convert__SSrcB321_0__SSrcB321_1, AMFBS_isGFX6GFX7GFX8GFX9, { MCK_SSrcB32, MCK_SSrcB32 }, },
18492   { 11798 /* s_sext_i32_i16 */, AMDGPU::S_SEXT_I32_I16_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18493   { 11798 /* s_sext_i32_i16 */, AMDGPU::S_SEXT_I32_I16_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18494   { 11798 /* s_sext_i32_i16 */, AMDGPU::S_SEXT_I32_I16_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18495   { 11813 /* s_sext_i32_i8 */, AMDGPU::S_SEXT_I32_I8_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18496   { 11813 /* s_sext_i32_i8 */, AMDGPU::S_SEXT_I32_I8_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18497   { 11813 /* s_sext_i32_i8 */, AMDGPU::S_SEXT_I32_I8_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18511   { 11881 /* s_sub_i32 */, AMDGPU::S_SUB_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18511   { 11881 /* s_sub_i32 */, AMDGPU::S_SUB_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18512   { 11881 /* s_sub_i32 */, AMDGPU::S_SUB_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18512   { 11881 /* s_sub_i32 */, AMDGPU::S_SUB_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18513   { 11881 /* s_sub_i32 */, AMDGPU::S_SUB_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18513   { 11881 /* s_sub_i32 */, AMDGPU::S_SUB_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18514   { 11891 /* s_sub_u32 */, AMDGPU::S_SUB_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18514   { 11891 /* s_sub_u32 */, AMDGPU::S_SUB_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18515   { 11891 /* s_sub_u32 */, AMDGPU::S_SUB_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18515   { 11891 /* s_sub_u32 */, AMDGPU::S_SUB_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18516   { 11891 /* s_sub_u32 */, AMDGPU::S_SUB_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18516   { 11891 /* s_sub_u32 */, AMDGPU::S_SUB_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18517   { 11901 /* s_subb_u32 */, AMDGPU::S_SUBB_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18517   { 11901 /* s_subb_u32 */, AMDGPU::S_SUBB_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18518   { 11901 /* s_subb_u32 */, AMDGPU::S_SUBB_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18518   { 11901 /* s_subb_u32 */, AMDGPU::S_SUBB_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18519   { 11901 /* s_subb_u32 */, AMDGPU::S_SUBB_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18519   { 11901 /* s_subb_u32 */, AMDGPU::S_SUBB_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18537   { 12131 /* s_wqm_b32 */, AMDGPU::S_WQM_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18538   { 12131 /* s_wqm_b32 */, AMDGPU::S_WQM_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18539   { 12131 /* s_wqm_b32 */, AMDGPU::S_WQM_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18543   { 12151 /* s_xnor_b32 */, AMDGPU::S_XNOR_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18543   { 12151 /* s_xnor_b32 */, AMDGPU::S_XNOR_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18544   { 12151 /* s_xnor_b32 */, AMDGPU::S_XNOR_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18544   { 12151 /* s_xnor_b32 */, AMDGPU::S_XNOR_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18545   { 12151 /* s_xnor_b32 */, AMDGPU::S_XNOR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18545   { 12151 /* s_xnor_b32 */, AMDGPU::S_XNOR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18549   { 12173 /* s_xnor_saveexec_b32 */, AMDGPU::S_XNOR_SAVEEXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18553   { 12213 /* s_xor_b32 */, AMDGPU::S_XOR_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18553   { 12213 /* s_xor_b32 */, AMDGPU::S_XOR_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18554   { 12213 /* s_xor_b32 */, AMDGPU::S_XOR_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18554   { 12213 /* s_xor_b32 */, AMDGPU::S_XOR_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18555   { 12213 /* s_xor_b32 */, AMDGPU::S_XOR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18555   { 12213 /* s_xor_b32 */, AMDGPU::S_XOR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18559   { 12233 /* s_xor_saveexec_b32 */, AMDGPU::S_XOR_SAVEEXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },

 6975   case MCK_SSrcB32: