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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 4575 case MCK_SReg_64: return true;
4982 case MCK_SReg_64: return true;
5013 case MCK_SReg_64: return true;
5052 case MCK_SReg_64: return true;
5061 case MCK_SReg_64: return true;
5067 case MCK_SReg_64:
6323 case AMDGPU::EXEC: OpKind = MCK_SReg_64; break;
10016 case MCK_SReg_64: return "MCK_SReg_64";
13114 { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13115 { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13118 { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13119 { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13121 { 5010 /* global_atomic_add_f32 */, AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13124 { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13125 { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13128 { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13129 { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13132 { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13133 { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13136 { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13137 { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13140 { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13141 { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13144 { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13145 { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13148 { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13149 { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13152 { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13153 { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13156 { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13157 { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13160 { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13161 { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13164 { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13165 { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13168 { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13169 { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13172 { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13173 { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13176 { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13177 { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13179 { 5178 /* global_atomic_fcmpswap */, AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13181 { 5178 /* global_atomic_fcmpswap */, AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13183 { 5201 /* global_atomic_fcmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13185 { 5201 /* global_atomic_fcmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13187 { 5227 /* global_atomic_fmax */, AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13189 { 5227 /* global_atomic_fmax */, AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13191 { 5246 /* global_atomic_fmax_x2 */, AMDGPU::GLOBAL_ATOMIC_FMAX_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13193 { 5246 /* global_atomic_fmax_x2 */, AMDGPU::GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13195 { 5268 /* global_atomic_fmin */, AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13197 { 5268 /* global_atomic_fmin */, AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13199 { 5287 /* global_atomic_fmin_x2 */, AMDGPU::GLOBAL_ATOMIC_FMIN_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13201 { 5287 /* global_atomic_fmin_x2 */, AMDGPU::GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13204 { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13205 { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13208 { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13209 { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13212 { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13213 { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13216 { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13217 { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13220 { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13221 { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13224 { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13225 { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13228 { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13229 { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13232 { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13233 { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13235 { 5385 /* global_atomic_pk_add_f16 */, AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13238 { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13239 { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13242 { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13243 { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13246 { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13247 { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13250 { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13251 { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13254 { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13255 { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13258 { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13259 { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13262 { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13263 { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13266 { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13267 { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13270 { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13271 { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13274 { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13275 { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13278 { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13279 { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13282 { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13283 { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13286 { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13287 { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13290 { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13291 { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13294 { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13295 { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13298 { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13299 { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13302 { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13303 { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13306 { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13307 { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13310 { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13311 { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13314 { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13315 { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13318 { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13319 { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13322 { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13323 { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13326 { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13327 { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13330 { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13331 { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13334 { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13335 { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13338 { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13339 { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13342 { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13343 { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13346 { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13347 { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13350 { 5693 /* global_load_dword */, AMDGPU::GLOBAL_LOAD_DWORD_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13351 { 5693 /* global_load_dword */, AMDGPU::GLOBAL_LOAD_DWORD_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13354 { 5711 /* global_load_dwordx2 */, AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13355 { 5711 /* global_load_dwordx2 */, AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13358 { 5731 /* global_load_dwordx3 */, AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13359 { 5731 /* global_load_dwordx3 */, AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13362 { 5751 /* global_load_dwordx4 */, AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13363 { 5751 /* global_load_dwordx4 */, AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13366 { 5771 /* global_load_sbyte */, AMDGPU::GLOBAL_LOAD_SBYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13367 { 5771 /* global_load_sbyte */, AMDGPU::GLOBAL_LOAD_SBYTE_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13370 { 5789 /* global_load_sbyte_d16 */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13371 { 5789 /* global_load_sbyte_d16 */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13374 { 5811 /* global_load_sbyte_d16_hi */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13375 { 5811 /* global_load_sbyte_d16_hi */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13378 { 5836 /* global_load_short_d16 */, AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13379 { 5836 /* global_load_short_d16 */, AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13382 { 5858 /* global_load_short_d16_hi */, AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13383 { 5858 /* global_load_short_d16_hi */, AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13386 { 5883 /* global_load_sshort */, AMDGPU::GLOBAL_LOAD_SSHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13387 { 5883 /* global_load_sshort */, AMDGPU::GLOBAL_LOAD_SSHORT_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13390 { 5902 /* global_load_ubyte */, AMDGPU::GLOBAL_LOAD_UBYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13391 { 5902 /* global_load_ubyte */, AMDGPU::GLOBAL_LOAD_UBYTE_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13394 { 5920 /* global_load_ubyte_d16 */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13395 { 5920 /* global_load_ubyte_d16 */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13398 { 5942 /* global_load_ubyte_d16_hi */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13399 { 5942 /* global_load_ubyte_d16_hi */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13402 { 5967 /* global_load_ushort */, AMDGPU::GLOBAL_LOAD_USHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13403 { 5967 /* global_load_ushort */, AMDGPU::GLOBAL_LOAD_USHORT_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13406 { 5986 /* global_store_byte */, AMDGPU::GLOBAL_STORE_BYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13407 { 5986 /* global_store_byte */, AMDGPU::GLOBAL_STORE_BYTE_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13410 { 6004 /* global_store_byte_d16_hi */, AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13411 { 6004 /* global_store_byte_d16_hi */, AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13414 { 6029 /* global_store_dword */, AMDGPU::GLOBAL_STORE_DWORD_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13415 { 6029 /* global_store_dword */, AMDGPU::GLOBAL_STORE_DWORD_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13418 { 6048 /* global_store_dwordx2 */, AMDGPU::GLOBAL_STORE_DWORDX2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13419 { 6048 /* global_store_dwordx2 */, AMDGPU::GLOBAL_STORE_DWORDX2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13422 { 6069 /* global_store_dwordx3 */, AMDGPU::GLOBAL_STORE_DWORDX3_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13423 { 6069 /* global_store_dwordx3 */, AMDGPU::GLOBAL_STORE_DWORDX3_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13426 { 6090 /* global_store_dwordx4 */, AMDGPU::GLOBAL_STORE_DWORDX4_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13427 { 6090 /* global_store_dwordx4 */, AMDGPU::GLOBAL_STORE_DWORDX4_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13430 { 6111 /* global_store_short */, AMDGPU::GLOBAL_STORE_SHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13431 { 6111 /* global_store_short */, AMDGPU::GLOBAL_STORE_SHORT_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13434 { 6130 /* global_store_short_d16_hi */, AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13435 { 6130 /* global_store_short_d16_hi */, AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
17562 { 7827 /* s_and_b64 */, AMDGPU::S_AND_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
17563 { 7827 /* s_and_b64 */, AMDGPU::S_AND_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
17564 { 7827 /* s_and_b64 */, AMDGPU::S_AND_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
17566 { 7856 /* s_and_saveexec_b64 */, AMDGPU::S_AND_SAVEEXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
17567 { 7856 /* s_and_saveexec_b64 */, AMDGPU::S_AND_SAVEEXEC_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
17568 { 7856 /* s_and_saveexec_b64 */, AMDGPU::S_AND_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
17570 { 7896 /* s_andn1_saveexec_b64 */, AMDGPU::S_ANDN1_SAVEEXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
17571 { 7896 /* s_andn1_saveexec_b64 */, AMDGPU::S_ANDN1_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
17573 { 7936 /* s_andn1_wrexec_b64 */, AMDGPU::S_ANDN1_WREXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
17574 { 7936 /* s_andn1_wrexec_b64 */, AMDGPU::S_ANDN1_WREXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
17578 { 7967 /* s_andn2_b64 */, AMDGPU::S_ANDN2_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
17579 { 7967 /* s_andn2_b64 */, AMDGPU::S_ANDN2_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
17580 { 7967 /* s_andn2_b64 */, AMDGPU::S_ANDN2_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
17582 { 8000 /* s_andn2_saveexec_b64 */, AMDGPU::S_ANDN2_SAVEEXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
17583 { 8000 /* s_andn2_saveexec_b64 */, AMDGPU::S_ANDN2_SAVEEXEC_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
17584 { 8000 /* s_andn2_saveexec_b64 */, AMDGPU::S_ANDN2_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
17586 { 8040 /* s_andn2_wrexec_b64 */, AMDGPU::S_ANDN2_WREXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
17587 { 8040 /* s_andn2_wrexec_b64 */, AMDGPU::S_ANDN2_WREXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
17591 { 8070 /* s_ashr_i64 */, AMDGPU::S_ASHR_I64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17592 { 8070 /* s_ashr_i64 */, AMDGPU::S_ASHR_I64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17593 { 8070 /* s_ashr_i64 */, AMDGPU::S_ASHR_I64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17594 { 8081 /* s_atc_probe */, AMDGPU::S_ATC_PROBE_SGPR_gfx10, Convert__Imm1_0__Reg1_1__Reg1_2, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_Imm, MCK_SReg_64, MCK_SReg_32 }, },
17595 { 8081 /* s_atc_probe */, AMDGPU::S_ATC_PROBE_SGPR_vi, Convert__Imm1_0__Reg1_1__Reg1_2, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_Imm, MCK_SReg_64, MCK_SReg_32 }, },
17596 { 8081 /* s_atc_probe */, AMDGPU::S_ATC_PROBE_IMM_gfx10, Convert__Imm1_0__Reg1_1__ImmSMRDOffset201_2, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_Imm, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
17597 { 8081 /* s_atc_probe */, AMDGPU::S_ATC_PROBE_IMM_vi, Convert__Imm1_0__Reg1_1__ImmSMRDOffset201_2, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_Imm, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
17602 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17603 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17604 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17605 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17606 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17607 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17608 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17609 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17610 { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17611 { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17612 { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17613 { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17614 { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17615 { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17616 { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17617 { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17618 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17619 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17620 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17621 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17622 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17623 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17624 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17625 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17626 { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17627 { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17628 { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17629 { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17630 { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17631 { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17632 { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17633 { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17634 { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17635 { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17636 { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17637 { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17638 { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17639 { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17640 { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17641 { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17642 { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17643 { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17644 { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17645 { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17646 { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17647 { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17648 { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17649 { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17650 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17651 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17652 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17653 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17654 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17655 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17656 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17657 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17658 { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17659 { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17660 { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17661 { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17662 { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17663 { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17664 { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17665 { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17666 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17667 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17668 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17669 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17670 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17671 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17672 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17673 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17674 { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17675 { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17676 { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17677 { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17678 { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17679 { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17680 { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17681 { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17682 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17683 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17684 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17685 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17686 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17687 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17688 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17689 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17690 { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17691 { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17692 { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17693 { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17694 { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17695 { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17696 { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17697 { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17698 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17699 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17700 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17701 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17702 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17703 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17704 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17705 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17706 { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17707 { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17708 { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17709 { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17710 { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17711 { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17712 { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17713 { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17714 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17715 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17716 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17717 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17718 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17719 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17720 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17721 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17722 { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17723 { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17724 { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17725 { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17726 { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17727 { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17728 { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17729 { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17730 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17731 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17732 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17733 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17734 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17735 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17736 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17737 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17738 { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17739 { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17740 { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17741 { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17742 { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17743 { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17744 { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17745 { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17746 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17747 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17748 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17749 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17750 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17751 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17752 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17753 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17754 { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17755 { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17756 { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17757 { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17758 { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17759 { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17760 { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17761 { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17762 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17763 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17764 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17765 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17766 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17767 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17768 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17769 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17770 { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17771 { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17772 { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17773 { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17774 { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17775 { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17776 { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17777 { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17778 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17779 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17780 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17781 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17782 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17783 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17784 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17785 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17786 { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17787 { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17788 { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17789 { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17790 { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17791 { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17792 { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17793 { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17794 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17795 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17796 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17797 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17798 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17799 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17800 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17801 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17802 { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17803 { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17804 { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17805 { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17806 { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17807 { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17808 { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17809 { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17826 { 8589 /* s_bfe_i64 */, AMDGPU::S_BFE_I64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17827 { 8589 /* s_bfe_i64 */, AMDGPU::S_BFE_I64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17828 { 8589 /* s_bfe_i64 */, AMDGPU::S_BFE_I64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17832 { 8609 /* s_bfe_u64 */, AMDGPU::S_BFE_U64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17833 { 8609 /* s_bfe_u64 */, AMDGPU::S_BFE_U64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17834 { 8609 /* s_bfe_u64 */, AMDGPU::S_BFE_U64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
17838 { 8629 /* s_bfm_b64 */, AMDGPU::S_BFM_B64_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB32, MCK_SSrcB32 }, },
17839 { 8629 /* s_bfm_b64 */, AMDGPU::S_BFM_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB32, MCK_SSrcB32 }, },
17840 { 8629 /* s_bfm_b64 */, AMDGPU::S_BFM_B64_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB32, MCK_SSrcB32 }, },
17845 { 8695 /* s_bitreplicate_b64_b32 */, AMDGPU::S_BITREPLICATE_B64_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB32 }, },
17846 { 8695 /* s_bitreplicate_b64_b32 */, AMDGPU::S_BITREPLICATE_B64_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB32 }, },
17850 { 8732 /* s_bitset0_b64 */, AMDGPU::S_BITSET0_B64_gfx10, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB32 }, },
17851 { 8732 /* s_bitset0_b64 */, AMDGPU::S_BITSET0_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB32 }, },
17852 { 8732 /* s_bitset0_b64 */, AMDGPU::S_BITSET0_B64_vi, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB32 }, },
17856 { 8760 /* s_bitset1_b64 */, AMDGPU::S_BITSET1_B64_gfx10, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB32 }, },
17857 { 8760 /* s_bitset1_b64 */, AMDGPU::S_BITSET1_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB32 }, },
17858 { 8760 /* s_bitset1_b64 */, AMDGPU::S_BITSET1_B64_vi, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB32 }, },
17864 { 8794 /* s_brev_b64 */, AMDGPU::S_BREV_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
17865 { 8794 /* s_brev_b64 */, AMDGPU::S_BREV_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
17866 { 8794 /* s_brev_b64 */, AMDGPU::S_BREV_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18122 { 9556 /* s_call_b64 */, AMDGPU::S_CALL_B64_gfx10, Convert__Reg1_0__SoppBrTarget1_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_64, MCK_SoppBrTarget }, },
18123 { 9556 /* s_call_b64 */, AMDGPU::S_CALL_B64_vi, Convert__Reg1_0__SoppBrTarget1_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_64, MCK_SoppBrTarget }, },
18138 { 9707 /* s_cbranch_i_fork */, AMDGPU::S_CBRANCH_I_FORK_gfx6_gfx7, Convert__Reg1_0__SoppBrTarget1_1, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_SReg_64, MCK_SoppBrTarget }, },
18139 { 9707 /* s_cbranch_i_fork */, AMDGPU::S_CBRANCH_I_FORK_vi, Convert__Reg1_0__SoppBrTarget1_1, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_SReg_64, MCK_SoppBrTarget }, },
18154 { 9820 /* s_cmov_b64 */, AMDGPU::S_CMOV_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18155 { 9820 /* s_cmov_b64 */, AMDGPU::S_CMOV_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18156 { 9820 /* s_cmov_b64 */, AMDGPU::S_CMOV_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18214 { 10218 /* s_cselect_b64 */, AMDGPU::S_CSELECT_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18215 { 10218 /* s_cselect_b64 */, AMDGPU::S_CSELECT_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18216 { 10218 /* s_cselect_b64 */, AMDGPU::S_CSELECT_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18217 { 10232 /* s_dcache_discard */, AMDGPU::S_DCACHE_DISCARD_SGPR_gfx10, Convert__Reg1_0__Reg1_1, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64, MCK_SReg_32 }, },
18218 { 10232 /* s_dcache_discard */, AMDGPU::S_DCACHE_DISCARD_SGPR_vi, Convert__Reg1_0__Reg1_1, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64, MCK_SReg_32 }, },
18219 { 10232 /* s_dcache_discard */, AMDGPU::S_DCACHE_DISCARD_IMM_gfx10, Convert__Reg1_0__ImmSMRDOffset201_1, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
18220 { 10232 /* s_dcache_discard */, AMDGPU::S_DCACHE_DISCARD_IMM_vi, Convert__Reg1_0__ImmSMRDOffset201_1, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
18221 { 10249 /* s_dcache_discard_x2 */, AMDGPU::S_DCACHE_DISCARD_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64, MCK_SReg_32 }, },
18222 { 10249 /* s_dcache_discard_x2 */, AMDGPU::S_DCACHE_DISCARD_X2_SGPR_vi, Convert__Reg1_0__Reg1_1, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64, MCK_SReg_32 }, },
18223 { 10249 /* s_dcache_discard_x2 */, AMDGPU::S_DCACHE_DISCARD_X2_IMM_gfx10, Convert__Reg1_0__ImmSMRDOffset201_1, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
18224 { 10249 /* s_dcache_discard_x2 */, AMDGPU::S_DCACHE_DISCARD_X2_IMM_vi, Convert__Reg1_0__ImmSMRDOffset201_1, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
18263 { 10547 /* s_getpc_b64 */, AMDGPU::S_GETPC_B64_gfx10, Convert__Reg1_0, AMFBS_isGFX10Plus, { MCK_SReg_64 }, },
18264 { 10547 /* s_getpc_b64 */, AMDGPU::S_GETPC_B64_gfx6_gfx7, Convert__Reg1_0, AMFBS_isGFX6GFX7, { MCK_SReg_64 }, },
18265 { 10547 /* s_getpc_b64 */, AMDGPU::S_GETPC_B64_vi, Convert__Reg1_0, AMFBS_isGFX8GFX9, { MCK_SReg_64 }, },
18273 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18274 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18275 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18276 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18277 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18278 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18279 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, },
18280 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_512, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18281 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_512, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18282 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_512, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18283 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_512, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18284 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_512, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18285 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_512, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18286 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_512, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, },
18287 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18288 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18289 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18290 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18291 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18292 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18293 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, },
18294 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18295 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18296 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18297 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18298 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18299 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18300 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, },
18301 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_256, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18302 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_256, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18303 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_256, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18304 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_256, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18305 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_256, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18306 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_256, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18307 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_256, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, },
18319 { 10775 /* s_lshl_b64 */, AMDGPU::S_LSHL_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
18320 { 10775 /* s_lshl_b64 */, AMDGPU::S_LSHL_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
18321 { 10775 /* s_lshl_b64 */, AMDGPU::S_LSHL_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
18325 { 10797 /* s_lshr_b64 */, AMDGPU::S_LSHR_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
18326 { 10797 /* s_lshr_b64 */, AMDGPU::S_LSHR_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
18327 { 10797 /* s_lshr_b64 */, AMDGPU::S_LSHR_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
18348 { 10882 /* s_mov_b64 */, AMDGPU::S_MOV_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18349 { 10882 /* s_mov_b64 */, AMDGPU::S_MOV_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18350 { 10882 /* s_mov_b64 */, AMDGPU::S_MOV_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18362 { 10947 /* s_movreld_b64 */, AMDGPU::S_MOVRELD_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18363 { 10947 /* s_movreld_b64 */, AMDGPU::S_MOVRELD_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18364 { 10947 /* s_movreld_b64 */, AMDGPU::S_MOVRELD_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18368 { 10975 /* s_movrels_b64 */, AMDGPU::S_MOVRELS_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18369 { 10975 /* s_movrels_b64 */, AMDGPU::S_MOVRELS_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18370 { 10975 /* s_movrels_b64 */, AMDGPU::S_MOVRELS_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18385 { 11064 /* s_nand_b64 */, AMDGPU::S_NAND_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18386 { 11064 /* s_nand_b64 */, AMDGPU::S_NAND_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18387 { 11064 /* s_nand_b64 */, AMDGPU::S_NAND_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18389 { 11095 /* s_nand_saveexec_b64 */, AMDGPU::S_NAND_SAVEEXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18390 { 11095 /* s_nand_saveexec_b64 */, AMDGPU::S_NAND_SAVEEXEC_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18391 { 11095 /* s_nand_saveexec_b64 */, AMDGPU::S_NAND_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18396 { 11131 /* s_nor_b64 */, AMDGPU::S_NOR_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18397 { 11131 /* s_nor_b64 */, AMDGPU::S_NOR_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18398 { 11131 /* s_nor_b64 */, AMDGPU::S_NOR_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18400 { 11160 /* s_nor_saveexec_b64 */, AMDGPU::S_NOR_SAVEEXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18401 { 11160 /* s_nor_saveexec_b64 */, AMDGPU::S_NOR_SAVEEXEC_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18402 { 11160 /* s_nor_saveexec_b64 */, AMDGPU::S_NOR_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18406 { 11189 /* s_not_b64 */, AMDGPU::S_NOT_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18407 { 11189 /* s_not_b64 */, AMDGPU::S_NOT_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18408 { 11189 /* s_not_b64 */, AMDGPU::S_NOT_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18412 { 11208 /* s_or_b64 */, AMDGPU::S_OR_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18413 { 11208 /* s_or_b64 */, AMDGPU::S_OR_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18414 { 11208 /* s_or_b64 */, AMDGPU::S_OR_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18416 { 11235 /* s_or_saveexec_b64 */, AMDGPU::S_OR_SAVEEXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18417 { 11235 /* s_or_saveexec_b64 */, AMDGPU::S_OR_SAVEEXEC_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18418 { 11235 /* s_or_saveexec_b64 */, AMDGPU::S_OR_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18420 { 11273 /* s_orn1_saveexec_b64 */, AMDGPU::S_ORN1_SAVEEXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18421 { 11273 /* s_orn1_saveexec_b64 */, AMDGPU::S_ORN1_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18425 { 11304 /* s_orn2_b64 */, AMDGPU::S_ORN2_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18426 { 11304 /* s_orn2_b64 */, AMDGPU::S_ORN2_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18427 { 11304 /* s_orn2_b64 */, AMDGPU::S_ORN2_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18429 { 11335 /* s_orn2_saveexec_b64 */, AMDGPU::S_ORN2_SAVEEXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18430 { 11335 /* s_orn2_saveexec_b64 */, AMDGPU::S_ORN2_SAVEEXEC_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18431 { 11335 /* s_orn2_saveexec_b64 */, AMDGPU::S_ORN2_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18441 { 11424 /* s_quadmask_b64 */, AMDGPU::S_QUADMASK_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18442 { 11424 /* s_quadmask_b64 */, AMDGPU::S_QUADMASK_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18443 { 11424 /* s_quadmask_b64 */, AMDGPU::S_QUADMASK_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18444 { 11439 /* s_rfe_b64 */, AMDGPU::S_RFE_B64_gfx10, Convert__Reg1_0, AMFBS_isGFX10Plus, { MCK_SReg_64 }, },
18445 { 11439 /* s_rfe_b64 */, AMDGPU::S_RFE_B64_gfx6_gfx7, Convert__Reg1_0, AMFBS_isGFX6GFX7, { MCK_SReg_64 }, },
18446 { 11439 /* s_rfe_b64 */, AMDGPU::S_RFE_B64_vi, Convert__Reg1_0, AMFBS_isGFX8GFX9, { MCK_SReg_64 }, },
18449 { 11480 /* s_scratch_load_dword */, AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18450 { 11480 /* s_scratch_load_dword */, AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18451 { 11480 /* s_scratch_load_dword */, AMDGPU::S_SCRATCH_LOAD_DWORD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18452 { 11480 /* s_scratch_load_dword */, AMDGPU::S_SCRATCH_LOAD_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18453 { 11501 /* s_scratch_load_dwordx2 */, AMDGPU::S_SCRATCH_LOAD_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18454 { 11501 /* s_scratch_load_dwordx2 */, AMDGPU::S_SCRATCH_LOAD_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18455 { 11501 /* s_scratch_load_dwordx2 */, AMDGPU::S_SCRATCH_LOAD_DWORDX2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18456 { 11501 /* s_scratch_load_dwordx2 */, AMDGPU::S_SCRATCH_LOAD_DWORDX2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18457 { 11524 /* s_scratch_load_dwordx4 */, AMDGPU::S_SCRATCH_LOAD_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18458 { 11524 /* s_scratch_load_dwordx4 */, AMDGPU::S_SCRATCH_LOAD_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18459 { 11524 /* s_scratch_load_dwordx4 */, AMDGPU::S_SCRATCH_LOAD_DWORDX4_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18460 { 11524 /* s_scratch_load_dwordx4 */, AMDGPU::S_SCRATCH_LOAD_DWORDX4_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18461 { 11547 /* s_scratch_store_dword */, AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18462 { 11547 /* s_scratch_store_dword */, AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18463 { 11547 /* s_scratch_store_dword */, AMDGPU::S_SCRATCH_STORE_DWORD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18464 { 11547 /* s_scratch_store_dword */, AMDGPU::S_SCRATCH_STORE_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18465 { 11569 /* s_scratch_store_dwordx2 */, AMDGPU::S_SCRATCH_STORE_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18466 { 11569 /* s_scratch_store_dwordx2 */, AMDGPU::S_SCRATCH_STORE_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18467 { 11569 /* s_scratch_store_dwordx2 */, AMDGPU::S_SCRATCH_STORE_DWORDX2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18468 { 11569 /* s_scratch_store_dwordx2 */, AMDGPU::S_SCRATCH_STORE_DWORDX2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18469 { 11593 /* s_scratch_store_dwordx4 */, AMDGPU::S_SCRATCH_STORE_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18470 { 11593 /* s_scratch_store_dwordx4 */, AMDGPU::S_SCRATCH_STORE_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18471 { 11593 /* s_scratch_store_dwordx4 */, AMDGPU::S_SCRATCH_STORE_DWORDX4_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18472 { 11593 /* s_scratch_store_dwordx4 */, AMDGPU::S_SCRATCH_STORE_DWORDX4_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18481 { 11733 /* s_setpc_b64 */, AMDGPU::S_SETPC_B64_gfx10, Convert__Reg1_0, AMFBS_isGFX10Plus, { MCK_SReg_64 }, },
18482 { 11733 /* s_setpc_b64 */, AMDGPU::S_SETPC_B64_gfx6_gfx7, Convert__Reg1_0, AMFBS_isGFX6GFX7, { MCK_SReg_64 }, },
18483 { 11733 /* s_setpc_b64 */, AMDGPU::S_SETPC_B64_vi, Convert__Reg1_0, AMFBS_isGFX8GFX9, { MCK_SReg_64 }, },
18499 { 11835 /* s_store_dword */, AMDGPU::S_STORE_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18500 { 11835 /* s_store_dword */, AMDGPU::S_STORE_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18501 { 11835 /* s_store_dword */, AMDGPU::S_STORE_DWORD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18502 { 11835 /* s_store_dword */, AMDGPU::S_STORE_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18503 { 11849 /* s_store_dwordx2 */, AMDGPU::S_STORE_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18504 { 11849 /* s_store_dwordx2 */, AMDGPU::S_STORE_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18505 { 11849 /* s_store_dwordx2 */, AMDGPU::S_STORE_DWORDX2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18506 { 11849 /* s_store_dwordx2 */, AMDGPU::S_STORE_DWORDX2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18507 { 11865 /* s_store_dwordx4 */, AMDGPU::S_STORE_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18508 { 11865 /* s_store_dwordx4 */, AMDGPU::S_STORE_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18509 { 11865 /* s_store_dwordx4 */, AMDGPU::S_STORE_DWORDX4_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18510 { 11865 /* s_store_dwordx4 */, AMDGPU::S_STORE_DWORDX4_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18522 { 11956 /* s_swappc_b64 */, AMDGPU::S_SWAPPC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18523 { 11956 /* s_swappc_b64 */, AMDGPU::S_SWAPPC_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18524 { 11956 /* s_swappc_b64 */, AMDGPU::S_SWAPPC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18540 { 12141 /* s_wqm_b64 */, AMDGPU::S_WQM_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18541 { 12141 /* s_wqm_b64 */, AMDGPU::S_WQM_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18542 { 12141 /* s_wqm_b64 */, AMDGPU::S_WQM_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18546 { 12162 /* s_xnor_b64 */, AMDGPU::S_XNOR_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18547 { 12162 /* s_xnor_b64 */, AMDGPU::S_XNOR_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18548 { 12162 /* s_xnor_b64 */, AMDGPU::S_XNOR_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18550 { 12193 /* s_xnor_saveexec_b64 */, AMDGPU::S_XNOR_SAVEEXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18551 { 12193 /* s_xnor_saveexec_b64 */, AMDGPU::S_XNOR_SAVEEXEC_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18552 { 12193 /* s_xnor_saveexec_b64 */, AMDGPU::S_XNOR_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
18556 { 12223 /* s_xor_b64 */, AMDGPU::S_XOR_B64_gfx10, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18557 { 12223 /* s_xor_b64 */, AMDGPU::S_XOR_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18558 { 12223 /* s_xor_b64 */, AMDGPU::S_XOR_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
18560 { 12252 /* s_xor_saveexec_b64 */, AMDGPU::S_XOR_SAVEEXEC_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_64, MCK_SSrcB64 }, },
18561 { 12252 /* s_xor_saveexec_b64 */, AMDGPU::S_XOR_SAVEEXEC_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_64, MCK_SSrcB64 }, },
18562 { 12252 /* s_xor_saveexec_b64 */, AMDGPU::S_XOR_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_64, MCK_SSrcB64 }, },
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 6995 case MCK_SReg_64: