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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 4584 case MCK_SReg_32_XM0_XEXEC: return true;
5022 case MCK_SReg_32_XM0_XEXEC: return true;
5077 case MCK_SReg_32_XM0_XEXEC: return true;
5088 case MCK_SReg_32_XM0_XEXEC:
6315 case AMDGPU::VCC_HI: OpKind = MCK_SReg_32_XM0_XEXEC; break;
6324 case AMDGPU::SRC_VCCZ: OpKind = MCK_SReg_32_XM0_XEXEC; break;
6325 case AMDGPU::SRC_EXECZ: OpKind = MCK_SReg_32_XM0_XEXEC; break;
6326 case AMDGPU::SRC_SCC: OpKind = MCK_SReg_32_XM0_XEXEC; break;
6329 case AMDGPU::SGPR_NULL: OpKind = MCK_SReg_32_XM0_XEXEC; break;
6330 case AMDGPU::SRC_SHARED_BASE: OpKind = MCK_SReg_32_XM0_XEXEC; break;
6331 case AMDGPU::SRC_SHARED_LIMIT: OpKind = MCK_SReg_32_XM0_XEXEC; break;
6332 case AMDGPU::SRC_PRIVATE_BASE: OpKind = MCK_SReg_32_XM0_XEXEC; break;
6333 case AMDGPU::SRC_PRIVATE_LIMIT: OpKind = MCK_SReg_32_XM0_XEXEC; break;
6334 case AMDGPU::SRC_POPS_EXITING_WAVE_ID: OpKind = MCK_SReg_32_XM0_XEXEC; break;
6336 case AMDGPU::XNACK_MASK_LO: OpKind = MCK_SReg_32_XM0_XEXEC; break;
6337 case AMDGPU::XNACK_MASK_HI: OpKind = MCK_SReg_32_XM0_XEXEC; break;
6339 case AMDGPU::TBA_LO: OpKind = MCK_SReg_32_XM0_XEXEC; break;
6340 case AMDGPU::TBA_HI: OpKind = MCK_SReg_32_XM0_XEXEC; break;
6342 case AMDGPU::TMA_LO: OpKind = MCK_SReg_32_XM0_XEXEC; break;
6343 case AMDGPU::TMA_HI: OpKind = MCK_SReg_32_XM0_XEXEC; break;
6361 case AMDGPU::FLAT_SCR_LO: OpKind = MCK_SReg_32_XM0_XEXEC; break;
6362 case AMDGPU::FLAT_SCR_HI: OpKind = MCK_SReg_32_XM0_XEXEC; break;
10018 case MCK_SReg_32_XM0_XEXEC: return "MCK_SReg_32_XM0_XEXEC";
17602 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17603 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17604 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17605 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17606 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17607 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17608 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17609 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17618 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17619 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17620 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17621 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17622 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17623 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17624 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17625 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17650 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17651 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17652 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17653 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17654 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17655 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17656 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17657 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17666 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17667 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17668 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17669 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17670 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17671 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17672 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17673 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17682 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17683 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17684 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17685 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17686 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17687 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17688 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17689 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17698 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17699 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17700 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17701 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17702 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17703 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17704 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17705 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17714 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17715 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17716 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17717 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17718 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17719 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17720 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17721 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17730 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17731 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17732 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17733 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17734 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17735 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17736 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17737 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17746 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17747 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17748 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17749 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17750 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17751 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17752 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17753 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17762 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17763 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17764 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17765 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17766 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17767 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17768 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17769 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17778 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17779 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17780 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17781 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17782 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17783 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17784 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17785 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17794 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17795 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17796 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17797 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17798 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17799 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17800 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17801 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17867 { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17868 { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17869 { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17870 { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17871 { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17872 { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17873 { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17874 { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17883 { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17884 { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17885 { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17886 { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17887 { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17888 { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17889 { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17890 { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17915 { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17916 { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17917 { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17918 { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17919 { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17920 { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17921 { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17922 { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17931 { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17932 { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17933 { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17934 { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17935 { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17936 { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17937 { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17938 { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17947 { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17948 { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17949 { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17950 { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17951 { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17952 { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17953 { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17954 { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17963 { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17964 { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17965 { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17966 { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17967 { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17968 { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17969 { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17970 { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17979 { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17980 { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17981 { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17982 { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17983 { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17984 { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17985 { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17986 { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
17995 { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17996 { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17997 { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17998 { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
17999 { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18000 { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18001 { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
18002 { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
18011 { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18012 { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18013 { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18014 { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18015 { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18016 { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18017 { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
18018 { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
18027 { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18028 { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18029 { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18030 { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18031 { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18032 { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18033 { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
18034 { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
18043 { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18044 { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18045 { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18046 { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18047 { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18048 { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18049 { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
18050 { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
18059 { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18060 { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18061 { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18062 { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmDLC }, },
18063 { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18064 { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18065 { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_IMM_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
18066 { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc, MCK_ImmDLC }, },
18075 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18076 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18077 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18078 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18079 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18080 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18081 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, },
18110 { 9489 /* s_buffer_store_dword */, AMDGPU::S_BUFFER_STORE_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18111 { 9489 /* s_buffer_store_dword */, AMDGPU::S_BUFFER_STORE_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18112 { 9489 /* s_buffer_store_dword */, AMDGPU::S_BUFFER_STORE_DWORD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18113 { 9489 /* s_buffer_store_dword */, AMDGPU::S_BUFFER_STORE_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18262 { 10521 /* s_get_waveid_in_workgroup */, AMDGPU::S_GET_WAVEID_IN_WORKGROUP_gfx10, Convert__Reg1_0, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC }, },
18273 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18274 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18275 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18276 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18277 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18278 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18279 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, },
18449 { 11480 /* s_scratch_load_dword */, AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18450 { 11480 /* s_scratch_load_dword */, AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18451 { 11480 /* s_scratch_load_dword */, AMDGPU::S_SCRATCH_LOAD_DWORD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18452 { 11480 /* s_scratch_load_dword */, AMDGPU::S_SCRATCH_LOAD_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18461 { 11547 /* s_scratch_store_dword */, AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18462 { 11547 /* s_scratch_store_dword */, AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18463 { 11547 /* s_scratch_store_dword */, AMDGPU::S_SCRATCH_STORE_DWORD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18464 { 11547 /* s_scratch_store_dword */, AMDGPU::S_SCRATCH_STORE_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18499 { 11835 /* s_store_dword */, AMDGPU::S_STORE_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18500 { 11835 /* s_store_dword */, AMDGPU::S_STORE_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18501 { 11835 /* s_store_dword */, AMDGPU::S_STORE_DWORD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18502 { 11835 /* s_store_dword */, AMDGPU::S_STORE_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },