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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 4563 case MCK_SReg_32: return true;
4588 case MCK_SReg_32: return true;
5026 case MCK_SReg_32: return true;
5081 case MCK_SReg_32: return true;
5094 case MCK_SReg_32: return true;
5106 case MCK_SReg_32: return true;
5115 case MCK_SReg_32: return true;
5123 case MCK_SReg_32: return true;
5128 case MCK_SReg_32:
10022 case MCK_SReg_32: return "MCK_SReg_32";
17541 { 7751 /* s_abs_i32 */, AMDGPU::S_ABS_I32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17542 { 7751 /* s_abs_i32 */, AMDGPU::S_ABS_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
17543 { 7751 /* s_abs_i32 */, AMDGPU::S_ABS_I32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
17544 { 7761 /* s_absdiff_i32 */, AMDGPU::S_ABSDIFF_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17545 { 7761 /* s_absdiff_i32 */, AMDGPU::S_ABSDIFF_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17546 { 7761 /* s_absdiff_i32 */, AMDGPU::S_ABSDIFF_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17547 { 7775 /* s_add_i32 */, AMDGPU::S_ADD_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17548 { 7775 /* s_add_i32 */, AMDGPU::S_ADD_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17549 { 7775 /* s_add_i32 */, AMDGPU::S_ADD_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17550 { 7785 /* s_add_u32 */, AMDGPU::S_ADD_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17551 { 7785 /* s_add_u32 */, AMDGPU::S_ADD_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17552 { 7785 /* s_add_u32 */, AMDGPU::S_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17553 { 7795 /* s_addc_u32 */, AMDGPU::S_ADDC_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17554 { 7795 /* s_addc_u32 */, AMDGPU::S_ADDC_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17555 { 7795 /* s_addc_u32 */, AMDGPU::S_ADDC_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17556 { 7806 /* s_addk_i32 */, AMDGPU::S_ADDK_I32_gfx10, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
17557 { 7806 /* s_addk_i32 */, AMDGPU::S_ADDK_I32_gfx6_gfx7, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
17558 { 7806 /* s_addk_i32 */, AMDGPU::S_ADDK_I32_vi, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
17559 { 7817 /* s_and_b32 */, AMDGPU::S_AND_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17560 { 7817 /* s_and_b32 */, AMDGPU::S_AND_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17561 { 7817 /* s_and_b32 */, AMDGPU::S_AND_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17565 { 7837 /* s_and_saveexec_b32 */, AMDGPU::S_AND_SAVEEXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17569 { 7875 /* s_andn1_saveexec_b32 */, AMDGPU::S_ANDN1_SAVEEXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17572 { 7917 /* s_andn1_wrexec_b32 */, AMDGPU::S_ANDN1_WREXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17575 { 7955 /* s_andn2_b32 */, AMDGPU::S_ANDN2_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17576 { 7955 /* s_andn2_b32 */, AMDGPU::S_ANDN2_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17577 { 7955 /* s_andn2_b32 */, AMDGPU::S_ANDN2_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17581 { 7979 /* s_andn2_saveexec_b32 */, AMDGPU::S_ANDN2_SAVEEXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17585 { 8021 /* s_andn2_wrexec_b32 */, AMDGPU::S_ANDN2_WREXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17588 { 8059 /* s_ashr_i32 */, AMDGPU::S_ASHR_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17589 { 8059 /* s_ashr_i32 */, AMDGPU::S_ASHR_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17590 { 8059 /* s_ashr_i32 */, AMDGPU::S_ASHR_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17594 { 8081 /* s_atc_probe */, AMDGPU::S_ATC_PROBE_SGPR_gfx10, Convert__Imm1_0__Reg1_1__Reg1_2, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_Imm, MCK_SReg_64, MCK_SReg_32 }, },
17595 { 8081 /* s_atc_probe */, AMDGPU::S_ATC_PROBE_SGPR_vi, Convert__Imm1_0__Reg1_1__Reg1_2, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_Imm, MCK_SReg_64, MCK_SReg_32 }, },
17598 { 8093 /* s_atc_probe_buffer */, AMDGPU::S_ATC_PROBE_BUFFER_SGPR_gfx10, Convert__Imm1_0__Reg1_1__Reg1_2, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_Imm, MCK_SReg_128, MCK_SReg_32 }, },
17599 { 8093 /* s_atc_probe_buffer */, AMDGPU::S_ATC_PROBE_BUFFER_SGPR_vi, Convert__Imm1_0__Reg1_1__Reg1_2, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_Imm, MCK_SReg_128, MCK_SReg_32 }, },
17602 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17603 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17606 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17607 { 8112 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17610 { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17611 { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17614 { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17615 { 8125 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17618 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17619 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17622 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17623 { 8141 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17626 { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17627 { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17630 { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17631 { 8154 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17634 { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17635 { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17638 { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17639 { 8170 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17642 { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17643 { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17646 { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17647 { 8187 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17650 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17651 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17654 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17655 { 8207 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17658 { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17659 { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17662 { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17663 { 8220 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17666 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17667 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17670 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17671 { 8236 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17674 { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17675 { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17678 { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17679 { 8249 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17682 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17683 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17686 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17687 { 8265 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17690 { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17691 { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17694 { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17695 { 8277 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17698 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17699 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17702 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17703 { 8292 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17706 { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17707 { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17710 { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17711 { 8306 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17714 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17715 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17718 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17719 { 8323 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17722 { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17723 { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17726 { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17727 { 8337 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17730 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17731 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17734 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17735 { 8354 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17738 { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17739 { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17742 { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17743 { 8367 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17746 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17747 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17750 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17751 { 8383 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17754 { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17755 { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17758 { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17759 { 8397 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17762 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17763 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17766 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17767 { 8414 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17770 { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17771 { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17774 { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17775 { 8428 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17778 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17779 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17782 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17783 { 8445 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17786 { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17787 { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17790 { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17791 { 8459 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17794 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17795 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17798 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17799 { 8476 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17802 { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17803 { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmDLC }, },
17806 { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17807 { 8489 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17811 { 8515 /* s_bcnt0_i32_b32 */, AMDGPU::S_BCNT0_I32_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17812 { 8515 /* s_bcnt0_i32_b32 */, AMDGPU::S_BCNT0_I32_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
17813 { 8515 /* s_bcnt0_i32_b32 */, AMDGPU::S_BCNT0_I32_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
17814 { 8531 /* s_bcnt0_i32_b64 */, AMDGPU::S_BCNT0_I32_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB64 }, },
17815 { 8531 /* s_bcnt0_i32_b64 */, AMDGPU::S_BCNT0_I32_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB64 }, },
17816 { 8531 /* s_bcnt0_i32_b64 */, AMDGPU::S_BCNT0_I32_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB64 }, },
17817 { 8547 /* s_bcnt1_i32_b32 */, AMDGPU::S_BCNT1_I32_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17818 { 8547 /* s_bcnt1_i32_b32 */, AMDGPU::S_BCNT1_I32_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
17819 { 8547 /* s_bcnt1_i32_b32 */, AMDGPU::S_BCNT1_I32_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
17820 { 8563 /* s_bcnt1_i32_b64 */, AMDGPU::S_BCNT1_I32_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB64 }, },
17821 { 8563 /* s_bcnt1_i32_b64 */, AMDGPU::S_BCNT1_I32_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB64 }, },
17822 { 8563 /* s_bcnt1_i32_b64 */, AMDGPU::S_BCNT1_I32_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB64 }, },
17823 { 8579 /* s_bfe_i32 */, AMDGPU::S_BFE_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17824 { 8579 /* s_bfe_i32 */, AMDGPU::S_BFE_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17825 { 8579 /* s_bfe_i32 */, AMDGPU::S_BFE_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17829 { 8599 /* s_bfe_u32 */, AMDGPU::S_BFE_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17830 { 8599 /* s_bfe_u32 */, AMDGPU::S_BFE_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17831 { 8599 /* s_bfe_u32 */, AMDGPU::S_BFE_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17835 { 8619 /* s_bfm_b32 */, AMDGPU::S_BFM_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17836 { 8619 /* s_bfm_b32 */, AMDGPU::S_BFM_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17837 { 8619 /* s_bfm_b32 */, AMDGPU::S_BFM_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
17847 { 8718 /* s_bitset0_b32 */, AMDGPU::S_BITSET0_B32_gfx10, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17848 { 8718 /* s_bitset0_b32 */, AMDGPU::S_BITSET0_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
17849 { 8718 /* s_bitset0_b32 */, AMDGPU::S_BITSET0_B32_vi, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
17853 { 8746 /* s_bitset1_b32 */, AMDGPU::S_BITSET1_B32_gfx10, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17854 { 8746 /* s_bitset1_b32 */, AMDGPU::S_BITSET1_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
17855 { 8746 /* s_bitset1_b32 */, AMDGPU::S_BITSET1_B32_vi, Convert__Reg1_0__SSrcB321_1__imm_95_0, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
17861 { 8783 /* s_brev_b32 */, AMDGPU::S_BREV_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
17862 { 8783 /* s_brev_b32 */, AMDGPU::S_BREV_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
17863 { 8783 /* s_brev_b32 */, AMDGPU::S_BREV_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
17867 { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17868 { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17871 { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17872 { 8805 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17875 { 8825 /* s_buffer_atomic_add_x2 */, AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17876 { 8825 /* s_buffer_atomic_add_x2 */, AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17879 { 8825 /* s_buffer_atomic_add_x2 */, AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17880 { 8825 /* s_buffer_atomic_add_x2 */, AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17883 { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17884 { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17887 { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17888 { 8848 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17891 { 8868 /* s_buffer_atomic_and_x2 */, AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17892 { 8868 /* s_buffer_atomic_and_x2 */, AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17895 { 8868 /* s_buffer_atomic_and_x2 */, AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17896 { 8868 /* s_buffer_atomic_and_x2 */, AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17899 { 8891 /* s_buffer_atomic_cmpswap */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17900 { 8891 /* s_buffer_atomic_cmpswap */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17903 { 8891 /* s_buffer_atomic_cmpswap */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17904 { 8891 /* s_buffer_atomic_cmpswap */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17907 { 8915 /* s_buffer_atomic_cmpswap_x2 */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17908 { 8915 /* s_buffer_atomic_cmpswap_x2 */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17911 { 8915 /* s_buffer_atomic_cmpswap_x2 */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17912 { 8915 /* s_buffer_atomic_cmpswap_x2 */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17915 { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17916 { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17919 { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17920 { 8942 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17923 { 8962 /* s_buffer_atomic_dec_x2 */, AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17924 { 8962 /* s_buffer_atomic_dec_x2 */, AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17927 { 8962 /* s_buffer_atomic_dec_x2 */, AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17928 { 8962 /* s_buffer_atomic_dec_x2 */, AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17931 { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17932 { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17935 { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17936 { 8985 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17939 { 9005 /* s_buffer_atomic_inc_x2 */, AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17940 { 9005 /* s_buffer_atomic_inc_x2 */, AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17943 { 9005 /* s_buffer_atomic_inc_x2 */, AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17944 { 9005 /* s_buffer_atomic_inc_x2 */, AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17947 { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17948 { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17951 { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17952 { 9028 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17955 { 9047 /* s_buffer_atomic_or_x2 */, AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17956 { 9047 /* s_buffer_atomic_or_x2 */, AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17959 { 9047 /* s_buffer_atomic_or_x2 */, AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17960 { 9047 /* s_buffer_atomic_or_x2 */, AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17963 { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17964 { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17967 { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17968 { 9069 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17971 { 9090 /* s_buffer_atomic_smax_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17972 { 9090 /* s_buffer_atomic_smax_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17975 { 9090 /* s_buffer_atomic_smax_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17976 { 9090 /* s_buffer_atomic_smax_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17979 { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17980 { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17983 { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17984 { 9114 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17987 { 9135 /* s_buffer_atomic_smin_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17988 { 9135 /* s_buffer_atomic_smin_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17991 { 9135 /* s_buffer_atomic_smin_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17992 { 9135 /* s_buffer_atomic_smin_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
17995 { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17996 { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
17999 { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18000 { 9159 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18003 { 9179 /* s_buffer_atomic_sub_x2 */, AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18004 { 9179 /* s_buffer_atomic_sub_x2 */, AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18007 { 9179 /* s_buffer_atomic_sub_x2 */, AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18008 { 9179 /* s_buffer_atomic_sub_x2 */, AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18011 { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18012 { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18015 { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18016 { 9202 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18019 { 9223 /* s_buffer_atomic_swap_x2 */, AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18020 { 9223 /* s_buffer_atomic_swap_x2 */, AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18023 { 9223 /* s_buffer_atomic_swap_x2 */, AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18024 { 9223 /* s_buffer_atomic_swap_x2 */, AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18027 { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18028 { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18031 { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18032 { 9247 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18035 { 9268 /* s_buffer_atomic_umax_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18036 { 9268 /* s_buffer_atomic_umax_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18039 { 9268 /* s_buffer_atomic_umax_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18040 { 9268 /* s_buffer_atomic_umax_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18043 { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18044 { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18047 { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18048 { 9292 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18051 { 9313 /* s_buffer_atomic_umin_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18052 { 9313 /* s_buffer_atomic_umin_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18055 { 9313 /* s_buffer_atomic_umin_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18056 { 9313 /* s_buffer_atomic_umin_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18059 { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18060 { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18063 { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18064 { 9337 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18067 { 9357 /* s_buffer_atomic_xor_x2 */, AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18068 { 9357 /* s_buffer_atomic_xor_x2 */, AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmDLC1_3, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmDLC }, },
18071 { 9357 /* s_buffer_atomic_xor_x2 */, AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_RTN_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18072 { 9357 /* s_buffer_atomic_xor_x2 */, AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDLC1_4, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc, MCK_ImmDLC }, },
18075 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18076 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18077 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18082 { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_512, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18083 { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_512, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18084 { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_512, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18089 { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18090 { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18091 { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18096 { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18097 { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18098 { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18103 { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_256, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18104 { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_256, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18105 { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_256, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18110 { 9489 /* s_buffer_store_dword */, AMDGPU::S_BUFFER_STORE_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18111 { 9489 /* s_buffer_store_dword */, AMDGPU::S_BUFFER_STORE_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18114 { 9510 /* s_buffer_store_dwordx2 */, AMDGPU::S_BUFFER_STORE_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18115 { 9510 /* s_buffer_store_dwordx2 */, AMDGPU::S_BUFFER_STORE_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18118 { 9533 /* s_buffer_store_dwordx4 */, AMDGPU::S_BUFFER_STORE_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18119 { 9533 /* s_buffer_store_dwordx4 */, AMDGPU::S_BUFFER_STORE_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18140 { 9724 /* s_cbranch_join */, AMDGPU::S_CBRANCH_JOIN_gfx6_gfx7, Convert__Reg1_0, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_SReg_32 }, },
18141 { 9724 /* s_cbranch_join */, AMDGPU::S_CBRANCH_JOIN_vi, Convert__Reg1_0, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_SReg_32 }, },
18151 { 9809 /* s_cmov_b32 */, AMDGPU::S_CMOV_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18152 { 9809 /* s_cmov_b32 */, AMDGPU::S_CMOV_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18153 { 9809 /* s_cmov_b32 */, AMDGPU::S_CMOV_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18157 { 9831 /* s_cmovk_i32 */, AMDGPU::S_CMOVK_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18158 { 9831 /* s_cmovk_i32 */, AMDGPU::S_CMOVK_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18159 { 9831 /* s_cmovk_i32 */, AMDGPU::S_CMOVK_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18174 { 10025 /* s_cmpk_eq_i32 */, AMDGPU::S_CMPK_EQ_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18175 { 10025 /* s_cmpk_eq_i32 */, AMDGPU::S_CMPK_EQ_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18176 { 10025 /* s_cmpk_eq_i32 */, AMDGPU::S_CMPK_EQ_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18177 { 10039 /* s_cmpk_eq_u32 */, AMDGPU::S_CMPK_EQ_U32_gfx10, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_U16Imm }, },
18178 { 10039 /* s_cmpk_eq_u32 */, AMDGPU::S_CMPK_EQ_U32_gfx6_gfx7, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_U16Imm }, },
18179 { 10039 /* s_cmpk_eq_u32 */, AMDGPU::S_CMPK_EQ_U32_vi, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_U16Imm }, },
18180 { 10053 /* s_cmpk_ge_i32 */, AMDGPU::S_CMPK_GE_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18181 { 10053 /* s_cmpk_ge_i32 */, AMDGPU::S_CMPK_GE_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18182 { 10053 /* s_cmpk_ge_i32 */, AMDGPU::S_CMPK_GE_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18183 { 10067 /* s_cmpk_ge_u32 */, AMDGPU::S_CMPK_GE_U32_gfx10, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_U16Imm }, },
18184 { 10067 /* s_cmpk_ge_u32 */, AMDGPU::S_CMPK_GE_U32_gfx6_gfx7, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_U16Imm }, },
18185 { 10067 /* s_cmpk_ge_u32 */, AMDGPU::S_CMPK_GE_U32_vi, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_U16Imm }, },
18186 { 10081 /* s_cmpk_gt_i32 */, AMDGPU::S_CMPK_GT_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18187 { 10081 /* s_cmpk_gt_i32 */, AMDGPU::S_CMPK_GT_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18188 { 10081 /* s_cmpk_gt_i32 */, AMDGPU::S_CMPK_GT_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18189 { 10095 /* s_cmpk_gt_u32 */, AMDGPU::S_CMPK_GT_U32_gfx10, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_U16Imm }, },
18190 { 10095 /* s_cmpk_gt_u32 */, AMDGPU::S_CMPK_GT_U32_gfx6_gfx7, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_U16Imm }, },
18191 { 10095 /* s_cmpk_gt_u32 */, AMDGPU::S_CMPK_GT_U32_vi, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_U16Imm }, },
18192 { 10109 /* s_cmpk_le_i32 */, AMDGPU::S_CMPK_LE_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18193 { 10109 /* s_cmpk_le_i32 */, AMDGPU::S_CMPK_LE_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18194 { 10109 /* s_cmpk_le_i32 */, AMDGPU::S_CMPK_LE_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18195 { 10123 /* s_cmpk_le_u32 */, AMDGPU::S_CMPK_LE_U32_gfx10, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_U16Imm }, },
18196 { 10123 /* s_cmpk_le_u32 */, AMDGPU::S_CMPK_LE_U32_gfx6_gfx7, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_U16Imm }, },
18197 { 10123 /* s_cmpk_le_u32 */, AMDGPU::S_CMPK_LE_U32_vi, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_U16Imm }, },
18198 { 10137 /* s_cmpk_lg_i32 */, AMDGPU::S_CMPK_LG_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18199 { 10137 /* s_cmpk_lg_i32 */, AMDGPU::S_CMPK_LG_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18200 { 10137 /* s_cmpk_lg_i32 */, AMDGPU::S_CMPK_LG_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18201 { 10151 /* s_cmpk_lg_u32 */, AMDGPU::S_CMPK_LG_U32_gfx10, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_U16Imm }, },
18202 { 10151 /* s_cmpk_lg_u32 */, AMDGPU::S_CMPK_LG_U32_gfx6_gfx7, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_U16Imm }, },
18203 { 10151 /* s_cmpk_lg_u32 */, AMDGPU::S_CMPK_LG_U32_vi, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_U16Imm }, },
18204 { 10165 /* s_cmpk_lt_i32 */, AMDGPU::S_CMPK_LT_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18205 { 10165 /* s_cmpk_lt_i32 */, AMDGPU::S_CMPK_LT_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18206 { 10165 /* s_cmpk_lt_i32 */, AMDGPU::S_CMPK_LT_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18207 { 10179 /* s_cmpk_lt_u32 */, AMDGPU::S_CMPK_LT_U32_gfx10, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_U16Imm }, },
18208 { 10179 /* s_cmpk_lt_u32 */, AMDGPU::S_CMPK_LT_U32_gfx6_gfx7, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_U16Imm }, },
18209 { 10179 /* s_cmpk_lt_u32 */, AMDGPU::S_CMPK_LT_U32_vi, Convert__Reg1_0__U16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_U16Imm }, },
18211 { 10204 /* s_cselect_b32 */, AMDGPU::S_CSELECT_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18212 { 10204 /* s_cselect_b32 */, AMDGPU::S_CSELECT_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18213 { 10204 /* s_cselect_b32 */, AMDGPU::S_CSELECT_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18217 { 10232 /* s_dcache_discard */, AMDGPU::S_DCACHE_DISCARD_SGPR_gfx10, Convert__Reg1_0__Reg1_1, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64, MCK_SReg_32 }, },
18218 { 10232 /* s_dcache_discard */, AMDGPU::S_DCACHE_DISCARD_SGPR_vi, Convert__Reg1_0__Reg1_1, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64, MCK_SReg_32 }, },
18221 { 10249 /* s_dcache_discard_x2 */, AMDGPU::S_DCACHE_DISCARD_X2_SGPR_gfx10, Convert__Reg1_0__Reg1_1, AMFBS_HasScalarAtomics_isGFX10Plus, { MCK_SReg_64, MCK_SReg_32 }, },
18222 { 10249 /* s_dcache_discard_x2 */, AMDGPU::S_DCACHE_DISCARD_X2_SGPR_vi, Convert__Reg1_0__Reg1_1, AMFBS_HasScalarAtomics_isGFX8GFX9, { MCK_SReg_64, MCK_SReg_32 }, },
18238 { 10405 /* s_ff0_i32_b32 */, AMDGPU::S_FF0_I32_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18239 { 10405 /* s_ff0_i32_b32 */, AMDGPU::S_FF0_I32_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18240 { 10405 /* s_ff0_i32_b32 */, AMDGPU::S_FF0_I32_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18241 { 10419 /* s_ff0_i32_b64 */, AMDGPU::S_FF0_I32_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB64 }, },
18242 { 10419 /* s_ff0_i32_b64 */, AMDGPU::S_FF0_I32_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB64 }, },
18243 { 10419 /* s_ff0_i32_b64 */, AMDGPU::S_FF0_I32_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB64 }, },
18244 { 10433 /* s_ff1_i32_b32 */, AMDGPU::S_FF1_I32_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18245 { 10433 /* s_ff1_i32_b32 */, AMDGPU::S_FF1_I32_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18246 { 10433 /* s_ff1_i32_b32 */, AMDGPU::S_FF1_I32_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18247 { 10447 /* s_ff1_i32_b64 */, AMDGPU::S_FF1_I32_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB64 }, },
18248 { 10447 /* s_ff1_i32_b64 */, AMDGPU::S_FF1_I32_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB64 }, },
18249 { 10447 /* s_ff1_i32_b64 */, AMDGPU::S_FF1_I32_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB64 }, },
18250 { 10461 /* s_flbit_i32 */, AMDGPU::S_FLBIT_I32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18251 { 10461 /* s_flbit_i32 */, AMDGPU::S_FLBIT_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18252 { 10461 /* s_flbit_i32 */, AMDGPU::S_FLBIT_I32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18253 { 10473 /* s_flbit_i32_b32 */, AMDGPU::S_FLBIT_I32_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18254 { 10473 /* s_flbit_i32_b32 */, AMDGPU::S_FLBIT_I32_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18255 { 10473 /* s_flbit_i32_b32 */, AMDGPU::S_FLBIT_I32_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18256 { 10489 /* s_flbit_i32_b64 */, AMDGPU::S_FLBIT_I32_B64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB64 }, },
18257 { 10489 /* s_flbit_i32_b64 */, AMDGPU::S_FLBIT_I32_B64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB64 }, },
18258 { 10489 /* s_flbit_i32_b64 */, AMDGPU::S_FLBIT_I32_B64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB64 }, },
18259 { 10505 /* s_flbit_i32_i64 */, AMDGPU::S_FLBIT_I32_I64_gfx10, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB64 }, },
18260 { 10505 /* s_flbit_i32_i64 */, AMDGPU::S_FLBIT_I32_I64_gfx6_gfx7, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB64 }, },
18261 { 10505 /* s_flbit_i32_i64 */, AMDGPU::S_FLBIT_I32_I64_vi, Convert__Reg1_0__SSrcB641_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB64 }, },
18266 { 10559 /* s_getreg_b32 */, AMDGPU::S_GETREG_B32_gfx10, Convert__Reg1_0__ImmHwreg1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_ImmHwreg }, },
18267 { 10559 /* s_getreg_b32 */, AMDGPU::S_GETREG_B32_gfx6_gfx7, Convert__Reg1_0__ImmHwreg1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_ImmHwreg }, },
18268 { 10559 /* s_getreg_b32 */, AMDGPU::S_GETREG_B32_vi, Convert__Reg1_0__ImmHwreg1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_ImmHwreg }, },
18273 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18274 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18275 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18280 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_512, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18281 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_512, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18282 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_512, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18287 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18288 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18289 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18294 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18295 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18296 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18301 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_256, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18302 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_256, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18303 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_256, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18308 { 10700 /* s_lshl1_add_u32 */, AMDGPU::S_LSHL1_ADD_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18309 { 10700 /* s_lshl1_add_u32 */, AMDGPU::S_LSHL1_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18310 { 10716 /* s_lshl2_add_u32 */, AMDGPU::S_LSHL2_ADD_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18311 { 10716 /* s_lshl2_add_u32 */, AMDGPU::S_LSHL2_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18312 { 10732 /* s_lshl3_add_u32 */, AMDGPU::S_LSHL3_ADD_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18313 { 10732 /* s_lshl3_add_u32 */, AMDGPU::S_LSHL3_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18314 { 10748 /* s_lshl4_add_u32 */, AMDGPU::S_LSHL4_ADD_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18315 { 10748 /* s_lshl4_add_u32 */, AMDGPU::S_LSHL4_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18316 { 10764 /* s_lshl_b32 */, AMDGPU::S_LSHL_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18317 { 10764 /* s_lshl_b32 */, AMDGPU::S_LSHL_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18318 { 10764 /* s_lshl_b32 */, AMDGPU::S_LSHL_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18322 { 10786 /* s_lshr_b32 */, AMDGPU::S_LSHR_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18323 { 10786 /* s_lshr_b32 */, AMDGPU::S_LSHR_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18324 { 10786 /* s_lshr_b32 */, AMDGPU::S_LSHR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18328 { 10808 /* s_max_i32 */, AMDGPU::S_MAX_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18329 { 10808 /* s_max_i32 */, AMDGPU::S_MAX_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18330 { 10808 /* s_max_i32 */, AMDGPU::S_MAX_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18331 { 10818 /* s_max_u32 */, AMDGPU::S_MAX_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18332 { 10818 /* s_max_u32 */, AMDGPU::S_MAX_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18333 { 10818 /* s_max_u32 */, AMDGPU::S_MAX_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18339 { 10852 /* s_min_i32 */, AMDGPU::S_MIN_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18340 { 10852 /* s_min_i32 */, AMDGPU::S_MIN_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18341 { 10852 /* s_min_i32 */, AMDGPU::S_MIN_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18342 { 10862 /* s_min_u32 */, AMDGPU::S_MIN_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18343 { 10862 /* s_min_u32 */, AMDGPU::S_MIN_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18344 { 10862 /* s_min_u32 */, AMDGPU::S_MIN_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18345 { 10872 /* s_mov_b32 */, AMDGPU::S_MOV_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18346 { 10872 /* s_mov_b32 */, AMDGPU::S_MOV_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18347 { 10872 /* s_mov_b32 */, AMDGPU::S_MOV_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18351 { 10892 /* s_mov_fed_b32 */, AMDGPU::S_MOV_FED_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18352 { 10892 /* s_mov_fed_b32 */, AMDGPU::S_MOV_FED_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18353 { 10892 /* s_mov_fed_b32 */, AMDGPU::S_MOV_FED_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18354 { 10906 /* s_mov_regrd_b32 */, AMDGPU::S_MOV_REGRD_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18355 { 10906 /* s_mov_regrd_b32 */, AMDGPU::S_MOV_REGRD_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18356 { 10922 /* s_movk_i32 */, AMDGPU::S_MOVK_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18357 { 10922 /* s_movk_i32 */, AMDGPU::S_MOVK_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18358 { 10922 /* s_movk_i32 */, AMDGPU::S_MOVK_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18359 { 10933 /* s_movreld_b32 */, AMDGPU::S_MOVRELD_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18360 { 10933 /* s_movreld_b32 */, AMDGPU::S_MOVRELD_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18361 { 10933 /* s_movreld_b32 */, AMDGPU::S_MOVRELD_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18365 { 10961 /* s_movrels_b32 */, AMDGPU::S_MOVRELS_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18366 { 10961 /* s_movrels_b32 */, AMDGPU::S_MOVRELS_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18367 { 10961 /* s_movrels_b32 */, AMDGPU::S_MOVRELS_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18371 { 10989 /* s_movrelsd_2_b32 */, AMDGPU::S_MOVRELSD_2_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18372 { 11006 /* s_mul_hi_i32 */, AMDGPU::S_MUL_HI_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18373 { 11006 /* s_mul_hi_i32 */, AMDGPU::S_MUL_HI_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18374 { 11019 /* s_mul_hi_u32 */, AMDGPU::S_MUL_HI_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18375 { 11019 /* s_mul_hi_u32 */, AMDGPU::S_MUL_HI_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18376 { 11032 /* s_mul_i32 */, AMDGPU::S_MUL_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18377 { 11032 /* s_mul_i32 */, AMDGPU::S_MUL_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18378 { 11032 /* s_mul_i32 */, AMDGPU::S_MUL_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18379 { 11042 /* s_mulk_i32 */, AMDGPU::S_MULK_I32_gfx10, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18380 { 11042 /* s_mulk_i32 */, AMDGPU::S_MULK_I32_gfx6_gfx7, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18381 { 11042 /* s_mulk_i32 */, AMDGPU::S_MULK_I32_vi, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18382 { 11053 /* s_nand_b32 */, AMDGPU::S_NAND_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18383 { 11053 /* s_nand_b32 */, AMDGPU::S_NAND_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18384 { 11053 /* s_nand_b32 */, AMDGPU::S_NAND_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18388 { 11075 /* s_nand_saveexec_b32 */, AMDGPU::S_NAND_SAVEEXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18393 { 11121 /* s_nor_b32 */, AMDGPU::S_NOR_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18394 { 11121 /* s_nor_b32 */, AMDGPU::S_NOR_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18395 { 11121 /* s_nor_b32 */, AMDGPU::S_NOR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18399 { 11141 /* s_nor_saveexec_b32 */, AMDGPU::S_NOR_SAVEEXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18403 { 11179 /* s_not_b32 */, AMDGPU::S_NOT_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18404 { 11179 /* s_not_b32 */, AMDGPU::S_NOT_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18405 { 11179 /* s_not_b32 */, AMDGPU::S_NOT_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18409 { 11199 /* s_or_b32 */, AMDGPU::S_OR_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18410 { 11199 /* s_or_b32 */, AMDGPU::S_OR_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18411 { 11199 /* s_or_b32 */, AMDGPU::S_OR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18415 { 11217 /* s_or_saveexec_b32 */, AMDGPU::S_OR_SAVEEXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18419 { 11253 /* s_orn1_saveexec_b32 */, AMDGPU::S_ORN1_SAVEEXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18422 { 11293 /* s_orn2_b32 */, AMDGPU::S_ORN2_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18423 { 11293 /* s_orn2_b32 */, AMDGPU::S_ORN2_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18424 { 11293 /* s_orn2_b32 */, AMDGPU::S_ORN2_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18428 { 11315 /* s_orn2_saveexec_b32 */, AMDGPU::S_ORN2_SAVEEXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18432 { 11355 /* s_pack_hh_b32_b16 */, AMDGPU::S_PACK_HH_B32_B16_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18433 { 11355 /* s_pack_hh_b32_b16 */, AMDGPU::S_PACK_HH_B32_B16_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18434 { 11373 /* s_pack_lh_b32_b16 */, AMDGPU::S_PACK_LH_B32_B16_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18435 { 11373 /* s_pack_lh_b32_b16 */, AMDGPU::S_PACK_LH_B32_B16_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18436 { 11391 /* s_pack_ll_b32_b16 */, AMDGPU::S_PACK_LL_B32_B16_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18437 { 11391 /* s_pack_ll_b32_b16 */, AMDGPU::S_PACK_LL_B32_B16_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18438 { 11409 /* s_quadmask_b32 */, AMDGPU::S_QUADMASK_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18439 { 11409 /* s_quadmask_b32 */, AMDGPU::S_QUADMASK_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18440 { 11409 /* s_quadmask_b32 */, AMDGPU::S_QUADMASK_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18449 { 11480 /* s_scratch_load_dword */, AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18450 { 11480 /* s_scratch_load_dword */, AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18453 { 11501 /* s_scratch_load_dwordx2 */, AMDGPU::S_SCRATCH_LOAD_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18454 { 11501 /* s_scratch_load_dwordx2 */, AMDGPU::S_SCRATCH_LOAD_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18457 { 11524 /* s_scratch_load_dwordx4 */, AMDGPU::S_SCRATCH_LOAD_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18458 { 11524 /* s_scratch_load_dwordx4 */, AMDGPU::S_SCRATCH_LOAD_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18461 { 11547 /* s_scratch_store_dword */, AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18462 { 11547 /* s_scratch_store_dword */, AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18465 { 11569 /* s_scratch_store_dwordx2 */, AMDGPU::S_SCRATCH_STORE_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18466 { 11569 /* s_scratch_store_dwordx2 */, AMDGPU::S_SCRATCH_STORE_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18469 { 11593 /* s_scratch_store_dwordx4 */, AMDGPU::S_SCRATCH_STORE_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18470 { 11593 /* s_scratch_store_dwordx4 */, AMDGPU::S_SCRATCH_STORE_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18485 { 11755 /* s_setreg_b32 */, AMDGPU::S_SETREG_B32_gfx10, Convert__Reg1_1__ImmHwreg1_0, AMFBS_isGFX10Plus, { MCK_ImmHwreg, MCK_SReg_32 }, },
18486 { 11755 /* s_setreg_b32 */, AMDGPU::S_SETREG_B32_gfx6_gfx7, Convert__Reg1_1__ImmHwreg1_0, AMFBS_isGFX6GFX7, { MCK_ImmHwreg, MCK_SReg_32 }, },
18487 { 11755 /* s_setreg_b32 */, AMDGPU::S_SETREG_B32_vi, Convert__Reg1_1__ImmHwreg1_0, AMFBS_isGFX8GFX9, { MCK_ImmHwreg, MCK_SReg_32 }, },
18492 { 11798 /* s_sext_i32_i16 */, AMDGPU::S_SEXT_I32_I16_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18493 { 11798 /* s_sext_i32_i16 */, AMDGPU::S_SEXT_I32_I16_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18494 { 11798 /* s_sext_i32_i16 */, AMDGPU::S_SEXT_I32_I16_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18495 { 11813 /* s_sext_i32_i8 */, AMDGPU::S_SEXT_I32_I8_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18496 { 11813 /* s_sext_i32_i8 */, AMDGPU::S_SEXT_I32_I8_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18497 { 11813 /* s_sext_i32_i8 */, AMDGPU::S_SEXT_I32_I8_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18499 { 11835 /* s_store_dword */, AMDGPU::S_STORE_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18500 { 11835 /* s_store_dword */, AMDGPU::S_STORE_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18503 { 11849 /* s_store_dwordx2 */, AMDGPU::S_STORE_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18504 { 11849 /* s_store_dwordx2 */, AMDGPU::S_STORE_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18507 { 11865 /* s_store_dwordx4 */, AMDGPU::S_STORE_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18508 { 11865 /* s_store_dwordx4 */, AMDGPU::S_STORE_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18511 { 11881 /* s_sub_i32 */, AMDGPU::S_SUB_I32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18512 { 11881 /* s_sub_i32 */, AMDGPU::S_SUB_I32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18513 { 11881 /* s_sub_i32 */, AMDGPU::S_SUB_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18514 { 11891 /* s_sub_u32 */, AMDGPU::S_SUB_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18515 { 11891 /* s_sub_u32 */, AMDGPU::S_SUB_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18516 { 11891 /* s_sub_u32 */, AMDGPU::S_SUB_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18517 { 11901 /* s_subb_u32 */, AMDGPU::S_SUBB_U32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18518 { 11901 /* s_subb_u32 */, AMDGPU::S_SUBB_U32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18519 { 11901 /* s_subb_u32 */, AMDGPU::S_SUBB_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18520 { 11912 /* s_subvector_loop_begin */, AMDGPU::S_SUBVECTOR_LOOP_BEGIN_gfx10, Convert__SoppBrTarget1_1__Reg1_0, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SoppBrTarget }, },
18521 { 11935 /* s_subvector_loop_end */, AMDGPU::S_SUBVECTOR_LOOP_END_gfx10, Convert__SoppBrTarget1_1__Reg1_0, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SoppBrTarget }, },
18532 { 12055 /* s_waitcnt_expcnt */, AMDGPU::S_WAITCNT_EXPCNT_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18533 { 12072 /* s_waitcnt_lgkmcnt */, AMDGPU::S_WAITCNT_LGKMCNT_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18534 { 12090 /* s_waitcnt_vmcnt */, AMDGPU::S_WAITCNT_VMCNT_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18535 { 12106 /* s_waitcnt_vscnt */, AMDGPU::S_WAITCNT_VSCNT_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18537 { 12131 /* s_wqm_b32 */, AMDGPU::S_WQM_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18538 { 12131 /* s_wqm_b32 */, AMDGPU::S_WQM_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32 }, },
18539 { 12131 /* s_wqm_b32 */, AMDGPU::S_WQM_B32_vi, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32 }, },
18543 { 12151 /* s_xnor_b32 */, AMDGPU::S_XNOR_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18544 { 12151 /* s_xnor_b32 */, AMDGPU::S_XNOR_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18545 { 12151 /* s_xnor_b32 */, AMDGPU::S_XNOR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18549 { 12173 /* s_xnor_saveexec_b32 */, AMDGPU::S_XNOR_SAVEEXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
18553 { 12213 /* s_xor_b32 */, AMDGPU::S_XOR_B32_gfx10, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18554 { 12213 /* s_xor_b32 */, AMDGPU::S_XOR_B32_gfx6_gfx7, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18555 { 12213 /* s_xor_b32 */, AMDGPU::S_XOR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
18559 { 12233 /* s_xor_saveexec_b32 */, AMDGPU::S_XOR_SAVEEXEC_B32_gfx10, Convert__Reg1_0__SSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_SSrcB32 }, },
21333 { 25672 /* v_readfirstlane_b32 */, AMDGPU::V_READFIRSTLANE_B32, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_SReg_32, MCK_VRegOrLds_32 }, },
21334 { 25692 /* v_readlane_b32 */, AMDGPU::V_READLANE_B32_gfx10, Convert__Reg1_0__Reg1_1__SCSrcB321_2, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_VRegOrLds_32, MCK_SCSrcB32 }, },
21335 { 25692 /* v_readlane_b32 */, AMDGPU::V_READLANE_B32_gfx6_gfx7, Convert__Reg1_0__Reg1_1__SCSrcB321_2, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_VRegOrLds_32, MCK_SCSrcB32 }, },
21336 { 25692 /* v_readlane_b32 */, AMDGPU::V_READLANE_B32_vi, Convert__Reg1_0__Reg1_1__SCSrcB321_2, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_VRegOrLds_32, MCK_SCSrcB32 }, },