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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 5371 case MCK_SDWAWithFP32InputMods: {
10052 case MCK_SDWAWithFP32InputMods: return "MCK_SDWAWithFP32InputMods";
22798 { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22798 { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22809 { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22811 { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22813 { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22813 { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22819 { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22819 { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22825 { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22825 { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22831 { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22831 { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22837 { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22837 { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22843 { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22843 { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22845 { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22845 { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22855 { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22855 { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22857 { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22857 { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22859 { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22859 { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22861 { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22861 { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22863 { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22863 { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22865 { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22865 { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22867 { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22867 { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22873 { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22873 { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22875 { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22875 { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22877 { 18811 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22879 { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22879 { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22885 { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22885 { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22891 { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22891 { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22897 { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22897 { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22903 { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22903 { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22909 { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22909 { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22911 { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22911 { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22921 { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22921 { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22923 { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22923 { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22925 { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22925 { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22927 { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22927 { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22929 { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22929 { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22931 { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22931 { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22933 { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22933 { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22939 { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22939 { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22941 { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22941 { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22950 { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22951 { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22961 { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22963 { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22967 { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22969 { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22971 { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22972 { 22919 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_isGFX7GFX8GFX9_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22977 { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22978 { 23133 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasDLInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22978 { 23133 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasDLInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22980 { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22982 { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22984 { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22987 { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22988 { 23521 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_isGFX7GFX8GFX9_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22994 { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22994 { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22996 { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22996 { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23002 { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23002 { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23010 { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23010 { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23014 { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23014 { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23021 { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23022 { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23024 { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23026 { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23029 { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23031 { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23037 { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23037 { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23051 { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23051 { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23055 { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23071 { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23071 { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23072 { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23072 { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23088 { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23089 { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23092 { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23093 { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23096 { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23096 { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23097 { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23097 { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23108 { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23108 { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23109 { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23109 { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23118 { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23118 { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23119 { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23119 { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23130 { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23130 { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23131 { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23131 { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23142 { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23142 { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23143 { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23143 { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23154 { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23154 { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23155 { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23155 { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23158 { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23158 { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23159 { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23159 { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23178 { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23178 { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23179 { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23179 { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23182 { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23182 { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23183 { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23183 { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23186 { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23186 { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23187 { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23187 { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23190 { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23190 { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23191 { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23191 { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23194 { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23194 { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23195 { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23195 { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23198 { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23198 { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23199 { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23199 { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23202 { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23202 { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23203 { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23203 { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23212 { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23212 { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23213 { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23213 { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23216 { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23216 { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23217 { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23217 { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23220 { 18811 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23221 { 18811 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23224 { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23224 { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23225 { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23225 { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23236 { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23236 { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23237 { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23237 { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23246 { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23246 { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23247 { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23247 { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23258 { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23258 { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23259 { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23259 { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23270 { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23270 { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23271 { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23271 { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23282 { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23282 { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23283 { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23283 { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23286 { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23286 { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23287 { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23287 { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23306 { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23306 { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23307 { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23307 { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23310 { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23310 { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23311 { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23311 { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23314 { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23314 { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23315 { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23315 { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23318 { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23318 { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23319 { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23319 { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23322 { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23322 { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23323 { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23323 { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23326 { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23326 { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23327 { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23327 { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23330 { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23330 { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23331 { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23331 { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23340 { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23340 { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23341 { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23341 { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23344 { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23344 { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23345 { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23345 { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23358 { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23359 { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23360 { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23361 { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23380 { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23381 { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23384 { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23385 { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23392 { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23393 { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23396 { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23397 { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23400 { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23401 { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23402 { 22919 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23411 { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23412 { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23415 { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23416 { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23419 { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23420 { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23423 { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23424 { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23429 { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23430 { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23431 { 23521 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23438 { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23438 { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23441 { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23441 { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23442 { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23442 { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23451 { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23451 { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23452 { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23452 { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23465 { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23465 { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23466 { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23466 { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23473 { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23473 { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23474 { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23474 { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23487 { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23488 { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23489 { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23490 { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23493 { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23494 { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23497 { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23498 { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23504 { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23505 { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23508 { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23509 { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23520 { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23520 { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23521 { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23521 { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23541 { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23541 { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23542 { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23542 { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23548 { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23549 { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
72958 { 13261 /* v_add_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
72970 { 13261 /* v_add_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
72977 { 13261 /* v_add_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73225 { 13609 /* v_ceil_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
73235 { 13609 /* v_ceil_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73241 { 13609 /* v_ceil_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73288 { 13677 /* v_cmp_class_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73293 { 13677 /* v_cmp_class_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73297 { 13677 /* v_cmp_class_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
73336 { 13779 /* v_cmp_eq_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73340 { 13779 /* v_cmp_eq_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73343 { 13779 /* v_cmp_eq_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
73448 { 14047 /* v_cmp_f_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73452 { 14047 /* v_cmp_f_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73455 { 14047 /* v_cmp_f_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
73550 { 14301 /* v_cmp_ge_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73554 { 14301 /* v_cmp_ge_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73557 { 14301 /* v_cmp_ge_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
73662 { 14571 /* v_cmp_gt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73666 { 14571 /* v_cmp_gt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73669 { 14571 /* v_cmp_gt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
73774 { 14841 /* v_cmp_le_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73778 { 14841 /* v_cmp_le_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73781 { 14841 /* v_cmp_le_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
73886 { 15111 /* v_cmp_lg_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73890 { 15111 /* v_cmp_lg_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73893 { 15111 /* v_cmp_lg_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
73934 { 15201 /* v_cmp_lt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73938 { 15201 /* v_cmp_lt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73941 { 15201 /* v_cmp_lt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74110 { 15653 /* v_cmp_neq_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74114 { 15653 /* v_cmp_neq_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74117 { 15653 /* v_cmp_neq_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74158 { 15749 /* v_cmp_nge_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74162 { 15749 /* v_cmp_nge_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74165 { 15749 /* v_cmp_nge_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74206 { 15845 /* v_cmp_ngt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74210 { 15845 /* v_cmp_ngt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74213 { 15845 /* v_cmp_ngt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74254 { 15941 /* v_cmp_nle_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74258 { 15941 /* v_cmp_nle_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74261 { 15941 /* v_cmp_nle_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74302 { 16037 /* v_cmp_nlg_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74306 { 16037 /* v_cmp_nlg_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74309 { 16037 /* v_cmp_nlg_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74350 { 16133 /* v_cmp_nlt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74354 { 16133 /* v_cmp_nlt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74357 { 16133 /* v_cmp_nlt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74398 { 16225 /* v_cmp_o_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74402 { 16225 /* v_cmp_o_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74405 { 16225 /* v_cmp_o_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74500 { 16481 /* v_cmp_tru_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74504 { 16481 /* v_cmp_tru_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74507 { 16481 /* v_cmp_tru_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74548 { 16573 /* v_cmp_u_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74552 { 16573 /* v_cmp_u_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74555 { 16573 /* v_cmp_u_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74782 { 18811 /* v_cmpx_class_f32 */, 1 /* 0 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74787 { 18811 /* v_cmpx_class_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74791 { 18811 /* v_cmpx_class_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74825 { 18919 /* v_cmpx_eq_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74829 { 18919 /* v_cmpx_eq_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74832 { 18919 /* v_cmpx_eq_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
74922 { 19205 /* v_cmpx_f_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74926 { 19205 /* v_cmpx_f_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74929 { 19205 /* v_cmpx_f_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75013 { 19477 /* v_cmpx_ge_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75017 { 19477 /* v_cmpx_ge_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75020 { 19477 /* v_cmpx_ge_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75110 { 19765 /* v_cmpx_gt_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75114 { 19765 /* v_cmpx_gt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75117 { 19765 /* v_cmpx_gt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75207 { 20053 /* v_cmpx_le_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75211 { 20053 /* v_cmpx_le_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75214 { 20053 /* v_cmpx_le_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75304 { 20341 /* v_cmpx_lg_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75308 { 20341 /* v_cmpx_lg_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75311 { 20341 /* v_cmpx_lg_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75347 { 20437 /* v_cmpx_lt_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75351 { 20437 /* v_cmpx_lt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75354 { 20437 /* v_cmpx_lt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75498 { 20919 /* v_cmpx_neq_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75502 { 20919 /* v_cmpx_neq_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75505 { 20919 /* v_cmpx_neq_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75541 { 21021 /* v_cmpx_nge_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75545 { 21021 /* v_cmpx_nge_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75548 { 21021 /* v_cmpx_nge_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75584 { 21123 /* v_cmpx_ngt_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75588 { 21123 /* v_cmpx_ngt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75591 { 21123 /* v_cmpx_ngt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75627 { 21225 /* v_cmpx_nle_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75631 { 21225 /* v_cmpx_nle_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75634 { 21225 /* v_cmpx_nle_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75670 { 21327 /* v_cmpx_nlg_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75674 { 21327 /* v_cmpx_nlg_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75677 { 21327 /* v_cmpx_nlg_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75713 { 21429 /* v_cmpx_nlt_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75717 { 21429 /* v_cmpx_nlt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75720 { 21429 /* v_cmpx_nlt_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75756 { 21527 /* v_cmpx_o_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75760 { 21527 /* v_cmpx_o_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75763 { 21527 /* v_cmpx_o_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75847 { 21801 /* v_cmpx_tru_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75851 { 21801 /* v_cmpx_tru_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75854 { 21801 /* v_cmpx_tru_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
75890 { 21899 /* v_cmpx_u_f32 */, 3 /* 0, 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75894 { 21899 /* v_cmpx_u_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75897 { 21899 /* v_cmpx_u_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
76017 { 21983 /* v_cos_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
76027 { 21983 /* v_cos_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76033 { 21983 /* v_cos_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76092 { 22045 /* v_cvt_f16_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
76102 { 22045 /* v_cvt_f16_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76108 { 22045 /* v_cvt_f16_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76465 { 22253 /* v_cvt_flr_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
76470 { 22253 /* v_cvt_flr_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76475 { 22253 /* v_cvt_flr_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76531 { 22285 /* v_cvt_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
76536 { 22285 /* v_cvt_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76541 { 22285 /* v_cvt_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76717 { 22543 /* v_cvt_rpi_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
76722 { 22543 /* v_cvt_rpi_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76727 { 22543 /* v_cvt_rpi_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76783 { 22575 /* v_cvt_u32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
76788 { 22575 /* v_cvt_u32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76793 { 22575 /* v_cvt_u32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77022 { 22909 /* v_exp_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
77032 { 22909 /* v_exp_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77038 { 22909 /* v_exp_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77056 { 22919 /* v_exp_legacy_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_isGFX7GFX8GFX9_HasSDWA },
77066 { 22919 /* v_exp_legacy_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77197 { 22981 /* v_floor_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
77207 { 22981 /* v_floor_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77213 { 22981 /* v_floor_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77314 { 23133 /* v_fmac_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasDLInsts_HasSDWA },
77375 { 23180 /* v_fract_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
77385 { 23180 /* v_fract_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77391 { 23180 /* v_fract_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77452 { 23224 /* v_frexp_exp_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
77457 { 23224 /* v_frexp_exp_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77462 { 23224 /* v_frexp_exp_i32_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77531 { 23281 /* v_frexp_mant_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
77541 { 23281 /* v_frexp_mant_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77547 { 23281 /* v_frexp_mant_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77765 { 23511 /* v_log_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
77775 { 23511 /* v_log_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77781 { 23511 /* v_log_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77799 { 23521 /* v_log_legacy_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_isGFX7GFX8GFX9_HasSDWA },
77809 { 23521 /* v_log_legacy_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77935 { 23705 /* v_mac_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
77961 { 23715 /* v_mac_legacy_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78131 { 24094 /* v_max_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
78143 { 24094 /* v_max_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78150 { 24094 /* v_max_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78420 { 24785 /* v_min_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
78432 { 24785 /* v_min_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78439 { 24785 /* v_min_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78664 { 24999 /* v_mul_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
78676 { 24999 /* v_mul_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78683 { 24999 /* v_mul_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78802 { 25093 /* v_mul_legacy_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
78814 { 25093 /* v_mul_legacy_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78821 { 25093 /* v_mul_legacy_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79188 { 25619 /* v_rcp_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
79198 { 25619 /* v_rcp_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79204 { 25619 /* v_rcp_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79236 { 25639 /* v_rcp_iflag_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
79246 { 25639 /* v_rcp_iflag_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79252 { 25639 /* v_rcp_iflag_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79314 { 25719 /* v_rndne_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
79324 { 25719 /* v_rndne_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79330 { 25719 /* v_rndne_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79404 { 25785 /* v_rsq_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
79414 { 25785 /* v_rsq_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79420 { 25785 /* v_rsq_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79538 { 25916 /* v_sin_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
79548 { 25916 /* v_sin_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79554 { 25916 /* v_sin_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79613 { 25937 /* v_sqrt_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
79623 { 25937 /* v_sqrt_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79629 { 25937 /* v_sqrt_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79760 { 25998 /* v_sub_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
79772 { 25998 /* v_sub_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79779 { 25998 /* v_sub_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
80007 { 26204 /* v_subrev_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
80019 { 26204 /* v_subrev_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
80026 { 26204 /* v_subrev_f32 */, 6 /* 1, 2 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
80147 { 26326 /* v_trunc_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA_HasSDWA },
80157 { 26326 /* v_trunc_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA10_isGFX10Plus },
80163 { 26326 /* v_trunc_f32 */, 2 /* 1 */, MCK_SDWAWithFP32InputMods, AMFBS_HasSDWA9_HasSDWA9 },
80263 case MCK_SDWAWithFP32InputMods: