reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

 5357   case MCK_SDWAWithFP16InputMods: {
10050   case MCK_SDWAWithFP16InputMods: return "MCK_SDWAWithFP16InputMods";
22797   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22797   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22808   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22810   { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22812   { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22812   { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22818   { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22818   { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22824   { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22824   { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22830   { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22830   { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22836   { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22836   { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22842   { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22842   { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22844   { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22844   { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22854   { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22854   { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22856   { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22856   { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22858   { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22858   { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22860   { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22860   { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22862   { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22862   { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22864   { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22864   { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22866   { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22866   { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22872   { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22872   { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22874   { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22874   { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22876   { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22878   { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22878   { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22884   { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22884   { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22890   { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22890   { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22896   { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22896   { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22902   { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22902   { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22908   { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22908   { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22910   { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22910   { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22920   { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22920   { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22922   { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22922   { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22924   { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22924   { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22926   { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22926   { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22928   { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22928   { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22930   { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22930   { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22932   { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22932   { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22938   { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22938   { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22940   { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22940   { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22949   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22954   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22962   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22964   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_isGFX9Plus_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22965   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_isGFX9Plus_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22968   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22970   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22976   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22979   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22981   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22983   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22985   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22986   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22993   { 23695 /* v_mac_f16 */, AMDGPU::V_MAC_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22993   { 23695 /* v_mac_f16 */, AMDGPU::V_MAC_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22995   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22995   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23001   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23001   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23009   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23009   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23020   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23023   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23025   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23028   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23030   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23036   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23036   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23050   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23050   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23054   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23069   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23069   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23070   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23070   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23086   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23087   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23090   { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23091   { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23094   { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23094   { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23095   { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23095   { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23106   { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23106   { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23107   { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23107   { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23116   { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23116   { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23117   { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23117   { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23128   { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23128   { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23129   { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23129   { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23140   { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23140   { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23141   { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23141   { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23152   { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23152   { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23153   { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23153   { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23156   { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23156   { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23157   { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23157   { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23176   { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23176   { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23177   { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23177   { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23180   { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23180   { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23181   { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23181   { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23184   { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23184   { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23185   { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23185   { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23188   { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23188   { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23189   { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23189   { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23192   { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23192   { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23193   { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23193   { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23196   { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23196   { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23197   { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23197   { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23200   { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23200   { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23201   { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23201   { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23210   { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23210   { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23211   { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23211   { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23214   { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23214   { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23215   { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23215   { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23218   { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23219   { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23222   { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23222   { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23223   { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23223   { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23234   { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23234   { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23235   { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23235   { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23244   { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23244   { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23245   { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23245   { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23256   { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23256   { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23257   { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23257   { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23268   { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23268   { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23269   { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23269   { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23280   { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23280   { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23281   { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23281   { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23284   { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23284   { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23285   { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23285   { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23304   { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23304   { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23305   { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23305   { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23308   { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23308   { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23309   { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23309   { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23312   { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23312   { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23313   { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23313   { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23316   { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23316   { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23317   { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23317   { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23320   { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23320   { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23321   { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23321   { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23324   { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23324   { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23325   { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23325   { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23328   { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23328   { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23329   { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23329   { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23338   { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23338   { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23339   { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23339   { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23342   { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23342   { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23343   { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23343   { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23356   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23357   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23366   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23367   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23382   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23383   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23386   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23387   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23388   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23389   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23394   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23395   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23398   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23399   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23409   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23410   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23413   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23414   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23417   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23418   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23421   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23422   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23425   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23426   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23427   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23428   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23439   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23439   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23440   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23440   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23449   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23449   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23450   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23450   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23463   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23463   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23464   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23464   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23485   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23486   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23491   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23492   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23495   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23496   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23502   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23503   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23506   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23507   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23518   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23518   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23519   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23519   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23539   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23539   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23540   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23540   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23546   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23547   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
72916   { 13251 /* v_add_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
72928   { 13251 /* v_add_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
72935   { 13251 /* v_add_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73186   { 13598 /* v_ceil_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73196   { 13598 /* v_ceil_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73202   { 13598 /* v_ceil_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73267   { 13641 /* v_cmp_class_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73272   { 13641 /* v_cmp_class_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73276   { 13641 /* v_cmp_class_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73315   { 13749 /* v_cmp_eq_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73319   { 13749 /* v_cmp_eq_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73322   { 13749 /* v_cmp_eq_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73427   { 14019 /* v_cmp_f_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73431   { 14019 /* v_cmp_f_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73434   { 14019 /* v_cmp_f_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73529   { 14271 /* v_cmp_ge_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73533   { 14271 /* v_cmp_ge_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73536   { 14271 /* v_cmp_ge_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73641   { 14541 /* v_cmp_gt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73645   { 14541 /* v_cmp_gt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73648   { 14541 /* v_cmp_gt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73753   { 14811 /* v_cmp_le_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73757   { 14811 /* v_cmp_le_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73760   { 14811 /* v_cmp_le_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73865   { 15081 /* v_cmp_lg_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73869   { 15081 /* v_cmp_lg_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73872   { 15081 /* v_cmp_lg_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73913   { 15171 /* v_cmp_lt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
73917   { 15171 /* v_cmp_lt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
73920   { 15171 /* v_cmp_lt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74089   { 15621 /* v_cmp_neq_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74093   { 15621 /* v_cmp_neq_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74096   { 15621 /* v_cmp_neq_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74137   { 15717 /* v_cmp_nge_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74141   { 15717 /* v_cmp_nge_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74144   { 15717 /* v_cmp_nge_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74185   { 15813 /* v_cmp_ngt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74189   { 15813 /* v_cmp_ngt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74192   { 15813 /* v_cmp_ngt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74233   { 15909 /* v_cmp_nle_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74237   { 15909 /* v_cmp_nle_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74240   { 15909 /* v_cmp_nle_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74281   { 16005 /* v_cmp_nlg_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74285   { 16005 /* v_cmp_nlg_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74288   { 16005 /* v_cmp_nlg_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74329   { 16101 /* v_cmp_nlt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74333   { 16101 /* v_cmp_nlt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74336   { 16101 /* v_cmp_nlt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74377   { 16197 /* v_cmp_o_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74381   { 16197 /* v_cmp_o_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74384   { 16197 /* v_cmp_o_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74479   { 16449 /* v_cmp_tru_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74483   { 16449 /* v_cmp_tru_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74486   { 16449 /* v_cmp_tru_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74527   { 16545 /* v_cmp_u_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74531   { 16545 /* v_cmp_u_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74534   { 16545 /* v_cmp_u_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74763   { 18773 /* v_cmpx_class_f16 */, 1 /* 0 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74768   { 18773 /* v_cmpx_class_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74772   { 18773 /* v_cmpx_class_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74806   { 18887 /* v_cmpx_eq_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74810   { 18887 /* v_cmpx_eq_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74813   { 18887 /* v_cmpx_eq_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74903   { 19175 /* v_cmpx_f_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74907   { 19175 /* v_cmpx_f_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
74910   { 19175 /* v_cmpx_f_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74994   { 19445 /* v_cmpx_ge_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
74998   { 19445 /* v_cmpx_ge_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75001   { 19445 /* v_cmpx_ge_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75091   { 19733 /* v_cmpx_gt_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75095   { 19733 /* v_cmpx_gt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75098   { 19733 /* v_cmpx_gt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75188   { 20021 /* v_cmpx_le_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75192   { 20021 /* v_cmpx_le_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75195   { 20021 /* v_cmpx_le_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75285   { 20309 /* v_cmpx_lg_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75289   { 20309 /* v_cmpx_lg_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75292   { 20309 /* v_cmpx_lg_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75328   { 20405 /* v_cmpx_lt_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75332   { 20405 /* v_cmpx_lt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75335   { 20405 /* v_cmpx_lt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75479   { 20885 /* v_cmpx_neq_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75483   { 20885 /* v_cmpx_neq_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75486   { 20885 /* v_cmpx_neq_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75522   { 20987 /* v_cmpx_nge_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75526   { 20987 /* v_cmpx_nge_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75529   { 20987 /* v_cmpx_nge_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75565   { 21089 /* v_cmpx_ngt_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75569   { 21089 /* v_cmpx_ngt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75572   { 21089 /* v_cmpx_ngt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75608   { 21191 /* v_cmpx_nle_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75612   { 21191 /* v_cmpx_nle_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75615   { 21191 /* v_cmpx_nle_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75651   { 21293 /* v_cmpx_nlg_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75655   { 21293 /* v_cmpx_nlg_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75658   { 21293 /* v_cmpx_nlg_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75694   { 21395 /* v_cmpx_nlt_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75698   { 21395 /* v_cmpx_nlt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75701   { 21395 /* v_cmpx_nlt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75737   { 21497 /* v_cmpx_o_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75741   { 21497 /* v_cmpx_o_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75744   { 21497 /* v_cmpx_o_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75828   { 21767 /* v_cmpx_tru_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75832   { 21767 /* v_cmpx_tru_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75835   { 21767 /* v_cmpx_tru_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75871   { 21869 /* v_cmpx_u_f16 */, 3 /* 0, 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75875   { 21869 /* v_cmpx_u_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
75878   { 21869 /* v_cmpx_u_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75978   { 21973 /* v_cos_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75988   { 21973 /* v_cos_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
75994   { 21973 /* v_cos_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76195   { 22087 /* v_cvt_f32_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA_HasSDWA },
76205   { 22087 /* v_cvt_f32_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76211   { 22087 /* v_cvt_f32_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76497   { 22271 /* v_cvt_i16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
76502   { 22271 /* v_cvt_i16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76507   { 22271 /* v_cvt_i16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76569   { 22313 /* v_cvt_norm_i16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_isGFX9Plus_HasSDWA },
76574   { 22313 /* v_cvt_norm_i16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76579   { 22313 /* v_cvt_norm_i16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76601   { 22332 /* v_cvt_norm_u16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_isGFX9Plus_HasSDWA },
76606   { 22332 /* v_cvt_norm_u16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76611   { 22332 /* v_cvt_norm_u16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76749   { 22561 /* v_cvt_u16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
76754   { 22561 /* v_cvt_u16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76759   { 22561 /* v_cvt_u16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
76983   { 22899 /* v_exp_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
76993   { 22899 /* v_exp_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
76999   { 22899 /* v_exp_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77158   { 22969 /* v_floor_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
77168   { 22969 /* v_floor_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77174   { 22969 /* v_floor_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77336   { 23168 /* v_fract_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
77346   { 23168 /* v_fract_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77352   { 23168 /* v_fract_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77418   { 23204 /* v_frexp_exp_i16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
77423   { 23204 /* v_frexp_exp_i16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77428   { 23204 /* v_frexp_exp_i16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77492   { 23264 /* v_frexp_mant_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
77502   { 23264 /* v_frexp_mant_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77508   { 23264 /* v_frexp_mant_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77661   { 23439 /* v_ldexp_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
77675   { 23439 /* v_ldexp_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77683   { 23439 /* v_ldexp_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77726   { 23501 /* v_log_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
77736   { 23501 /* v_log_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
77742   { 23501 /* v_log_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
77913   { 23695 /* v_mac_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
78089   { 24084 /* v_max_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
78101   { 24084 /* v_max_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78108   { 24084 /* v_max_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78378   { 24775 /* v_min_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
78390   { 24775 /* v_min_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78397   { 24775 /* v_min_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
78622   { 24989 /* v_mul_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
78634   { 24989 /* v_mul_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
78641   { 24989 /* v_mul_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79149   { 25609 /* v_rcp_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
79159   { 25609 /* v_rcp_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79165   { 25609 /* v_rcp_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79275   { 25707 /* v_rndne_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
79285   { 25707 /* v_rndne_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79291   { 25707 /* v_rndne_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79365   { 25775 /* v_rsq_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
79375   { 25775 /* v_rsq_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79381   { 25775 /* v_rsq_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79499   { 25906 /* v_sin_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
79509   { 25906 /* v_sin_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79515   { 25906 /* v_sin_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79574   { 25926 /* v_sqrt_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
79584   { 25926 /* v_sqrt_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79590   { 25926 /* v_sqrt_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79718   { 25988 /* v_sub_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
79730   { 25988 /* v_sub_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79737   { 25988 /* v_sub_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
79965   { 26191 /* v_subrev_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
79977   { 26191 /* v_subrev_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
79984   { 26191 /* v_subrev_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
80108   { 26314 /* v_trunc_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
80118   { 26314 /* v_trunc_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA10_isGFX10Plus },
80124   { 26314 /* v_trunc_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_HasSDWA9_HasSDWA9 },
80259   case MCK_SDWAWithFP16InputMods: