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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 6295 case MCK_S16Imm: {
10184 case MCK_S16Imm: return "MCK_S16Imm";
17556 { 7806 /* s_addk_i32 */, AMDGPU::S_ADDK_I32_gfx10, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
17557 { 7806 /* s_addk_i32 */, AMDGPU::S_ADDK_I32_gfx6_gfx7, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
17558 { 7806 /* s_addk_i32 */, AMDGPU::S_ADDK_I32_vi, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18150 { 9800 /* s_clause */, AMDGPU::S_CLAUSE, Convert__S16Imm1_0, AMFBS_isGFX10Plus, { MCK_S16Imm }, },
18157 { 9831 /* s_cmovk_i32 */, AMDGPU::S_CMOVK_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18158 { 9831 /* s_cmovk_i32 */, AMDGPU::S_CMOVK_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18159 { 9831 /* s_cmovk_i32 */, AMDGPU::S_CMOVK_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18174 { 10025 /* s_cmpk_eq_i32 */, AMDGPU::S_CMPK_EQ_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18175 { 10025 /* s_cmpk_eq_i32 */, AMDGPU::S_CMPK_EQ_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18176 { 10025 /* s_cmpk_eq_i32 */, AMDGPU::S_CMPK_EQ_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18180 { 10053 /* s_cmpk_ge_i32 */, AMDGPU::S_CMPK_GE_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18181 { 10053 /* s_cmpk_ge_i32 */, AMDGPU::S_CMPK_GE_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18182 { 10053 /* s_cmpk_ge_i32 */, AMDGPU::S_CMPK_GE_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18186 { 10081 /* s_cmpk_gt_i32 */, AMDGPU::S_CMPK_GT_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18187 { 10081 /* s_cmpk_gt_i32 */, AMDGPU::S_CMPK_GT_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18188 { 10081 /* s_cmpk_gt_i32 */, AMDGPU::S_CMPK_GT_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18192 { 10109 /* s_cmpk_le_i32 */, AMDGPU::S_CMPK_LE_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18193 { 10109 /* s_cmpk_le_i32 */, AMDGPU::S_CMPK_LE_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18194 { 10109 /* s_cmpk_le_i32 */, AMDGPU::S_CMPK_LE_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18198 { 10137 /* s_cmpk_lg_i32 */, AMDGPU::S_CMPK_LG_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18199 { 10137 /* s_cmpk_lg_i32 */, AMDGPU::S_CMPK_LG_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18200 { 10137 /* s_cmpk_lg_i32 */, AMDGPU::S_CMPK_LG_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18204 { 10165 /* s_cmpk_lt_i32 */, AMDGPU::S_CMPK_LT_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18205 { 10165 /* s_cmpk_lt_i32 */, AMDGPU::S_CMPK_LT_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18206 { 10165 /* s_cmpk_lt_i32 */, AMDGPU::S_CMPK_LT_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18272 { 10610 /* s_inst_prefetch */, AMDGPU::S_INST_PREFETCH, Convert__S16Imm1_0, AMFBS_isGFX10Plus, { MCK_S16Imm }, },
18356 { 10922 /* s_movk_i32 */, AMDGPU::S_MOVK_I32_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18357 { 10922 /* s_movk_i32 */, AMDGPU::S_MOVK_I32_gfx6_gfx7, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18358 { 10922 /* s_movk_i32 */, AMDGPU::S_MOVK_I32_vi, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18379 { 11042 /* s_mulk_i32 */, AMDGPU::S_MULK_I32_gfx10, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, AMFBS_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18380 { 11042 /* s_mulk_i32 */, AMDGPU::S_MULK_I32_gfx6_gfx7, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, AMFBS_isGFX6GFX7, { MCK_SReg_32, MCK_S16Imm }, },
18381 { 11042 /* s_mulk_i32 */, AMDGPU::S_MULK_I32_vi, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, AMFBS_isGFX8GFX9, { MCK_SReg_32, MCK_S16Imm }, },
18448 { 11467 /* s_round_mode */, AMDGPU::S_ROUND_MODE, Convert__S16Imm1_0, AMFBS_isGFX10Plus, { MCK_S16Imm }, },
18527 { 11989 /* s_ttracedata_imm */, AMDGPU::S_TTRACEDATA_IMM, Convert__S16Imm1_0, AMFBS_isGFX10Plus, { MCK_S16Imm }, },
18528 { 12006 /* s_version */, AMDGPU::S_VERSION_gfx10, Convert__S16Imm1_0, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_S16Imm }, },
18531 { 12038 /* s_waitcnt_depctr */, AMDGPU::S_WAITCNT_DEPCTR, Convert__S16Imm1_0, AMFBS_isGFX10Plus, { MCK_S16Imm }, },
18532 { 12055 /* s_waitcnt_expcnt */, AMDGPU::S_WAITCNT_EXPCNT_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18533 { 12072 /* s_waitcnt_lgkmcnt */, AMDGPU::S_WAITCNT_LGKMCNT_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18534 { 12090 /* s_waitcnt_vmcnt */, AMDGPU::S_WAITCNT_VMCNT_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },
18535 { 12106 /* s_waitcnt_vscnt */, AMDGPU::S_WAITCNT_VSCNT_gfx10, Convert__Reg1_0__S16Imm1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_SReg_32, MCK_S16Imm }, },