reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
5413 case MCK_RegOrImmWithInt32InputMods: { 10058 case MCK_RegOrImmWithInt32InputMods: return "MCK_RegOrImmWithInt32InputMods"; 22195 { 22402 /* v_cvt_pk_u8_f32 */, AMDGPU::V_CVT_PK_U8_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, }, 22195 { 22402 /* v_cvt_pk_u8_f32 */, AMDGPU::V_CVT_PK_U8_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, }, 22196 { 22402 /* v_cvt_pk_u8_f32 */, AMDGPU::V_CVT_PK_U8_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, }, 22196 { 22402 /* v_cvt_pk_u8_f32 */, AMDGPU::V_CVT_PK_U8_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, }, 22197 { 22402 /* v_cvt_pk_u8_f32 */, AMDGPU::V_CVT_PK_U8_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, }, 22197 { 22402 /* v_cvt_pk_u8_f32 */, AMDGPU::V_CVT_PK_U8_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, }, 22199 { 22418 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, }, 22200 { 22418 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, }, 22345 { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, }, 22346 { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, }, 22348 { 23451 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, }, 22349 { 23451 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, }, 22350 { 23451 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, }, 22351 { 23463 /* v_ldexp_f64 */, AMDGPU::V_LDEXP_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, }, 22352 { 23463 /* v_ldexp_f64 */, AMDGPU::V_LDEXP_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, }, 22353 { 23463 /* v_ldexp_f64 */, AMDGPU::V_LDEXP_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, }, 22771 { 26297 /* v_trig_preop_f64 */, AMDGPU::V_TRIG_PREOP_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, }, 22772 { 26297 /* v_trig_preop_f64 */, AMDGPU::V_TRIG_PREOP_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, }, 22773 { 26297 /* v_trig_preop_f64 */, AMDGPU::V_TRIG_PREOP_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, }, 76662 { 22402 /* v_cvt_pk_u8_f32 */, 12 /* 2, 3 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX10Plus }, 76665 { 22402 /* v_cvt_pk_u8_f32 */, 12 /* 2, 3 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX6GFX7 }, 76668 { 22402 /* v_cvt_pk_u8_f32 */, 12 /* 2, 3 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX8GFX9 }, 76671 { 22418 /* v_cvt_pkaccum_u8_f32 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX6GFX7 }, 76674 { 22418 /* v_cvt_pkaccum_u8_f32 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX8GFX9 }, 77648 { 23439 /* v_ldexp_f16 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_Has16BitInsts_isGFX10Plus }, 77652 { 23439 /* v_ldexp_f16 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_Has16BitInsts_isGFX8GFX9 }, 77692 { 23451 /* v_ldexp_f32 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX10Plus }, 77696 { 23451 /* v_ldexp_f32 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX6GFX7 }, 77700 { 23451 /* v_ldexp_f32 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX8GFX9 }, 77704 { 23463 /* v_ldexp_f64 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX10Plus }, 77708 { 23463 /* v_ldexp_f64 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX6GFX7 }, 77712 { 23463 /* v_ldexp_f64 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX8GFX9 }, 80089 { 26297 /* v_trig_preop_f64 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX10Plus }, 80093 { 26297 /* v_trig_preop_f64 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX6GFX7 }, 80097 { 26297 /* v_trig_preop_f64 */, 4 /* 2 */, MCK_RegOrImmWithInt32InputMods, AMFBS_isGFX8GFX9 }, 80273 case MCK_RegOrImmWithInt32InputMods: