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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 5225 case MCK_ImmSWZ:
6085 case MCK_ImmSWZ: {
10154 case MCK_ImmSWZ: return "MCK_ImmSWZ";
11871 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11872 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11873 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11874 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11875 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11876 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11877 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11878 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11879 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11880 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11881 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11882 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11883 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11884 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11885 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11886 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11887 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11888 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11889 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11890 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11891 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11892 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11893 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11894 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11895 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11896 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11897 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11898 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11899 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11900 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11901 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11902 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11903 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11904 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11905 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11906 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11907 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11908 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11909 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11910 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11911 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11912 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11913 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11914 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11915 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11916 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11917 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11918 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11919 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11920 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11921 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11922 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11923 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11924 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11925 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11926 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11927 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11928 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11929 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11930 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11931 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11932 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11933 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11934 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11935 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11936 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11937 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11938 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11939 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11940 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11941 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11942 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11943 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11944 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11945 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11946 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11947 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11948 { 809 /* buffer_load_format_d16_hi_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11949 { 809 /* buffer_load_format_d16_hi_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11950 { 809 /* buffer_load_format_d16_hi_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11951 { 809 /* buffer_load_format_d16_hi_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11952 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11953 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11954 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11955 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11956 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11957 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11958 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11959 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11960 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11961 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11962 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11963 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11964 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11965 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11966 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11967 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11968 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11969 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11970 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11971 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11972 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11973 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11974 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11975 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11976 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11977 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11978 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11979 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11980 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11981 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11982 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11983 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11984 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11985 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11986 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11987 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11988 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11989 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11990 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11991 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11992 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11993 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11994 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11995 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11996 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11997 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11998 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11999 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12000 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12001 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12002 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12003 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12004 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12005 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12006 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12007 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12008 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12009 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12010 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12011 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12012 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12013 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12014 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12015 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12016 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12017 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12018 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12019 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12020 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12021 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12022 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12023 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12024 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12025 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12026 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12027 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12028 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12029 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12030 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12031 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12032 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12033 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12034 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12035 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12036 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12037 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12038 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12039 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12040 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12041 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12042 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12043 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12044 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12045 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12046 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12047 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12048 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12049 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12050 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12051 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12052 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12053 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12054 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12055 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12056 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12057 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12058 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12059 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12060 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12061 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12062 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12063 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12064 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12065 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12066 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12067 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12068 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12069 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12070 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12071 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12072 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12073 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12074 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12075 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12076 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12077 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12078 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12079 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12080 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12081 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12082 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12083 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12084 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12085 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12086 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12087 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12088 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12089 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12090 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12091 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12092 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12093 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12094 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12095 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12096 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12097 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12098 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12099 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12100 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12101 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12102 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12103 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12104 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12105 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12106 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12107 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12108 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12109 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12110 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12111 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12112 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12113 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12114 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12115 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12116 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12117 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12118 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12119 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12120 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12121 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12122 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12123 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12124 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12125 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12126 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12127 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12128 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12129 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12130 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12131 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12132 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12133 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12134 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12135 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12136 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12137 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12138 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12139 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12140 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12141 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12142 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12143 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12144 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12145 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12146 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12147 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12148 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12149 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12150 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12151 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12152 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12153 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12154 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12155 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12156 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12157 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12158 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12159 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12160 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12161 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12162 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12163 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12164 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12165 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12166 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12167 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12168 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12169 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12170 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12171 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12172 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12173 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12174 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12175 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12176 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12177 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12178 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12179 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12180 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12181 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12182 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12183 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12184 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12185 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12186 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12187 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12188 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12189 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12190 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12191 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12192 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12193 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12194 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12195 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12196 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12197 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12198 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12199 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12200 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12201 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12202 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12203 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12204 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12205 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12206 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12207 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12208 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12209 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12210 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12211 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12212 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12213 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12214 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12215 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12216 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12217 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12218 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12219 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12220 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12221 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12222 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12223 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12224 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12225 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12226 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12227 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12228 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12229 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12230 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12231 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12232 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12233 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12234 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12235 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12236 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12237 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12238 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12239 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12240 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12241 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12242 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12243 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12244 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12245 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12246 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12247 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12248 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12249 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12250 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12251 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12252 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12253 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12254 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12255 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12256 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12257 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12258 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12259 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12260 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12261 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12262 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12263 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12264 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12265 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12266 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12267 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12268 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12269 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12270 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12271 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12272 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12273 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12274 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12275 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12276 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12277 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12278 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12279 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12280 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12281 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12282 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12283 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12284 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12285 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12286 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12287 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12288 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12289 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12290 { 1373 /* buffer_store_format_d16_hi_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12291 { 1373 /* buffer_store_format_d16_hi_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12292 { 1373 /* buffer_store_format_d16_hi_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12293 { 1373 /* buffer_store_format_d16_hi_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12294 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12295 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12296 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12297 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12298 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12299 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12300 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12301 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12302 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12303 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12304 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12305 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12306 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12307 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12308 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12309 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12310 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12311 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12312 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12313 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12314 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12315 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12316 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12317 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12318 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12319 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12320 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12321 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12322 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12323 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12324 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12325 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12326 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12327 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12328 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12329 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12330 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12331 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12332 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12333 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12334 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12335 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12336 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12337 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12338 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12339 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12340 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12341 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12342 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12343 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12344 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12345 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12346 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12347 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12348 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12349 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12350 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12351 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12352 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12353 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12354 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12355 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12356 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12357 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12358 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12359 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12360 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12361 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12362 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12363 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12364 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12365 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12366 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12367 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12368 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12369 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12370 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12371 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12372 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12373 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12374 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12375 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12376 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12377 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12378 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12379 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12380 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12381 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12382 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12383 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12384 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12385 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12386 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12387 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12388 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12389 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12390 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12391 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12392 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12393 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12394 { 1606 /* buffer_store_lds_dword */, AMDGPU::BUFFER_STORE_LDS_DWORD_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_lds, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmSWZ }, },
12395 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12396 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12397 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12398 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12399 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12400 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12401 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12402 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12403 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12404 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12405 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12406 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12407 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12408 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12409 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12410 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12411 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12412 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12413 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12414 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12415 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18651 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18652 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18653 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18654 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18655 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18656 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18657 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18658 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18659 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18660 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18661 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18662 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18663 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18664 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18665 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18666 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18667 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18668 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18669 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18670 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18671 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18672 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18673 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18674 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18675 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18676 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18677 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18678 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18679 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18680 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18681 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18682 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18683 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18684 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18685 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18686 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18687 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18688 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18689 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18690 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18691 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18692 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18693 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18694 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18695 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18696 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18697 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18698 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18699 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18700 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18701 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18702 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18703 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18704 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18705 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18706 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18707 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18708 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18709 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18710 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18711 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18712 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18713 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18714 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18715 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18716 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18717 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18718 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18719 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18720 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18721 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18722 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18723 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18724 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18725 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18726 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18727 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18728 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18729 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18730 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18731 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18732 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18733 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18734 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18735 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18736 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18737 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18738 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18739 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18740 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18741 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18742 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18743 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18744 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18745 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18746 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18747 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18748 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18749 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18750 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18751 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18752 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18753 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18754 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18755 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18756 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18757 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18758 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18759 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18760 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18761 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18762 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18763 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18764 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18765 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18766 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18767 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18768 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18769 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18770 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18771 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18772 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18773 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18774 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18775 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18776 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18777 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18778 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18779 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18780 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18781 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18782 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18783 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18784 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18785 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18786 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18787 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18788 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18789 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18790 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18791 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18792 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18793 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18794 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18795 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18796 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18797 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18798 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18799 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18800 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18801 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18802 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18803 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18804 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18805 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18806 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18807 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18808 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18809 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18810 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18811 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18812 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18813 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18814 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18815 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18816 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18817 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18818 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18819 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18820 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18821 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18822 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18823 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18824 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18825 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18826 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18827 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18828 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18829 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18830 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18831 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18832 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18833 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18834 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18835 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18836 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18837 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18838 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18839 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18840 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18841 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18842 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18843 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18844 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18845 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18846 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18847 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18848 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18849 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18850 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
25745 { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25750 { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25755 { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25761 { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25767 { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25773 { 731 /* buffer_load_dword */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25778 { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25784 { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25789 { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25794 { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25799 { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25805 { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25811 { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25817 { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25822 { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25827 { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25832 { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25838 { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25844 { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25850 { 731 /* buffer_load_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25855 { 731 /* buffer_load_dword */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25860 { 731 /* buffer_load_dword */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25865 { 731 /* buffer_load_dword */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25871 { 731 /* buffer_load_dword */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25877 { 731 /* buffer_load_dword */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25883 { 731 /* buffer_load_dword */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25888 { 749 /* buffer_load_dwordx2 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9_isGFX8GFX9 },
25894 { 749 /* buffer_load_dwordx2 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25900 { 749 /* buffer_load_dwordx2 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25906 { 749 /* buffer_load_dwordx2 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25912 { 749 /* buffer_load_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25917 { 749 /* buffer_load_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9_isGFX8GFX9 },
25923 { 749 /* buffer_load_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25929 { 749 /* buffer_load_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25935 { 749 /* buffer_load_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25940 { 749 /* buffer_load_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9_isGFX8GFX9 },
25946 { 749 /* buffer_load_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25952 { 749 /* buffer_load_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25958 { 749 /* buffer_load_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25963 { 749 /* buffer_load_dwordx2 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9_isGFX8GFX9 },
25969 { 749 /* buffer_load_dwordx2 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25975 { 749 /* buffer_load_dwordx2 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
25981 { 749 /* buffer_load_dwordx2 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
25986 { 769 /* buffer_load_dwordx3 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9_isGFX8GFX9 },
25992 { 769 /* buffer_load_dwordx3 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
25998 { 769 /* buffer_load_dwordx3 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26004 { 769 /* buffer_load_dwordx3 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26010 { 769 /* buffer_load_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26015 { 769 /* buffer_load_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26021 { 769 /* buffer_load_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26027 { 769 /* buffer_load_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26033 { 769 /* buffer_load_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26038 { 769 /* buffer_load_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26044 { 769 /* buffer_load_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26050 { 769 /* buffer_load_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26056 { 769 /* buffer_load_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26061 { 769 /* buffer_load_dwordx3 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26067 { 769 /* buffer_load_dwordx3 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26073 { 769 /* buffer_load_dwordx3 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26079 { 769 /* buffer_load_dwordx3 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26084 { 789 /* buffer_load_dwordx4 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26090 { 789 /* buffer_load_dwordx4 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26096 { 789 /* buffer_load_dwordx4 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26102 { 789 /* buffer_load_dwordx4 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26108 { 789 /* buffer_load_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26113 { 789 /* buffer_load_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26119 { 789 /* buffer_load_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26125 { 789 /* buffer_load_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26131 { 789 /* buffer_load_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26136 { 789 /* buffer_load_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26142 { 789 /* buffer_load_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26148 { 789 /* buffer_load_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26154 { 789 /* buffer_load_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26159 { 789 /* buffer_load_dwordx4 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26165 { 789 /* buffer_load_dwordx4 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26171 { 789 /* buffer_load_dwordx4 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26177 { 789 /* buffer_load_dwordx4 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26183 { 809 /* buffer_load_format_d16_hi_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
26189 { 809 /* buffer_load_format_d16_hi_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
26195 { 809 /* buffer_load_format_d16_hi_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
26201 { 809 /* buffer_load_format_d16_hi_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
26207 { 837 /* buffer_load_format_d16_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
26213 { 837 /* buffer_load_format_d16_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26219 { 837 /* buffer_load_format_d16_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26225 { 837 /* buffer_load_format_d16_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
26231 { 837 /* buffer_load_format_d16_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26237 { 837 /* buffer_load_format_d16_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26243 { 837 /* buffer_load_format_d16_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
26249 { 837 /* buffer_load_format_d16_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26255 { 837 /* buffer_load_format_d16_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26261 { 837 /* buffer_load_format_d16_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
26267 { 837 /* buffer_load_format_d16_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26273 { 837 /* buffer_load_format_d16_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26279 { 862 /* buffer_load_format_d16_xy */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26285 { 862 /* buffer_load_format_d16_xy */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
26291 { 862 /* buffer_load_format_d16_xy */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26297 { 862 /* buffer_load_format_d16_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26303 { 862 /* buffer_load_format_d16_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26309 { 862 /* buffer_load_format_d16_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
26315 { 862 /* buffer_load_format_d16_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26321 { 862 /* buffer_load_format_d16_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
26327 { 862 /* buffer_load_format_d16_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26333 { 862 /* buffer_load_format_d16_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26339 { 862 /* buffer_load_format_d16_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
26345 { 862 /* buffer_load_format_d16_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26351 { 888 /* buffer_load_format_d16_xyz */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26357 { 888 /* buffer_load_format_d16_xyz */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
26363 { 888 /* buffer_load_format_d16_xyz */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26369 { 888 /* buffer_load_format_d16_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26375 { 888 /* buffer_load_format_d16_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26381 { 888 /* buffer_load_format_d16_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
26387 { 888 /* buffer_load_format_d16_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26393 { 888 /* buffer_load_format_d16_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
26399 { 888 /* buffer_load_format_d16_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26405 { 888 /* buffer_load_format_d16_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26411 { 888 /* buffer_load_format_d16_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
26417 { 888 /* buffer_load_format_d16_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26423 { 915 /* buffer_load_format_d16_xyzw */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26429 { 915 /* buffer_load_format_d16_xyzw */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
26435 { 915 /* buffer_load_format_d16_xyzw */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26441 { 915 /* buffer_load_format_d16_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26447 { 915 /* buffer_load_format_d16_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26453 { 915 /* buffer_load_format_d16_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
26459 { 915 /* buffer_load_format_d16_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26465 { 915 /* buffer_load_format_d16_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
26471 { 915 /* buffer_load_format_d16_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26477 { 915 /* buffer_load_format_d16_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26483 { 915 /* buffer_load_format_d16_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
26489 { 915 /* buffer_load_format_d16_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26494 { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26499 { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26504 { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26510 { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26516 { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26522 { 943 /* buffer_load_format_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26527 { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26533 { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26538 { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26543 { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26548 { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26554 { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26560 { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26566 { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26571 { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26576 { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26581 { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26587 { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26593 { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26599 { 943 /* buffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26604 { 943 /* buffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26609 { 943 /* buffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26614 { 943 /* buffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26620 { 943 /* buffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26626 { 943 /* buffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26632 { 943 /* buffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26638 { 964 /* buffer_load_format_xy */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26644 { 964 /* buffer_load_format_xy */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26650 { 964 /* buffer_load_format_xy */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26656 { 964 /* buffer_load_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26662 { 964 /* buffer_load_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26668 { 964 /* buffer_load_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26674 { 964 /* buffer_load_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26680 { 964 /* buffer_load_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26686 { 964 /* buffer_load_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26692 { 964 /* buffer_load_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26698 { 964 /* buffer_load_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26704 { 964 /* buffer_load_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26710 { 964 /* buffer_load_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26716 { 986 /* buffer_load_format_xyz */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26722 { 986 /* buffer_load_format_xyz */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26728 { 986 /* buffer_load_format_xyz */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26734 { 986 /* buffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26740 { 986 /* buffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26746 { 986 /* buffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26752 { 986 /* buffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26758 { 986 /* buffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26764 { 986 /* buffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26770 { 986 /* buffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26776 { 986 /* buffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26782 { 986 /* buffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26788 { 986 /* buffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26794 { 1009 /* buffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26800 { 1009 /* buffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26806 { 1009 /* buffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26812 { 1009 /* buffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26818 { 1009 /* buffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26824 { 1009 /* buffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26830 { 1009 /* buffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26836 { 1009 /* buffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26842 { 1009 /* buffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26848 { 1009 /* buffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26854 { 1009 /* buffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26860 { 1009 /* buffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26866 { 1009 /* buffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26871 { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26876 { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26881 { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26887 { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26893 { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26899 { 1033 /* buffer_load_sbyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26904 { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26910 { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26915 { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26920 { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26925 { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26931 { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26937 { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26943 { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26948 { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26953 { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26958 { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26964 { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26970 { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26976 { 1033 /* buffer_load_sbyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26981 { 1033 /* buffer_load_sbyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
26986 { 1033 /* buffer_load_sbyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
26991 { 1033 /* buffer_load_sbyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
26997 { 1033 /* buffer_load_sbyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27003 { 1033 /* buffer_load_sbyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27009 { 1033 /* buffer_load_sbyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27015 { 1051 /* buffer_load_sbyte_d16 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27021 { 1051 /* buffer_load_sbyte_d16 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27027 { 1051 /* buffer_load_sbyte_d16 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27033 { 1051 /* buffer_load_sbyte_d16 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27039 { 1051 /* buffer_load_sbyte_d16 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27045 { 1051 /* buffer_load_sbyte_d16 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27051 { 1051 /* buffer_load_sbyte_d16 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27057 { 1051 /* buffer_load_sbyte_d16 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27063 { 1073 /* buffer_load_sbyte_d16_hi */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27069 { 1073 /* buffer_load_sbyte_d16_hi */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27075 { 1073 /* buffer_load_sbyte_d16_hi */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27081 { 1073 /* buffer_load_sbyte_d16_hi */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27087 { 1073 /* buffer_load_sbyte_d16_hi */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27093 { 1073 /* buffer_load_sbyte_d16_hi */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27099 { 1073 /* buffer_load_sbyte_d16_hi */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27105 { 1073 /* buffer_load_sbyte_d16_hi */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27111 { 1098 /* buffer_load_short_d16 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27117 { 1098 /* buffer_load_short_d16 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27123 { 1098 /* buffer_load_short_d16 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27129 { 1098 /* buffer_load_short_d16 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27135 { 1098 /* buffer_load_short_d16 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27141 { 1098 /* buffer_load_short_d16 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27147 { 1098 /* buffer_load_short_d16 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27153 { 1098 /* buffer_load_short_d16 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27159 { 1120 /* buffer_load_short_d16_hi */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27165 { 1120 /* buffer_load_short_d16_hi */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27171 { 1120 /* buffer_load_short_d16_hi */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27177 { 1120 /* buffer_load_short_d16_hi */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27183 { 1120 /* buffer_load_short_d16_hi */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27189 { 1120 /* buffer_load_short_d16_hi */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27195 { 1120 /* buffer_load_short_d16_hi */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27201 { 1120 /* buffer_load_short_d16_hi */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27206 { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27211 { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27216 { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27222 { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27228 { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27234 { 1145 /* buffer_load_sshort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27239 { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27245 { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27250 { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27255 { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27260 { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27266 { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27272 { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27278 { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27283 { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27288 { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27293 { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27299 { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27305 { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27311 { 1145 /* buffer_load_sshort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27316 { 1145 /* buffer_load_sshort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27321 { 1145 /* buffer_load_sshort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27326 { 1145 /* buffer_load_sshort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27332 { 1145 /* buffer_load_sshort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27338 { 1145 /* buffer_load_sshort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27344 { 1145 /* buffer_load_sshort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27349 { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27354 { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27359 { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27365 { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27371 { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27377 { 1164 /* buffer_load_ubyte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27382 { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27388 { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27393 { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27398 { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27403 { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27409 { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27415 { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27421 { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27426 { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27431 { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27436 { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27442 { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27448 { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27454 { 1164 /* buffer_load_ubyte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27459 { 1164 /* buffer_load_ubyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27464 { 1164 /* buffer_load_ubyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27469 { 1164 /* buffer_load_ubyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27475 { 1164 /* buffer_load_ubyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27481 { 1164 /* buffer_load_ubyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27487 { 1164 /* buffer_load_ubyte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27493 { 1182 /* buffer_load_ubyte_d16 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27499 { 1182 /* buffer_load_ubyte_d16 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27505 { 1182 /* buffer_load_ubyte_d16 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27511 { 1182 /* buffer_load_ubyte_d16 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27517 { 1182 /* buffer_load_ubyte_d16 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27523 { 1182 /* buffer_load_ubyte_d16 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27529 { 1182 /* buffer_load_ubyte_d16 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27535 { 1182 /* buffer_load_ubyte_d16 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27541 { 1204 /* buffer_load_ubyte_d16_hi */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27547 { 1204 /* buffer_load_ubyte_d16_hi */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27553 { 1204 /* buffer_load_ubyte_d16_hi */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27559 { 1204 /* buffer_load_ubyte_d16_hi */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27565 { 1204 /* buffer_load_ubyte_d16_hi */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27571 { 1204 /* buffer_load_ubyte_d16_hi */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27577 { 1204 /* buffer_load_ubyte_d16_hi */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27583 { 1204 /* buffer_load_ubyte_d16_hi */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27588 { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27593 { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27598 { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27604 { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27610 { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27616 { 1229 /* buffer_load_ushort */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27621 { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27627 { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27632 { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27637 { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27642 { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27648 { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27654 { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27660 { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27665 { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27670 { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27675 { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27681 { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27687 { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27693 { 1229 /* buffer_load_ushort */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27698 { 1229 /* buffer_load_ushort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27703 { 1229 /* buffer_load_ushort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27708 { 1229 /* buffer_load_ushort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27714 { 1229 /* buffer_load_ushort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27720 { 1229 /* buffer_load_ushort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27726 { 1229 /* buffer_load_ushort */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27732 { 1248 /* buffer_store_byte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27738 { 1248 /* buffer_store_byte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27744 { 1248 /* buffer_store_byte */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27750 { 1248 /* buffer_store_byte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27756 { 1248 /* buffer_store_byte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27762 { 1248 /* buffer_store_byte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27768 { 1248 /* buffer_store_byte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27774 { 1248 /* buffer_store_byte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27780 { 1248 /* buffer_store_byte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27786 { 1248 /* buffer_store_byte */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27792 { 1248 /* buffer_store_byte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27798 { 1248 /* buffer_store_byte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27804 { 1248 /* buffer_store_byte */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27810 { 1266 /* buffer_store_byte_d16_hi */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27816 { 1266 /* buffer_store_byte_d16_hi */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27822 { 1266 /* buffer_store_byte_d16_hi */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27828 { 1266 /* buffer_store_byte_d16_hi */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27834 { 1266 /* buffer_store_byte_d16_hi */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27840 { 1266 /* buffer_store_byte_d16_hi */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27846 { 1266 /* buffer_store_byte_d16_hi */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
27852 { 1266 /* buffer_store_byte_d16_hi */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27858 { 1291 /* buffer_store_dword */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27864 { 1291 /* buffer_store_dword */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27870 { 1291 /* buffer_store_dword */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27876 { 1291 /* buffer_store_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27882 { 1291 /* buffer_store_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27888 { 1291 /* buffer_store_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27894 { 1291 /* buffer_store_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27900 { 1291 /* buffer_store_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27906 { 1291 /* buffer_store_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27912 { 1291 /* buffer_store_dword */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27918 { 1291 /* buffer_store_dword */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27924 { 1291 /* buffer_store_dword */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27930 { 1291 /* buffer_store_dword */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27936 { 1310 /* buffer_store_dwordx2 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27942 { 1310 /* buffer_store_dwordx2 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27948 { 1310 /* buffer_store_dwordx2 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27954 { 1310 /* buffer_store_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27960 { 1310 /* buffer_store_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27966 { 1310 /* buffer_store_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27972 { 1310 /* buffer_store_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27978 { 1310 /* buffer_store_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
27984 { 1310 /* buffer_store_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
27990 { 1310 /* buffer_store_dwordx2 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
27996 { 1310 /* buffer_store_dwordx2 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28002 { 1310 /* buffer_store_dwordx2 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28008 { 1310 /* buffer_store_dwordx2 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28014 { 1331 /* buffer_store_dwordx3 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28020 { 1331 /* buffer_store_dwordx3 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28026 { 1331 /* buffer_store_dwordx3 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28032 { 1331 /* buffer_store_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28038 { 1331 /* buffer_store_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28044 { 1331 /* buffer_store_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28050 { 1331 /* buffer_store_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28056 { 1331 /* buffer_store_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28062 { 1331 /* buffer_store_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28068 { 1331 /* buffer_store_dwordx3 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28074 { 1331 /* buffer_store_dwordx3 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28080 { 1331 /* buffer_store_dwordx3 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28086 { 1331 /* buffer_store_dwordx3 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28092 { 1352 /* buffer_store_dwordx4 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28098 { 1352 /* buffer_store_dwordx4 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28104 { 1352 /* buffer_store_dwordx4 */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28110 { 1352 /* buffer_store_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28116 { 1352 /* buffer_store_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28122 { 1352 /* buffer_store_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28128 { 1352 /* buffer_store_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28134 { 1352 /* buffer_store_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28140 { 1352 /* buffer_store_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28146 { 1352 /* buffer_store_dwordx4 */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28152 { 1352 /* buffer_store_dwordx4 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28158 { 1352 /* buffer_store_dwordx4 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28164 { 1352 /* buffer_store_dwordx4 */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28170 { 1373 /* buffer_store_format_d16_hi_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28176 { 1373 /* buffer_store_format_d16_hi_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28182 { 1373 /* buffer_store_format_d16_hi_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28188 { 1373 /* buffer_store_format_d16_hi_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28194 { 1402 /* buffer_store_format_d16_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
28200 { 1402 /* buffer_store_format_d16_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28206 { 1402 /* buffer_store_format_d16_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28212 { 1402 /* buffer_store_format_d16_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
28218 { 1402 /* buffer_store_format_d16_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28224 { 1402 /* buffer_store_format_d16_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28230 { 1402 /* buffer_store_format_d16_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
28236 { 1402 /* buffer_store_format_d16_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28242 { 1402 /* buffer_store_format_d16_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28248 { 1402 /* buffer_store_format_d16_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
28254 { 1402 /* buffer_store_format_d16_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28260 { 1402 /* buffer_store_format_d16_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28266 { 1428 /* buffer_store_format_d16_xy */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28272 { 1428 /* buffer_store_format_d16_xy */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
28278 { 1428 /* buffer_store_format_d16_xy */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28284 { 1428 /* buffer_store_format_d16_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28290 { 1428 /* buffer_store_format_d16_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28296 { 1428 /* buffer_store_format_d16_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
28302 { 1428 /* buffer_store_format_d16_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28308 { 1428 /* buffer_store_format_d16_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
28314 { 1428 /* buffer_store_format_d16_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28320 { 1428 /* buffer_store_format_d16_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28326 { 1428 /* buffer_store_format_d16_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
28332 { 1428 /* buffer_store_format_d16_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28338 { 1455 /* buffer_store_format_d16_xyz */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28344 { 1455 /* buffer_store_format_d16_xyz */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
28350 { 1455 /* buffer_store_format_d16_xyz */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28356 { 1455 /* buffer_store_format_d16_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28362 { 1455 /* buffer_store_format_d16_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28368 { 1455 /* buffer_store_format_d16_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
28374 { 1455 /* buffer_store_format_d16_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28380 { 1455 /* buffer_store_format_d16_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
28386 { 1455 /* buffer_store_format_d16_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28392 { 1455 /* buffer_store_format_d16_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28398 { 1455 /* buffer_store_format_d16_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
28404 { 1455 /* buffer_store_format_d16_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28410 { 1483 /* buffer_store_format_d16_xyzw */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28416 { 1483 /* buffer_store_format_d16_xyzw */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
28422 { 1483 /* buffer_store_format_d16_xyzw */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28428 { 1483 /* buffer_store_format_d16_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28434 { 1483 /* buffer_store_format_d16_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28440 { 1483 /* buffer_store_format_d16_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
28446 { 1483 /* buffer_store_format_d16_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28452 { 1483 /* buffer_store_format_d16_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
28458 { 1483 /* buffer_store_format_d16_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28464 { 1483 /* buffer_store_format_d16_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28470 { 1483 /* buffer_store_format_d16_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
28476 { 1483 /* buffer_store_format_d16_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28482 { 1512 /* buffer_store_format_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28488 { 1512 /* buffer_store_format_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28494 { 1512 /* buffer_store_format_x */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28500 { 1512 /* buffer_store_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28506 { 1512 /* buffer_store_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28512 { 1512 /* buffer_store_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28518 { 1512 /* buffer_store_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28524 { 1512 /* buffer_store_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28530 { 1512 /* buffer_store_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28536 { 1512 /* buffer_store_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28542 { 1512 /* buffer_store_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28548 { 1512 /* buffer_store_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28554 { 1512 /* buffer_store_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28560 { 1534 /* buffer_store_format_xy */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28566 { 1534 /* buffer_store_format_xy */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28572 { 1534 /* buffer_store_format_xy */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28578 { 1534 /* buffer_store_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28584 { 1534 /* buffer_store_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28590 { 1534 /* buffer_store_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28596 { 1534 /* buffer_store_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28602 { 1534 /* buffer_store_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28608 { 1534 /* buffer_store_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28614 { 1534 /* buffer_store_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28620 { 1534 /* buffer_store_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28626 { 1534 /* buffer_store_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28632 { 1534 /* buffer_store_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28638 { 1557 /* buffer_store_format_xyz */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28644 { 1557 /* buffer_store_format_xyz */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28650 { 1557 /* buffer_store_format_xyz */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28656 { 1557 /* buffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28662 { 1557 /* buffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28668 { 1557 /* buffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28674 { 1557 /* buffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28680 { 1557 /* buffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28686 { 1557 /* buffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28692 { 1557 /* buffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28698 { 1557 /* buffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28704 { 1557 /* buffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28710 { 1557 /* buffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28716 { 1581 /* buffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28722 { 1581 /* buffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28728 { 1581 /* buffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28734 { 1581 /* buffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28740 { 1581 /* buffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28746 { 1581 /* buffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28752 { 1581 /* buffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28758 { 1581 /* buffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28764 { 1581 /* buffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28770 { 1581 /* buffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28776 { 1581 /* buffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28782 { 1581 /* buffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28788 { 1581 /* buffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28792 { 1606 /* buffer_store_lds_dword */, 64 /* 6 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9_isGFX8GFX9 },
28798 { 1629 /* buffer_store_short */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28804 { 1629 /* buffer_store_short */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28810 { 1629 /* buffer_store_short */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28816 { 1629 /* buffer_store_short */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28822 { 1629 /* buffer_store_short */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28828 { 1629 /* buffer_store_short */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28834 { 1629 /* buffer_store_short */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28840 { 1629 /* buffer_store_short */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28846 { 1629 /* buffer_store_short */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28852 { 1629 /* buffer_store_short */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28858 { 1629 /* buffer_store_short */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
28864 { 1629 /* buffer_store_short */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
28870 { 1629 /* buffer_store_short */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
28876 { 1648 /* buffer_store_short_d16_hi */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
28882 { 1648 /* buffer_store_short_d16_hi */, 512 /* 9 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28888 { 1648 /* buffer_store_short_d16_hi */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
28894 { 1648 /* buffer_store_short_d16_hi */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28900 { 1648 /* buffer_store_short_d16_hi */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
28906 { 1648 /* buffer_store_short_d16_hi */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28912 { 1648 /* buffer_store_short_d16_hi */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX10Plus },
28918 { 1648 /* buffer_store_short_d16_hi */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasD16LoadStore_isGFX8GFX9 },
71453 { 12756 /* tbuffer_load_format_d16_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
71460 { 12756 /* tbuffer_load_format_d16_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71467 { 12756 /* tbuffer_load_format_d16_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71474 { 12756 /* tbuffer_load_format_d16_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
71481 { 12756 /* tbuffer_load_format_d16_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71488 { 12756 /* tbuffer_load_format_d16_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71495 { 12756 /* tbuffer_load_format_d16_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
71502 { 12756 /* tbuffer_load_format_d16_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71509 { 12756 /* tbuffer_load_format_d16_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71516 { 12756 /* tbuffer_load_format_d16_x */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
71523 { 12756 /* tbuffer_load_format_d16_x */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71530 { 12756 /* tbuffer_load_format_d16_x */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71537 { 12782 /* tbuffer_load_format_d16_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71544 { 12782 /* tbuffer_load_format_d16_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
71551 { 12782 /* tbuffer_load_format_d16_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71558 { 12782 /* tbuffer_load_format_d16_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71565 { 12782 /* tbuffer_load_format_d16_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71572 { 12782 /* tbuffer_load_format_d16_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
71579 { 12782 /* tbuffer_load_format_d16_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71586 { 12782 /* tbuffer_load_format_d16_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
71593 { 12782 /* tbuffer_load_format_d16_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71600 { 12782 /* tbuffer_load_format_d16_xy */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71607 { 12782 /* tbuffer_load_format_d16_xy */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
71614 { 12782 /* tbuffer_load_format_d16_xy */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71621 { 12809 /* tbuffer_load_format_d16_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71628 { 12809 /* tbuffer_load_format_d16_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
71635 { 12809 /* tbuffer_load_format_d16_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71642 { 12809 /* tbuffer_load_format_d16_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71649 { 12809 /* tbuffer_load_format_d16_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71656 { 12809 /* tbuffer_load_format_d16_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
71663 { 12809 /* tbuffer_load_format_d16_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71670 { 12809 /* tbuffer_load_format_d16_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
71677 { 12809 /* tbuffer_load_format_d16_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71684 { 12809 /* tbuffer_load_format_d16_xyz */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71691 { 12809 /* tbuffer_load_format_d16_xyz */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
71698 { 12809 /* tbuffer_load_format_d16_xyz */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71705 { 12837 /* tbuffer_load_format_d16_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71712 { 12837 /* tbuffer_load_format_d16_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
71719 { 12837 /* tbuffer_load_format_d16_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71726 { 12837 /* tbuffer_load_format_d16_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71733 { 12837 /* tbuffer_load_format_d16_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71740 { 12837 /* tbuffer_load_format_d16_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
71747 { 12837 /* tbuffer_load_format_d16_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71754 { 12837 /* tbuffer_load_format_d16_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
71761 { 12837 /* tbuffer_load_format_d16_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71768 { 12837 /* tbuffer_load_format_d16_xyzw */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71775 { 12837 /* tbuffer_load_format_d16_xyzw */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
71782 { 12837 /* tbuffer_load_format_d16_xyzw */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71789 { 12866 /* tbuffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
71796 { 12866 /* tbuffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71803 { 12866 /* tbuffer_load_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
71810 { 12866 /* tbuffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71817 { 12866 /* tbuffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
71824 { 12866 /* tbuffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71831 { 12866 /* tbuffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
71838 { 12866 /* tbuffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
71845 { 12866 /* tbuffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71852 { 12866 /* tbuffer_load_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
71859 { 12866 /* tbuffer_load_format_x */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
71866 { 12866 /* tbuffer_load_format_x */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71873 { 12866 /* tbuffer_load_format_x */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
71880 { 12888 /* tbuffer_load_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
71887 { 12888 /* tbuffer_load_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71894 { 12888 /* tbuffer_load_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
71901 { 12888 /* tbuffer_load_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71908 { 12888 /* tbuffer_load_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
71915 { 12888 /* tbuffer_load_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71922 { 12888 /* tbuffer_load_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
71929 { 12888 /* tbuffer_load_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
71936 { 12888 /* tbuffer_load_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71943 { 12888 /* tbuffer_load_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
71950 { 12888 /* tbuffer_load_format_xy */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
71957 { 12888 /* tbuffer_load_format_xy */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71964 { 12888 /* tbuffer_load_format_xy */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
71971 { 12911 /* tbuffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
71978 { 12911 /* tbuffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71985 { 12911 /* tbuffer_load_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
71992 { 12911 /* tbuffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
71999 { 12911 /* tbuffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72006 { 12911 /* tbuffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72013 { 12911 /* tbuffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72020 { 12911 /* tbuffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72027 { 12911 /* tbuffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72034 { 12911 /* tbuffer_load_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72041 { 12911 /* tbuffer_load_format_xyz */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72048 { 12911 /* tbuffer_load_format_xyz */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72055 { 12911 /* tbuffer_load_format_xyz */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72062 { 12935 /* tbuffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72069 { 12935 /* tbuffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72076 { 12935 /* tbuffer_load_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72083 { 12935 /* tbuffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72090 { 12935 /* tbuffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72097 { 12935 /* tbuffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72104 { 12935 /* tbuffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72111 { 12935 /* tbuffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72118 { 12935 /* tbuffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72125 { 12935 /* tbuffer_load_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72132 { 12935 /* tbuffer_load_format_xyzw */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72139 { 12935 /* tbuffer_load_format_xyzw */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72146 { 12935 /* tbuffer_load_format_xyzw */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72153 { 12960 /* tbuffer_store_format_d16_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
72160 { 12960 /* tbuffer_store_format_d16_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72167 { 12960 /* tbuffer_store_format_d16_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72174 { 12960 /* tbuffer_store_format_d16_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
72181 { 12960 /* tbuffer_store_format_d16_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72188 { 12960 /* tbuffer_store_format_d16_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72195 { 12960 /* tbuffer_store_format_d16_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
72202 { 12960 /* tbuffer_store_format_d16_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72209 { 12960 /* tbuffer_store_format_d16_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72216 { 12960 /* tbuffer_store_format_d16_x */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
72223 { 12960 /* tbuffer_store_format_d16_x */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72230 { 12960 /* tbuffer_store_format_d16_x */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72237 { 12987 /* tbuffer_store_format_d16_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72244 { 12987 /* tbuffer_store_format_d16_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
72251 { 12987 /* tbuffer_store_format_d16_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72258 { 12987 /* tbuffer_store_format_d16_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72265 { 12987 /* tbuffer_store_format_d16_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72272 { 12987 /* tbuffer_store_format_d16_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
72279 { 12987 /* tbuffer_store_format_d16_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72286 { 12987 /* tbuffer_store_format_d16_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
72293 { 12987 /* tbuffer_store_format_d16_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72300 { 12987 /* tbuffer_store_format_d16_xy */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72307 { 12987 /* tbuffer_store_format_d16_xy */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
72314 { 12987 /* tbuffer_store_format_d16_xy */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72321 { 13015 /* tbuffer_store_format_d16_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72328 { 13015 /* tbuffer_store_format_d16_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
72335 { 13015 /* tbuffer_store_format_d16_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72342 { 13015 /* tbuffer_store_format_d16_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72349 { 13015 /* tbuffer_store_format_d16_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72356 { 13015 /* tbuffer_store_format_d16_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
72363 { 13015 /* tbuffer_store_format_d16_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72370 { 13015 /* tbuffer_store_format_d16_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
72377 { 13015 /* tbuffer_store_format_d16_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72384 { 13015 /* tbuffer_store_format_d16_xyz */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72391 { 13015 /* tbuffer_store_format_d16_xyz */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
72398 { 13015 /* tbuffer_store_format_d16_xyz */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72405 { 13044 /* tbuffer_store_format_d16_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72412 { 13044 /* tbuffer_store_format_d16_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
72419 { 13044 /* tbuffer_store_format_d16_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72426 { 13044 /* tbuffer_store_format_d16_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72433 { 13044 /* tbuffer_store_format_d16_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72440 { 13044 /* tbuffer_store_format_d16_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
72447 { 13044 /* tbuffer_store_format_d16_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72454 { 13044 /* tbuffer_store_format_d16_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
72461 { 13044 /* tbuffer_store_format_d16_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72468 { 13044 /* tbuffer_store_format_d16_xyzw */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72475 { 13044 /* tbuffer_store_format_d16_xyzw */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX10Plus },
72482 { 13044 /* tbuffer_store_format_d16_xyzw */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72489 { 13074 /* tbuffer_store_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72496 { 13074 /* tbuffer_store_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72503 { 13074 /* tbuffer_store_format_x */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72510 { 13074 /* tbuffer_store_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72517 { 13074 /* tbuffer_store_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72524 { 13074 /* tbuffer_store_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72531 { 13074 /* tbuffer_store_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72538 { 13074 /* tbuffer_store_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72545 { 13074 /* tbuffer_store_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72552 { 13074 /* tbuffer_store_format_x */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72559 { 13074 /* tbuffer_store_format_x */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72566 { 13074 /* tbuffer_store_format_x */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72573 { 13074 /* tbuffer_store_format_x */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72580 { 13097 /* tbuffer_store_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72587 { 13097 /* tbuffer_store_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72594 { 13097 /* tbuffer_store_format_xy */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72601 { 13097 /* tbuffer_store_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72608 { 13097 /* tbuffer_store_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72615 { 13097 /* tbuffer_store_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72622 { 13097 /* tbuffer_store_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72629 { 13097 /* tbuffer_store_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72636 { 13097 /* tbuffer_store_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72643 { 13097 /* tbuffer_store_format_xy */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72650 { 13097 /* tbuffer_store_format_xy */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72657 { 13097 /* tbuffer_store_format_xy */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72664 { 13097 /* tbuffer_store_format_xy */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72671 { 13121 /* tbuffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72678 { 13121 /* tbuffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72685 { 13121 /* tbuffer_store_format_xyz */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72692 { 13121 /* tbuffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72699 { 13121 /* tbuffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72706 { 13121 /* tbuffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72713 { 13121 /* tbuffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72720 { 13121 /* tbuffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72727 { 13121 /* tbuffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72734 { 13121 /* tbuffer_store_format_xyz */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72741 { 13121 /* tbuffer_store_format_xyz */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72748 { 13121 /* tbuffer_store_format_xyz */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72755 { 13121 /* tbuffer_store_format_xyz */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72762 { 13146 /* tbuffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72769 { 13146 /* tbuffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72776 { 13146 /* tbuffer_store_format_xyzw */, 1024 /* 10 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72783 { 13146 /* tbuffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72790 { 13146 /* tbuffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72797 { 13146 /* tbuffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72804 { 13146 /* tbuffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72811 { 13146 /* tbuffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72818 { 13146 /* tbuffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72825 { 13146 /* tbuffer_store_format_xyzw */, 2048 /* 11 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
72832 { 13146 /* tbuffer_store_format_xyzw */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX10Plus },
72839 { 13146 /* tbuffer_store_format_xyzw */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX6GFX7 },
72846 { 13146 /* tbuffer_store_format_xyzw */, 4096 /* 12 */, MCK_ImmSWZ, AMFBS_isGFX8GFX9 },
80339 case MCK_ImmSWZ: