reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
5171 case MCK_ImmSMRDOffset8: 5518 case MCK_ImmSMRDOffset8: { 10073 case MCK_ImmSMRDOffset8: return "MCK_ImmSMRDOffset8"; 18078 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, }, 18085 { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_512, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, }, 18092 { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, }, 18099 { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, }, 18106 { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_256, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, }, 18276 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, }, 18283 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_512, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, }, 18290 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, }, 18297 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, }, 18304 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_256, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, }, 70757 { 9380 /* s_buffer_load_dword */, 4 /* 2 */, MCK_ImmSMRDOffset8, AMFBS_isGFX6GFX7 }, 70775 { 9400 /* s_buffer_load_dwordx16 */, 4 /* 2 */, MCK_ImmSMRDOffset8, AMFBS_isGFX6GFX7 }, 70793 { 9423 /* s_buffer_load_dwordx2 */, 4 /* 2 */, MCK_ImmSMRDOffset8, AMFBS_isGFX6GFX7 }, 70811 { 9445 /* s_buffer_load_dwordx4 */, 4 /* 2 */, MCK_ImmSMRDOffset8, AMFBS_isGFX6GFX7 }, 70829 { 9467 /* s_buffer_load_dwordx8 */, 4 /* 2 */, MCK_ImmSMRDOffset8, AMFBS_isGFX6GFX7 }, 70909 { 10626 /* s_load_dword */, 4 /* 2 */, MCK_ImmSMRDOffset8, AMFBS_isGFX6GFX7 }, 70927 { 10639 /* s_load_dwordx16 */, 4 /* 2 */, MCK_ImmSMRDOffset8, AMFBS_isGFX6GFX7 }, 70945 { 10655 /* s_load_dwordx2 */, 4 /* 2 */, MCK_ImmSMRDOffset8, AMFBS_isGFX6GFX7 }, 70963 { 10670 /* s_load_dwordx4 */, 4 /* 2 */, MCK_ImmSMRDOffset8, AMFBS_isGFX6GFX7 }, 70981 { 10685 /* s_load_dwordx8 */, 4 /* 2 */, MCK_ImmSMRDOffset8, AMFBS_isGFX6GFX7 }, 80303 case MCK_ImmSMRDOffset8: