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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 5219 case MCK_ImmSLC:
6071 case MCK_ImmSLC: {
10152 case MCK_ImmSLC: return "MCK_ImmSLC";
11077 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11078 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11079 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11080 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11081 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11082 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11083 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11084 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11085 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11086 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11087 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11088 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11089 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11090 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11091 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11092 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11093 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11094 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11095 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11096 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11097 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11098 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11099 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11100 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11101 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11102 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11103 { 18 /* buffer_atomic_add_f32 */, AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11104 { 18 /* buffer_atomic_add_f32 */, AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11105 { 18 /* buffer_atomic_add_f32 */, AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11106 { 18 /* buffer_atomic_add_f32 */, AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11107 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11108 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11109 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11110 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11111 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11112 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11113 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11114 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11115 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11116 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11117 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11118 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11119 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11120 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11121 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11122 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11123 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11124 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11125 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11126 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11127 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11128 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11129 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11130 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11131 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11132 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11133 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11134 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11135 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11136 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11137 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11138 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11139 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11140 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11141 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11142 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11143 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11144 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11145 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11146 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11147 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11148 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11149 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11150 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11151 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11152 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11153 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11154 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11155 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11156 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11157 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11158 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11159 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11160 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11161 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11162 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11163 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11164 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11165 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11166 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11167 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11168 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11169 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11170 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11171 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11172 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11173 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11174 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11175 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11176 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11177 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11178 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11179 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11180 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11181 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11182 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11183 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11184 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11185 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11186 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11187 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11188 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11189 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11190 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11191 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11192 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11193 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11194 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11195 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11196 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11197 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11198 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11199 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11200 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11201 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11202 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11203 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11204 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11205 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11206 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11207 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11208 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11209 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11210 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11211 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11212 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11213 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11214 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11215 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11216 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11217 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11218 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11219 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11220 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11221 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11222 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11223 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11224 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11225 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11226 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11227 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11228 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11229 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11230 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11231 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11232 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11233 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11234 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11235 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11236 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11237 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11238 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11239 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11240 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11241 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11242 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11243 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11244 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11245 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11246 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11247 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11248 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11249 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11250 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11251 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11252 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11253 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11254 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11255 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11256 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11257 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11258 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11259 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11260 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11261 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11262 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11263 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11264 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11265 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11266 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11267 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11268 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11269 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11270 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11271 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11272 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11273 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11274 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11275 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11276 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11277 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11278 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11279 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11280 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11281 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11282 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11283 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11284 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11285 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11286 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11287 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11288 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11289 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11290 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11291 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11292 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11293 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11294 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11295 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11296 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11297 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11298 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11299 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11300 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11301 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11302 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11303 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11304 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11305 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11306 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11307 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11308 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11309 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11310 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11311 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11312 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11313 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11314 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11315 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11316 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11317 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11318 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11319 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11320 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11321 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11322 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11323 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11324 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11325 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11326 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11327 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11328 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11329 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11330 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11331 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11332 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11333 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11334 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11335 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11336 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11337 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11338 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11339 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11340 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11341 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11342 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11343 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11344 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11345 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11346 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11347 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11348 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11349 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11350 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11351 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11352 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11353 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11354 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11355 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11356 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11357 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11358 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11359 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11360 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11361 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11362 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11363 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11364 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11365 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11366 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11367 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11368 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11369 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11370 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11371 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11372 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11373 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11374 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11375 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11376 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11377 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11378 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11379 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11380 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11381 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11382 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11383 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11384 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11385 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11386 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11387 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11388 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11389 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11390 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11391 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11392 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11393 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11394 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11395 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11396 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11397 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11398 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11399 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11400 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11401 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11402 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11403 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11404 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11405 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11406 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11407 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11408 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11409 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11410 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11411 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11412 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11413 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11414 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11415 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11416 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11417 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11418 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11419 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11420 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11421 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11422 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11423 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11424 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11425 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11426 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11427 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11428 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11429 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11430 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11431 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11432 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11433 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11434 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11435 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11436 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11437 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11438 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11439 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11440 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11441 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11442 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11443 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11444 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11445 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11446 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11447 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11448 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11449 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11450 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11451 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11452 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11453 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11454 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11455 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11456 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11457 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11458 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11459 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11460 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11461 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11462 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11463 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11464 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11465 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11466 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11467 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11468 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11469 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11470 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11471 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11472 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11473 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11474 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11475 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11476 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11477 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11478 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11479 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11480 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11481 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11482 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11483 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11484 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11485 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11486 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11487 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11488 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11489 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11490 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11491 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11492 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11493 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11494 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11495 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11496 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11497 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11498 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11499 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11500 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11501 { 393 /* buffer_atomic_pk_add_f16 */, AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11502 { 393 /* buffer_atomic_pk_add_f16 */, AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11503 { 393 /* buffer_atomic_pk_add_f16 */, AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11504 { 393 /* buffer_atomic_pk_add_f16 */, AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11505 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11506 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11507 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11508 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11509 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11510 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11511 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11512 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11513 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11514 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11515 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11516 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11517 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11518 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11519 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11520 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11521 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11522 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11523 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11524 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11525 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11526 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11527 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11528 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11529 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11530 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11531 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11532 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11533 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11534 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11535 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11536 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11537 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11538 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11539 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11540 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11541 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11542 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11543 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11544 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11545 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11546 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11547 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11548 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11549 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11550 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11551 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11552 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11553 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11554 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11555 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11556 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11557 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11558 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11559 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11560 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11561 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11562 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11563 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11564 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11565 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11566 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11567 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11568 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11569 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11570 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11571 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11572 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11573 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11574 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11575 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11576 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11577 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11578 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11579 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11580 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11581 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11582 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11583 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11584 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11585 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11586 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11587 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11588 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11589 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11590 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11591 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11592 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11593 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11594 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11595 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11596 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11597 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11598 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11599 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11600 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11601 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11602 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11603 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11604 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11605 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11606 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11607 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11608 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11609 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11610 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11611 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11612 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11613 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11614 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11615 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11616 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11617 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11618 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11619 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11620 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11621 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11622 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11623 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11624 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11625 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11626 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11627 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11628 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11629 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11630 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11631 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11632 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11633 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11634 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11635 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11636 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11637 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11638 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11639 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11640 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11641 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11642 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11643 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11644 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11645 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11646 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11647 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11648 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11649 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11650 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11651 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11652 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11653 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11654 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11655 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11656 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11657 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11658 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11659 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11660 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11661 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11662 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11663 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11664 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11665 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11666 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11667 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11668 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11669 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11670 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11671 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11672 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11673 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11674 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11675 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11676 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11677 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11678 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11679 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11680 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11681 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11682 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11683 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11684 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11685 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11686 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11687 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11688 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11689 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11690 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11691 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11692 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11693 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11694 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11695 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11696 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11697 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11698 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11699 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11700 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11701 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11702 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11703 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11704 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11705 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11706 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11707 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11708 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11709 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11710 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11711 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11712 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11713 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11714 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11715 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11716 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11717 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11718 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11719 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11720 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11721 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11722 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11723 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11724 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11725 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11726 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11727 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11728 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11729 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11730 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11731 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11732 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11733 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11734 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11735 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11736 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11737 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11738 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11739 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11740 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11741 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11742 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11743 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11744 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11745 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11746 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11747 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11748 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11749 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11750 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11751 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11752 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11753 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11754 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11755 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11756 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11757 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11758 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11759 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11760 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11761 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11762 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11763 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11764 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11765 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11766 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11767 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11768 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11769 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11770 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11771 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11772 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11773 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11774 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11775 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11776 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11777 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11778 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11779 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11780 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11781 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11782 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11783 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11784 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11785 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11786 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11787 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11788 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11789 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11790 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11791 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11792 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11793 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11794 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11795 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11796 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11797 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11798 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11799 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11800 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11801 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11802 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11803 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11804 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11805 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11806 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11807 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11808 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11809 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11810 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11811 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11812 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11813 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11814 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11815 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11816 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11817 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11818 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11819 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11820 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11821 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11822 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11823 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11824 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11825 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11826 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11827 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11828 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11829 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11830 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11831 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11832 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11833 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11834 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11835 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11836 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11837 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11838 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11839 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11840 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11841 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11842 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11843 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11844 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11845 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11846 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11847 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11848 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11849 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11850 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11851 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11852 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11853 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11854 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11855 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11856 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11857 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11858 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11859 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11860 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11861 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11862 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11863 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11864 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11865 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11866 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11867 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11868 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11871 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11872 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11873 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11874 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11875 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11876 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11877 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11878 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11879 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11880 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11881 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11882 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11883 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11884 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11885 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11886 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11887 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11888 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11889 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11890 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11891 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11892 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11893 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11894 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11895 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11896 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11897 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11898 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11899 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11900 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11901 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11902 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11903 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11904 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11905 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11906 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11907 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11908 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11909 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11910 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11911 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11912 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11913 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11914 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11915 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11916 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11917 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11918 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11919 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11920 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11921 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11922 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11923 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11924 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11925 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11926 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11927 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11928 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11929 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11930 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11931 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11932 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11933 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11934 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11935 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11936 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11937 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11938 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11939 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11940 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11941 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11942 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11943 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11944 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11945 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11946 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11947 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11948 { 809 /* buffer_load_format_d16_hi_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11949 { 809 /* buffer_load_format_d16_hi_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11950 { 809 /* buffer_load_format_d16_hi_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11951 { 809 /* buffer_load_format_d16_hi_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11952 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11953 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11954 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11955 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11956 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11957 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11958 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11959 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11960 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11961 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11962 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11963 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11964 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11965 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11966 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11967 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11968 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11969 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11970 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11971 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11972 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11973 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11974 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11975 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11976 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11977 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11978 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11979 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11980 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11981 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11982 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11983 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11984 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11985 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11986 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11987 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11988 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11989 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11990 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11991 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11992 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11993 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11994 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11995 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11996 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11997 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11998 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11999 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12000 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12001 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12002 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12003 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12004 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12005 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12006 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12007 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12008 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12009 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12010 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12011 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12012 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12013 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12014 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12015 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12016 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12017 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12018 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12019 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12020 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12021 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12022 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12023 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12024 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12025 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12026 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12027 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12028 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12029 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12030 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12031 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12032 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12033 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12034 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12035 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12036 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12037 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12038 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12039 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12040 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12041 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12042 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12043 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12044 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12045 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12046 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12047 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12048 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12049 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12050 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12051 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12052 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12053 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12054 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12055 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12056 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12057 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12058 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12059 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12060 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12061 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12062 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12063 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12064 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12065 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12066 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12067 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12068 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12069 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12070 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12071 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12072 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12073 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12074 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12075 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12076 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12077 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12078 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12079 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12080 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12081 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12082 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12083 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12084 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12085 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12086 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12087 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12088 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12089 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12090 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12091 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12092 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12093 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12094 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12095 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12096 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12097 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12098 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12099 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12100 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12101 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12102 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12103 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12104 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12105 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12106 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12107 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12108 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12109 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12110 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12111 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12112 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12113 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12114 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12115 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12116 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12117 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12118 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12119 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12120 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12121 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12122 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12123 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12124 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12125 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12126 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12127 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12128 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12129 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12130 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12131 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12132 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12133 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12134 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12135 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12136 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12137 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12138 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12139 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12140 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12141 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12142 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12143 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12144 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12145 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12146 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12147 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12148 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12149 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12150 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12151 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12152 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12153 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12154 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12155 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12156 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12157 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12158 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12159 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12160 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12161 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12162 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12163 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12164 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12165 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12166 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12167 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12168 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12169 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12170 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12171 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12172 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12173 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12174 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12175 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12176 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12177 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12178 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12179 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12180 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12181 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12182 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12183 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12184 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12185 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12186 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12187 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12188 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12189 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12190 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12191 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12192 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12193 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12194 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12195 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12196 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12197 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12198 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12199 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12200 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12201 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12202 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12203 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12204 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12205 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12206 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12207 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12208 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12209 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12210 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12211 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12212 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12213 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12214 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12215 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12216 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12217 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12218 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12219 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12220 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12221 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12222 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12223 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12224 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12225 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12226 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12227 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12228 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12229 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12230 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12231 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12232 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12233 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12234 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12235 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12236 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12237 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12238 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12239 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12240 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12241 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12242 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12243 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12244 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12245 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12246 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12247 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12248 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12249 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12250 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12251 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12252 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12253 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12254 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12255 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12256 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12257 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12258 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12259 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12260 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12261 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12262 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12263 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12264 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12265 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12266 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12267 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12268 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12269 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12270 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12271 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12272 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12273 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12274 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12275 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12276 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12277 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12278 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12279 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12280 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12281 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12282 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12283 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12284 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12285 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12286 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12287 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12288 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12289 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12290 { 1373 /* buffer_store_format_d16_hi_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12291 { 1373 /* buffer_store_format_d16_hi_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12292 { 1373 /* buffer_store_format_d16_hi_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12293 { 1373 /* buffer_store_format_d16_hi_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12294 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12295 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12296 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12297 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12298 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12299 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12300 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12301 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12302 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12303 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12304 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12305 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12306 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12307 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12308 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12309 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12310 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12311 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12312 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12313 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12314 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12315 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12316 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12317 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12318 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12319 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12320 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12321 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12322 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12323 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12324 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12325 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12326 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12327 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12328 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12329 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12330 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12331 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12332 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12333 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12334 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12335 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12336 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12337 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12338 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12339 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12340 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12341 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12342 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12343 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12344 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12345 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12346 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12347 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12348 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12349 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12350 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12351 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12352 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12353 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12354 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12355 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12356 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12357 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12358 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12359 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12360 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12361 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12362 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12363 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12364 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12365 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12366 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12367 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12368 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12369 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12370 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12371 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12372 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12373 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12374 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12375 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12376 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12377 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12378 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12379 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12380 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12381 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12382 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12383 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12384 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12385 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12386 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12387 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12388 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12389 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12390 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12391 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12392 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12393 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12394 { 1606 /* buffer_store_lds_dword */, AMDGPU::BUFFER_STORE_LDS_DWORD_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_lds, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmSWZ }, },
12395 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12396 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12397 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12398 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12399 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12400 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12401 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12402 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12403 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12404 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12405 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12406 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12407 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12408 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12409 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12410 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12411 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12412 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12413 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12414 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12415 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12874 { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12875 { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12876 { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12877 { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12878 { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12879 { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12880 { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12881 { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12882 { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12883 { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12884 { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12885 { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12886 { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12887 { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12888 { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12889 { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12890 { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12891 { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12892 { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12893 { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12894 { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12895 { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12896 { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12897 { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12898 { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12899 { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12900 { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12901 { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12902 { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12903 { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12904 { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12905 { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12906 { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12907 { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12908 { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12909 { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12910 { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12911 { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12912 { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12913 { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12914 { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12915 { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12916 { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12917 { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12918 { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12919 { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12920 { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12921 { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12922 { 4131 /* flat_atomic_fcmpswap */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12923 { 4131 /* flat_atomic_fcmpswap */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12924 { 4131 /* flat_atomic_fcmpswap */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12925 { 4131 /* flat_atomic_fcmpswap */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12926 { 4152 /* flat_atomic_fcmpswap_x2 */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12927 { 4152 /* flat_atomic_fcmpswap_x2 */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12928 { 4152 /* flat_atomic_fcmpswap_x2 */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12929 { 4152 /* flat_atomic_fcmpswap_x2 */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12930 { 4176 /* flat_atomic_fmax */, AMDGPU::FLAT_ATOMIC_FMAX_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12931 { 4176 /* flat_atomic_fmax */, AMDGPU::FLAT_ATOMIC_FMAX_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12932 { 4176 /* flat_atomic_fmax */, AMDGPU::FLAT_ATOMIC_FMAX_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12933 { 4176 /* flat_atomic_fmax */, AMDGPU::FLAT_ATOMIC_FMAX_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12934 { 4193 /* flat_atomic_fmax_x2 */, AMDGPU::FLAT_ATOMIC_FMAX_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12935 { 4193 /* flat_atomic_fmax_x2 */, AMDGPU::FLAT_ATOMIC_FMAX_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12936 { 4193 /* flat_atomic_fmax_x2 */, AMDGPU::FLAT_ATOMIC_FMAX_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12937 { 4193 /* flat_atomic_fmax_x2 */, AMDGPU::FLAT_ATOMIC_FMAX_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12938 { 4213 /* flat_atomic_fmin */, AMDGPU::FLAT_ATOMIC_FMIN_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12939 { 4213 /* flat_atomic_fmin */, AMDGPU::FLAT_ATOMIC_FMIN_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12940 { 4213 /* flat_atomic_fmin */, AMDGPU::FLAT_ATOMIC_FMIN_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12941 { 4213 /* flat_atomic_fmin */, AMDGPU::FLAT_ATOMIC_FMIN_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12942 { 4230 /* flat_atomic_fmin_x2 */, AMDGPU::FLAT_ATOMIC_FMIN_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12943 { 4230 /* flat_atomic_fmin_x2 */, AMDGPU::FLAT_ATOMIC_FMIN_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12944 { 4230 /* flat_atomic_fmin_x2 */, AMDGPU::FLAT_ATOMIC_FMIN_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12945 { 4230 /* flat_atomic_fmin_x2 */, AMDGPU::FLAT_ATOMIC_FMIN_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12946 { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12947 { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12948 { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12949 { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12950 { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12951 { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12952 { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12953 { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12954 { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12955 { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12956 { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12957 { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12958 { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12959 { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12960 { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12961 { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12962 { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12963 { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12964 { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12965 { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12966 { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12967 { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12968 { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12969 { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12970 { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12971 { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12972 { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12973 { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12974 { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12975 { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12976 { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12977 { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12978 { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12979 { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12980 { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12981 { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12982 { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12983 { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12984 { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12985 { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12986 { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12987 { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12988 { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12989 { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12990 { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12991 { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12992 { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12993 { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12994 { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12995 { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12996 { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12997 { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12998 { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12999 { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13000 { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13001 { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13002 { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13003 { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13004 { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13005 { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13006 { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13007 { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13008 { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13009 { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13010 { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13011 { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13012 { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13013 { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13014 { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13015 { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13016 { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13017 { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13018 { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13019 { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13020 { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13021 { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13022 { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13023 { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13024 { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13025 { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13026 { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13027 { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13028 { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13029 { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13030 { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13031 { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13032 { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13033 { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13034 { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13035 { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13036 { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13037 { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13038 { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13039 { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13040 { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13041 { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13042 { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13043 { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13044 { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13045 { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13046 { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13047 { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13048 { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13049 { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13050 { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13051 { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13052 { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13053 { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13054 { 4573 /* flat_load_dword */, AMDGPU::FLAT_LOAD_DWORD_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13055 { 4573 /* flat_load_dword */, AMDGPU::FLAT_LOAD_DWORD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13056 { 4573 /* flat_load_dword */, AMDGPU::FLAT_LOAD_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13057 { 4589 /* flat_load_dwordx2 */, AMDGPU::FLAT_LOAD_DWORDX2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13058 { 4589 /* flat_load_dwordx2 */, AMDGPU::FLAT_LOAD_DWORDX2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13059 { 4589 /* flat_load_dwordx2 */, AMDGPU::FLAT_LOAD_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13060 { 4607 /* flat_load_dwordx3 */, AMDGPU::FLAT_LOAD_DWORDX3_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_96, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13061 { 4607 /* flat_load_dwordx3 */, AMDGPU::FLAT_LOAD_DWORDX3_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13062 { 4607 /* flat_load_dwordx3 */, AMDGPU::FLAT_LOAD_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13063 { 4625 /* flat_load_dwordx4 */, AMDGPU::FLAT_LOAD_DWORDX4_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_128, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13064 { 4625 /* flat_load_dwordx4 */, AMDGPU::FLAT_LOAD_DWORDX4_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13065 { 4625 /* flat_load_dwordx4 */, AMDGPU::FLAT_LOAD_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13066 { 4643 /* flat_load_sbyte */, AMDGPU::FLAT_LOAD_SBYTE_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13067 { 4643 /* flat_load_sbyte */, AMDGPU::FLAT_LOAD_SBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13068 { 4643 /* flat_load_sbyte */, AMDGPU::FLAT_LOAD_SBYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13069 { 4659 /* flat_load_sbyte_d16 */, AMDGPU::FLAT_LOAD_SBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13070 { 4659 /* flat_load_sbyte_d16 */, AMDGPU::FLAT_LOAD_SBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13071 { 4679 /* flat_load_sbyte_d16_hi */, AMDGPU::FLAT_LOAD_SBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13072 { 4679 /* flat_load_sbyte_d16_hi */, AMDGPU::FLAT_LOAD_SBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13073 { 4702 /* flat_load_short_d16 */, AMDGPU::FLAT_LOAD_SHORT_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13074 { 4702 /* flat_load_short_d16 */, AMDGPU::FLAT_LOAD_SHORT_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13075 { 4722 /* flat_load_short_d16_hi */, AMDGPU::FLAT_LOAD_SHORT_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13076 { 4722 /* flat_load_short_d16_hi */, AMDGPU::FLAT_LOAD_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13077 { 4745 /* flat_load_sshort */, AMDGPU::FLAT_LOAD_SSHORT_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13078 { 4745 /* flat_load_sshort */, AMDGPU::FLAT_LOAD_SSHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13079 { 4745 /* flat_load_sshort */, AMDGPU::FLAT_LOAD_SSHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13080 { 4762 /* flat_load_ubyte */, AMDGPU::FLAT_LOAD_UBYTE_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13081 { 4762 /* flat_load_ubyte */, AMDGPU::FLAT_LOAD_UBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13082 { 4762 /* flat_load_ubyte */, AMDGPU::FLAT_LOAD_UBYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13083 { 4778 /* flat_load_ubyte_d16 */, AMDGPU::FLAT_LOAD_UBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13084 { 4778 /* flat_load_ubyte_d16 */, AMDGPU::FLAT_LOAD_UBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13085 { 4798 /* flat_load_ubyte_d16_hi */, AMDGPU::FLAT_LOAD_UBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13086 { 4798 /* flat_load_ubyte_d16_hi */, AMDGPU::FLAT_LOAD_UBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13087 { 4821 /* flat_load_ushort */, AMDGPU::FLAT_LOAD_USHORT_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13088 { 4821 /* flat_load_ushort */, AMDGPU::FLAT_LOAD_USHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13089 { 4821 /* flat_load_ushort */, AMDGPU::FLAT_LOAD_USHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13090 { 4838 /* flat_store_byte */, AMDGPU::FLAT_STORE_BYTE_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13091 { 4838 /* flat_store_byte */, AMDGPU::FLAT_STORE_BYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13092 { 4838 /* flat_store_byte */, AMDGPU::FLAT_STORE_BYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13093 { 4854 /* flat_store_byte_d16_hi */, AMDGPU::FLAT_STORE_BYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13094 { 4854 /* flat_store_byte_d16_hi */, AMDGPU::FLAT_STORE_BYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13095 { 4877 /* flat_store_dword */, AMDGPU::FLAT_STORE_DWORD_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13096 { 4877 /* flat_store_dword */, AMDGPU::FLAT_STORE_DWORD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13097 { 4877 /* flat_store_dword */, AMDGPU::FLAT_STORE_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13098 { 4894 /* flat_store_dwordx2 */, AMDGPU::FLAT_STORE_DWORDX2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13099 { 4894 /* flat_store_dwordx2 */, AMDGPU::FLAT_STORE_DWORDX2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13100 { 4894 /* flat_store_dwordx2 */, AMDGPU::FLAT_STORE_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13101 { 4913 /* flat_store_dwordx3 */, AMDGPU::FLAT_STORE_DWORDX3_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_96, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13102 { 4913 /* flat_store_dwordx3 */, AMDGPU::FLAT_STORE_DWORDX3_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13103 { 4913 /* flat_store_dwordx3 */, AMDGPU::FLAT_STORE_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13104 { 4932 /* flat_store_dwordx4 */, AMDGPU::FLAT_STORE_DWORDX4_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13105 { 4932 /* flat_store_dwordx4 */, AMDGPU::FLAT_STORE_DWORDX4_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13106 { 4932 /* flat_store_dwordx4 */, AMDGPU::FLAT_STORE_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13107 { 4951 /* flat_store_short */, AMDGPU::FLAT_STORE_SHORT_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13108 { 4951 /* flat_store_short */, AMDGPU::FLAT_STORE_SHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13109 { 4951 /* flat_store_short */, AMDGPU::FLAT_STORE_SHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13110 { 4968 /* flat_store_short_d16_hi */, AMDGPU::FLAT_STORE_SHORT_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13111 { 4968 /* flat_store_short_d16_hi */, AMDGPU::FLAT_STORE_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13112 { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13113 { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13114 { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13115 { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13116 { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13117 { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13118 { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13119 { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13120 { 5010 /* global_atomic_add_f32 */, AMDGPU::GLOBAL_ATOMIC_ADD_F32_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13121 { 5010 /* global_atomic_add_f32 */, AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13122 { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13123 { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13124 { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13125 { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13126 { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13127 { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13128 { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13129 { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13130 { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13131 { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13132 { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13133 { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13134 { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13135 { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13136 { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13137 { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13138 { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13139 { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13140 { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13141 { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13142 { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13143 { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13144 { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13145 { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13146 { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13147 { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13148 { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13149 { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13150 { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13151 { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13152 { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13153 { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13154 { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13155 { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13156 { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13157 { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13158 { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13159 { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13160 { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13161 { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13162 { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13163 { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13164 { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13165 { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13166 { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13167 { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13168 { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13169 { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13170 { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13171 { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13172 { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13173 { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13174 { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13175 { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13176 { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13177 { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13178 { 5178 /* global_atomic_fcmpswap */, AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13179 { 5178 /* global_atomic_fcmpswap */, AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13180 { 5178 /* global_atomic_fcmpswap */, AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13181 { 5178 /* global_atomic_fcmpswap */, AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13182 { 5201 /* global_atomic_fcmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13183 { 5201 /* global_atomic_fcmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13184 { 5201 /* global_atomic_fcmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13185 { 5201 /* global_atomic_fcmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13186 { 5227 /* global_atomic_fmax */, AMDGPU::GLOBAL_ATOMIC_FMAX_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13187 { 5227 /* global_atomic_fmax */, AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13188 { 5227 /* global_atomic_fmax */, AMDGPU::GLOBAL_ATOMIC_FMAX_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13189 { 5227 /* global_atomic_fmax */, AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13190 { 5246 /* global_atomic_fmax_x2 */, AMDGPU::GLOBAL_ATOMIC_FMAX_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13191 { 5246 /* global_atomic_fmax_x2 */, AMDGPU::GLOBAL_ATOMIC_FMAX_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13192 { 5246 /* global_atomic_fmax_x2 */, AMDGPU::GLOBAL_ATOMIC_FMAX_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13193 { 5246 /* global_atomic_fmax_x2 */, AMDGPU::GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13194 { 5268 /* global_atomic_fmin */, AMDGPU::GLOBAL_ATOMIC_FMIN_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13195 { 5268 /* global_atomic_fmin */, AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13196 { 5268 /* global_atomic_fmin */, AMDGPU::GLOBAL_ATOMIC_FMIN_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13197 { 5268 /* global_atomic_fmin */, AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13198 { 5287 /* global_atomic_fmin_x2 */, AMDGPU::GLOBAL_ATOMIC_FMIN_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13199 { 5287 /* global_atomic_fmin_x2 */, AMDGPU::GLOBAL_ATOMIC_FMIN_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13200 { 5287 /* global_atomic_fmin_x2 */, AMDGPU::GLOBAL_ATOMIC_FMIN_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13201 { 5287 /* global_atomic_fmin_x2 */, AMDGPU::GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13202 { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13203 { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13204 { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13205 { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13206 { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13207 { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13208 { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13209 { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13210 { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13211 { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13212 { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13213 { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13214 { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13215 { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13216 { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13217 { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13218 { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13219 { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13220 { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13221 { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13222 { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13223 { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13224 { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13225 { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13226 { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13227 { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13228 { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13229 { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13230 { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13231 { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13232 { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13233 { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13234 { 5385 /* global_atomic_pk_add_f16 */, AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13235 { 5385 /* global_atomic_pk_add_f16 */, AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13236 { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13237 { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13238 { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13239 { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13240 { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13241 { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13242 { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13243 { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13244 { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13245 { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13246 { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13247 { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13248 { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13249 { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13250 { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13251 { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13252 { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13253 { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13254 { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13255 { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13256 { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13257 { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13258 { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13259 { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13260 { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13261 { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13262 { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13263 { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13264 { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13265 { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13266 { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13267 { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13268 { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13269 { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13270 { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13271 { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13272 { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13273 { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13274 { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13275 { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13276 { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13277 { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13278 { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13279 { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13280 { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13281 { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13282 { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13283 { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13284 { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13285 { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13286 { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13287 { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13288 { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13289 { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13290 { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13291 { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13292 { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13293 { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13294 { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13295 { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13296 { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13297 { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13298 { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13299 { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13300 { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13301 { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13302 { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13303 { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13304 { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13305 { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13306 { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13307 { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13308 { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13309 { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13310 { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13311 { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13312 { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13313 { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13314 { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13315 { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13316 { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13317 { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13318 { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13319 { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13320 { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13321 { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13322 { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13323 { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13324 { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13325 { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13326 { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13327 { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13328 { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13329 { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13330 { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13331 { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13332 { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13333 { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13334 { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13335 { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13336 { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13337 { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13338 { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13339 { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13340 { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13341 { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13342 { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13343 { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13344 { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13345 { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13346 { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13347 { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13348 { 5693 /* global_load_dword */, AMDGPU::GLOBAL_LOAD_DWORD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13349 { 5693 /* global_load_dword */, AMDGPU::GLOBAL_LOAD_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13350 { 5693 /* global_load_dword */, AMDGPU::GLOBAL_LOAD_DWORD_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13351 { 5693 /* global_load_dword */, AMDGPU::GLOBAL_LOAD_DWORD_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13352 { 5711 /* global_load_dwordx2 */, AMDGPU::GLOBAL_LOAD_DWORDX2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13353 { 5711 /* global_load_dwordx2 */, AMDGPU::GLOBAL_LOAD_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13354 { 5711 /* global_load_dwordx2 */, AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13355 { 5711 /* global_load_dwordx2 */, AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13356 { 5731 /* global_load_dwordx3 */, AMDGPU::GLOBAL_LOAD_DWORDX3_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13357 { 5731 /* global_load_dwordx3 */, AMDGPU::GLOBAL_LOAD_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13358 { 5731 /* global_load_dwordx3 */, AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13359 { 5731 /* global_load_dwordx3 */, AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13360 { 5751 /* global_load_dwordx4 */, AMDGPU::GLOBAL_LOAD_DWORDX4_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13361 { 5751 /* global_load_dwordx4 */, AMDGPU::GLOBAL_LOAD_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13362 { 5751 /* global_load_dwordx4 */, AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13363 { 5751 /* global_load_dwordx4 */, AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13364 { 5771 /* global_load_sbyte */, AMDGPU::GLOBAL_LOAD_SBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13365 { 5771 /* global_load_sbyte */, AMDGPU::GLOBAL_LOAD_SBYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13366 { 5771 /* global_load_sbyte */, AMDGPU::GLOBAL_LOAD_SBYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13367 { 5771 /* global_load_sbyte */, AMDGPU::GLOBAL_LOAD_SBYTE_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13368 { 5789 /* global_load_sbyte_d16 */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13369 { 5789 /* global_load_sbyte_d16 */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13370 { 5789 /* global_load_sbyte_d16 */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13371 { 5789 /* global_load_sbyte_d16 */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13372 { 5811 /* global_load_sbyte_d16_hi */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13373 { 5811 /* global_load_sbyte_d16_hi */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13374 { 5811 /* global_load_sbyte_d16_hi */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13375 { 5811 /* global_load_sbyte_d16_hi */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13376 { 5836 /* global_load_short_d16 */, AMDGPU::GLOBAL_LOAD_SHORT_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13377 { 5836 /* global_load_short_d16 */, AMDGPU::GLOBAL_LOAD_SHORT_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13378 { 5836 /* global_load_short_d16 */, AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13379 { 5836 /* global_load_short_d16 */, AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13380 { 5858 /* global_load_short_d16_hi */, AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13381 { 5858 /* global_load_short_d16_hi */, AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13382 { 5858 /* global_load_short_d16_hi */, AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13383 { 5858 /* global_load_short_d16_hi */, AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13384 { 5883 /* global_load_sshort */, AMDGPU::GLOBAL_LOAD_SSHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13385 { 5883 /* global_load_sshort */, AMDGPU::GLOBAL_LOAD_SSHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13386 { 5883 /* global_load_sshort */, AMDGPU::GLOBAL_LOAD_SSHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13387 { 5883 /* global_load_sshort */, AMDGPU::GLOBAL_LOAD_SSHORT_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13388 { 5902 /* global_load_ubyte */, AMDGPU::GLOBAL_LOAD_UBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13389 { 5902 /* global_load_ubyte */, AMDGPU::GLOBAL_LOAD_UBYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13390 { 5902 /* global_load_ubyte */, AMDGPU::GLOBAL_LOAD_UBYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13391 { 5902 /* global_load_ubyte */, AMDGPU::GLOBAL_LOAD_UBYTE_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13392 { 5920 /* global_load_ubyte_d16 */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13393 { 5920 /* global_load_ubyte_d16 */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13394 { 5920 /* global_load_ubyte_d16 */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13395 { 5920 /* global_load_ubyte_d16 */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13396 { 5942 /* global_load_ubyte_d16_hi */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13397 { 5942 /* global_load_ubyte_d16_hi */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13398 { 5942 /* global_load_ubyte_d16_hi */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13399 { 5942 /* global_load_ubyte_d16_hi */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13400 { 5967 /* global_load_ushort */, AMDGPU::GLOBAL_LOAD_USHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13401 { 5967 /* global_load_ushort */, AMDGPU::GLOBAL_LOAD_USHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13402 { 5967 /* global_load_ushort */, AMDGPU::GLOBAL_LOAD_USHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13403 { 5967 /* global_load_ushort */, AMDGPU::GLOBAL_LOAD_USHORT_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13404 { 5986 /* global_store_byte */, AMDGPU::GLOBAL_STORE_BYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13405 { 5986 /* global_store_byte */, AMDGPU::GLOBAL_STORE_BYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13406 { 5986 /* global_store_byte */, AMDGPU::GLOBAL_STORE_BYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13407 { 5986 /* global_store_byte */, AMDGPU::GLOBAL_STORE_BYTE_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13408 { 6004 /* global_store_byte_d16_hi */, AMDGPU::GLOBAL_STORE_BYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13409 { 6004 /* global_store_byte_d16_hi */, AMDGPU::GLOBAL_STORE_BYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13410 { 6004 /* global_store_byte_d16_hi */, AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13411 { 6004 /* global_store_byte_d16_hi */, AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13412 { 6029 /* global_store_dword */, AMDGPU::GLOBAL_STORE_DWORD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13413 { 6029 /* global_store_dword */, AMDGPU::GLOBAL_STORE_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13414 { 6029 /* global_store_dword */, AMDGPU::GLOBAL_STORE_DWORD_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13415 { 6029 /* global_store_dword */, AMDGPU::GLOBAL_STORE_DWORD_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13416 { 6048 /* global_store_dwordx2 */, AMDGPU::GLOBAL_STORE_DWORDX2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13417 { 6048 /* global_store_dwordx2 */, AMDGPU::GLOBAL_STORE_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13418 { 6048 /* global_store_dwordx2 */, AMDGPU::GLOBAL_STORE_DWORDX2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13419 { 6048 /* global_store_dwordx2 */, AMDGPU::GLOBAL_STORE_DWORDX2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13420 { 6069 /* global_store_dwordx3 */, AMDGPU::GLOBAL_STORE_DWORDX3_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13421 { 6069 /* global_store_dwordx3 */, AMDGPU::GLOBAL_STORE_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13422 { 6069 /* global_store_dwordx3 */, AMDGPU::GLOBAL_STORE_DWORDX3_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13423 { 6069 /* global_store_dwordx3 */, AMDGPU::GLOBAL_STORE_DWORDX3_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13424 { 6090 /* global_store_dwordx4 */, AMDGPU::GLOBAL_STORE_DWORDX4_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13425 { 6090 /* global_store_dwordx4 */, AMDGPU::GLOBAL_STORE_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13426 { 6090 /* global_store_dwordx4 */, AMDGPU::GLOBAL_STORE_DWORDX4_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13427 { 6090 /* global_store_dwordx4 */, AMDGPU::GLOBAL_STORE_DWORDX4_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13428 { 6111 /* global_store_short */, AMDGPU::GLOBAL_STORE_SHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13429 { 6111 /* global_store_short */, AMDGPU::GLOBAL_STORE_SHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13430 { 6111 /* global_store_short */, AMDGPU::GLOBAL_STORE_SHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13431 { 6111 /* global_store_short */, AMDGPU::GLOBAL_STORE_SHORT_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13432 { 6130 /* global_store_short_d16_hi */, AMDGPU::GLOBAL_STORE_SHORT_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13433 { 6130 /* global_store_short_d16_hi */, AMDGPU::GLOBAL_STORE_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13434 { 6130 /* global_store_short_d16_hi */, AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13435 { 6130 /* global_store_short_d16_hi */, AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13436 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13437 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13438 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13439 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13440 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13441 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13442 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13443 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13444 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13445 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13446 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13447 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13448 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13449 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13450 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13451 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13452 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13453 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13454 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13455 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13456 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13457 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13458 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13459 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13460 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13461 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13462 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13463 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13464 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13465 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13466 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13467 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13468 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13469 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13470 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13471 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13472 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13473 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13474 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13475 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13476 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13477 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13478 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13479 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13480 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13481 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13482 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13483 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13484 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13485 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13486 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13487 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13488 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13489 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13490 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13491 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13492 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13493 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13494 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13495 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13496 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13497 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13498 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13499 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13500 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13501 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13502 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13503 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13504 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13505 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13506 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13507 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13508 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13509 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13510 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13511 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13512 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13513 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13514 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13515 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13516 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13517 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13518 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13519 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13520 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13521 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13522 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13523 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13524 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13525 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13526 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13527 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13528 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13529 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13530 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13531 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13532 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13533 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13534 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13535 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13536 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13537 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13538 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13539 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13540 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13541 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13542 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13543 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13544 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13545 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13546 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13547 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13548 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13549 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13550 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13551 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13552 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13553 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13554 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13555 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13556 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13557 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13558 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13559 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13560 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13561 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13562 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13563 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13564 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13565 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13566 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13567 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13568 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13569 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13570 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13571 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13572 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13573 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13574 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13575 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13576 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13577 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13578 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13579 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13580 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13581 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13582 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13583 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13584 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13585 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13586 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13587 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13588 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13589 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13590 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13591 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13592 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13593 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13594 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13595 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13596 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13597 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13598 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13599 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13600 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13601 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13602 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13603 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13604 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13605 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13606 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13607 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13608 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13609 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13610 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13611 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13612 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13613 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13614 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13615 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13616 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13617 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13618 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13619 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13620 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13621 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13622 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13623 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13624 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13625 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13626 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13627 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13628 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13629 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13630 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13631 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13632 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13633 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13634 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13635 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13636 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13637 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13638 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13639 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13640 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13641 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13642 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13643 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13644 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13645 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13646 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13647 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13648 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13649 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13650 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13651 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13652 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13653 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13654 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13655 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13656 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13657 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13658 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13659 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13660 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13661 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13662 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13663 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13664 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13665 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13666 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13667 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13668 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13669 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13670 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13671 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13672 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13673 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13674 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13675 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13676 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13677 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13678 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13679 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13680 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13681 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13682 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13683 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13684 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13685 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13686 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13687 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13688 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13689 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13690 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13691 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13692 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13693 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13694 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13695 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13696 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13697 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13698 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13699 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13700 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13701 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13702 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13703 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13704 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13705 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13706 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13707 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13708 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13709 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13710 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13711 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13712 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13713 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13714 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13715 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13716 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13717 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13718 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13719 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13720 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13721 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13722 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13723 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13724 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13725 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13726 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13727 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13728 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13729 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13730 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13731 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13732 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13733 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13734 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13735 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13736 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13737 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13738 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13739 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13740 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13741 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13742 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13743 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13744 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13745 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13746 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13747 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13748 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13749 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13750 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13751 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13752 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13753 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13754 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13755 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13756 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13757 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13758 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13759 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13760 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13761 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13762 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13763 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13764 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13765 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13766 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13767 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13768 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13769 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13770 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13771 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13772 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13773 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13774 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13775 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13776 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13777 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13778 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13779 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13780 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13781 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13782 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13783 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13784 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13785 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13786 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13787 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13788 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13789 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13790 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13791 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13792 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13793 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13794 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13795 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13796 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13797 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13798 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13799 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13800 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13801 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13802 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13803 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13804 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13805 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13806 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13807 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13808 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13809 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13810 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13811 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13812 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13813 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13814 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13815 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13816 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13817 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13818 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13819 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13820 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13821 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13822 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13823 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13824 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13825 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13826 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13827 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13828 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13829 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13830 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13831 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13832 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13833 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13834 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13835 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13836 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13837 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13838 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13839 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13840 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13841 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13842 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13843 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13844 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13845 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13846 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13847 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13848 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13849 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13850 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13851 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13852 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13853 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13854 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13855 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13856 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13857 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13858 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13859 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13860 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13861 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13862 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13863 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13864 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13865 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13866 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13867 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13868 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13869 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13870 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13871 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13872 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13873 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13874 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13875 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13876 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13877 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13878 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13879 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13880 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13881 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13882 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13883 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13884 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13885 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13886 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13887 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13888 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13889 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13890 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13891 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13892 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13893 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13894 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13895 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13896 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13897 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13898 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13899 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13900 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13901 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13902 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13903 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13904 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13905 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13906 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13907 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13908 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13909 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13910 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13911 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13912 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13913 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13914 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13915 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13916 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13917 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13918 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13919 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13920 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13921 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13922 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13923 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13924 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13925 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13926 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13927 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13928 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13929 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13930 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13931 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13932 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13933 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13934 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13935 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13936 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13937 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13938 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13939 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13940 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13941 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13942 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13943 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13944 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13945 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13946 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13947 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13948 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13949 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13950 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13951 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13952 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13953 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13954 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13955 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13956 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13957 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13958 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13959 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13960 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13961 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13962 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13963 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13964 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13965 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13966 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13967 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13968 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13969 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13970 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13971 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13972 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13973 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13974 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13975 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13976 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13977 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13978 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13979 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13980 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13981 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13982 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13983 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13984 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13985 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13986 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13987 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13988 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13989 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13990 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13991 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13992 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13993 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13994 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13995 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13996 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13997 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13998 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13999 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14000 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14001 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14002 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14003 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14004 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14005 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14006 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14007 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14008 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14009 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14010 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14011 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14012 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14013 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14014 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14015 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14016 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14017 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14018 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14019 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14020 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14021 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14022 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14023 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14024 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14025 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14026 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14027 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14028 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14029 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14030 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14031 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14032 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14033 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14034 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14035 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14036 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14037 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14038 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14039 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14040 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14041 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14042 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14043 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14044 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14045 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14046 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14047 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14048 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14049 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14050 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14051 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14052 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14053 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14054 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14055 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14056 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14057 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14058 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14059 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14060 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14061 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14062 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14063 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14064 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14065 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14066 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14067 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14068 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14069 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14070 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14071 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14072 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14073 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14074 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14075 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14076 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14077 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14078 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14079 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14080 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14081 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14082 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14083 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14084 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14085 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14086 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14087 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14088 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14089 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14090 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14091 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14092 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14093 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14094 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14095 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14096 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14097 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14098 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14099 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14100 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14101 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14102 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14103 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14104 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14105 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14106 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14107 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14108 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14109 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14110 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14111 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14112 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14113 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14114 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14115 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14116 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14117 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14118 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14119 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14120 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14121 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14122 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14123 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14124 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14125 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14126 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14127 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14128 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14129 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14130 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14131 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14132 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14133 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14134 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14135 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14136 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14137 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14138 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14139 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14140 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14141 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14142 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14143 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14144 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14145 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14146 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14147 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14148 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14149 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14150 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14151 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14152 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14153 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14154 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14155 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14156 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14157 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14158 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14159 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14160 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14161 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14162 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14163 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14164 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14165 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14166 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14167 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14168 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14169 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14170 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14171 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14172 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14173 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14174 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14175 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14176 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14177 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14178 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14179 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14180 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14181 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14182 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14183 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14184 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14185 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14186 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14187 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14188 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14189 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14190 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14191 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14192 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14193 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14194 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14195 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14196 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14197 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14198 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14199 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14200 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14201 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14202 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14203 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14204 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14205 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14206 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14207 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14208 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14209 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14210 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14211 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14212 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14213 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14214 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14215 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14216 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14217 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14218 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14219 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14220 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14221 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14222 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14223 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14224 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14225 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14226 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14227 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14228 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14229 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14230 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14231 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14232 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14233 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14234 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14235 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14236 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14237 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14238 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14239 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14240 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14241 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14242 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14243 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14244 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14245 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14246 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14247 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14248 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14249 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14250 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14251 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14252 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14253 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14254 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14255 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14256 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14257 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14258 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14259 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14260 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14261 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14262 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14263 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14264 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14265 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14266 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14267 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14268 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14269 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14270 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14271 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14272 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14273 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14274 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14275 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14276 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14277 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14278 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14279 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14280 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14281 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14282 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14283 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14284 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14285 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14286 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14287 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14288 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14289 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14290 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14291 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14292 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14293 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14294 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14295 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14296 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14297 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14298 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14299 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14300 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14301 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14302 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14303 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14304 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14305 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14306 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14307 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14308 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14309 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14310 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14311 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14312 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14313 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14314 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14315 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14316 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14317 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14318 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14319 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14320 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14321 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14322 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14323 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14324 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14325 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14326 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14327 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14328 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14329 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14330 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14331 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14332 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14333 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14334 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14335 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14336 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14337 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14338 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14339 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14340 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14341 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14342 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14343 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14344 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14345 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14346 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14347 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14348 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14349 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14350 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14351 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14352 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14353 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14354 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14355 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14356 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14357 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14358 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14359 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14360 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14361 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14362 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14363 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14364 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14365 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14366 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14367 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14368 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14369 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14370 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14371 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14372 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14373 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14374 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14375 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14376 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14377 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14378 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14379 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14380 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14381 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14382 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14383 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14384 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14385 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14386 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14387 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14388 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14389 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14390 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14391 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14392 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14393 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14394 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14395 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14396 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14397 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14398 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14399 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14400 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14401 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14402 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14403 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14404 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14405 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14406 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14407 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14408 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14409 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14410 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14411 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14412 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14413 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14414 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14415 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14416 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14417 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14418 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14419 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14420 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14421 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14422 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14423 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14424 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14425 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14426 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14427 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14428 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14429 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14430 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14431 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14432 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14433 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14434 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14435 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14436 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14437 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14438 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14439 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14440 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14441 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14442 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14443 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14444 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14445 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14446 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14447 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14448 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14449 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14450 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14451 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14452 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14453 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14454 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14455 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14456 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14457 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14458 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14459 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14460 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14461 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14462 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14463 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14464 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14465 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14466 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14467 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14468 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14469 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14470 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14471 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14472 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14473 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14474 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14475 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14476 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14477 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14478 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14479 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14480 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14481 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14482 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14483 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14484 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14485 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14486 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14487 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14488 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14489 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14490 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14491 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14492 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14493 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14494 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14495 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14496 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14497 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14498 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14499 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14500 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14501 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14502 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14503 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14504 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14505 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14506 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14507 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14508 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14509 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14510 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14511 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14512 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14513 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14514 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14515 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14516 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14517 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14518 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14519 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14520 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14521 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14522 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14523 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14524 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14525 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14526 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14527 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14528 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14529 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14530 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14531 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14532 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14533 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14534 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14535 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14536 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14537 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14538 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14539 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14540 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14541 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14542 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14543 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14544 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14545 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14546 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14547 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14548 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14549 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14550 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14551 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14552 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14553 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14554 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14555 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14556 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14557 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14558 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14559 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14560 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14561 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14562 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14563 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14564 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14565 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14566 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14567 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14568 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14569 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14570 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14571 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14572 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14573 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14574 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14575 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14576 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14577 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14578 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14579 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14580 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14581 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14582 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14583 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14584 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14585 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14586 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14587 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14588 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14589 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14590 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14591 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14592 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14593 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14594 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14595 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14596 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14597 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14598 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14599 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14600 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14601 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14602 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14603 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14604 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14605 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14606 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14607 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14608 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14609 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14610 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14611 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14612 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14613 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14614 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14615 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14616 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14617 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14618 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14619 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14620 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14621 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14622 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14623 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14624 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14625 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14626 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14627 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14628 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14629 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14630 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14631 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14632 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14633 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14634 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14635 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14636 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14637 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14638 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14639 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14640 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14641 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14642 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14643 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14644 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14645 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14646 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14647 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14648 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14649 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14650 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14651 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14652 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14653 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14654 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14655 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14656 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14657 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14658 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14659 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14660 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14661 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14662 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14663 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14664 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14665 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14666 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14667 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14668 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14669 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14670 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14671 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14672 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14673 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14674 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14675 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14676 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14677 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14678 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14679 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14680 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14681 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14682 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14683 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14684 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14685 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14686 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14687 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14688 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14689 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14690 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14691 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14692 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14693 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14694 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14695 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14696 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14697 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14698 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14699 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14700 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14701 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14702 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14703 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14704 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14705 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14706 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14707 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14708 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14709 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14710 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14711 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14712 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14713 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14714 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14715 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14716 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14717 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14718 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14719 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14720 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14721 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14722 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14723 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14724 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14725 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14726 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14727 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14728 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14729 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14730 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14731 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14732 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14733 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14734 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14735 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14736 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14737 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14738 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14739 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14740 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14741 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14742 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14743 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14744 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14745 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14746 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14747 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14748 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14749 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14750 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14751 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14752 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14753 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14754 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14755 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14756 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14757 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14758 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14759 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14760 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14761 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14762 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14763 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14764 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14765 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14766 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14767 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14768 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14769 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14770 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14771 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14772 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14773 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14774 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14775 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14776 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14777 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14778 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14779 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14780 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14781 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14782 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14783 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14784 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14785 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14786 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14787 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14788 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14789 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14790 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14791 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14792 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14793 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14794 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14795 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14796 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14797 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14798 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14799 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14800 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14801 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14802 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14803 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14804 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14805 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14806 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14807 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14808 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14809 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14810 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14811 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14812 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14813 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14814 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14815 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14816 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14817 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14818 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14819 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14820 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14821 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14822 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14823 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14824 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14825 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14826 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14827 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14828 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14829 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14830 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14831 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14832 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14833 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14834 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14835 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14836 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14837 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14838 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14839 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14840 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14841 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14842 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14843 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14844 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14845 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14846 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14847 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14848 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14849 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14850 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14851 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14852 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14853 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14854 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14855 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14856 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14857 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14858 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14859 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14860 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14861 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14862 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14863 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14864 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14865 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14866 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14867 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14868 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14869 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14870 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14871 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14872 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14873 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14874 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14875 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14876 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14877 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14878 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14879 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14880 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14881 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14882 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14883 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14884 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14885 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14886 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14887 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14888 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14889 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14890 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14891 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14892 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14893 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14894 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14895 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14896 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14897 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14898 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14899 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14900 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14901 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14902 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14903 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14904 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14905 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14906 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14907 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14908 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14909 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14910 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14911 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14912 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14913 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14914 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14915 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14916 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14917 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14918 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14919 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14920 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14921 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14922 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14923 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14924 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14925 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14926 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14927 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14928 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14929 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14930 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14931 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14932 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14933 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14934 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14935 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14936 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14937 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14938 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14939 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14940 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14941 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14942 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14943 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14944 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14945 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14946 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14947 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14948 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14949 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14950 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14951 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14952 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14953 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14954 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14955 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14956 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14957 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14958 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14959 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14960 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14961 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14962 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14963 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14964 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14965 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14966 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14967 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14968 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14969 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14970 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14971 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14972 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14973 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14974 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14975 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14976 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14977 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14978 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14979 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14980 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14981 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14982 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14983 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14984 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14985 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14986 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14987 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14988 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14989 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14990 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14991 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14992 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14993 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14994 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14995 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14996 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14997 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14998 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14999 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15000 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15001 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15002 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15003 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15004 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15005 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15006 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15007 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15008 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15009 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15010 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15011 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15012 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15013 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15014 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15015 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15016 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15017 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15018 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15019 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15020 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15021 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15022 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15023 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15024 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15025 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15026 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15027 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15028 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15029 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15030 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15031 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15032 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15033 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15034 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15035 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15036 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15037 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15038 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15039 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15040 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15041 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15042 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15043 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15044 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15045 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15046 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15047 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15048 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15049 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15050 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15051 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15052 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15053 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15054 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15055 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15056 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15057 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15058 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15059 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15060 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15061 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15062 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15063 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15064 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15065 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15066 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15067 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15068 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15069 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15070 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15071 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15072 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15073 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15074 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15075 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15076 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15077 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15078 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15079 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15080 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15081 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15082 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15083 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15084 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15085 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15086 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15087 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15088 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15089 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15090 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15091 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15092 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15093 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15094 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15095 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15096 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15097 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15098 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15099 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15100 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15101 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15102 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15103 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15104 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15105 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15106 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15107 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15108 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15109 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15110 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15111 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15112 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15113 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15114 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15115 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15116 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15117 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15118 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15119 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15120 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15121 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15122 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15123 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15124 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15125 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15126 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15127 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15128 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15129 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15130 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15131 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15132 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15133 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15134 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15135 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15136 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15137 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15138 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15139 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15140 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15141 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15142 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15143 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15144 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15145 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15146 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15147 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15148 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15149 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15150 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15151 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15152 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15153 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15154 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15155 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15156 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15157 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15158 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15159 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15160 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15161 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15162 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15163 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15164 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15165 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15166 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15167 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15168 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15169 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15170 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15171 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15172 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15173 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15174 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15175 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15176 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15177 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15178 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15179 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15180 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15181 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15182 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15183 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15184 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15185 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15186 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15187 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15188 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15189 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15190 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15191 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15192 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15193 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15194 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15195 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15196 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15197 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15198 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15199 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15200 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15201 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15202 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15203 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15204 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15205 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15206 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15207 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15208 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15209 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15210 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15211 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15212 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15213 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15214 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15215 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15216 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15217 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15218 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15219 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15220 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15221 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15222 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15223 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15224 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15225 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15226 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15227 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15228 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15229 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15230 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15231 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15232 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15233 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15234 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15235 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15236 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15237 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15238 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15239 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15240 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15241 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15242 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15243 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15244 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15245 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15246 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15247 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15248 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15249 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15250 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15251 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15252 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15253 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15254 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15255 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15256 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15257 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15258 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15259 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15260 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15261 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15262 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15263 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15264 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15265 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15266 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15267 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15268 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15269 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15270 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15271 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15272 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15273 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15274 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15275 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15276 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15277 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15278 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15279 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15280 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15281 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15282 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15283 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15284 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15285 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15286 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15287 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15288 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15289 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15290 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15291 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15292 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15293 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15294 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15295 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15296 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15297 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15298 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15299 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15300 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15301 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15302 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15303 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15304 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15305 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15306 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15307 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15308 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15309 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15310 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15311 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15312 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15313 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15314 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15315 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15316 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15317 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15318 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15319 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15320 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15321 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15322 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15323 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15324 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15325 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15326 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15327 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15328 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15329 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15330 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15331 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15332 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15333 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15334 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15335 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15336 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15337 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15338 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15339 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15340 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15341 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15342 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15343 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15344 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15345 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15346 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15347 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15348 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15349 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15350 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15351 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15352 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15353 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15354 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15355 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15356 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15357 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15358 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15359 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15360 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15361 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15362 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15363 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15364 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15365 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15366 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15367 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15368 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15369 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15370 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15371 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15372 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15373 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15374 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15375 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15376 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15377 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15378 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15379 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15380 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15381 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15382 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15383 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15384 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15385 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15386 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15387 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15388 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15389 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15390 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15391 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15392 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15393 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15394 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15395 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15396 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15397 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15398 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15399 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15400 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15401 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15402 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15403 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15404 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15405 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15406 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15407 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15408 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15409 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15410 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15411 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15412 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15413 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15414 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15415 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15416 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15417 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15418 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15419 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15420 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15421 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15422 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15423 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15424 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15425 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15426 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15427 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15428 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15429 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15430 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15431 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15432 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15433 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15434 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15435 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15436 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15437 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15438 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15439 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15440 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15441 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15442 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15443 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15444 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15445 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15446 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15447 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15448 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15449 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15450 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15451 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15452 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15453 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15454 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15455 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15456 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15457 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15458 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15459 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15460 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15461 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15462 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15463 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15464 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15465 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15466 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15467 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15468 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15469 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15470 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15471 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15472 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15473 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15474 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15475 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15476 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15477 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15478 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15479 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15480 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15481 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15482 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15483 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15484 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15485 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15486 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15487 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15488 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15489 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15490 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15491 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15492 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15493 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15494 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15495 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15496 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15497 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15498 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15499 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15500 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15501 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15502 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15503 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15504 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15505 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15506 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15507 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15508 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15509 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15510 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15511 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15512 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15513 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15514 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15515 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15516 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15517 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15518 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15519 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15520 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15521 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15522 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15523 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15524 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15525 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15526 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15527 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15528 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15529 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15530 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15531 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15532 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15533 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15534 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15535 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15536 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15537 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15538 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15539 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15540 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15541 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15542 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15543 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15544 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15545 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15546 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15547 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15548 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15549 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15550 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15551 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15552 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15553 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15554 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15555 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15556 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15557 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15558 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15559 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15560 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15561 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15562 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15563 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15564 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15565 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15566 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15567 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15568 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15569 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15570 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15571 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15572 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15573 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15574 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15575 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15576 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15577 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15578 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15579 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15580 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15581 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15582 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15583 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15584 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15585 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15586 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15587 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15588 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15589 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15590 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15591 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15592 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15593 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15594 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15595 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15596 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15597 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15598 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15599 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15600 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15601 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15602 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15603 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15604 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15605 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15606 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15607 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15608 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15609 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15610 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15611 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15612 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15613 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15614 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15615 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15616 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15617 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15618 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15619 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15620 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15621 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15622 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15623 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15624 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15625 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15626 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15627 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15628 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15629 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15630 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15631 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15632 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15633 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15634 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15635 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15636 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15637 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15638 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15639 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15640 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15641 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15642 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15643 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15644 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15645 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15646 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15647 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15648 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15649 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15650 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V12_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15651 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V12_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15652 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V12_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15653 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V12_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15654 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V12_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15655 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15656 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15657 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15658 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15659 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15660 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15661 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15662 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15663 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15664 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15665 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15666 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15667 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15668 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15669 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15670 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15671 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15672 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15673 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15674 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15675 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15676 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15677 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15678 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15679 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15680 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15681 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15682 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15683 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15684 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15685 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15686 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15687 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15688 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15689 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15690 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15691 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15692 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15693 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15694 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15695 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15696 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15697 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15698 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15699 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15700 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15701 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15702 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15703 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15704 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15705 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15706 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15707 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15708 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15709 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15710 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15711 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15712 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15713 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15714 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15715 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15716 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15717 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15718 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15719 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15720 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15721 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15722 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15723 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15724 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15725 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15726 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15727 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15728 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15729 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15730 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15731 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15732 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15733 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15734 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15735 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15736 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15737 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15738 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15739 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15740 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15741 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15742 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15743 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15744 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15745 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15746 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15747 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15748 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15749 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15750 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15751 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15752 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15753 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15754 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15755 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15756 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15757 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15758 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15759 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15760 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15761 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15762 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15763 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15764 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15765 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15766 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15767 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15768 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15769 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15770 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15771 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15772 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15773 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15774 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15775 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15776 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15777 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15778 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15779 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15780 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15781 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15782 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15783 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15784 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15785 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15786 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15787 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15788 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15789 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15790 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15791 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15792 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15793 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15794 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15795 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15796 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15797 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15798 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15799 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15800 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15801 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15802 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15803 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15804 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15805 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15806 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15807 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15808 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15809 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15810 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15811 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15812 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15813 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15814 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15815 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15816 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15817 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15818 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15819 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15820 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15821 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15822 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15823 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15824 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15825 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15826 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15827 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15828 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15829 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15830 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15831 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15832 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15833 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15834 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15835 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15836 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15837 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15838 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15839 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15840 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15841 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15842 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15843 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15844 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15845 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15846 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15847 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15848 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15849 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15850 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15851 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15852 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15853 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15854 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15855 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15856 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15857 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15858 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15859 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15860 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15861 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15862 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15863 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15864 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15865 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15866 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15867 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15868 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15869 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15870 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15871 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15872 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15873 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15874 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15875 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15876 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15877 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15878 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15879 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15880 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15881 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15882 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15883 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15884 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15885 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15886 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15887 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15888 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15889 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15890 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15891 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15892 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15893 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15894 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15895 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15896 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15897 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15898 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15899 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15900 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15901 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15902 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15903 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15904 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15905 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15906 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15907 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15908 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15909 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15910 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15911 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15912 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15913 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15914 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15915 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15916 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15917 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15918 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15919 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15920 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15921 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15922 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15923 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15924 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15925 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15926 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15927 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15928 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15929 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15930 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15931 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15932 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15933 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15934 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15935 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15936 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15937 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15938 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15939 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15940 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15941 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15942 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15943 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15944 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15945 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15946 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15947 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15948 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15949 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15950 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15951 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15952 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15953 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15954 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15955 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15956 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15957 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15958 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15959 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15960 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15961 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15962 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15963 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15964 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15965 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15966 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15967 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15968 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15969 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15970 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15971 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15972 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15973 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15974 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15975 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15976 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15977 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15978 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15979 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15980 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15981 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15982 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15983 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15984 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15985 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15986 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15987 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15988 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15989 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15990 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15991 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15992 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15993 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15994 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15995 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15996 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15997 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15998 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15999 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16000 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16001 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16002 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16003 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16004 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16005 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16006 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16007 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16008 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16009 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16010 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16011 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16012 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16013 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16014 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16015 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16016 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16017 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16018 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16019 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16020 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16021 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16022 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16023 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16024 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16025 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16026 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16027 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16028 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16029 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16030 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16031 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16032 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16033 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16034 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16035 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16036 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16037 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16038 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16039 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16040 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V12_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16041 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V12_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16042 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V12_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16043 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V12_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16044 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V12_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16045 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16046 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16047 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16048 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16049 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16050 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16051 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16052 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16053 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16054 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16055 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16056 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16057 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16058 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16059 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16060 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16061 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16062 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16063 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16064 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16065 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16066 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16067 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16068 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16069 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16070 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16071 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16072 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16073 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16074 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16075 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16076 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16077 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16078 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16079 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16080 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16081 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16082 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16083 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16084 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16085 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16086 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16087 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16088 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16089 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16090 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16091 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16092 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16093 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16094 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16095 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16096 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16097 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16098 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16099 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16100 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16101 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16102 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16103 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16104 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16105 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16106 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16107 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16108 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16109 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16110 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16111 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16112 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16113 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16114 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16115 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16116 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16117 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16118 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16119 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16120 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16121 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16122 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16123 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16124 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16125 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16126 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16127 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16128 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16129 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16130 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16131 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16132 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16133 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16134 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16135 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16136 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16137 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16138 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16139 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16140 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16141 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16142 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16143 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16144 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16145 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16146 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16147 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16148 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16149 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16150 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16151 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16152 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16153 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16154 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16155 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16156 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16157 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16158 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16159 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16160 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16161 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16162 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16163 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16164 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16165 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16166 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16167 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16168 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16169 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16170 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16171 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16172 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16173 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16174 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16175 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16176 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16177 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16178 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16179 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16180 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16181 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16182 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16183 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16184 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16185 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16186 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16187 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16188 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16189 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16190 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16191 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16192 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16193 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16194 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16195 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16196 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16197 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16198 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16199 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16200 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16201 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16202 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16203 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16204 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16205 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16206 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16207 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16208 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16209 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16210 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16211 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16212 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16213 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16214 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16215 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16216 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16217 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16218 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16219 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16220 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16221 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16222 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16223 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16224 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16225 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16226 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16227 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16228 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16229 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16230 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16231 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16232 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16233 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16234 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16235 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16236 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16237 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16238 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16239 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16240 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16241 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16242 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16243 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16244 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16245 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16246 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16247 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16248 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16249 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16250 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16251 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16252 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16253 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16254 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16255 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16256 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16257 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16258 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16259 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16260 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16261 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16262 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16263 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16264 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16265 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16266 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16267 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16268 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16269 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16270 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16271 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16272 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16273 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16274 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16275 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16276 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16277 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16278 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16279 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16280 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16281 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16282 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16283 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16284 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16285 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16286 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16287 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16288 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16289 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16290 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16291 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16292 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16293 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16294 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16295 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16296 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16297 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16298 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16299 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16300 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16301 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16302 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16303 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16304 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16305 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16306 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16307 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16308 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16309 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16310 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16311 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16312 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16313 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16314 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16315 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16316 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16317 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16318 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16319 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16320 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16321 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16322 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16323 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16324 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16325 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16326 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16327 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16328 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16329 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16330 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16331 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16332 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16333 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16334 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16335 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16336 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16337 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16338 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16339 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16340 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16341 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16342 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16343 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16344 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16345 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16346 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16347 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16348 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16349 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16350 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16351 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16352 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16353 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16354 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16355 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16356 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16357 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16358 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16359 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16360 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16361 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16362 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16363 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16364 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16365 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16366 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16367 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16368 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16369 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16370 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16371 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16372 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16373 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16374 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16375 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16376 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16377 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16378 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16379 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16380 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16381 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16382 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16383 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16384 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16385 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16386 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16387 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16388 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16389 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16390 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16391 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16392 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16393 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16394 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16395 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16396 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16397 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16398 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16399 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16400 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16401 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16402 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16403 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16404 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16405 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16406 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16407 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16408 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16409 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16410 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16411 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16412 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16413 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16414 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16415 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16416 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16417 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16418 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16419 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16420 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16421 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16422 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16423 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16424 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16425 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16426 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16427 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16428 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16429 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16430 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16431 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16432 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16433 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16434 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16435 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16436 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16437 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16438 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16439 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16440 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16441 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16442 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16443 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16444 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16445 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16446 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16447 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16448 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16449 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16450 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16451 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16452 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16453 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16454 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16455 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16456 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16457 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16458 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16459 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16460 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16461 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16462 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16463 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16464 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16465 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16466 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16467 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16468 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16469 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16470 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16471 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16472 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16473 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16474 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16475 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16476 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16477 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16478 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16479 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16480 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16481 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16482 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16483 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16484 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16485 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16486 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16487 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16488 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16489 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16490 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16491 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16492 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16493 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16494 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16495 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16496 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16497 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16498 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16499 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16500 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16501 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16502 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16503 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16504 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16505 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16506 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16507 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16508 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16509 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16510 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16511 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16512 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16513 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16514 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16515 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16516 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16517 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16518 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16519 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16520 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16521 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16522 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16523 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16524 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16525 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16526 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16527 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16528 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16529 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16530 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16531 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16532 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16533 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16534 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16535 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16536 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16537 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16538 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16539 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16540 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16541 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16542 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16543 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16544 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16545 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16546 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16547 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16548 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16549 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16550 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16551 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16552 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16553 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16554 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16555 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16556 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16557 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16558 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16559 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16560 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16561 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16562 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16563 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16564 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16565 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16566 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16567 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16568 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16569 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16570 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16571 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16572 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16573 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16574 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16575 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16576 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16577 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16578 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16579 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16580 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16581 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16582 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16583 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16584 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16585 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16586 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16587 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16588 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16589 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16590 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16591 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16592 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16593 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16594 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16595 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16596 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16597 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16598 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16599 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16600 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16601 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16602 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16603 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16604 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16605 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16606 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16607 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16608 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16609 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16610 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16611 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16612 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16613 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16614 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16615 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16616 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16617 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16618 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16619 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16620 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16621 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16622 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16623 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16624 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16625 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16626 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16627 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16628 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16629 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16630 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16631 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16632 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16633 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16634 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16635 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16636 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16637 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16638 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16639 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16640 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16641 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16642 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16643 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16644 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16645 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16646 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16647 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16648 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16649 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16650 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16651 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16652 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16653 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16654 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16655 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16656 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16657 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16658 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16659 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16660 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16661 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16662 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16663 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16664 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16665 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16666 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16667 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16668 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16669 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16670 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16671 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16672 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16673 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16674 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16675 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16676 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16677 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16678 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16679 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16680 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16681 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16682 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16683 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16684 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16685 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16686 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16687 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16688 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16689 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16690 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16691 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16692 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16693 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16694 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16695 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16696 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16697 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16698 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16699 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16700 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16701 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16702 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16703 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16704 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16705 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16706 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16707 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16708 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16709 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16710 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16711 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16712 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16713 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16714 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16715 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16716 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16717 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16718 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16719 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16720 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16721 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16722 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16723 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16724 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16725 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16726 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16727 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16728 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16729 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16730 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16731 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16732 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16733 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16734 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16735 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16736 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16737 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16738 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16739 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16740 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16741 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16742 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16743 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16744 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16745 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16746 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16747 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16748 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16749 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16750 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16751 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16752 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16753 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16754 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16755 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16756 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16757 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16758 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16759 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16760 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16761 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16762 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16763 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16764 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16765 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16766 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16767 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16768 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16769 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16770 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16771 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16772 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16773 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16774 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16775 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16776 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16777 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16778 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16779 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16780 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16781 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16782 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16783 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16784 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16785 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16786 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16787 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16788 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16789 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16790 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16791 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16792 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16793 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16794 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16795 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16796 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16797 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16798 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16799 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16800 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16801 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16802 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16803 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16804 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16805 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16806 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16807 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16808 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16809 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16810 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16811 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16812 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16813 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16814 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16815 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16816 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16817 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16818 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16819 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16820 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16821 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16822 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16823 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16824 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16825 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16826 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16827 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16828 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16829 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16830 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16831 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16832 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16833 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16834 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16835 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16836 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16837 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16838 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16839 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16840 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16841 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16842 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16843 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16844 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16845 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16846 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16847 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16848 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16849 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16850 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16851 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16852 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16853 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16854 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16855 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16856 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16857 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16858 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16859 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16860 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16861 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16862 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16863 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16864 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16865 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16866 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16867 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16868 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16869 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16870 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16871 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16872 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16873 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16874 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16875 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16876 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16877 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16878 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16879 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16880 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16881 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16882 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16883 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16884 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16885 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16886 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16887 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16888 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16889 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16890 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16891 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16892 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16893 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16894 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16895 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16896 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16897 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16898 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16899 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16900 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16901 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16902 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16903 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16904 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16905 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16906 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16907 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16908 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16909 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16910 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16911 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16912 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16913 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16914 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16915 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16916 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16917 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16918 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16919 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16920 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16921 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16922 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16923 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16924 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16925 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16926 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16927 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16928 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16929 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16930 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16931 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16932 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16933 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16934 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16935 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16936 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16937 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16938 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16939 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16940 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16941 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16942 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16943 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16944 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16945 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16946 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16947 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16948 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16949 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16950 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16951 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16952 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16953 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16954 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16955 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16956 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16957 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16958 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16959 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16960 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16961 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16962 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16963 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16964 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16965 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16966 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16967 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16968 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16969 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16970 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16971 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16972 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16973 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16974 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16975 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16976 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16977 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16978 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16979 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16980 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16981 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16982 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16983 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16984 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16985 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16986 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16987 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16988 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16989 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16990 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16991 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16992 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16993 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16994 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16995 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16996 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16997 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16998 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16999 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17000 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17001 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17002 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17003 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17004 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17005 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17006 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17007 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17008 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17009 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17010 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17011 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17012 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17013 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17014 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17015 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17016 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17017 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17018 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17019 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17020 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17021 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17022 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17023 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17024 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17025 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17026 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17027 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17028 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17029 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17030 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17031 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17032 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17033 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17034 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17035 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17036 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17037 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17038 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17039 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17040 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17041 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17042 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17043 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17044 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17045 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17046 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17047 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17048 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17049 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17050 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17051 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17052 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17053 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17054 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17055 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17056 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17057 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17058 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17059 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17060 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17061 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17062 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17063 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17064 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17065 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17066 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17067 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17068 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17069 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17070 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17071 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17072 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17073 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17074 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17075 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17076 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17077 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17078 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17079 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17080 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17081 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17082 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17083 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17084 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17085 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17086 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17087 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17088 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17089 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17090 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17091 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17092 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17093 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17094 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17095 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17096 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17097 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17098 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17099 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17100 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17101 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17102 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17103 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17104 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17105 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17106 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17107 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17108 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17109 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17110 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17111 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17112 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17113 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17114 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17115 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17116 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17117 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17118 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17119 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17120 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17121 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17122 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17123 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17124 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17125 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17126 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17127 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17128 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17129 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17130 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17131 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17132 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17133 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17134 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17135 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17136 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17137 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17138 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17139 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17140 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17141 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17142 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17143 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17144 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17145 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17146 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17147 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17148 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17149 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17150 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17151 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17152 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17153 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17154 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17155 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17156 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17157 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17158 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17159 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17160 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17161 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17162 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17163 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17164 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17165 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17166 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17167 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17168 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17169 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17170 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17171 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17172 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17173 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17174 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17175 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17176 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17177 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17178 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17179 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17180 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17181 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17182 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17183 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17184 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17185 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17186 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17187 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17188 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17189 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17190 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17191 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17192 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17193 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17194 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17195 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17196 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17197 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17198 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17199 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17200 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17201 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17202 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17203 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17204 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17205 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17206 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17207 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17208 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17209 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17210 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17211 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17212 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17213 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17214 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17215 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17216 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17217 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17218 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17219 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17220 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17221 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17222 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17223 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17224 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17225 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17226 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17227 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17228 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17229 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17230 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17231 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17232 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17233 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17234 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17235 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17236 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17237 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17238 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17239 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17240 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17241 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17242 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17243 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17244 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17245 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17246 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17247 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17248 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17249 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17250 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17251 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17252 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17253 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17254 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17255 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17256 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17257 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17258 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17259 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17260 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17261 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17262 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17263 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17264 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17265 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17266 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17267 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17268 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17269 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17270 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17271 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17272 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17273 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17274 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17275 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17276 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17277 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17278 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17279 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17280 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17281 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17282 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17283 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17284 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17285 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17286 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17287 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17288 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17289 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17290 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17291 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17292 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17293 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17294 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17295 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17296 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17297 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17298 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17299 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17300 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17301 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17302 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17303 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17304 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17305 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17306 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17307 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17308 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17309 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17310 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17311 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17312 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17313 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17314 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17315 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17316 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17317 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17318 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17319 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17320 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17321 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17322 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17323 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17324 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17325 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17326 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17327 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17328 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17329 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17330 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17331 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17332 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17333 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17334 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17335 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17336 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17337 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17338 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17339 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17340 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17341 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17342 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17343 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17344 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17345 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17346 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17347 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17348 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17349 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17350 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17351 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17352 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17353 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17354 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17355 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17356 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17357 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17358 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17359 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17360 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17361 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17362 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17363 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17364 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17365 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17366 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17367 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17368 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17369 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17370 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17371 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17372 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17373 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17374 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17375 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17376 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17377 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17378 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17379 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17380 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17381 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17382 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17383 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17384 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17385 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17386 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17387 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17388 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17389 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17390 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17391 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17392 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17393 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17394 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17395 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17396 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17397 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17398 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17399 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17400 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17401 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17402 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17403 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17404 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17405 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17406 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17407 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17408 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17409 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17410 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17411 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17412 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17413 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17414 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17415 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17416 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17417 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17418 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17419 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17420 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17421 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17422 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17423 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17424 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17425 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17426 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17427 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17428 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17429 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17430 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17431 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17432 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17433 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17434 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17435 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17436 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17437 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17438 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17439 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17440 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17441 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17442 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17443 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17444 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17445 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17446 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17447 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17448 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17449 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17450 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17451 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17452 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17453 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17454 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17455 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17456 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17457 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17458 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17459 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17460 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17461 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17462 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17463 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17464 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17465 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17466 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17467 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17468 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17469 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17470 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17471 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17472 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17473 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17474 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17475 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17476 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17477 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17478 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17479 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17480 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17481 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17482 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17483 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17484 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17485 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17486 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17487 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17488 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17489 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17490 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17491 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17492 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17493 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17494 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17495 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17496 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17497 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17498 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17499 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17500 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17501 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17502 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17503 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17504 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17505 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17506 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17507 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17508 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17509 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17510 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17511 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17512 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17513 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17514 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17515 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17516 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17517 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17518 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17519 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17520 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17521 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17522 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17523 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17524 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17525 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17526 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17527 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17528 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17529 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17530 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17531 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17532 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17533 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17534 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17535 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17536 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17537 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17538 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17539 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17540 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
18563 { 12271 /* scratch_load_dword */, AMDGPU::SCRATCH_LOAD_DWORD_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18564 { 12271 /* scratch_load_dword */, AMDGPU::SCRATCH_LOAD_DWORD_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18565 { 12271 /* scratch_load_dword */, AMDGPU::SCRATCH_LOAD_DWORD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18566 { 12271 /* scratch_load_dword */, AMDGPU::SCRATCH_LOAD_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18567 { 12290 /* scratch_load_dwordx2 */, AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18568 { 12290 /* scratch_load_dwordx2 */, AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18569 { 12290 /* scratch_load_dwordx2 */, AMDGPU::SCRATCH_LOAD_DWORDX2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18570 { 12290 /* scratch_load_dwordx2 */, AMDGPU::SCRATCH_LOAD_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18571 { 12311 /* scratch_load_dwordx3 */, AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18572 { 12311 /* scratch_load_dwordx3 */, AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18573 { 12311 /* scratch_load_dwordx3 */, AMDGPU::SCRATCH_LOAD_DWORDX3_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18574 { 12311 /* scratch_load_dwordx3 */, AMDGPU::SCRATCH_LOAD_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18575 { 12332 /* scratch_load_dwordx4 */, AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18576 { 12332 /* scratch_load_dwordx4 */, AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18577 { 12332 /* scratch_load_dwordx4 */, AMDGPU::SCRATCH_LOAD_DWORDX4_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18578 { 12332 /* scratch_load_dwordx4 */, AMDGPU::SCRATCH_LOAD_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18579 { 12353 /* scratch_load_sbyte */, AMDGPU::SCRATCH_LOAD_SBYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18580 { 12353 /* scratch_load_sbyte */, AMDGPU::SCRATCH_LOAD_SBYTE_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18581 { 12353 /* scratch_load_sbyte */, AMDGPU::SCRATCH_LOAD_SBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18582 { 12353 /* scratch_load_sbyte */, AMDGPU::SCRATCH_LOAD_SBYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18583 { 12372 /* scratch_load_sbyte_d16 */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18584 { 12372 /* scratch_load_sbyte_d16 */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18585 { 12372 /* scratch_load_sbyte_d16 */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18586 { 12372 /* scratch_load_sbyte_d16 */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18587 { 12395 /* scratch_load_sbyte_d16_hi */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18588 { 12395 /* scratch_load_sbyte_d16_hi */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18589 { 12395 /* scratch_load_sbyte_d16_hi */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18590 { 12395 /* scratch_load_sbyte_d16_hi */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18591 { 12421 /* scratch_load_short_d16 */, AMDGPU::SCRATCH_LOAD_SHORT_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18592 { 12421 /* scratch_load_short_d16 */, AMDGPU::SCRATCH_LOAD_SHORT_D16_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18593 { 12421 /* scratch_load_short_d16 */, AMDGPU::SCRATCH_LOAD_SHORT_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18594 { 12421 /* scratch_load_short_d16 */, AMDGPU::SCRATCH_LOAD_SHORT_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18595 { 12444 /* scratch_load_short_d16_hi */, AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18596 { 12444 /* scratch_load_short_d16_hi */, AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18597 { 12444 /* scratch_load_short_d16_hi */, AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18598 { 12444 /* scratch_load_short_d16_hi */, AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18599 { 12470 /* scratch_load_sshort */, AMDGPU::SCRATCH_LOAD_SSHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18600 { 12470 /* scratch_load_sshort */, AMDGPU::SCRATCH_LOAD_SSHORT_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18601 { 12470 /* scratch_load_sshort */, AMDGPU::SCRATCH_LOAD_SSHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18602 { 12470 /* scratch_load_sshort */, AMDGPU::SCRATCH_LOAD_SSHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18603 { 12490 /* scratch_load_ubyte */, AMDGPU::SCRATCH_LOAD_UBYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18604 { 12490 /* scratch_load_ubyte */, AMDGPU::SCRATCH_LOAD_UBYTE_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18605 { 12490 /* scratch_load_ubyte */, AMDGPU::SCRATCH_LOAD_UBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18606 { 12490 /* scratch_load_ubyte */, AMDGPU::SCRATCH_LOAD_UBYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18607 { 12509 /* scratch_load_ubyte_d16 */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18608 { 12509 /* scratch_load_ubyte_d16 */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18609 { 12509 /* scratch_load_ubyte_d16 */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18610 { 12509 /* scratch_load_ubyte_d16 */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18611 { 12532 /* scratch_load_ubyte_d16_hi */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18612 { 12532 /* scratch_load_ubyte_d16_hi */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18613 { 12532 /* scratch_load_ubyte_d16_hi */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18614 { 12532 /* scratch_load_ubyte_d16_hi */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18615 { 12558 /* scratch_load_ushort */, AMDGPU::SCRATCH_LOAD_USHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18616 { 12558 /* scratch_load_ushort */, AMDGPU::SCRATCH_LOAD_USHORT_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18617 { 12558 /* scratch_load_ushort */, AMDGPU::SCRATCH_LOAD_USHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18618 { 12558 /* scratch_load_ushort */, AMDGPU::SCRATCH_LOAD_USHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18619 { 12578 /* scratch_store_byte */, AMDGPU::SCRATCH_STORE_BYTE_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18620 { 12578 /* scratch_store_byte */, AMDGPU::SCRATCH_STORE_BYTE_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18621 { 12578 /* scratch_store_byte */, AMDGPU::SCRATCH_STORE_BYTE_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18622 { 12578 /* scratch_store_byte */, AMDGPU::SCRATCH_STORE_BYTE_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18623 { 12597 /* scratch_store_byte_d16_hi */, AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18624 { 12597 /* scratch_store_byte_d16_hi */, AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18625 { 12597 /* scratch_store_byte_d16_hi */, AMDGPU::SCRATCH_STORE_BYTE_D16_HI_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18626 { 12597 /* scratch_store_byte_d16_hi */, AMDGPU::SCRATCH_STORE_BYTE_D16_HI_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18627 { 12623 /* scratch_store_dword */, AMDGPU::SCRATCH_STORE_DWORD_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18628 { 12623 /* scratch_store_dword */, AMDGPU::SCRATCH_STORE_DWORD_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18629 { 12623 /* scratch_store_dword */, AMDGPU::SCRATCH_STORE_DWORD_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18630 { 12623 /* scratch_store_dword */, AMDGPU::SCRATCH_STORE_DWORD_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18631 { 12643 /* scratch_store_dwordx2 */, AMDGPU::SCRATCH_STORE_DWORDX2_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VReg_64, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18632 { 12643 /* scratch_store_dwordx2 */, AMDGPU::SCRATCH_STORE_DWORDX2_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VReg_64, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18633 { 12643 /* scratch_store_dwordx2 */, AMDGPU::SCRATCH_STORE_DWORDX2_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18634 { 12643 /* scratch_store_dwordx2 */, AMDGPU::SCRATCH_STORE_DWORDX2_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18635 { 12665 /* scratch_store_dwordx3 */, AMDGPU::SCRATCH_STORE_DWORDX3_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VReg_96, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18636 { 12665 /* scratch_store_dwordx3 */, AMDGPU::SCRATCH_STORE_DWORDX3_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VReg_96, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18637 { 12665 /* scratch_store_dwordx3 */, AMDGPU::SCRATCH_STORE_DWORDX3_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18638 { 12665 /* scratch_store_dwordx3 */, AMDGPU::SCRATCH_STORE_DWORDX3_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18639 { 12687 /* scratch_store_dwordx4 */, AMDGPU::SCRATCH_STORE_DWORDX4_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VReg_128, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18640 { 12687 /* scratch_store_dwordx4 */, AMDGPU::SCRATCH_STORE_DWORDX4_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VReg_128, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18641 { 12687 /* scratch_store_dwordx4 */, AMDGPU::SCRATCH_STORE_DWORDX4_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18642 { 12687 /* scratch_store_dwordx4 */, AMDGPU::SCRATCH_STORE_DWORDX4_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18643 { 12709 /* scratch_store_short */, AMDGPU::SCRATCH_STORE_SHORT_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18644 { 12709 /* scratch_store_short */, AMDGPU::SCRATCH_STORE_SHORT_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18645 { 12709 /* scratch_store_short */, AMDGPU::SCRATCH_STORE_SHORT_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18646 { 12709 /* scratch_store_short */, AMDGPU::SCRATCH_STORE_SHORT_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18647 { 12729 /* scratch_store_short_d16_hi */, AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18648 { 12729 /* scratch_store_short_d16_hi */, AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18649 { 12729 /* scratch_store_short_d16_hi */, AMDGPU::SCRATCH_STORE_SHORT_D16_HI_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18650 { 12729 /* scratch_store_short_d16_hi */, AMDGPU::SCRATCH_STORE_SHORT_D16_HI_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18651 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18652 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18653 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18654 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18655 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18656 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18657 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18658 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18659 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18660 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18661 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18662 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18663 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18664 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18665 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18666 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18667 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18668 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18669 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18670 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18671 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18672 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18673 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18674 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18675 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18676 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18677 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18678 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18679 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18680 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18681 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18682 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18683 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18684 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18685 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18686 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18687 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18688 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18689 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18690 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18691 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18692 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18693 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18694 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18695 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18696 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18697 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18698 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18699 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18700 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18701 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18702 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18703 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18704 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18705 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18706 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18707 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18708 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18709 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18710 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18711 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18712 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18713 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18714 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18715 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18716 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18717 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18718 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18719 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18720 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18721 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18722 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18723 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18724 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18725 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18726 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18727 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18728 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18729 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18730 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18731 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18732 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18733 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18734 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18735 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18736 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18737 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18738 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18739 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18740 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18741 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18742 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18743 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18744 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18745 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18746 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18747 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18748 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18749 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18750 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18751 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18752 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18753 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18754 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18755 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18756 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18757 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18758 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18759 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18760 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18761 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18762 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18763 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18764 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18765 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18766 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18767 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18768 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18769 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18770 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18771 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18772 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18773 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18774 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18775 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18776 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18777 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18778 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18779 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18780 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18781 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18782 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18783 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18784 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18785 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18786 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18787 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18788 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18789 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18790 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18791 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18792 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18793 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18794 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18795 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18796 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18797 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18798 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18799 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18800 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18801 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18802 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18803 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18804 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18805 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18806 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18807 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18808 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18809 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18810 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18811 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18812 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18813 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18814 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18815 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18816 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18817 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18818 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18819 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18820 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18821 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18822 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18823 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18824 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18825 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18826 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18827 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18828 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18829 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18830 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18831 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18832 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18833 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18834 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18835 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18836 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18837 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18838 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18839 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18840 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18841 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18842 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18843 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18844 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18845 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18846 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18847 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18848 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18849 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18850 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
24158 { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24160 { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24162 { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24164 { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24166 { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24168 { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24170 { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24172 { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24174 { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24176 { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24178 { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24180 { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24182 { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24184 { 0 /* buffer_atomic_add */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24186 { 0 /* buffer_atomic_add */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24188 { 0 /* buffer_atomic_add */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24190 { 0 /* buffer_atomic_add */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24192 { 0 /* buffer_atomic_add */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24194 { 0 /* buffer_atomic_add */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24196 { 0 /* buffer_atomic_add */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24198 { 0 /* buffer_atomic_add */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24200 { 0 /* buffer_atomic_add */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24202 { 0 /* buffer_atomic_add */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24204 { 0 /* buffer_atomic_add */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24206 { 0 /* buffer_atomic_add */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24208 { 0 /* buffer_atomic_add */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24210 { 18 /* buffer_atomic_add_f32 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
24212 { 18 /* buffer_atomic_add_f32 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
24214 { 18 /* buffer_atomic_add_f32 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
24216 { 18 /* buffer_atomic_add_f32 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
24218 { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24220 { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24222 { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24224 { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24226 { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24228 { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24230 { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24232 { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24234 { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24236 { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24238 { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24240 { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24242 { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24244 { 40 /* buffer_atomic_add_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24246 { 40 /* buffer_atomic_add_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24248 { 40 /* buffer_atomic_add_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24250 { 40 /* buffer_atomic_add_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24252 { 40 /* buffer_atomic_add_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24254 { 40 /* buffer_atomic_add_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24256 { 40 /* buffer_atomic_add_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24258 { 40 /* buffer_atomic_add_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24260 { 40 /* buffer_atomic_add_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24262 { 40 /* buffer_atomic_add_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24264 { 40 /* buffer_atomic_add_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24266 { 40 /* buffer_atomic_add_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24268 { 40 /* buffer_atomic_add_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24270 { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24272 { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24274 { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24276 { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24278 { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24280 { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24282 { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24284 { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24286 { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24288 { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24290 { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24292 { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24294 { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24296 { 61 /* buffer_atomic_and */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24298 { 61 /* buffer_atomic_and */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24300 { 61 /* buffer_atomic_and */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24302 { 61 /* buffer_atomic_and */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24304 { 61 /* buffer_atomic_and */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24306 { 61 /* buffer_atomic_and */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24308 { 61 /* buffer_atomic_and */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24310 { 61 /* buffer_atomic_and */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24312 { 61 /* buffer_atomic_and */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24314 { 61 /* buffer_atomic_and */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24316 { 61 /* buffer_atomic_and */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24318 { 61 /* buffer_atomic_and */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24320 { 61 /* buffer_atomic_and */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24322 { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24324 { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24326 { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24328 { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24330 { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24332 { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24334 { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24336 { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24338 { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24340 { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24342 { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24344 { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24346 { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24348 { 79 /* buffer_atomic_and_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24350 { 79 /* buffer_atomic_and_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24352 { 79 /* buffer_atomic_and_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24354 { 79 /* buffer_atomic_and_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24356 { 79 /* buffer_atomic_and_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24358 { 79 /* buffer_atomic_and_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24360 { 79 /* buffer_atomic_and_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24362 { 79 /* buffer_atomic_and_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24364 { 79 /* buffer_atomic_and_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24366 { 79 /* buffer_atomic_and_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24368 { 79 /* buffer_atomic_and_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24370 { 79 /* buffer_atomic_and_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24372 { 79 /* buffer_atomic_and_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24374 { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24376 { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24378 { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24380 { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24382 { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24384 { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24386 { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24388 { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24390 { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24392 { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24394 { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24396 { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24398 { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24400 { 100 /* buffer_atomic_cmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24402 { 100 /* buffer_atomic_cmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24404 { 100 /* buffer_atomic_cmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24406 { 100 /* buffer_atomic_cmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24408 { 100 /* buffer_atomic_cmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24410 { 100 /* buffer_atomic_cmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24412 { 100 /* buffer_atomic_cmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24414 { 100 /* buffer_atomic_cmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24416 { 100 /* buffer_atomic_cmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24418 { 100 /* buffer_atomic_cmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24420 { 100 /* buffer_atomic_cmpswap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24422 { 100 /* buffer_atomic_cmpswap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24424 { 100 /* buffer_atomic_cmpswap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24426 { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24428 { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24430 { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24432 { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24434 { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24436 { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24438 { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24440 { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24442 { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24444 { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24446 { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24448 { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24450 { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24452 { 122 /* buffer_atomic_cmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24454 { 122 /* buffer_atomic_cmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24456 { 122 /* buffer_atomic_cmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24458 { 122 /* buffer_atomic_cmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24460 { 122 /* buffer_atomic_cmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24462 { 122 /* buffer_atomic_cmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24464 { 122 /* buffer_atomic_cmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24466 { 122 /* buffer_atomic_cmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24468 { 122 /* buffer_atomic_cmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24470 { 122 /* buffer_atomic_cmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24472 { 122 /* buffer_atomic_cmpswap_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24474 { 122 /* buffer_atomic_cmpswap_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24476 { 122 /* buffer_atomic_cmpswap_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24478 { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24480 { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24482 { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24484 { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24486 { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24488 { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24490 { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24492 { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24494 { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24496 { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24498 { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24500 { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24502 { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24504 { 147 /* buffer_atomic_dec */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24506 { 147 /* buffer_atomic_dec */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24508 { 147 /* buffer_atomic_dec */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24510 { 147 /* buffer_atomic_dec */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24512 { 147 /* buffer_atomic_dec */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24514 { 147 /* buffer_atomic_dec */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24516 { 147 /* buffer_atomic_dec */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24518 { 147 /* buffer_atomic_dec */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24520 { 147 /* buffer_atomic_dec */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24522 { 147 /* buffer_atomic_dec */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24524 { 147 /* buffer_atomic_dec */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24526 { 147 /* buffer_atomic_dec */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24528 { 147 /* buffer_atomic_dec */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24530 { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24532 { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24534 { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24536 { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24538 { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24540 { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24542 { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24544 { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24546 { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24548 { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24550 { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24552 { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24554 { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24556 { 165 /* buffer_atomic_dec_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24558 { 165 /* buffer_atomic_dec_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24560 { 165 /* buffer_atomic_dec_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24562 { 165 /* buffer_atomic_dec_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24564 { 165 /* buffer_atomic_dec_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24566 { 165 /* buffer_atomic_dec_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24568 { 165 /* buffer_atomic_dec_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24570 { 165 /* buffer_atomic_dec_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24572 { 165 /* buffer_atomic_dec_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24574 { 165 /* buffer_atomic_dec_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24576 { 165 /* buffer_atomic_dec_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24578 { 165 /* buffer_atomic_dec_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24580 { 165 /* buffer_atomic_dec_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24582 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24584 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24586 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24588 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24590 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24592 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24594 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24596 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24598 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24600 { 186 /* buffer_atomic_fcmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24602 { 186 /* buffer_atomic_fcmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24604 { 186 /* buffer_atomic_fcmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24606 { 186 /* buffer_atomic_fcmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24608 { 186 /* buffer_atomic_fcmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24610 { 186 /* buffer_atomic_fcmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24612 { 186 /* buffer_atomic_fcmpswap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24614 { 186 /* buffer_atomic_fcmpswap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24616 { 186 /* buffer_atomic_fcmpswap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24618 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24620 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24622 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24624 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24626 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24628 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24630 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24632 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24634 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24636 { 209 /* buffer_atomic_fcmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24638 { 209 /* buffer_atomic_fcmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24640 { 209 /* buffer_atomic_fcmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24642 { 209 /* buffer_atomic_fcmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24644 { 209 /* buffer_atomic_fcmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24646 { 209 /* buffer_atomic_fcmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24648 { 209 /* buffer_atomic_fcmpswap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24650 { 209 /* buffer_atomic_fcmpswap_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24652 { 209 /* buffer_atomic_fcmpswap_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24654 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24656 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24658 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24660 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24662 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24664 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24666 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24668 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24670 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24672 { 235 /* buffer_atomic_fmax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24674 { 235 /* buffer_atomic_fmax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24676 { 235 /* buffer_atomic_fmax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24678 { 235 /* buffer_atomic_fmax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24680 { 235 /* buffer_atomic_fmax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24682 { 235 /* buffer_atomic_fmax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24684 { 235 /* buffer_atomic_fmax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24686 { 235 /* buffer_atomic_fmax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24688 { 235 /* buffer_atomic_fmax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24690 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24692 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24694 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24696 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24698 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24700 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24702 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24704 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24706 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24708 { 254 /* buffer_atomic_fmax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24710 { 254 /* buffer_atomic_fmax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24712 { 254 /* buffer_atomic_fmax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24714 { 254 /* buffer_atomic_fmax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24716 { 254 /* buffer_atomic_fmax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24718 { 254 /* buffer_atomic_fmax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24720 { 254 /* buffer_atomic_fmax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24722 { 254 /* buffer_atomic_fmax_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24724 { 254 /* buffer_atomic_fmax_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24726 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24728 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24730 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24732 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24734 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24736 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24738 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24740 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24742 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24744 { 276 /* buffer_atomic_fmin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24746 { 276 /* buffer_atomic_fmin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24748 { 276 /* buffer_atomic_fmin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24750 { 276 /* buffer_atomic_fmin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24752 { 276 /* buffer_atomic_fmin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24754 { 276 /* buffer_atomic_fmin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24756 { 276 /* buffer_atomic_fmin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24758 { 276 /* buffer_atomic_fmin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24760 { 276 /* buffer_atomic_fmin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24762 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24764 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24766 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24768 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24770 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24772 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24774 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24776 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24778 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24780 { 295 /* buffer_atomic_fmin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24782 { 295 /* buffer_atomic_fmin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24784 { 295 /* buffer_atomic_fmin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24786 { 295 /* buffer_atomic_fmin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24788 { 295 /* buffer_atomic_fmin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24790 { 295 /* buffer_atomic_fmin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24792 { 295 /* buffer_atomic_fmin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24794 { 295 /* buffer_atomic_fmin_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24796 { 295 /* buffer_atomic_fmin_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24798 { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24800 { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24802 { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24804 { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24806 { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24808 { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24810 { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24812 { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24814 { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24816 { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24818 { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24820 { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24822 { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24824 { 317 /* buffer_atomic_inc */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24826 { 317 /* buffer_atomic_inc */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24828 { 317 /* buffer_atomic_inc */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24830 { 317 /* buffer_atomic_inc */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24832 { 317 /* buffer_atomic_inc */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24834 { 317 /* buffer_atomic_inc */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24836 { 317 /* buffer_atomic_inc */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24838 { 317 /* buffer_atomic_inc */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24840 { 317 /* buffer_atomic_inc */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24842 { 317 /* buffer_atomic_inc */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24844 { 317 /* buffer_atomic_inc */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24846 { 317 /* buffer_atomic_inc */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24848 { 317 /* buffer_atomic_inc */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24850 { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24852 { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24854 { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24856 { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24858 { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24860 { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24862 { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24864 { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24866 { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24868 { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24870 { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24872 { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24874 { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24876 { 335 /* buffer_atomic_inc_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24878 { 335 /* buffer_atomic_inc_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24880 { 335 /* buffer_atomic_inc_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24882 { 335 /* buffer_atomic_inc_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24884 { 335 /* buffer_atomic_inc_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24886 { 335 /* buffer_atomic_inc_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24888 { 335 /* buffer_atomic_inc_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24890 { 335 /* buffer_atomic_inc_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24892 { 335 /* buffer_atomic_inc_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24894 { 335 /* buffer_atomic_inc_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24896 { 335 /* buffer_atomic_inc_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24898 { 335 /* buffer_atomic_inc_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24900 { 335 /* buffer_atomic_inc_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24902 { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24904 { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24906 { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24908 { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24910 { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24912 { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24914 { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24916 { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24918 { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24920 { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24922 { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24924 { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24926 { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24928 { 356 /* buffer_atomic_or */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24930 { 356 /* buffer_atomic_or */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24932 { 356 /* buffer_atomic_or */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24934 { 356 /* buffer_atomic_or */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24936 { 356 /* buffer_atomic_or */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24938 { 356 /* buffer_atomic_or */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24940 { 356 /* buffer_atomic_or */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24942 { 356 /* buffer_atomic_or */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24944 { 356 /* buffer_atomic_or */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24946 { 356 /* buffer_atomic_or */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24948 { 356 /* buffer_atomic_or */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24950 { 356 /* buffer_atomic_or */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24952 { 356 /* buffer_atomic_or */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24954 { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24956 { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24958 { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24960 { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24962 { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24964 { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24966 { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24968 { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24970 { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24972 { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24974 { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24976 { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24978 { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24980 { 373 /* buffer_atomic_or_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24982 { 373 /* buffer_atomic_or_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24984 { 373 /* buffer_atomic_or_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24986 { 373 /* buffer_atomic_or_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24988 { 373 /* buffer_atomic_or_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24990 { 373 /* buffer_atomic_or_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24992 { 373 /* buffer_atomic_or_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
24994 { 373 /* buffer_atomic_or_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
24996 { 373 /* buffer_atomic_or_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
24998 { 373 /* buffer_atomic_or_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25000 { 373 /* buffer_atomic_or_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25002 { 373 /* buffer_atomic_or_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25004 { 373 /* buffer_atomic_or_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25006 { 393 /* buffer_atomic_pk_add_f16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
25008 { 393 /* buffer_atomic_pk_add_f16 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
25010 { 393 /* buffer_atomic_pk_add_f16 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
25012 { 393 /* buffer_atomic_pk_add_f16 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
25014 { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25016 { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25018 { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25020 { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25022 { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25024 { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25026 { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25028 { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25030 { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25032 { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25034 { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25036 { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25038 { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25040 { 418 /* buffer_atomic_smax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25042 { 418 /* buffer_atomic_smax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25044 { 418 /* buffer_atomic_smax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25046 { 418 /* buffer_atomic_smax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25048 { 418 /* buffer_atomic_smax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25050 { 418 /* buffer_atomic_smax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25052 { 418 /* buffer_atomic_smax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25054 { 418 /* buffer_atomic_smax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25056 { 418 /* buffer_atomic_smax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25058 { 418 /* buffer_atomic_smax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25060 { 418 /* buffer_atomic_smax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25062 { 418 /* buffer_atomic_smax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25064 { 418 /* buffer_atomic_smax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25066 { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25068 { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25070 { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25072 { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25074 { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25076 { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25078 { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25080 { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25082 { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25084 { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25086 { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25088 { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25090 { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25092 { 437 /* buffer_atomic_smax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25094 { 437 /* buffer_atomic_smax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25096 { 437 /* buffer_atomic_smax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25098 { 437 /* buffer_atomic_smax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25100 { 437 /* buffer_atomic_smax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25102 { 437 /* buffer_atomic_smax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25104 { 437 /* buffer_atomic_smax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25106 { 437 /* buffer_atomic_smax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25108 { 437 /* buffer_atomic_smax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25110 { 437 /* buffer_atomic_smax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25112 { 437 /* buffer_atomic_smax_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25114 { 437 /* buffer_atomic_smax_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25116 { 437 /* buffer_atomic_smax_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25118 { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25120 { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25122 { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25124 { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25126 { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25128 { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25130 { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25132 { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25134 { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25136 { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25138 { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25140 { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25142 { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25144 { 459 /* buffer_atomic_smin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25146 { 459 /* buffer_atomic_smin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25148 { 459 /* buffer_atomic_smin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25150 { 459 /* buffer_atomic_smin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25152 { 459 /* buffer_atomic_smin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25154 { 459 /* buffer_atomic_smin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25156 { 459 /* buffer_atomic_smin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25158 { 459 /* buffer_atomic_smin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25160 { 459 /* buffer_atomic_smin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25162 { 459 /* buffer_atomic_smin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25164 { 459 /* buffer_atomic_smin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25166 { 459 /* buffer_atomic_smin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25168 { 459 /* buffer_atomic_smin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25170 { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25172 { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25174 { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25176 { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25178 { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25180 { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25182 { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25184 { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25186 { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25188 { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25190 { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25192 { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25194 { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25196 { 478 /* buffer_atomic_smin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25198 { 478 /* buffer_atomic_smin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25200 { 478 /* buffer_atomic_smin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25202 { 478 /* buffer_atomic_smin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25204 { 478 /* buffer_atomic_smin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25206 { 478 /* buffer_atomic_smin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25208 { 478 /* buffer_atomic_smin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25210 { 478 /* buffer_atomic_smin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25212 { 478 /* buffer_atomic_smin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25214 { 478 /* buffer_atomic_smin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25216 { 478 /* buffer_atomic_smin_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25218 { 478 /* buffer_atomic_smin_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25220 { 478 /* buffer_atomic_smin_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25222 { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25224 { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25226 { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25228 { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25230 { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25232 { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25234 { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25236 { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25238 { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25240 { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25242 { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25244 { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25246 { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25248 { 500 /* buffer_atomic_sub */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25250 { 500 /* buffer_atomic_sub */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25252 { 500 /* buffer_atomic_sub */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25254 { 500 /* buffer_atomic_sub */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25256 { 500 /* buffer_atomic_sub */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25258 { 500 /* buffer_atomic_sub */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25260 { 500 /* buffer_atomic_sub */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25262 { 500 /* buffer_atomic_sub */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25264 { 500 /* buffer_atomic_sub */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25266 { 500 /* buffer_atomic_sub */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25268 { 500 /* buffer_atomic_sub */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25270 { 500 /* buffer_atomic_sub */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25272 { 500 /* buffer_atomic_sub */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25274 { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25276 { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25278 { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25280 { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25282 { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25284 { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25286 { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25288 { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25290 { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25292 { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25294 { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25296 { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25298 { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25300 { 518 /* buffer_atomic_sub_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25302 { 518 /* buffer_atomic_sub_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25304 { 518 /* buffer_atomic_sub_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25306 { 518 /* buffer_atomic_sub_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25308 { 518 /* buffer_atomic_sub_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25310 { 518 /* buffer_atomic_sub_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25312 { 518 /* buffer_atomic_sub_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25314 { 518 /* buffer_atomic_sub_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25316 { 518 /* buffer_atomic_sub_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25318 { 518 /* buffer_atomic_sub_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25320 { 518 /* buffer_atomic_sub_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25322 { 518 /* buffer_atomic_sub_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25324 { 518 /* buffer_atomic_sub_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25326 { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25328 { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25330 { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25332 { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25334 { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25336 { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25338 { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25340 { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25342 { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25344 { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25346 { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25348 { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25350 { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25352 { 539 /* buffer_atomic_swap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25354 { 539 /* buffer_atomic_swap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25356 { 539 /* buffer_atomic_swap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25358 { 539 /* buffer_atomic_swap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25360 { 539 /* buffer_atomic_swap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25362 { 539 /* buffer_atomic_swap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25364 { 539 /* buffer_atomic_swap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25366 { 539 /* buffer_atomic_swap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25368 { 539 /* buffer_atomic_swap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25370 { 539 /* buffer_atomic_swap */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25372 { 539 /* buffer_atomic_swap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25374 { 539 /* buffer_atomic_swap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25376 { 539 /* buffer_atomic_swap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25378 { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25380 { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25382 { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25384 { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25386 { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25388 { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25390 { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25392 { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25394 { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25396 { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25398 { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25400 { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25402 { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25404 { 558 /* buffer_atomic_swap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25406 { 558 /* buffer_atomic_swap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25408 { 558 /* buffer_atomic_swap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25410 { 558 /* buffer_atomic_swap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25412 { 558 /* buffer_atomic_swap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25414 { 558 /* buffer_atomic_swap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25416 { 558 /* buffer_atomic_swap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25418 { 558 /* buffer_atomic_swap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25420 { 558 /* buffer_atomic_swap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25422 { 558 /* buffer_atomic_swap_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25424 { 558 /* buffer_atomic_swap_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25426 { 558 /* buffer_atomic_swap_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25428 { 558 /* buffer_atomic_swap_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25430 { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25432 { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25434 { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25436 { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25438 { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25440 { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25442 { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25444 { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25446 { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25448 { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25450 { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25452 { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25454 { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25456 { 580 /* buffer_atomic_umax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25458 { 580 /* buffer_atomic_umax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25460 { 580 /* buffer_atomic_umax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25462 { 580 /* buffer_atomic_umax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25464 { 580 /* buffer_atomic_umax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25466 { 580 /* buffer_atomic_umax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25468 { 580 /* buffer_atomic_umax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25470 { 580 /* buffer_atomic_umax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25472 { 580 /* buffer_atomic_umax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25474 { 580 /* buffer_atomic_umax */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25476 { 580 /* buffer_atomic_umax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25478 { 580 /* buffer_atomic_umax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25480 { 580 /* buffer_atomic_umax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25482 { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25484 { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25486 { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25488 { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25490 { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25492 { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25494 { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25496 { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25498 { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25500 { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25502 { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25504 { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25506 { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25508 { 599 /* buffer_atomic_umax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25510 { 599 /* buffer_atomic_umax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25512 { 599 /* buffer_atomic_umax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25514 { 599 /* buffer_atomic_umax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25516 { 599 /* buffer_atomic_umax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25518 { 599 /* buffer_atomic_umax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25520 { 599 /* buffer_atomic_umax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25522 { 599 /* buffer_atomic_umax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25524 { 599 /* buffer_atomic_umax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25526 { 599 /* buffer_atomic_umax_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25528 { 599 /* buffer_atomic_umax_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25530 { 599 /* buffer_atomic_umax_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25532 { 599 /* buffer_atomic_umax_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25534 { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25536 { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25538 { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25540 { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25542 { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25544 { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25546 { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25548 { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25550 { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25552 { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25554 { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25556 { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25558 { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25560 { 621 /* buffer_atomic_umin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25562 { 621 /* buffer_atomic_umin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25564 { 621 /* buffer_atomic_umin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25566 { 621 /* buffer_atomic_umin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25568 { 621 /* buffer_atomic_umin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25570 { 621 /* buffer_atomic_umin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25572 { 621 /* buffer_atomic_umin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25574 { 621 /* buffer_atomic_umin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25576 { 621 /* buffer_atomic_umin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25578 { 621 /* buffer_atomic_umin */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25580 { 621 /* buffer_atomic_umin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25582 { 621 /* buffer_atomic_umin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25584 { 621 /* buffer_atomic_umin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25586 { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25588 { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25590 { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25592 { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25594 { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25596 { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25598 { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25600 { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25602 { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25604 { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25606 { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25608 { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25610 { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25612 { 640 /* buffer_atomic_umin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25614 { 640 /* buffer_atomic_umin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25616 { 640 /* buffer_atomic_umin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25618 { 640 /* buffer_atomic_umin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25620 { 640 /* buffer_atomic_umin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25622 { 640 /* buffer_atomic_umin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25624 { 640 /* buffer_atomic_umin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25626 { 640 /* buffer_atomic_umin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25628 { 640 /* buffer_atomic_umin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25630 { 640 /* buffer_atomic_umin_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25632 { 640 /* buffer_atomic_umin_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25634 { 640 /* buffer_atomic_umin_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25636 { 640 /* buffer_atomic_umin_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25638 { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25640 { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25642 { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25644 { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25646 { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25648 { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25650 { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25652 { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25654 { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25656 { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25658 { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25660 { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25662 { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25664 { 662 /* buffer_atomic_xor */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25666 { 662 /* buffer_atomic_xor */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25668 { 662 /* buffer_atomic_xor */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25670 { 662 /* buffer_atomic_xor */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25672 { 662 /* buffer_atomic_xor */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25674 { 662 /* buffer_atomic_xor */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25676 { 662 /* buffer_atomic_xor */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25678 { 662 /* buffer_atomic_xor */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25680 { 662 /* buffer_atomic_xor */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25682 { 662 /* buffer_atomic_xor */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25684 { 662 /* buffer_atomic_xor */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25686 { 662 /* buffer_atomic_xor */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25688 { 662 /* buffer_atomic_xor */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25690 { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25692 { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25694 { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25696 { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25698 { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25700 { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25702 { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25704 { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25706 { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25708 { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25710 { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25712 { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25714 { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25716 { 680 /* buffer_atomic_xor_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25718 { 680 /* buffer_atomic_xor_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25720 { 680 /* buffer_atomic_xor_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25722 { 680 /* buffer_atomic_xor_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25724 { 680 /* buffer_atomic_xor_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25726 { 680 /* buffer_atomic_xor_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25728 { 680 /* buffer_atomic_xor_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25730 { 680 /* buffer_atomic_xor_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25732 { 680 /* buffer_atomic_xor_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25734 { 680 /* buffer_atomic_xor_x2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25736 { 680 /* buffer_atomic_xor_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25738 { 680 /* buffer_atomic_xor_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25740 { 680 /* buffer_atomic_xor_x2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25744 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25749 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25754 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25759 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25765 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25771 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25777 { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25782 { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25788 { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25793 { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25798 { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25803 { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25809 { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25815 { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25821 { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25826 { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25831 { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25836 { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25842 { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25848 { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25854 { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25859 { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25864 { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25869 { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25875 { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25881 { 731 /* buffer_load_dword */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25887 { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
25892 { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25898 { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25904 { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25910 { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25916 { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
25921 { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25927 { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25933 { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25939 { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
25944 { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25950 { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25956 { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25962 { 749 /* buffer_load_dwordx2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
25967 { 749 /* buffer_load_dwordx2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25973 { 749 /* buffer_load_dwordx2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
25979 { 749 /* buffer_load_dwordx2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
25985 { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
25990 { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
25996 { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26002 { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26008 { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26014 { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26019 { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26025 { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26031 { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26037 { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26042 { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26048 { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26054 { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26060 { 769 /* buffer_load_dwordx3 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26065 { 769 /* buffer_load_dwordx3 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26071 { 769 /* buffer_load_dwordx3 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26077 { 769 /* buffer_load_dwordx3 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26083 { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26088 { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26094 { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26100 { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26106 { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26112 { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26117 { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26123 { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26129 { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26135 { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26140 { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26146 { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26152 { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26158 { 789 /* buffer_load_dwordx4 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26163 { 789 /* buffer_load_dwordx4 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26169 { 789 /* buffer_load_dwordx4 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26175 { 789 /* buffer_load_dwordx4 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26181 { 809 /* buffer_load_format_d16_hi_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
26187 { 809 /* buffer_load_format_d16_hi_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
26193 { 809 /* buffer_load_format_d16_hi_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
26199 { 809 /* buffer_load_format_d16_hi_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
26205 { 837 /* buffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26211 { 837 /* buffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26217 { 837 /* buffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26223 { 837 /* buffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26229 { 837 /* buffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26235 { 837 /* buffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26241 { 837 /* buffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26247 { 837 /* buffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26253 { 837 /* buffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26259 { 837 /* buffer_load_format_d16_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26265 { 837 /* buffer_load_format_d16_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26271 { 837 /* buffer_load_format_d16_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26277 { 862 /* buffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26283 { 862 /* buffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26289 { 862 /* buffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26295 { 862 /* buffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26301 { 862 /* buffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26307 { 862 /* buffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26313 { 862 /* buffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26319 { 862 /* buffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26325 { 862 /* buffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26331 { 862 /* buffer_load_format_d16_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26337 { 862 /* buffer_load_format_d16_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26343 { 862 /* buffer_load_format_d16_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26349 { 888 /* buffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26355 { 888 /* buffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26361 { 888 /* buffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26367 { 888 /* buffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26373 { 888 /* buffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26379 { 888 /* buffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26385 { 888 /* buffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26391 { 888 /* buffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26397 { 888 /* buffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26403 { 888 /* buffer_load_format_d16_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26409 { 888 /* buffer_load_format_d16_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26415 { 888 /* buffer_load_format_d16_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26421 { 915 /* buffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26427 { 915 /* buffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26433 { 915 /* buffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26439 { 915 /* buffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26445 { 915 /* buffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26451 { 915 /* buffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26457 { 915 /* buffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26463 { 915 /* buffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26469 { 915 /* buffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26475 { 915 /* buffer_load_format_d16_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26481 { 915 /* buffer_load_format_d16_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26487 { 915 /* buffer_load_format_d16_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26493 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26498 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26503 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26508 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26514 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26520 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26526 { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26531 { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26537 { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26542 { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26547 { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26552 { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26558 { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26564 { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26570 { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26575 { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26580 { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26585 { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26591 { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26597 { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26603 { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26608 { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26613 { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26618 { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26624 { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26630 { 943 /* buffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26636 { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26642 { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26648 { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26654 { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26660 { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26666 { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26672 { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26678 { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26684 { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26690 { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26696 { 964 /* buffer_load_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26702 { 964 /* buffer_load_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26708 { 964 /* buffer_load_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26714 { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26720 { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26726 { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26732 { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26738 { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26744 { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26750 { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26756 { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26762 { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26768 { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26774 { 986 /* buffer_load_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26780 { 986 /* buffer_load_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26786 { 986 /* buffer_load_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26792 { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26798 { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26804 { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26810 { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26816 { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26822 { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26828 { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26834 { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26840 { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26846 { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26852 { 1009 /* buffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26858 { 1009 /* buffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26864 { 1009 /* buffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26870 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26875 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26880 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26885 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26891 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26897 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26903 { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26908 { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26914 { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26919 { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26924 { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26929 { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26935 { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26941 { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26947 { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26952 { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26957 { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26962 { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26968 { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26974 { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26980 { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
26985 { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
26990 { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
26995 { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27001 { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27007 { 1033 /* buffer_load_sbyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27013 { 1051 /* buffer_load_sbyte_d16 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27019 { 1051 /* buffer_load_sbyte_d16 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27025 { 1051 /* buffer_load_sbyte_d16 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27031 { 1051 /* buffer_load_sbyte_d16 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27037 { 1051 /* buffer_load_sbyte_d16 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27043 { 1051 /* buffer_load_sbyte_d16 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27049 { 1051 /* buffer_load_sbyte_d16 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27055 { 1051 /* buffer_load_sbyte_d16 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27061 { 1073 /* buffer_load_sbyte_d16_hi */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27067 { 1073 /* buffer_load_sbyte_d16_hi */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27073 { 1073 /* buffer_load_sbyte_d16_hi */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27079 { 1073 /* buffer_load_sbyte_d16_hi */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27085 { 1073 /* buffer_load_sbyte_d16_hi */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27091 { 1073 /* buffer_load_sbyte_d16_hi */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27097 { 1073 /* buffer_load_sbyte_d16_hi */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27103 { 1073 /* buffer_load_sbyte_d16_hi */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27109 { 1098 /* buffer_load_short_d16 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27115 { 1098 /* buffer_load_short_d16 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27121 { 1098 /* buffer_load_short_d16 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27127 { 1098 /* buffer_load_short_d16 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27133 { 1098 /* buffer_load_short_d16 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27139 { 1098 /* buffer_load_short_d16 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27145 { 1098 /* buffer_load_short_d16 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27151 { 1098 /* buffer_load_short_d16 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27157 { 1120 /* buffer_load_short_d16_hi */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27163 { 1120 /* buffer_load_short_d16_hi */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27169 { 1120 /* buffer_load_short_d16_hi */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27175 { 1120 /* buffer_load_short_d16_hi */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27181 { 1120 /* buffer_load_short_d16_hi */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27187 { 1120 /* buffer_load_short_d16_hi */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27193 { 1120 /* buffer_load_short_d16_hi */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27199 { 1120 /* buffer_load_short_d16_hi */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27205 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27210 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27215 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27220 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27226 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27232 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27238 { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27243 { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27249 { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27254 { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27259 { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27264 { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27270 { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27276 { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27282 { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27287 { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27292 { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27297 { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27303 { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27309 { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27315 { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27320 { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27325 { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27330 { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27336 { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27342 { 1145 /* buffer_load_sshort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27348 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27353 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27358 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27363 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27369 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27375 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27381 { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27386 { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27392 { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27397 { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27402 { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27407 { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27413 { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27419 { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27425 { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27430 { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27435 { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27440 { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27446 { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27452 { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27458 { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27463 { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27468 { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27473 { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27479 { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27485 { 1164 /* buffer_load_ubyte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27491 { 1182 /* buffer_load_ubyte_d16 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27497 { 1182 /* buffer_load_ubyte_d16 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27503 { 1182 /* buffer_load_ubyte_d16 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27509 { 1182 /* buffer_load_ubyte_d16 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27515 { 1182 /* buffer_load_ubyte_d16 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27521 { 1182 /* buffer_load_ubyte_d16 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27527 { 1182 /* buffer_load_ubyte_d16 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27533 { 1182 /* buffer_load_ubyte_d16 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27539 { 1204 /* buffer_load_ubyte_d16_hi */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27545 { 1204 /* buffer_load_ubyte_d16_hi */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27551 { 1204 /* buffer_load_ubyte_d16_hi */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27557 { 1204 /* buffer_load_ubyte_d16_hi */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27563 { 1204 /* buffer_load_ubyte_d16_hi */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27569 { 1204 /* buffer_load_ubyte_d16_hi */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27575 { 1204 /* buffer_load_ubyte_d16_hi */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27581 { 1204 /* buffer_load_ubyte_d16_hi */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27587 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27592 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27597 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27602 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27608 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27614 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27620 { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27625 { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27631 { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27636 { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27641 { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27646 { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27652 { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27658 { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27664 { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27669 { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27674 { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27679 { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27685 { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27691 { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27697 { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27702 { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27707 { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27712 { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27718 { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27724 { 1229 /* buffer_load_ushort */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27730 { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27736 { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27742 { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27748 { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27754 { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27760 { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27766 { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27772 { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27778 { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27784 { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27790 { 1248 /* buffer_store_byte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27796 { 1248 /* buffer_store_byte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27802 { 1248 /* buffer_store_byte */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27808 { 1266 /* buffer_store_byte_d16_hi */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27814 { 1266 /* buffer_store_byte_d16_hi */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27820 { 1266 /* buffer_store_byte_d16_hi */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27826 { 1266 /* buffer_store_byte_d16_hi */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27832 { 1266 /* buffer_store_byte_d16_hi */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27838 { 1266 /* buffer_store_byte_d16_hi */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27844 { 1266 /* buffer_store_byte_d16_hi */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27850 { 1266 /* buffer_store_byte_d16_hi */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27856 { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27862 { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27868 { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27874 { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27880 { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27886 { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27892 { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27898 { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27904 { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27910 { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27916 { 1291 /* buffer_store_dword */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27922 { 1291 /* buffer_store_dword */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27928 { 1291 /* buffer_store_dword */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27934 { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27940 { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27946 { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27952 { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27958 { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27964 { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27970 { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27976 { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
27982 { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
27988 { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
27994 { 1310 /* buffer_store_dwordx2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28000 { 1310 /* buffer_store_dwordx2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28006 { 1310 /* buffer_store_dwordx2 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28012 { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28018 { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28024 { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28030 { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28036 { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28042 { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28048 { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28054 { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28060 { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28066 { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28072 { 1331 /* buffer_store_dwordx3 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28078 { 1331 /* buffer_store_dwordx3 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28084 { 1331 /* buffer_store_dwordx3 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28090 { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28096 { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28102 { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28108 { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28114 { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28120 { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28126 { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28132 { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28138 { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28144 { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28150 { 1352 /* buffer_store_dwordx4 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28156 { 1352 /* buffer_store_dwordx4 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28162 { 1352 /* buffer_store_dwordx4 */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28168 { 1373 /* buffer_store_format_d16_hi_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28174 { 1373 /* buffer_store_format_d16_hi_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28180 { 1373 /* buffer_store_format_d16_hi_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28186 { 1373 /* buffer_store_format_d16_hi_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28192 { 1402 /* buffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28198 { 1402 /* buffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28204 { 1402 /* buffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28210 { 1402 /* buffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28216 { 1402 /* buffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28222 { 1402 /* buffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28228 { 1402 /* buffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28234 { 1402 /* buffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28240 { 1402 /* buffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28246 { 1402 /* buffer_store_format_d16_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28252 { 1402 /* buffer_store_format_d16_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28258 { 1402 /* buffer_store_format_d16_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28264 { 1428 /* buffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28270 { 1428 /* buffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28276 { 1428 /* buffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28282 { 1428 /* buffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28288 { 1428 /* buffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28294 { 1428 /* buffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28300 { 1428 /* buffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28306 { 1428 /* buffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28312 { 1428 /* buffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28318 { 1428 /* buffer_store_format_d16_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28324 { 1428 /* buffer_store_format_d16_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28330 { 1428 /* buffer_store_format_d16_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28336 { 1455 /* buffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28342 { 1455 /* buffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28348 { 1455 /* buffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28354 { 1455 /* buffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28360 { 1455 /* buffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28366 { 1455 /* buffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28372 { 1455 /* buffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28378 { 1455 /* buffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28384 { 1455 /* buffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28390 { 1455 /* buffer_store_format_d16_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28396 { 1455 /* buffer_store_format_d16_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28402 { 1455 /* buffer_store_format_d16_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28408 { 1483 /* buffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28414 { 1483 /* buffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28420 { 1483 /* buffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28426 { 1483 /* buffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28432 { 1483 /* buffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28438 { 1483 /* buffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28444 { 1483 /* buffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28450 { 1483 /* buffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28456 { 1483 /* buffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28462 { 1483 /* buffer_store_format_d16_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28468 { 1483 /* buffer_store_format_d16_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28474 { 1483 /* buffer_store_format_d16_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28480 { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28486 { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28492 { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28498 { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28504 { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28510 { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28516 { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28522 { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28528 { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28534 { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28540 { 1512 /* buffer_store_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28546 { 1512 /* buffer_store_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28552 { 1512 /* buffer_store_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28558 { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28564 { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28570 { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28576 { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28582 { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28588 { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28594 { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28600 { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28606 { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28612 { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28618 { 1534 /* buffer_store_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28624 { 1534 /* buffer_store_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28630 { 1534 /* buffer_store_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28636 { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28642 { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28648 { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28654 { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28660 { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28666 { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28672 { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28678 { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28684 { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28690 { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28696 { 1557 /* buffer_store_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28702 { 1557 /* buffer_store_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28708 { 1557 /* buffer_store_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28714 { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28720 { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28726 { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28732 { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28738 { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28744 { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28750 { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28756 { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28762 { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28768 { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28774 { 1581 /* buffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28780 { 1581 /* buffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28786 { 1581 /* buffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28791 { 1606 /* buffer_store_lds_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
28796 { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28802 { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28808 { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28814 { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28820 { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28826 { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28832 { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28838 { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28844 { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28850 { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28856 { 1629 /* buffer_store_short */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
28862 { 1629 /* buffer_store_short */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
28868 { 1629 /* buffer_store_short */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
28874 { 1648 /* buffer_store_short_d16_hi */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
28880 { 1648 /* buffer_store_short_d16_hi */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28886 { 1648 /* buffer_store_short_d16_hi */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
28892 { 1648 /* buffer_store_short_d16_hi */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28898 { 1648 /* buffer_store_short_d16_hi */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
28904 { 1648 /* buffer_store_short_d16_hi */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28910 { 1648 /* buffer_store_short_d16_hi */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
28916 { 1648 /* buffer_store_short_d16_hi */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
29843 { 3983 /* flat_atomic_add */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29845 { 3983 /* flat_atomic_add */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29847 { 3983 /* flat_atomic_add */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29849 { 3983 /* flat_atomic_add */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29851 { 3983 /* flat_atomic_add */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29853 { 3983 /* flat_atomic_add */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29855 { 3999 /* flat_atomic_add_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29857 { 3999 /* flat_atomic_add_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29859 { 3999 /* flat_atomic_add_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29861 { 3999 /* flat_atomic_add_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29863 { 3999 /* flat_atomic_add_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29865 { 3999 /* flat_atomic_add_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29867 { 4018 /* flat_atomic_and */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29869 { 4018 /* flat_atomic_and */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29871 { 4018 /* flat_atomic_and */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29873 { 4018 /* flat_atomic_and */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29875 { 4018 /* flat_atomic_and */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29877 { 4018 /* flat_atomic_and */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29879 { 4034 /* flat_atomic_and_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29881 { 4034 /* flat_atomic_and_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29883 { 4034 /* flat_atomic_and_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29885 { 4034 /* flat_atomic_and_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29887 { 4034 /* flat_atomic_and_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29889 { 4034 /* flat_atomic_and_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29891 { 4053 /* flat_atomic_cmpswap */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29893 { 4053 /* flat_atomic_cmpswap */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29895 { 4053 /* flat_atomic_cmpswap */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29897 { 4053 /* flat_atomic_cmpswap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29899 { 4053 /* flat_atomic_cmpswap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29901 { 4053 /* flat_atomic_cmpswap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29903 { 4073 /* flat_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29905 { 4073 /* flat_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29907 { 4073 /* flat_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29909 { 4073 /* flat_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29911 { 4073 /* flat_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29913 { 4073 /* flat_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29915 { 4096 /* flat_atomic_dec */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29917 { 4096 /* flat_atomic_dec */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29919 { 4096 /* flat_atomic_dec */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29921 { 4096 /* flat_atomic_dec */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29923 { 4096 /* flat_atomic_dec */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29925 { 4096 /* flat_atomic_dec */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29927 { 4112 /* flat_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29929 { 4112 /* flat_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29931 { 4112 /* flat_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29933 { 4112 /* flat_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29935 { 4112 /* flat_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29937 { 4112 /* flat_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29939 { 4131 /* flat_atomic_fcmpswap */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only },
29941 { 4131 /* flat_atomic_fcmpswap */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus },
29943 { 4131 /* flat_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only },
29945 { 4131 /* flat_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus },
29947 { 4152 /* flat_atomic_fcmpswap_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only },
29949 { 4152 /* flat_atomic_fcmpswap_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus },
29951 { 4152 /* flat_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only },
29953 { 4152 /* flat_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus },
29955 { 4176 /* flat_atomic_fmax */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only },
29957 { 4176 /* flat_atomic_fmax */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus },
29959 { 4176 /* flat_atomic_fmax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only },
29961 { 4176 /* flat_atomic_fmax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus },
29963 { 4193 /* flat_atomic_fmax_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only },
29965 { 4193 /* flat_atomic_fmax_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus },
29967 { 4193 /* flat_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only },
29969 { 4193 /* flat_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus },
29971 { 4213 /* flat_atomic_fmin */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only },
29973 { 4213 /* flat_atomic_fmin */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus },
29975 { 4213 /* flat_atomic_fmin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only },
29977 { 4213 /* flat_atomic_fmin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus },
29979 { 4230 /* flat_atomic_fmin_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only },
29981 { 4230 /* flat_atomic_fmin_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus },
29983 { 4230 /* flat_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX7Only },
29985 { 4230 /* flat_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_isGFX7GFX10_isGFX10Plus },
29987 { 4250 /* flat_atomic_inc */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29989 { 4250 /* flat_atomic_inc */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29991 { 4250 /* flat_atomic_inc */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29993 { 4250 /* flat_atomic_inc */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29995 { 4250 /* flat_atomic_inc */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29997 { 4250 /* flat_atomic_inc */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29999 { 4266 /* flat_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30001 { 4266 /* flat_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30003 { 4266 /* flat_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30005 { 4266 /* flat_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30007 { 4266 /* flat_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30009 { 4266 /* flat_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30011 { 4285 /* flat_atomic_or */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30013 { 4285 /* flat_atomic_or */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30015 { 4285 /* flat_atomic_or */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30017 { 4285 /* flat_atomic_or */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30019 { 4285 /* flat_atomic_or */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30021 { 4285 /* flat_atomic_or */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30023 { 4300 /* flat_atomic_or_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30025 { 4300 /* flat_atomic_or_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30027 { 4300 /* flat_atomic_or_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30029 { 4300 /* flat_atomic_or_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30031 { 4300 /* flat_atomic_or_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30033 { 4300 /* flat_atomic_or_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30035 { 4318 /* flat_atomic_smax */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30037 { 4318 /* flat_atomic_smax */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30039 { 4318 /* flat_atomic_smax */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30041 { 4318 /* flat_atomic_smax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30043 { 4318 /* flat_atomic_smax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30045 { 4318 /* flat_atomic_smax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30047 { 4335 /* flat_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30049 { 4335 /* flat_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30051 { 4335 /* flat_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30053 { 4335 /* flat_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30055 { 4335 /* flat_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30057 { 4335 /* flat_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30059 { 4355 /* flat_atomic_smin */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30061 { 4355 /* flat_atomic_smin */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30063 { 4355 /* flat_atomic_smin */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30065 { 4355 /* flat_atomic_smin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30067 { 4355 /* flat_atomic_smin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30069 { 4355 /* flat_atomic_smin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30071 { 4372 /* flat_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30073 { 4372 /* flat_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30075 { 4372 /* flat_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30077 { 4372 /* flat_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30079 { 4372 /* flat_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30081 { 4372 /* flat_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30083 { 4392 /* flat_atomic_sub */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30085 { 4392 /* flat_atomic_sub */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30087 { 4392 /* flat_atomic_sub */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30089 { 4392 /* flat_atomic_sub */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30091 { 4392 /* flat_atomic_sub */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30093 { 4392 /* flat_atomic_sub */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30095 { 4408 /* flat_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30097 { 4408 /* flat_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30099 { 4408 /* flat_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30101 { 4408 /* flat_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30103 { 4408 /* flat_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30105 { 4408 /* flat_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30107 { 4427 /* flat_atomic_swap */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30109 { 4427 /* flat_atomic_swap */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30111 { 4427 /* flat_atomic_swap */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30113 { 4427 /* flat_atomic_swap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30115 { 4427 /* flat_atomic_swap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30117 { 4427 /* flat_atomic_swap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30119 { 4444 /* flat_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30121 { 4444 /* flat_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30123 { 4444 /* flat_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30125 { 4444 /* flat_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30127 { 4444 /* flat_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30129 { 4444 /* flat_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30131 { 4464 /* flat_atomic_umax */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30133 { 4464 /* flat_atomic_umax */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30135 { 4464 /* flat_atomic_umax */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30137 { 4464 /* flat_atomic_umax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30139 { 4464 /* flat_atomic_umax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30141 { 4464 /* flat_atomic_umax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30143 { 4481 /* flat_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30145 { 4481 /* flat_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30147 { 4481 /* flat_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30149 { 4481 /* flat_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30151 { 4481 /* flat_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30153 { 4481 /* flat_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30155 { 4501 /* flat_atomic_umin */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30157 { 4501 /* flat_atomic_umin */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30159 { 4501 /* flat_atomic_umin */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30161 { 4501 /* flat_atomic_umin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30163 { 4501 /* flat_atomic_umin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30165 { 4501 /* flat_atomic_umin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30167 { 4518 /* flat_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30169 { 4518 /* flat_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30171 { 4518 /* flat_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30173 { 4518 /* flat_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30175 { 4518 /* flat_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30177 { 4518 /* flat_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30179 { 4538 /* flat_atomic_xor */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30181 { 4538 /* flat_atomic_xor */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30183 { 4538 /* flat_atomic_xor */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30185 { 4538 /* flat_atomic_xor */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30187 { 4538 /* flat_atomic_xor */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30189 { 4538 /* flat_atomic_xor */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30191 { 4554 /* flat_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30193 { 4554 /* flat_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30195 { 4554 /* flat_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30197 { 4554 /* flat_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30199 { 4554 /* flat_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30201 { 4554 /* flat_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30205 { 4573 /* flat_load_dword */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30209 { 4573 /* flat_load_dword */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30213 { 4573 /* flat_load_dword */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30217 { 4589 /* flat_load_dwordx2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30221 { 4589 /* flat_load_dwordx2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30225 { 4589 /* flat_load_dwordx2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30229 { 4607 /* flat_load_dwordx3 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30233 { 4607 /* flat_load_dwordx3 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30237 { 4607 /* flat_load_dwordx3 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30241 { 4625 /* flat_load_dwordx4 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30245 { 4625 /* flat_load_dwordx4 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30249 { 4625 /* flat_load_dwordx4 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30253 { 4643 /* flat_load_sbyte */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30257 { 4643 /* flat_load_sbyte */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30261 { 4643 /* flat_load_sbyte */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30265 { 4659 /* flat_load_sbyte_d16 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
30269 { 4659 /* flat_load_sbyte_d16 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30273 { 4679 /* flat_load_sbyte_d16_hi */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
30277 { 4679 /* flat_load_sbyte_d16_hi */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30281 { 4702 /* flat_load_short_d16 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
30285 { 4702 /* flat_load_short_d16 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30289 { 4722 /* flat_load_short_d16_hi */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
30293 { 4722 /* flat_load_short_d16_hi */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30297 { 4745 /* flat_load_sshort */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30301 { 4745 /* flat_load_sshort */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30305 { 4745 /* flat_load_sshort */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30309 { 4762 /* flat_load_ubyte */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30313 { 4762 /* flat_load_ubyte */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30317 { 4762 /* flat_load_ubyte */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30321 { 4778 /* flat_load_ubyte_d16 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
30325 { 4778 /* flat_load_ubyte_d16 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30329 { 4798 /* flat_load_ubyte_d16_hi */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
30333 { 4798 /* flat_load_ubyte_d16_hi */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30337 { 4821 /* flat_load_ushort */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30341 { 4821 /* flat_load_ushort */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30345 { 4821 /* flat_load_ushort */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30349 { 4838 /* flat_store_byte */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30353 { 4838 /* flat_store_byte */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30357 { 4838 /* flat_store_byte */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30361 { 4854 /* flat_store_byte_d16_hi */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
30365 { 4854 /* flat_store_byte_d16_hi */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30369 { 4877 /* flat_store_dword */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30373 { 4877 /* flat_store_dword */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30377 { 4877 /* flat_store_dword */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30381 { 4894 /* flat_store_dwordx2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30385 { 4894 /* flat_store_dwordx2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30389 { 4894 /* flat_store_dwordx2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30393 { 4913 /* flat_store_dwordx3 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30397 { 4913 /* flat_store_dwordx3 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30401 { 4913 /* flat_store_dwordx3 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30405 { 4932 /* flat_store_dwordx4 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30409 { 4932 /* flat_store_dwordx4 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30413 { 4932 /* flat_store_dwordx4 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30417 { 4951 /* flat_store_short */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30421 { 4951 /* flat_store_short */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30425 { 4951 /* flat_store_short */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30429 { 4968 /* flat_store_short_d16_hi */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX10Plus },
30433 { 4968 /* flat_store_short_d16_hi */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30435 { 4992 /* global_atomic_add */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30437 { 4992 /* global_atomic_add */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30439 { 4992 /* global_atomic_add */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30441 { 4992 /* global_atomic_add */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30443 { 4992 /* global_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30445 { 4992 /* global_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30447 { 4992 /* global_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30449 { 4992 /* global_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30451 { 5010 /* global_atomic_add_f32 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
30453 { 5010 /* global_atomic_add_f32 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
30455 { 5032 /* global_atomic_add_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30457 { 5032 /* global_atomic_add_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30459 { 5032 /* global_atomic_add_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30461 { 5032 /* global_atomic_add_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30463 { 5032 /* global_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30465 { 5032 /* global_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30467 { 5032 /* global_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30469 { 5032 /* global_atomic_add_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30471 { 5053 /* global_atomic_and */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30473 { 5053 /* global_atomic_and */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30475 { 5053 /* global_atomic_and */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30477 { 5053 /* global_atomic_and */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30479 { 5053 /* global_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30481 { 5053 /* global_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30483 { 5053 /* global_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30485 { 5053 /* global_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30487 { 5071 /* global_atomic_and_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30489 { 5071 /* global_atomic_and_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30491 { 5071 /* global_atomic_and_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30493 { 5071 /* global_atomic_and_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30495 { 5071 /* global_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30497 { 5071 /* global_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30499 { 5071 /* global_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30501 { 5071 /* global_atomic_and_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30503 { 5092 /* global_atomic_cmpswap */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30505 { 5092 /* global_atomic_cmpswap */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30507 { 5092 /* global_atomic_cmpswap */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30509 { 5092 /* global_atomic_cmpswap */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30511 { 5092 /* global_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30513 { 5092 /* global_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30515 { 5092 /* global_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30517 { 5092 /* global_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30519 { 5114 /* global_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30521 { 5114 /* global_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30523 { 5114 /* global_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30525 { 5114 /* global_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30527 { 5114 /* global_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30529 { 5114 /* global_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30531 { 5114 /* global_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30533 { 5114 /* global_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30535 { 5139 /* global_atomic_dec */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30537 { 5139 /* global_atomic_dec */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30539 { 5139 /* global_atomic_dec */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30541 { 5139 /* global_atomic_dec */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30543 { 5139 /* global_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30545 { 5139 /* global_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30547 { 5139 /* global_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30549 { 5139 /* global_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30551 { 5157 /* global_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30553 { 5157 /* global_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30555 { 5157 /* global_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30557 { 5157 /* global_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30559 { 5157 /* global_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30561 { 5157 /* global_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30563 { 5157 /* global_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30565 { 5157 /* global_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30567 { 5178 /* global_atomic_fcmpswap */, 16 /* 4 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30569 { 5178 /* global_atomic_fcmpswap */, 16 /* 4 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30571 { 5178 /* global_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30573 { 5178 /* global_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30575 { 5201 /* global_atomic_fcmpswap_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30577 { 5201 /* global_atomic_fcmpswap_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30579 { 5201 /* global_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30581 { 5201 /* global_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30583 { 5227 /* global_atomic_fmax */, 16 /* 4 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30585 { 5227 /* global_atomic_fmax */, 16 /* 4 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30587 { 5227 /* global_atomic_fmax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30589 { 5227 /* global_atomic_fmax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30591 { 5246 /* global_atomic_fmax_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30593 { 5246 /* global_atomic_fmax_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30595 { 5246 /* global_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30597 { 5246 /* global_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30599 { 5268 /* global_atomic_fmin */, 16 /* 4 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30601 { 5268 /* global_atomic_fmin */, 16 /* 4 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30603 { 5268 /* global_atomic_fmin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30605 { 5268 /* global_atomic_fmin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30607 { 5287 /* global_atomic_fmin_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30609 { 5287 /* global_atomic_fmin_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30611 { 5287 /* global_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30613 { 5287 /* global_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
30615 { 5309 /* global_atomic_inc */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30617 { 5309 /* global_atomic_inc */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30619 { 5309 /* global_atomic_inc */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30621 { 5309 /* global_atomic_inc */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30623 { 5309 /* global_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30625 { 5309 /* global_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30627 { 5309 /* global_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30629 { 5309 /* global_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30631 { 5327 /* global_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30633 { 5327 /* global_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30635 { 5327 /* global_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30637 { 5327 /* global_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30639 { 5327 /* global_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30641 { 5327 /* global_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30643 { 5327 /* global_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30645 { 5327 /* global_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30647 { 5348 /* global_atomic_or */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30649 { 5348 /* global_atomic_or */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30651 { 5348 /* global_atomic_or */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30653 { 5348 /* global_atomic_or */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30655 { 5348 /* global_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30657 { 5348 /* global_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30659 { 5348 /* global_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30661 { 5348 /* global_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30663 { 5365 /* global_atomic_or_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30665 { 5365 /* global_atomic_or_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30667 { 5365 /* global_atomic_or_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30669 { 5365 /* global_atomic_or_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30671 { 5365 /* global_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30673 { 5365 /* global_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30675 { 5365 /* global_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30677 { 5365 /* global_atomic_or_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30679 { 5385 /* global_atomic_pk_add_f16 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
30681 { 5385 /* global_atomic_pk_add_f16 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
30683 { 5410 /* global_atomic_smax */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30685 { 5410 /* global_atomic_smax */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30687 { 5410 /* global_atomic_smax */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30689 { 5410 /* global_atomic_smax */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30691 { 5410 /* global_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30693 { 5410 /* global_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30695 { 5410 /* global_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30697 { 5410 /* global_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30699 { 5429 /* global_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30701 { 5429 /* global_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30703 { 5429 /* global_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30705 { 5429 /* global_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30707 { 5429 /* global_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30709 { 5429 /* global_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30711 { 5429 /* global_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30713 { 5429 /* global_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30715 { 5451 /* global_atomic_smin */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30717 { 5451 /* global_atomic_smin */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30719 { 5451 /* global_atomic_smin */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30721 { 5451 /* global_atomic_smin */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30723 { 5451 /* global_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30725 { 5451 /* global_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30727 { 5451 /* global_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30729 { 5451 /* global_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30731 { 5470 /* global_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30733 { 5470 /* global_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30735 { 5470 /* global_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30737 { 5470 /* global_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30739 { 5470 /* global_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30741 { 5470 /* global_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30743 { 5470 /* global_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30745 { 5470 /* global_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30747 { 5492 /* global_atomic_sub */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30749 { 5492 /* global_atomic_sub */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30751 { 5492 /* global_atomic_sub */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30753 { 5492 /* global_atomic_sub */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30755 { 5492 /* global_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30757 { 5492 /* global_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30759 { 5492 /* global_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30761 { 5492 /* global_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30763 { 5510 /* global_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30765 { 5510 /* global_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30767 { 5510 /* global_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30769 { 5510 /* global_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30771 { 5510 /* global_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30773 { 5510 /* global_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30775 { 5510 /* global_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30777 { 5510 /* global_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30779 { 5531 /* global_atomic_swap */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30781 { 5531 /* global_atomic_swap */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30783 { 5531 /* global_atomic_swap */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30785 { 5531 /* global_atomic_swap */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30787 { 5531 /* global_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30789 { 5531 /* global_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30791 { 5531 /* global_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30793 { 5531 /* global_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30795 { 5550 /* global_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30797 { 5550 /* global_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30799 { 5550 /* global_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30801 { 5550 /* global_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30803 { 5550 /* global_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30805 { 5550 /* global_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30807 { 5550 /* global_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30809 { 5550 /* global_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30811 { 5572 /* global_atomic_umax */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30813 { 5572 /* global_atomic_umax */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30815 { 5572 /* global_atomic_umax */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30817 { 5572 /* global_atomic_umax */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30819 { 5572 /* global_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30821 { 5572 /* global_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30823 { 5572 /* global_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30825 { 5572 /* global_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30827 { 5591 /* global_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30829 { 5591 /* global_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30831 { 5591 /* global_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30833 { 5591 /* global_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30835 { 5591 /* global_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30837 { 5591 /* global_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30839 { 5591 /* global_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30841 { 5591 /* global_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30843 { 5613 /* global_atomic_umin */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30845 { 5613 /* global_atomic_umin */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30847 { 5613 /* global_atomic_umin */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30849 { 5613 /* global_atomic_umin */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30851 { 5613 /* global_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30853 { 5613 /* global_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30855 { 5613 /* global_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30857 { 5613 /* global_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30859 { 5632 /* global_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30861 { 5632 /* global_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30863 { 5632 /* global_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30865 { 5632 /* global_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30867 { 5632 /* global_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30869 { 5632 /* global_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30871 { 5632 /* global_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30873 { 5632 /* global_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30875 { 5654 /* global_atomic_xor */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30877 { 5654 /* global_atomic_xor */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30879 { 5654 /* global_atomic_xor */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30881 { 5654 /* global_atomic_xor */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30883 { 5654 /* global_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30885 { 5654 /* global_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30887 { 5654 /* global_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30889 { 5654 /* global_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30891 { 5672 /* global_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30893 { 5672 /* global_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30895 { 5672 /* global_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30897 { 5672 /* global_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30899 { 5672 /* global_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30901 { 5672 /* global_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30903 { 5672 /* global_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30905 { 5672 /* global_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30909 { 5693 /* global_load_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30913 { 5693 /* global_load_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30917 { 5693 /* global_load_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30921 { 5693 /* global_load_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30925 { 5711 /* global_load_dwordx2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30929 { 5711 /* global_load_dwordx2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30933 { 5711 /* global_load_dwordx2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30937 { 5711 /* global_load_dwordx2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30941 { 5731 /* global_load_dwordx3 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30945 { 5731 /* global_load_dwordx3 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30949 { 5731 /* global_load_dwordx3 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30953 { 5731 /* global_load_dwordx3 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30957 { 5751 /* global_load_dwordx4 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30961 { 5751 /* global_load_dwordx4 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30965 { 5751 /* global_load_dwordx4 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30969 { 5751 /* global_load_dwordx4 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30973 { 5771 /* global_load_sbyte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30977 { 5771 /* global_load_sbyte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30981 { 5771 /* global_load_sbyte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30985 { 5771 /* global_load_sbyte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30989 { 5789 /* global_load_sbyte_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30993 { 5789 /* global_load_sbyte_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30997 { 5789 /* global_load_sbyte_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31001 { 5789 /* global_load_sbyte_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31005 { 5811 /* global_load_sbyte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31009 { 5811 /* global_load_sbyte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31013 { 5811 /* global_load_sbyte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31017 { 5811 /* global_load_sbyte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31021 { 5836 /* global_load_short_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31025 { 5836 /* global_load_short_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31029 { 5836 /* global_load_short_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31033 { 5836 /* global_load_short_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31037 { 5858 /* global_load_short_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31041 { 5858 /* global_load_short_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31045 { 5858 /* global_load_short_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31049 { 5858 /* global_load_short_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31053 { 5883 /* global_load_sshort */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31057 { 5883 /* global_load_sshort */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31061 { 5883 /* global_load_sshort */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31065 { 5883 /* global_load_sshort */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31069 { 5902 /* global_load_ubyte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31073 { 5902 /* global_load_ubyte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31077 { 5902 /* global_load_ubyte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31081 { 5902 /* global_load_ubyte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31085 { 5920 /* global_load_ubyte_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31089 { 5920 /* global_load_ubyte_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31093 { 5920 /* global_load_ubyte_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31097 { 5920 /* global_load_ubyte_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31101 { 5942 /* global_load_ubyte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31105 { 5942 /* global_load_ubyte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31109 { 5942 /* global_load_ubyte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31113 { 5942 /* global_load_ubyte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31117 { 5967 /* global_load_ushort */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31121 { 5967 /* global_load_ushort */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31125 { 5967 /* global_load_ushort */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31129 { 5967 /* global_load_ushort */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31133 { 5986 /* global_store_byte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31137 { 5986 /* global_store_byte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31141 { 5986 /* global_store_byte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31145 { 5986 /* global_store_byte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31149 { 6004 /* global_store_byte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31153 { 6004 /* global_store_byte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31157 { 6004 /* global_store_byte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31161 { 6004 /* global_store_byte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31165 { 6029 /* global_store_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31169 { 6029 /* global_store_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31173 { 6029 /* global_store_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31177 { 6029 /* global_store_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31181 { 6048 /* global_store_dwordx2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31185 { 6048 /* global_store_dwordx2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31189 { 6048 /* global_store_dwordx2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31193 { 6048 /* global_store_dwordx2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31197 { 6069 /* global_store_dwordx3 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31201 { 6069 /* global_store_dwordx3 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31205 { 6069 /* global_store_dwordx3 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31209 { 6069 /* global_store_dwordx3 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31213 { 6090 /* global_store_dwordx4 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31217 { 6090 /* global_store_dwordx4 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31221 { 6090 /* global_store_dwordx4 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31225 { 6090 /* global_store_dwordx4 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31229 { 6111 /* global_store_short */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31233 { 6111 /* global_store_short */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31237 { 6111 /* global_store_short */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31241 { 6111 /* global_store_short */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31245 { 6130 /* global_store_short_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31249 { 6130 /* global_store_short_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31253 { 6130 /* global_store_short_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31257 { 6130 /* global_store_short_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31259 { 6156 /* image_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31267 { 6156 /* image_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31275 { 6156 /* image_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31283 { 6156 /* image_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31291 { 6156 /* image_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31299 { 6156 /* image_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31307 { 6156 /* image_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31315 { 6156 /* image_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31323 { 6156 /* image_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31331 { 6156 /* image_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31339 { 6156 /* image_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31347 { 6156 /* image_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31355 { 6156 /* image_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31363 { 6156 /* image_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31371 { 6156 /* image_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31379 { 6156 /* image_atomic_add */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31388 { 6156 /* image_atomic_add */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31397 { 6156 /* image_atomic_add */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31406 { 6156 /* image_atomic_add */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31415 { 6156 /* image_atomic_add */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31424 { 6156 /* image_atomic_add */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31433 { 6156 /* image_atomic_add */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31442 { 6156 /* image_atomic_add */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31451 { 6156 /* image_atomic_add */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31460 { 6156 /* image_atomic_add */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31469 { 6156 /* image_atomic_add */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31478 { 6156 /* image_atomic_add */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31487 { 6156 /* image_atomic_add */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31496 { 6156 /* image_atomic_add */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31505 { 6156 /* image_atomic_add */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31513 { 6173 /* image_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31521 { 6173 /* image_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31529 { 6173 /* image_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31537 { 6173 /* image_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31545 { 6173 /* image_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31553 { 6173 /* image_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31561 { 6173 /* image_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31569 { 6173 /* image_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31577 { 6173 /* image_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31585 { 6173 /* image_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31593 { 6173 /* image_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31601 { 6173 /* image_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31609 { 6173 /* image_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31617 { 6173 /* image_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31625 { 6173 /* image_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31633 { 6173 /* image_atomic_and */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31642 { 6173 /* image_atomic_and */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31651 { 6173 /* image_atomic_and */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31660 { 6173 /* image_atomic_and */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31669 { 6173 /* image_atomic_and */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31678 { 6173 /* image_atomic_and */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31687 { 6173 /* image_atomic_and */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31696 { 6173 /* image_atomic_and */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31705 { 6173 /* image_atomic_and */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31714 { 6173 /* image_atomic_and */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31723 { 6173 /* image_atomic_and */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31732 { 6173 /* image_atomic_and */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31741 { 6173 /* image_atomic_and */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31750 { 6173 /* image_atomic_and */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31759 { 6173 /* image_atomic_and */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31767 { 6190 /* image_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31775 { 6190 /* image_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31783 { 6190 /* image_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31791 { 6190 /* image_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31799 { 6190 /* image_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31807 { 6190 /* image_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31815 { 6190 /* image_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31823 { 6190 /* image_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31831 { 6190 /* image_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31839 { 6190 /* image_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31847 { 6190 /* image_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31855 { 6190 /* image_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31863 { 6190 /* image_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31871 { 6190 /* image_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31879 { 6190 /* image_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31887 { 6190 /* image_atomic_cmpswap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31896 { 6190 /* image_atomic_cmpswap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31905 { 6190 /* image_atomic_cmpswap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31914 { 6190 /* image_atomic_cmpswap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31923 { 6190 /* image_atomic_cmpswap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31932 { 6190 /* image_atomic_cmpswap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31941 { 6190 /* image_atomic_cmpswap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31950 { 6190 /* image_atomic_cmpswap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31959 { 6190 /* image_atomic_cmpswap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31968 { 6190 /* image_atomic_cmpswap */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31977 { 6190 /* image_atomic_cmpswap */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31986 { 6190 /* image_atomic_cmpswap */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
31995 { 6190 /* image_atomic_cmpswap */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32004 { 6190 /* image_atomic_cmpswap */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32013 { 6190 /* image_atomic_cmpswap */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32021 { 6211 /* image_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32029 { 6211 /* image_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32037 { 6211 /* image_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32045 { 6211 /* image_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32053 { 6211 /* image_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32061 { 6211 /* image_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32069 { 6211 /* image_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32077 { 6211 /* image_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32085 { 6211 /* image_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32093 { 6211 /* image_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32101 { 6211 /* image_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32109 { 6211 /* image_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32117 { 6211 /* image_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32125 { 6211 /* image_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32133 { 6211 /* image_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32141 { 6211 /* image_atomic_dec */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32150 { 6211 /* image_atomic_dec */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32159 { 6211 /* image_atomic_dec */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32168 { 6211 /* image_atomic_dec */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32177 { 6211 /* image_atomic_dec */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32186 { 6211 /* image_atomic_dec */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32195 { 6211 /* image_atomic_dec */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32204 { 6211 /* image_atomic_dec */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32213 { 6211 /* image_atomic_dec */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32222 { 6211 /* image_atomic_dec */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32231 { 6211 /* image_atomic_dec */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32240 { 6211 /* image_atomic_dec */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32249 { 6211 /* image_atomic_dec */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32258 { 6211 /* image_atomic_dec */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32267 { 6211 /* image_atomic_dec */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32275 { 6228 /* image_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32283 { 6228 /* image_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32291 { 6228 /* image_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32299 { 6228 /* image_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32307 { 6228 /* image_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32315 { 6228 /* image_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32323 { 6228 /* image_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32331 { 6228 /* image_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32339 { 6228 /* image_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32347 { 6228 /* image_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32355 { 6228 /* image_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32363 { 6228 /* image_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32371 { 6228 /* image_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32379 { 6228 /* image_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32387 { 6228 /* image_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32395 { 6228 /* image_atomic_inc */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32404 { 6228 /* image_atomic_inc */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32413 { 6228 /* image_atomic_inc */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32422 { 6228 /* image_atomic_inc */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32431 { 6228 /* image_atomic_inc */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32440 { 6228 /* image_atomic_inc */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32449 { 6228 /* image_atomic_inc */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32458 { 6228 /* image_atomic_inc */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32467 { 6228 /* image_atomic_inc */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32476 { 6228 /* image_atomic_inc */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32485 { 6228 /* image_atomic_inc */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32494 { 6228 /* image_atomic_inc */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32503 { 6228 /* image_atomic_inc */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32512 { 6228 /* image_atomic_inc */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32521 { 6228 /* image_atomic_inc */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32529 { 6245 /* image_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32537 { 6245 /* image_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32545 { 6245 /* image_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32553 { 6245 /* image_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32561 { 6245 /* image_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32569 { 6245 /* image_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32577 { 6245 /* image_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32585 { 6245 /* image_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32593 { 6245 /* image_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32601 { 6245 /* image_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32609 { 6245 /* image_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32617 { 6245 /* image_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32625 { 6245 /* image_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32633 { 6245 /* image_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32641 { 6245 /* image_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32649 { 6245 /* image_atomic_or */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32658 { 6245 /* image_atomic_or */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32667 { 6245 /* image_atomic_or */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32676 { 6245 /* image_atomic_or */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32685 { 6245 /* image_atomic_or */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32694 { 6245 /* image_atomic_or */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32703 { 6245 /* image_atomic_or */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32712 { 6245 /* image_atomic_or */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32721 { 6245 /* image_atomic_or */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32730 { 6245 /* image_atomic_or */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32739 { 6245 /* image_atomic_or */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32748 { 6245 /* image_atomic_or */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32757 { 6245 /* image_atomic_or */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32766 { 6245 /* image_atomic_or */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32775 { 6245 /* image_atomic_or */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32783 { 6261 /* image_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32791 { 6261 /* image_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32799 { 6261 /* image_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32807 { 6261 /* image_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32815 { 6261 /* image_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32823 { 6261 /* image_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32831 { 6261 /* image_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32839 { 6261 /* image_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32847 { 6261 /* image_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32855 { 6261 /* image_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32863 { 6261 /* image_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32871 { 6261 /* image_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32879 { 6261 /* image_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32887 { 6261 /* image_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32895 { 6261 /* image_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32903 { 6261 /* image_atomic_smax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32912 { 6261 /* image_atomic_smax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32921 { 6261 /* image_atomic_smax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32930 { 6261 /* image_atomic_smax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32939 { 6261 /* image_atomic_smax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32948 { 6261 /* image_atomic_smax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32957 { 6261 /* image_atomic_smax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32966 { 6261 /* image_atomic_smax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32975 { 6261 /* image_atomic_smax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32984 { 6261 /* image_atomic_smax */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
32993 { 6261 /* image_atomic_smax */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33002 { 6261 /* image_atomic_smax */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33011 { 6261 /* image_atomic_smax */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33020 { 6261 /* image_atomic_smax */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33029 { 6261 /* image_atomic_smax */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33037 { 6279 /* image_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33045 { 6279 /* image_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33053 { 6279 /* image_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33061 { 6279 /* image_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33069 { 6279 /* image_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33077 { 6279 /* image_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33085 { 6279 /* image_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33093 { 6279 /* image_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33101 { 6279 /* image_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33109 { 6279 /* image_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33117 { 6279 /* image_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33125 { 6279 /* image_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33133 { 6279 /* image_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33141 { 6279 /* image_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33149 { 6279 /* image_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33157 { 6279 /* image_atomic_smin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33166 { 6279 /* image_atomic_smin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33175 { 6279 /* image_atomic_smin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33184 { 6279 /* image_atomic_smin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33193 { 6279 /* image_atomic_smin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33202 { 6279 /* image_atomic_smin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33211 { 6279 /* image_atomic_smin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33220 { 6279 /* image_atomic_smin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33229 { 6279 /* image_atomic_smin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33238 { 6279 /* image_atomic_smin */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33247 { 6279 /* image_atomic_smin */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33256 { 6279 /* image_atomic_smin */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33265 { 6279 /* image_atomic_smin */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33274 { 6279 /* image_atomic_smin */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33283 { 6279 /* image_atomic_smin */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33291 { 6297 /* image_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33299 { 6297 /* image_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33307 { 6297 /* image_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33315 { 6297 /* image_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33323 { 6297 /* image_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33331 { 6297 /* image_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33339 { 6297 /* image_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33347 { 6297 /* image_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33355 { 6297 /* image_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33363 { 6297 /* image_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33371 { 6297 /* image_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33379 { 6297 /* image_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33387 { 6297 /* image_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33395 { 6297 /* image_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33403 { 6297 /* image_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33411 { 6297 /* image_atomic_sub */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33420 { 6297 /* image_atomic_sub */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33429 { 6297 /* image_atomic_sub */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33438 { 6297 /* image_atomic_sub */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33447 { 6297 /* image_atomic_sub */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33456 { 6297 /* image_atomic_sub */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33465 { 6297 /* image_atomic_sub */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33474 { 6297 /* image_atomic_sub */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33483 { 6297 /* image_atomic_sub */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33492 { 6297 /* image_atomic_sub */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33501 { 6297 /* image_atomic_sub */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33510 { 6297 /* image_atomic_sub */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33519 { 6297 /* image_atomic_sub */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33528 { 6297 /* image_atomic_sub */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33537 { 6297 /* image_atomic_sub */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33545 { 6314 /* image_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33553 { 6314 /* image_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33561 { 6314 /* image_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33569 { 6314 /* image_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33577 { 6314 /* image_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33585 { 6314 /* image_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33593 { 6314 /* image_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33601 { 6314 /* image_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33609 { 6314 /* image_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33617 { 6314 /* image_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33625 { 6314 /* image_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33633 { 6314 /* image_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33641 { 6314 /* image_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33649 { 6314 /* image_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33657 { 6314 /* image_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33665 { 6314 /* image_atomic_swap */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33674 { 6314 /* image_atomic_swap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33683 { 6314 /* image_atomic_swap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33692 { 6314 /* image_atomic_swap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33701 { 6314 /* image_atomic_swap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33710 { 6314 /* image_atomic_swap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33719 { 6314 /* image_atomic_swap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33728 { 6314 /* image_atomic_swap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33737 { 6314 /* image_atomic_swap */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33746 { 6314 /* image_atomic_swap */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33755 { 6314 /* image_atomic_swap */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33764 { 6314 /* image_atomic_swap */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33773 { 6314 /* image_atomic_swap */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33782 { 6314 /* image_atomic_swap */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33791 { 6314 /* image_atomic_swap */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33799 { 6332 /* image_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33807 { 6332 /* image_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33815 { 6332 /* image_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33823 { 6332 /* image_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33831 { 6332 /* image_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33839 { 6332 /* image_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33847 { 6332 /* image_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33855 { 6332 /* image_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33863 { 6332 /* image_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33871 { 6332 /* image_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33879 { 6332 /* image_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33887 { 6332 /* image_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33895 { 6332 /* image_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33903 { 6332 /* image_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33911 { 6332 /* image_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33919 { 6332 /* image_atomic_umax */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33928 { 6332 /* image_atomic_umax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33937 { 6332 /* image_atomic_umax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33946 { 6332 /* image_atomic_umax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33955 { 6332 /* image_atomic_umax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33964 { 6332 /* image_atomic_umax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33973 { 6332 /* image_atomic_umax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33982 { 6332 /* image_atomic_umax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
33991 { 6332 /* image_atomic_umax */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34000 { 6332 /* image_atomic_umax */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34009 { 6332 /* image_atomic_umax */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34018 { 6332 /* image_atomic_umax */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34027 { 6332 /* image_atomic_umax */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34036 { 6332 /* image_atomic_umax */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34045 { 6332 /* image_atomic_umax */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34053 { 6350 /* image_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34061 { 6350 /* image_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34069 { 6350 /* image_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34077 { 6350 /* image_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34085 { 6350 /* image_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34093 { 6350 /* image_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34101 { 6350 /* image_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34109 { 6350 /* image_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34117 { 6350 /* image_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34125 { 6350 /* image_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34133 { 6350 /* image_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34141 { 6350 /* image_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34149 { 6350 /* image_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34157 { 6350 /* image_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34165 { 6350 /* image_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34173 { 6350 /* image_atomic_umin */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34182 { 6350 /* image_atomic_umin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34191 { 6350 /* image_atomic_umin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34200 { 6350 /* image_atomic_umin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34209 { 6350 /* image_atomic_umin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34218 { 6350 /* image_atomic_umin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34227 { 6350 /* image_atomic_umin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34236 { 6350 /* image_atomic_umin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34245 { 6350 /* image_atomic_umin */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34254 { 6350 /* image_atomic_umin */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34263 { 6350 /* image_atomic_umin */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34272 { 6350 /* image_atomic_umin */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34281 { 6350 /* image_atomic_umin */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34290 { 6350 /* image_atomic_umin */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34299 { 6350 /* image_atomic_umin */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34307 { 6368 /* image_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34315 { 6368 /* image_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34323 { 6368 /* image_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34331 { 6368 /* image_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34339 { 6368 /* image_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34347 { 6368 /* image_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34355 { 6368 /* image_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34363 { 6368 /* image_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34371 { 6368 /* image_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34379 { 6368 /* image_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34387 { 6368 /* image_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34395 { 6368 /* image_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34403 { 6368 /* image_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34411 { 6368 /* image_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34419 { 6368 /* image_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34427 { 6368 /* image_atomic_xor */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34436 { 6368 /* image_atomic_xor */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34445 { 6368 /* image_atomic_xor */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34454 { 6368 /* image_atomic_xor */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34463 { 6368 /* image_atomic_xor */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34472 { 6368 /* image_atomic_xor */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34481 { 6368 /* image_atomic_xor */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34490 { 6368 /* image_atomic_xor */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34499 { 6368 /* image_atomic_xor */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34508 { 6368 /* image_atomic_xor */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34517 { 6368 /* image_atomic_xor */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34526 { 6368 /* image_atomic_xor */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34535 { 6368 /* image_atomic_xor */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34544 { 6368 /* image_atomic_xor */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34553 { 6368 /* image_atomic_xor */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34561 { 6385 /* image_gather4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34570 { 6385 /* image_gather4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34579 { 6385 /* image_gather4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34588 { 6385 /* image_gather4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34597 { 6385 /* image_gather4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34606 { 6385 /* image_gather4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34615 { 6385 /* image_gather4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34624 { 6385 /* image_gather4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34633 { 6385 /* image_gather4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34642 { 6385 /* image_gather4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34651 { 6385 /* image_gather4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34660 { 6385 /* image_gather4 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34670 { 6385 /* image_gather4 */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34680 { 6385 /* image_gather4 */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34690 { 6385 /* image_gather4 */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34700 { 6385 /* image_gather4 */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34710 { 6385 /* image_gather4 */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34720 { 6385 /* image_gather4 */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34730 { 6385 /* image_gather4 */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34740 { 6385 /* image_gather4 */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34750 { 6385 /* image_gather4 */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34760 { 6385 /* image_gather4 */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34770 { 6385 /* image_gather4 */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34780 { 6385 /* image_gather4 */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34790 { 6385 /* image_gather4 */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34800 { 6385 /* image_gather4 */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34810 { 6385 /* image_gather4 */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34820 { 6385 /* image_gather4 */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34830 { 6385 /* image_gather4 */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34840 { 6385 /* image_gather4 */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34849 { 6399 /* image_gather4_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34858 { 6399 /* image_gather4_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34867 { 6399 /* image_gather4_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34876 { 6399 /* image_gather4_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34885 { 6399 /* image_gather4_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34894 { 6399 /* image_gather4_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34903 { 6399 /* image_gather4_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34912 { 6399 /* image_gather4_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34921 { 6399 /* image_gather4_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34931 { 6399 /* image_gather4_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34941 { 6399 /* image_gather4_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34951 { 6399 /* image_gather4_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34961 { 6399 /* image_gather4_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34971 { 6399 /* image_gather4_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34981 { 6399 /* image_gather4_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
34991 { 6399 /* image_gather4_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35001 { 6399 /* image_gather4_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35011 { 6399 /* image_gather4_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35021 { 6399 /* image_gather4_b */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35031 { 6399 /* image_gather4_b */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35041 { 6399 /* image_gather4_b */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35051 { 6399 /* image_gather4_b */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35061 { 6399 /* image_gather4_b */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35071 { 6399 /* image_gather4_b */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35081 { 6399 /* image_gather4_b */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35091 { 6399 /* image_gather4_b */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35101 { 6399 /* image_gather4_b */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35110 { 6415 /* image_gather4_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35119 { 6415 /* image_gather4_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35128 { 6415 /* image_gather4_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35137 { 6415 /* image_gather4_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35146 { 6415 /* image_gather4_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35155 { 6415 /* image_gather4_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35164 { 6415 /* image_gather4_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35173 { 6415 /* image_gather4_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35182 { 6415 /* image_gather4_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35191 { 6415 /* image_gather4_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35200 { 6415 /* image_gather4_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35209 { 6415 /* image_gather4_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35219 { 6415 /* image_gather4_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35229 { 6415 /* image_gather4_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35239 { 6415 /* image_gather4_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35249 { 6415 /* image_gather4_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35259 { 6415 /* image_gather4_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35269 { 6415 /* image_gather4_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35279 { 6415 /* image_gather4_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35289 { 6415 /* image_gather4_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35299 { 6415 /* image_gather4_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35309 { 6415 /* image_gather4_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35319 { 6415 /* image_gather4_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35329 { 6415 /* image_gather4_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35339 { 6415 /* image_gather4_b_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35349 { 6415 /* image_gather4_b_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35359 { 6415 /* image_gather4_b_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35369 { 6415 /* image_gather4_b_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35379 { 6415 /* image_gather4_b_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35389 { 6415 /* image_gather4_b_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35399 { 6415 /* image_gather4_b_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35409 { 6415 /* image_gather4_b_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35419 { 6415 /* image_gather4_b_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35429 { 6415 /* image_gather4_b_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35439 { 6415 /* image_gather4_b_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35449 { 6415 /* image_gather4_b_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35458 { 6434 /* image_gather4_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35467 { 6434 /* image_gather4_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35476 { 6434 /* image_gather4_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35485 { 6434 /* image_gather4_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35494 { 6434 /* image_gather4_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35503 { 6434 /* image_gather4_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35512 { 6434 /* image_gather4_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35521 { 6434 /* image_gather4_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35530 { 6434 /* image_gather4_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35540 { 6434 /* image_gather4_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35550 { 6434 /* image_gather4_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35560 { 6434 /* image_gather4_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35570 { 6434 /* image_gather4_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35580 { 6434 /* image_gather4_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35590 { 6434 /* image_gather4_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35600 { 6434 /* image_gather4_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35610 { 6434 /* image_gather4_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35620 { 6434 /* image_gather4_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35630 { 6434 /* image_gather4_b_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35640 { 6434 /* image_gather4_b_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35650 { 6434 /* image_gather4_b_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35660 { 6434 /* image_gather4_b_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35670 { 6434 /* image_gather4_b_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35680 { 6434 /* image_gather4_b_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35690 { 6434 /* image_gather4_b_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35700 { 6434 /* image_gather4_b_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35710 { 6434 /* image_gather4_b_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35720 { 6434 /* image_gather4_b_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35730 { 6434 /* image_gather4_b_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35740 { 6434 /* image_gather4_b_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35749 { 6455 /* image_gather4_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35758 { 6455 /* image_gather4_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35767 { 6455 /* image_gather4_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35776 { 6455 /* image_gather4_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35785 { 6455 /* image_gather4_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35794 { 6455 /* image_gather4_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35803 { 6455 /* image_gather4_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35812 { 6455 /* image_gather4_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35821 { 6455 /* image_gather4_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35831 { 6455 /* image_gather4_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35841 { 6455 /* image_gather4_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35851 { 6455 /* image_gather4_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35861 { 6455 /* image_gather4_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35871 { 6455 /* image_gather4_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35881 { 6455 /* image_gather4_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35891 { 6455 /* image_gather4_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35901 { 6455 /* image_gather4_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35911 { 6455 /* image_gather4_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35921 { 6455 /* image_gather4_b_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35931 { 6455 /* image_gather4_b_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35941 { 6455 /* image_gather4_b_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35951 { 6455 /* image_gather4_b_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35961 { 6455 /* image_gather4_b_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35971 { 6455 /* image_gather4_b_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35981 { 6455 /* image_gather4_b_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
35991 { 6455 /* image_gather4_b_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36001 { 6455 /* image_gather4_b_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36010 { 6473 /* image_gather4_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36019 { 6473 /* image_gather4_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36028 { 6473 /* image_gather4_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36037 { 6473 /* image_gather4_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36046 { 6473 /* image_gather4_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36055 { 6473 /* image_gather4_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36064 { 6473 /* image_gather4_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36073 { 6473 /* image_gather4_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36082 { 6473 /* image_gather4_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36092 { 6473 /* image_gather4_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36102 { 6473 /* image_gather4_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36112 { 6473 /* image_gather4_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36122 { 6473 /* image_gather4_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36132 { 6473 /* image_gather4_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36142 { 6473 /* image_gather4_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36152 { 6473 /* image_gather4_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36162 { 6473 /* image_gather4_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36172 { 6473 /* image_gather4_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36182 { 6473 /* image_gather4_c */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36192 { 6473 /* image_gather4_c */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36202 { 6473 /* image_gather4_c */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36212 { 6473 /* image_gather4_c */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36222 { 6473 /* image_gather4_c */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36232 { 6473 /* image_gather4_c */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36242 { 6473 /* image_gather4_c */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36252 { 6473 /* image_gather4_c */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36262 { 6473 /* image_gather4_c */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36271 { 6489 /* image_gather4_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36280 { 6489 /* image_gather4_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36289 { 6489 /* image_gather4_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36298 { 6489 /* image_gather4_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36307 { 6489 /* image_gather4_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36316 { 6489 /* image_gather4_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36325 { 6489 /* image_gather4_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36334 { 6489 /* image_gather4_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36343 { 6489 /* image_gather4_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36353 { 6489 /* image_gather4_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36363 { 6489 /* image_gather4_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36373 { 6489 /* image_gather4_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36383 { 6489 /* image_gather4_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36393 { 6489 /* image_gather4_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36403 { 6489 /* image_gather4_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36413 { 6489 /* image_gather4_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36423 { 6489 /* image_gather4_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36433 { 6489 /* image_gather4_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36443 { 6489 /* image_gather4_c_b */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36453 { 6489 /* image_gather4_c_b */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36463 { 6489 /* image_gather4_c_b */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36473 { 6489 /* image_gather4_c_b */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36483 { 6489 /* image_gather4_c_b */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36493 { 6489 /* image_gather4_c_b */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36503 { 6489 /* image_gather4_c_b */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36513 { 6489 /* image_gather4_c_b */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36523 { 6489 /* image_gather4_c_b */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36532 { 6507 /* image_gather4_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36541 { 6507 /* image_gather4_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36550 { 6507 /* image_gather4_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36559 { 6507 /* image_gather4_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36568 { 6507 /* image_gather4_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36577 { 6507 /* image_gather4_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36586 { 6507 /* image_gather4_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36595 { 6507 /* image_gather4_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36604 { 6507 /* image_gather4_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36614 { 6507 /* image_gather4_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36624 { 6507 /* image_gather4_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36634 { 6507 /* image_gather4_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36644 { 6507 /* image_gather4_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36654 { 6507 /* image_gather4_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36664 { 6507 /* image_gather4_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36674 { 6507 /* image_gather4_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36684 { 6507 /* image_gather4_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36694 { 6507 /* image_gather4_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36704 { 6507 /* image_gather4_c_b_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36714 { 6507 /* image_gather4_c_b_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36724 { 6507 /* image_gather4_c_b_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36734 { 6507 /* image_gather4_c_b_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36744 { 6507 /* image_gather4_c_b_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36754 { 6507 /* image_gather4_c_b_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36764 { 6507 /* image_gather4_c_b_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36774 { 6507 /* image_gather4_c_b_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36784 { 6507 /* image_gather4_c_b_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36794 { 6507 /* image_gather4_c_b_cl */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36804 { 6507 /* image_gather4_c_b_cl */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36814 { 6507 /* image_gather4_c_b_cl */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36823 { 6528 /* image_gather4_c_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36832 { 6528 /* image_gather4_c_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36841 { 6528 /* image_gather4_c_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36850 { 6528 /* image_gather4_c_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36859 { 6528 /* image_gather4_c_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36868 { 6528 /* image_gather4_c_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36878 { 6528 /* image_gather4_c_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36888 { 6528 /* image_gather4_c_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36898 { 6528 /* image_gather4_c_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36908 { 6528 /* image_gather4_c_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36918 { 6528 /* image_gather4_c_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36928 { 6528 /* image_gather4_c_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36938 { 6528 /* image_gather4_c_b_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36948 { 6528 /* image_gather4_c_b_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36958 { 6528 /* image_gather4_c_b_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36968 { 6528 /* image_gather4_c_b_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36978 { 6528 /* image_gather4_c_b_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36988 { 6528 /* image_gather4_c_b_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
36998 { 6528 /* image_gather4_c_b_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37008 { 6528 /* image_gather4_c_b_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37018 { 6528 /* image_gather4_c_b_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37028 { 6528 /* image_gather4_c_b_cl_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37038 { 6528 /* image_gather4_c_b_cl_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37048 { 6528 /* image_gather4_c_b_cl_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37057 { 6551 /* image_gather4_c_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37066 { 6551 /* image_gather4_c_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37075 { 6551 /* image_gather4_c_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37084 { 6551 /* image_gather4_c_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37093 { 6551 /* image_gather4_c_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37102 { 6551 /* image_gather4_c_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37112 { 6551 /* image_gather4_c_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37122 { 6551 /* image_gather4_c_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37132 { 6551 /* image_gather4_c_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37142 { 6551 /* image_gather4_c_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37152 { 6551 /* image_gather4_c_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37162 { 6551 /* image_gather4_c_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37172 { 6551 /* image_gather4_c_b_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37182 { 6551 /* image_gather4_c_b_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37192 { 6551 /* image_gather4_c_b_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37202 { 6551 /* image_gather4_c_b_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37212 { 6551 /* image_gather4_c_b_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37222 { 6551 /* image_gather4_c_b_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37232 { 6551 /* image_gather4_c_b_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37242 { 6551 /* image_gather4_c_b_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37252 { 6551 /* image_gather4_c_b_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37261 { 6571 /* image_gather4_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37270 { 6571 /* image_gather4_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37279 { 6571 /* image_gather4_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37288 { 6571 /* image_gather4_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37297 { 6571 /* image_gather4_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37306 { 6571 /* image_gather4_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37315 { 6571 /* image_gather4_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37324 { 6571 /* image_gather4_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37333 { 6571 /* image_gather4_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37342 { 6571 /* image_gather4_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37351 { 6571 /* image_gather4_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37360 { 6571 /* image_gather4_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37370 { 6571 /* image_gather4_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37380 { 6571 /* image_gather4_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37390 { 6571 /* image_gather4_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37400 { 6571 /* image_gather4_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37410 { 6571 /* image_gather4_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37420 { 6571 /* image_gather4_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37430 { 6571 /* image_gather4_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37440 { 6571 /* image_gather4_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37450 { 6571 /* image_gather4_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37460 { 6571 /* image_gather4_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37470 { 6571 /* image_gather4_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37480 { 6571 /* image_gather4_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37490 { 6571 /* image_gather4_c_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37500 { 6571 /* image_gather4_c_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37510 { 6571 /* image_gather4_c_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37520 { 6571 /* image_gather4_c_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37530 { 6571 /* image_gather4_c_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37540 { 6571 /* image_gather4_c_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37550 { 6571 /* image_gather4_c_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37560 { 6571 /* image_gather4_c_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37570 { 6571 /* image_gather4_c_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37580 { 6571 /* image_gather4_c_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37590 { 6571 /* image_gather4_c_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37600 { 6571 /* image_gather4_c_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37609 { 6590 /* image_gather4_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37618 { 6590 /* image_gather4_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37627 { 6590 /* image_gather4_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37636 { 6590 /* image_gather4_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37645 { 6590 /* image_gather4_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37654 { 6590 /* image_gather4_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37663 { 6590 /* image_gather4_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37672 { 6590 /* image_gather4_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37681 { 6590 /* image_gather4_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37691 { 6590 /* image_gather4_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37701 { 6590 /* image_gather4_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37711 { 6590 /* image_gather4_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37721 { 6590 /* image_gather4_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37731 { 6590 /* image_gather4_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37741 { 6590 /* image_gather4_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37751 { 6590 /* image_gather4_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37761 { 6590 /* image_gather4_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37771 { 6590 /* image_gather4_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37781 { 6590 /* image_gather4_c_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37791 { 6590 /* image_gather4_c_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37801 { 6590 /* image_gather4_c_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37811 { 6590 /* image_gather4_c_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37821 { 6590 /* image_gather4_c_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37831 { 6590 /* image_gather4_c_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37841 { 6590 /* image_gather4_c_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37851 { 6590 /* image_gather4_c_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37861 { 6590 /* image_gather4_c_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37871 { 6590 /* image_gather4_c_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37881 { 6590 /* image_gather4_c_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37891 { 6590 /* image_gather4_c_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
37900 { 6611 /* image_gather4_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37909 { 6611 /* image_gather4_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37918 { 6611 /* image_gather4_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37927 { 6611 /* image_gather4_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37936 { 6611 /* image_gather4_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37945 { 6611 /* image_gather4_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37954 { 6611 /* image_gather4_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37963 { 6611 /* image_gather4_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37972 { 6611 /* image_gather4_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37981 { 6611 /* image_gather4_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37990 { 6611 /* image_gather4_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37999 { 6611 /* image_gather4_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38009 { 6611 /* image_gather4_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38019 { 6611 /* image_gather4_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38029 { 6611 /* image_gather4_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38039 { 6611 /* image_gather4_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38049 { 6611 /* image_gather4_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38059 { 6611 /* image_gather4_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38069 { 6611 /* image_gather4_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38079 { 6611 /* image_gather4_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38089 { 6611 /* image_gather4_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38099 { 6611 /* image_gather4_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38109 { 6611 /* image_gather4_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38119 { 6611 /* image_gather4_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38129 { 6611 /* image_gather4_c_l */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38139 { 6611 /* image_gather4_c_l */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38149 { 6611 /* image_gather4_c_l */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38159 { 6611 /* image_gather4_c_l */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38169 { 6611 /* image_gather4_c_l */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38179 { 6611 /* image_gather4_c_l */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38189 { 6611 /* image_gather4_c_l */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38199 { 6611 /* image_gather4_c_l */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38209 { 6611 /* image_gather4_c_l */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38219 { 6611 /* image_gather4_c_l */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38229 { 6611 /* image_gather4_c_l */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38239 { 6611 /* image_gather4_c_l */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38248 { 6629 /* image_gather4_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38257 { 6629 /* image_gather4_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38266 { 6629 /* image_gather4_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38275 { 6629 /* image_gather4_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38284 { 6629 /* image_gather4_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38293 { 6629 /* image_gather4_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38302 { 6629 /* image_gather4_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38311 { 6629 /* image_gather4_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38320 { 6629 /* image_gather4_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38330 { 6629 /* image_gather4_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38340 { 6629 /* image_gather4_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38350 { 6629 /* image_gather4_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38360 { 6629 /* image_gather4_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38370 { 6629 /* image_gather4_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38380 { 6629 /* image_gather4_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38390 { 6629 /* image_gather4_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38400 { 6629 /* image_gather4_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38410 { 6629 /* image_gather4_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38420 { 6629 /* image_gather4_c_l_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38430 { 6629 /* image_gather4_c_l_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38440 { 6629 /* image_gather4_c_l_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38450 { 6629 /* image_gather4_c_l_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38460 { 6629 /* image_gather4_c_l_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38470 { 6629 /* image_gather4_c_l_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38480 { 6629 /* image_gather4_c_l_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38490 { 6629 /* image_gather4_c_l_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38500 { 6629 /* image_gather4_c_l_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38510 { 6629 /* image_gather4_c_l_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38520 { 6629 /* image_gather4_c_l_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38530 { 6629 /* image_gather4_c_l_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38539 { 6649 /* image_gather4_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38548 { 6649 /* image_gather4_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38557 { 6649 /* image_gather4_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38566 { 6649 /* image_gather4_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38575 { 6649 /* image_gather4_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38584 { 6649 /* image_gather4_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38593 { 6649 /* image_gather4_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38602 { 6649 /* image_gather4_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38611 { 6649 /* image_gather4_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38621 { 6649 /* image_gather4_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38631 { 6649 /* image_gather4_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38641 { 6649 /* image_gather4_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38651 { 6649 /* image_gather4_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38661 { 6649 /* image_gather4_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38671 { 6649 /* image_gather4_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38681 { 6649 /* image_gather4_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38691 { 6649 /* image_gather4_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38701 { 6649 /* image_gather4_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38711 { 6649 /* image_gather4_c_lz */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38721 { 6649 /* image_gather4_c_lz */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38731 { 6649 /* image_gather4_c_lz */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38741 { 6649 /* image_gather4_c_lz */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38751 { 6649 /* image_gather4_c_lz */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38761 { 6649 /* image_gather4_c_lz */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38771 { 6649 /* image_gather4_c_lz */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38781 { 6649 /* image_gather4_c_lz */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38791 { 6649 /* image_gather4_c_lz */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38800 { 6668 /* image_gather4_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38809 { 6668 /* image_gather4_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38818 { 6668 /* image_gather4_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38827 { 6668 /* image_gather4_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38836 { 6668 /* image_gather4_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38845 { 6668 /* image_gather4_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38854 { 6668 /* image_gather4_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38863 { 6668 /* image_gather4_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38872 { 6668 /* image_gather4_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38882 { 6668 /* image_gather4_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38892 { 6668 /* image_gather4_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38902 { 6668 /* image_gather4_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38912 { 6668 /* image_gather4_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38922 { 6668 /* image_gather4_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38932 { 6668 /* image_gather4_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38942 { 6668 /* image_gather4_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38952 { 6668 /* image_gather4_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38962 { 6668 /* image_gather4_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38972 { 6668 /* image_gather4_c_lz_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38982 { 6668 /* image_gather4_c_lz_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
38992 { 6668 /* image_gather4_c_lz_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39002 { 6668 /* image_gather4_c_lz_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39012 { 6668 /* image_gather4_c_lz_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39022 { 6668 /* image_gather4_c_lz_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39032 { 6668 /* image_gather4_c_lz_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39042 { 6668 /* image_gather4_c_lz_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39052 { 6668 /* image_gather4_c_lz_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39061 { 6689 /* image_gather4_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39070 { 6689 /* image_gather4_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39079 { 6689 /* image_gather4_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39088 { 6689 /* image_gather4_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39097 { 6689 /* image_gather4_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39106 { 6689 /* image_gather4_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39115 { 6689 /* image_gather4_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39124 { 6689 /* image_gather4_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39133 { 6689 /* image_gather4_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39143 { 6689 /* image_gather4_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39153 { 6689 /* image_gather4_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39163 { 6689 /* image_gather4_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39173 { 6689 /* image_gather4_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39183 { 6689 /* image_gather4_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39193 { 6689 /* image_gather4_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39203 { 6689 /* image_gather4_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39213 { 6689 /* image_gather4_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39223 { 6689 /* image_gather4_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39233 { 6689 /* image_gather4_c_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39243 { 6689 /* image_gather4_c_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39253 { 6689 /* image_gather4_c_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39263 { 6689 /* image_gather4_c_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39273 { 6689 /* image_gather4_c_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39283 { 6689 /* image_gather4_c_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39293 { 6689 /* image_gather4_c_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39303 { 6689 /* image_gather4_c_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39313 { 6689 /* image_gather4_c_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39322 { 6707 /* image_gather4_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39331 { 6707 /* image_gather4_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39340 { 6707 /* image_gather4_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39349 { 6707 /* image_gather4_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39358 { 6707 /* image_gather4_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39367 { 6707 /* image_gather4_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39376 { 6707 /* image_gather4_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39385 { 6707 /* image_gather4_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39394 { 6707 /* image_gather4_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39403 { 6707 /* image_gather4_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39412 { 6707 /* image_gather4_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39421 { 6707 /* image_gather4_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39431 { 6707 /* image_gather4_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39441 { 6707 /* image_gather4_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39451 { 6707 /* image_gather4_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39461 { 6707 /* image_gather4_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39471 { 6707 /* image_gather4_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39481 { 6707 /* image_gather4_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39491 { 6707 /* image_gather4_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39501 { 6707 /* image_gather4_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39511 { 6707 /* image_gather4_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39521 { 6707 /* image_gather4_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39531 { 6707 /* image_gather4_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39541 { 6707 /* image_gather4_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39551 { 6707 /* image_gather4_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39561 { 6707 /* image_gather4_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39571 { 6707 /* image_gather4_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39581 { 6707 /* image_gather4_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39591 { 6707 /* image_gather4_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39601 { 6707 /* image_gather4_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39611 { 6707 /* image_gather4_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39621 { 6707 /* image_gather4_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39631 { 6707 /* image_gather4_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39640 { 6724 /* image_gather4_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39649 { 6724 /* image_gather4_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39658 { 6724 /* image_gather4_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39667 { 6724 /* image_gather4_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39676 { 6724 /* image_gather4_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39685 { 6724 /* image_gather4_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39694 { 6724 /* image_gather4_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39703 { 6724 /* image_gather4_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39712 { 6724 /* image_gather4_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39721 { 6724 /* image_gather4_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39730 { 6724 /* image_gather4_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39739 { 6724 /* image_gather4_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39749 { 6724 /* image_gather4_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39759 { 6724 /* image_gather4_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39769 { 6724 /* image_gather4_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39779 { 6724 /* image_gather4_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39789 { 6724 /* image_gather4_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39799 { 6724 /* image_gather4_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39809 { 6724 /* image_gather4_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39819 { 6724 /* image_gather4_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39829 { 6724 /* image_gather4_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39839 { 6724 /* image_gather4_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39849 { 6724 /* image_gather4_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39859 { 6724 /* image_gather4_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39869 { 6724 /* image_gather4_cl_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39879 { 6724 /* image_gather4_cl_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39889 { 6724 /* image_gather4_cl_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39899 { 6724 /* image_gather4_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39909 { 6724 /* image_gather4_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39919 { 6724 /* image_gather4_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39929 { 6724 /* image_gather4_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39939 { 6724 /* image_gather4_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39949 { 6724 /* image_gather4_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39959 { 6724 /* image_gather4_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39969 { 6724 /* image_gather4_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39979 { 6724 /* image_gather4_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
39988 { 6743 /* image_gather4_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39997 { 6743 /* image_gather4_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40006 { 6743 /* image_gather4_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40015 { 6743 /* image_gather4_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40024 { 6743 /* image_gather4_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40033 { 6743 /* image_gather4_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40042 { 6743 /* image_gather4_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40051 { 6743 /* image_gather4_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40060 { 6743 /* image_gather4_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40069 { 6743 /* image_gather4_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40078 { 6743 /* image_gather4_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40087 { 6743 /* image_gather4_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40097 { 6743 /* image_gather4_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40107 { 6743 /* image_gather4_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40117 { 6743 /* image_gather4_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40127 { 6743 /* image_gather4_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40137 { 6743 /* image_gather4_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40147 { 6743 /* image_gather4_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40157 { 6743 /* image_gather4_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40167 { 6743 /* image_gather4_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40177 { 6743 /* image_gather4_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40187 { 6743 /* image_gather4_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40197 { 6743 /* image_gather4_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40207 { 6743 /* image_gather4_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40217 { 6743 /* image_gather4_l */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40227 { 6743 /* image_gather4_l */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40237 { 6743 /* image_gather4_l */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40247 { 6743 /* image_gather4_l */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40257 { 6743 /* image_gather4_l */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40267 { 6743 /* image_gather4_l */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40277 { 6743 /* image_gather4_l */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40287 { 6743 /* image_gather4_l */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40297 { 6743 /* image_gather4_l */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40306 { 6759 /* image_gather4_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40315 { 6759 /* image_gather4_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40324 { 6759 /* image_gather4_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40333 { 6759 /* image_gather4_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40342 { 6759 /* image_gather4_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40351 { 6759 /* image_gather4_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40360 { 6759 /* image_gather4_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40369 { 6759 /* image_gather4_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40378 { 6759 /* image_gather4_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40387 { 6759 /* image_gather4_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40396 { 6759 /* image_gather4_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40405 { 6759 /* image_gather4_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40415 { 6759 /* image_gather4_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40425 { 6759 /* image_gather4_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40435 { 6759 /* image_gather4_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40445 { 6759 /* image_gather4_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40455 { 6759 /* image_gather4_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40465 { 6759 /* image_gather4_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40475 { 6759 /* image_gather4_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40485 { 6759 /* image_gather4_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40495 { 6759 /* image_gather4_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40505 { 6759 /* image_gather4_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40515 { 6759 /* image_gather4_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40525 { 6759 /* image_gather4_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40535 { 6759 /* image_gather4_l_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40545 { 6759 /* image_gather4_l_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40555 { 6759 /* image_gather4_l_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40565 { 6759 /* image_gather4_l_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40575 { 6759 /* image_gather4_l_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40585 { 6759 /* image_gather4_l_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40595 { 6759 /* image_gather4_l_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40605 { 6759 /* image_gather4_l_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40615 { 6759 /* image_gather4_l_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40625 { 6759 /* image_gather4_l_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40635 { 6759 /* image_gather4_l_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40645 { 6759 /* image_gather4_l_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40654 { 6777 /* image_gather4_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40663 { 6777 /* image_gather4_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40672 { 6777 /* image_gather4_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40681 { 6777 /* image_gather4_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40690 { 6777 /* image_gather4_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40699 { 6777 /* image_gather4_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40708 { 6777 /* image_gather4_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40717 { 6777 /* image_gather4_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40726 { 6777 /* image_gather4_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40735 { 6777 /* image_gather4_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40744 { 6777 /* image_gather4_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40753 { 6777 /* image_gather4_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40763 { 6777 /* image_gather4_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40773 { 6777 /* image_gather4_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40783 { 6777 /* image_gather4_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40793 { 6777 /* image_gather4_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40803 { 6777 /* image_gather4_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40813 { 6777 /* image_gather4_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40823 { 6777 /* image_gather4_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40833 { 6777 /* image_gather4_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40843 { 6777 /* image_gather4_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40853 { 6777 /* image_gather4_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40863 { 6777 /* image_gather4_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40873 { 6777 /* image_gather4_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40883 { 6777 /* image_gather4_lz */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40893 { 6777 /* image_gather4_lz */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40903 { 6777 /* image_gather4_lz */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40913 { 6777 /* image_gather4_lz */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40923 { 6777 /* image_gather4_lz */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40933 { 6777 /* image_gather4_lz */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
40942 { 6794 /* image_gather4_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40951 { 6794 /* image_gather4_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40960 { 6794 /* image_gather4_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40969 { 6794 /* image_gather4_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40978 { 6794 /* image_gather4_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40987 { 6794 /* image_gather4_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40996 { 6794 /* image_gather4_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41005 { 6794 /* image_gather4_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41014 { 6794 /* image_gather4_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41024 { 6794 /* image_gather4_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41034 { 6794 /* image_gather4_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41044 { 6794 /* image_gather4_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41054 { 6794 /* image_gather4_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41064 { 6794 /* image_gather4_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41074 { 6794 /* image_gather4_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41084 { 6794 /* image_gather4_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41094 { 6794 /* image_gather4_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41104 { 6794 /* image_gather4_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41114 { 6794 /* image_gather4_lz_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41124 { 6794 /* image_gather4_lz_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41134 { 6794 /* image_gather4_lz_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41144 { 6794 /* image_gather4_lz_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41154 { 6794 /* image_gather4_lz_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41164 { 6794 /* image_gather4_lz_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41174 { 6794 /* image_gather4_lz_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41184 { 6794 /* image_gather4_lz_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41194 { 6794 /* image_gather4_lz_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41203 { 6813 /* image_gather4_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41212 { 6813 /* image_gather4_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41221 { 6813 /* image_gather4_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41230 { 6813 /* image_gather4_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41239 { 6813 /* image_gather4_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41248 { 6813 /* image_gather4_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41257 { 6813 /* image_gather4_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41266 { 6813 /* image_gather4_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41275 { 6813 /* image_gather4_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41285 { 6813 /* image_gather4_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41295 { 6813 /* image_gather4_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41305 { 6813 /* image_gather4_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41315 { 6813 /* image_gather4_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41325 { 6813 /* image_gather4_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41335 { 6813 /* image_gather4_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41345 { 6813 /* image_gather4_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41355 { 6813 /* image_gather4_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41365 { 6813 /* image_gather4_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41375 { 6813 /* image_gather4_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41385 { 6813 /* image_gather4_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41395 { 6813 /* image_gather4_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41405 { 6813 /* image_gather4_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41415 { 6813 /* image_gather4_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41425 { 6813 /* image_gather4_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41435 { 6813 /* image_gather4_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41445 { 6813 /* image_gather4_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41455 { 6813 /* image_gather4_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41464 { 6829 /* image_get_lod */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41472 { 6829 /* image_get_lod */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41480 { 6829 /* image_get_lod */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41488 { 6829 /* image_get_lod */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41496 { 6829 /* image_get_lod */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41504 { 6829 /* image_get_lod */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41512 { 6829 /* image_get_lod */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41520 { 6829 /* image_get_lod */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41528 { 6829 /* image_get_lod */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41536 { 6829 /* image_get_lod */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41544 { 6829 /* image_get_lod */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41552 { 6829 /* image_get_lod */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41560 { 6829 /* image_get_lod */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41568 { 6829 /* image_get_lod */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41576 { 6829 /* image_get_lod */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41584 { 6829 /* image_get_lod */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41592 { 6829 /* image_get_lod */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41600 { 6829 /* image_get_lod */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41608 { 6829 /* image_get_lod */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41616 { 6829 /* image_get_lod */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41625 { 6829 /* image_get_lod */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41634 { 6829 /* image_get_lod */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41643 { 6829 /* image_get_lod */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41652 { 6829 /* image_get_lod */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41661 { 6829 /* image_get_lod */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41670 { 6829 /* image_get_lod */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41679 { 6829 /* image_get_lod */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41688 { 6829 /* image_get_lod */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41697 { 6829 /* image_get_lod */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41706 { 6829 /* image_get_lod */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41715 { 6829 /* image_get_lod */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41724 { 6829 /* image_get_lod */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41733 { 6829 /* image_get_lod */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41742 { 6829 /* image_get_lod */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41751 { 6829 /* image_get_lod */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41760 { 6829 /* image_get_lod */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41769 { 6829 /* image_get_lod */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41778 { 6829 /* image_get_lod */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41787 { 6829 /* image_get_lod */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41796 { 6829 /* image_get_lod */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41805 { 6829 /* image_get_lod */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41814 { 6829 /* image_get_lod */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41823 { 6829 /* image_get_lod */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41832 { 6829 /* image_get_lod */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41841 { 6829 /* image_get_lod */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41850 { 6829 /* image_get_lod */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41859 { 6829 /* image_get_lod */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41868 { 6829 /* image_get_lod */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41877 { 6829 /* image_get_lod */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41886 { 6829 /* image_get_lod */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
41894 { 6843 /* image_get_resinfo */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41902 { 6843 /* image_get_resinfo */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41910 { 6843 /* image_get_resinfo */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41918 { 6843 /* image_get_resinfo */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41926 { 6843 /* image_get_resinfo */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41934 { 6843 /* image_get_resinfo */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41942 { 6843 /* image_get_resinfo */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41950 { 6843 /* image_get_resinfo */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41958 { 6843 /* image_get_resinfo */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41966 { 6843 /* image_get_resinfo */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41974 { 6843 /* image_get_resinfo */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41982 { 6843 /* image_get_resinfo */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41990 { 6843 /* image_get_resinfo */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41998 { 6843 /* image_get_resinfo */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42006 { 6843 /* image_get_resinfo */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42014 { 6843 /* image_get_resinfo */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42022 { 6843 /* image_get_resinfo */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42030 { 6843 /* image_get_resinfo */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42038 { 6843 /* image_get_resinfo */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42046 { 6843 /* image_get_resinfo */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42055 { 6843 /* image_get_resinfo */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42064 { 6843 /* image_get_resinfo */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42073 { 6843 /* image_get_resinfo */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42082 { 6843 /* image_get_resinfo */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42091 { 6843 /* image_get_resinfo */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42100 { 6843 /* image_get_resinfo */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42109 { 6843 /* image_get_resinfo */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42118 { 6843 /* image_get_resinfo */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42127 { 6843 /* image_get_resinfo */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42136 { 6843 /* image_get_resinfo */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42145 { 6843 /* image_get_resinfo */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42154 { 6843 /* image_get_resinfo */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42163 { 6843 /* image_get_resinfo */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42172 { 6843 /* image_get_resinfo */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42181 { 6843 /* image_get_resinfo */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42190 { 6843 /* image_get_resinfo */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42199 { 6843 /* image_get_resinfo */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42208 { 6843 /* image_get_resinfo */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42217 { 6843 /* image_get_resinfo */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42226 { 6843 /* image_get_resinfo */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42235 { 6843 /* image_get_resinfo */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42244 { 6843 /* image_get_resinfo */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42253 { 6843 /* image_get_resinfo */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42262 { 6843 /* image_get_resinfo */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42271 { 6843 /* image_get_resinfo */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42280 { 6843 /* image_get_resinfo */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42289 { 6843 /* image_get_resinfo */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42298 { 6843 /* image_get_resinfo */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42307 { 6843 /* image_get_resinfo */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42316 { 6843 /* image_get_resinfo */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42325 { 6843 /* image_get_resinfo */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42334 { 6843 /* image_get_resinfo */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42343 { 6843 /* image_get_resinfo */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42352 { 6843 /* image_get_resinfo */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42361 { 6843 /* image_get_resinfo */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42369 { 6861 /* image_load */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42378 { 6861 /* image_load */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42387 { 6861 /* image_load */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42396 { 6861 /* image_load */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42405 { 6861 /* image_load */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42414 { 6861 /* image_load */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42423 { 6861 /* image_load */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42432 { 6861 /* image_load */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42441 { 6861 /* image_load */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42450 { 6861 /* image_load */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42459 { 6861 /* image_load */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42468 { 6861 /* image_load */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42477 { 6861 /* image_load */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42486 { 6861 /* image_load */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42495 { 6861 /* image_load */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42504 { 6861 /* image_load */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42513 { 6861 /* image_load */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42522 { 6861 /* image_load */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42531 { 6861 /* image_load */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42540 { 6861 /* image_load */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42550 { 6861 /* image_load */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42560 { 6861 /* image_load */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42570 { 6861 /* image_load */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42580 { 6861 /* image_load */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42590 { 6861 /* image_load */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42600 { 6861 /* image_load */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42610 { 6861 /* image_load */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42620 { 6861 /* image_load */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42630 { 6861 /* image_load */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42640 { 6861 /* image_load */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42650 { 6861 /* image_load */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42660 { 6861 /* image_load */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42670 { 6861 /* image_load */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42680 { 6861 /* image_load */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42690 { 6861 /* image_load */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42700 { 6861 /* image_load */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42710 { 6861 /* image_load */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42720 { 6861 /* image_load */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42730 { 6861 /* image_load */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42740 { 6861 /* image_load */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42750 { 6861 /* image_load */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42760 { 6861 /* image_load */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42770 { 6861 /* image_load */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42780 { 6861 /* image_load */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42790 { 6861 /* image_load */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42800 { 6861 /* image_load */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42810 { 6861 /* image_load */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42820 { 6861 /* image_load */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42830 { 6861 /* image_load */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42840 { 6861 /* image_load */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42850 { 6861 /* image_load */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42860 { 6861 /* image_load */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42870 { 6861 /* image_load */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42880 { 6861 /* image_load */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42890 { 6861 /* image_load */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
42899 { 6872 /* image_load_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42908 { 6872 /* image_load_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42917 { 6872 /* image_load_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42926 { 6872 /* image_load_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42935 { 6872 /* image_load_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42944 { 6872 /* image_load_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42953 { 6872 /* image_load_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42962 { 6872 /* image_load_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42971 { 6872 /* image_load_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42980 { 6872 /* image_load_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42989 { 6872 /* image_load_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42998 { 6872 /* image_load_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43007 { 6872 /* image_load_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43016 { 6872 /* image_load_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43025 { 6872 /* image_load_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43034 { 6872 /* image_load_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43043 { 6872 /* image_load_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43052 { 6872 /* image_load_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43061 { 6872 /* image_load_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43070 { 6872 /* image_load_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43080 { 6872 /* image_load_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43090 { 6872 /* image_load_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43100 { 6872 /* image_load_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43110 { 6872 /* image_load_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43120 { 6872 /* image_load_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43130 { 6872 /* image_load_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43140 { 6872 /* image_load_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43150 { 6872 /* image_load_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43160 { 6872 /* image_load_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43170 { 6872 /* image_load_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43180 { 6872 /* image_load_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43190 { 6872 /* image_load_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43200 { 6872 /* image_load_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43210 { 6872 /* image_load_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43220 { 6872 /* image_load_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43230 { 6872 /* image_load_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43240 { 6872 /* image_load_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43250 { 6872 /* image_load_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43260 { 6872 /* image_load_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43270 { 6872 /* image_load_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43280 { 6872 /* image_load_mip */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43290 { 6872 /* image_load_mip */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43300 { 6872 /* image_load_mip */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43310 { 6872 /* image_load_mip */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43320 { 6872 /* image_load_mip */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43330 { 6872 /* image_load_mip */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43340 { 6872 /* image_load_mip */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43350 { 6872 /* image_load_mip */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43360 { 6872 /* image_load_mip */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43370 { 6872 /* image_load_mip */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43380 { 6872 /* image_load_mip */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43390 { 6872 /* image_load_mip */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43400 { 6872 /* image_load_mip */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43410 { 6872 /* image_load_mip */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43420 { 6872 /* image_load_mip */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43429 { 6887 /* image_load_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43437 { 6887 /* image_load_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43445 { 6887 /* image_load_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43453 { 6887 /* image_load_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43461 { 6887 /* image_load_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43469 { 6887 /* image_load_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43477 { 6887 /* image_load_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43485 { 6887 /* image_load_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43493 { 6887 /* image_load_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43501 { 6887 /* image_load_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43509 { 6887 /* image_load_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43517 { 6887 /* image_load_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43525 { 6887 /* image_load_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43533 { 6887 /* image_load_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43541 { 6887 /* image_load_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43549 { 6887 /* image_load_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43557 { 6887 /* image_load_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43565 { 6887 /* image_load_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43573 { 6887 /* image_load_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43581 { 6887 /* image_load_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43590 { 6887 /* image_load_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43599 { 6887 /* image_load_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43608 { 6887 /* image_load_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43617 { 6887 /* image_load_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43626 { 6887 /* image_load_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43635 { 6887 /* image_load_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43644 { 6887 /* image_load_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43653 { 6887 /* image_load_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43662 { 6887 /* image_load_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43671 { 6887 /* image_load_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43680 { 6887 /* image_load_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43689 { 6887 /* image_load_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43698 { 6887 /* image_load_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43707 { 6887 /* image_load_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43716 { 6887 /* image_load_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43725 { 6887 /* image_load_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43734 { 6887 /* image_load_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43743 { 6887 /* image_load_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43752 { 6887 /* image_load_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43761 { 6887 /* image_load_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43770 { 6887 /* image_load_mip_pck */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43779 { 6887 /* image_load_mip_pck */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43788 { 6887 /* image_load_mip_pck */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43797 { 6887 /* image_load_mip_pck */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43806 { 6887 /* image_load_mip_pck */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43815 { 6887 /* image_load_mip_pck */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43824 { 6887 /* image_load_mip_pck */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43833 { 6887 /* image_load_mip_pck */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43842 { 6887 /* image_load_mip_pck */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43851 { 6887 /* image_load_mip_pck */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43860 { 6887 /* image_load_mip_pck */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43869 { 6887 /* image_load_mip_pck */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43878 { 6887 /* image_load_mip_pck */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43887 { 6887 /* image_load_mip_pck */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43896 { 6887 /* image_load_mip_pck */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
43904 { 6906 /* image_load_mip_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43912 { 6906 /* image_load_mip_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43920 { 6906 /* image_load_mip_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43928 { 6906 /* image_load_mip_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43936 { 6906 /* image_load_mip_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43944 { 6906 /* image_load_mip_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43952 { 6906 /* image_load_mip_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43960 { 6906 /* image_load_mip_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43968 { 6906 /* image_load_mip_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43976 { 6906 /* image_load_mip_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43984 { 6906 /* image_load_mip_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43992 { 6906 /* image_load_mip_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44000 { 6906 /* image_load_mip_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44008 { 6906 /* image_load_mip_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44016 { 6906 /* image_load_mip_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44024 { 6906 /* image_load_mip_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44032 { 6906 /* image_load_mip_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44040 { 6906 /* image_load_mip_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44048 { 6906 /* image_load_mip_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44056 { 6906 /* image_load_mip_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44065 { 6906 /* image_load_mip_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44074 { 6906 /* image_load_mip_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44083 { 6906 /* image_load_mip_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44092 { 6906 /* image_load_mip_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44101 { 6906 /* image_load_mip_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44110 { 6906 /* image_load_mip_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44119 { 6906 /* image_load_mip_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44128 { 6906 /* image_load_mip_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44137 { 6906 /* image_load_mip_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44146 { 6906 /* image_load_mip_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44155 { 6906 /* image_load_mip_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44164 { 6906 /* image_load_mip_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44173 { 6906 /* image_load_mip_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44182 { 6906 /* image_load_mip_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44191 { 6906 /* image_load_mip_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44200 { 6906 /* image_load_mip_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44209 { 6906 /* image_load_mip_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44218 { 6906 /* image_load_mip_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44227 { 6906 /* image_load_mip_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44236 { 6906 /* image_load_mip_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44245 { 6906 /* image_load_mip_pck_sgn */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44254 { 6906 /* image_load_mip_pck_sgn */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44263 { 6906 /* image_load_mip_pck_sgn */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44272 { 6906 /* image_load_mip_pck_sgn */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44281 { 6906 /* image_load_mip_pck_sgn */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44290 { 6906 /* image_load_mip_pck_sgn */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44299 { 6906 /* image_load_mip_pck_sgn */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44308 { 6906 /* image_load_mip_pck_sgn */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44317 { 6906 /* image_load_mip_pck_sgn */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44326 { 6906 /* image_load_mip_pck_sgn */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44335 { 6906 /* image_load_mip_pck_sgn */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44344 { 6906 /* image_load_mip_pck_sgn */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44353 { 6906 /* image_load_mip_pck_sgn */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44362 { 6906 /* image_load_mip_pck_sgn */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44371 { 6906 /* image_load_mip_pck_sgn */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44379 { 6929 /* image_load_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44387 { 6929 /* image_load_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44395 { 6929 /* image_load_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44403 { 6929 /* image_load_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44411 { 6929 /* image_load_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44419 { 6929 /* image_load_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44427 { 6929 /* image_load_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44435 { 6929 /* image_load_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44443 { 6929 /* image_load_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44451 { 6929 /* image_load_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44459 { 6929 /* image_load_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44467 { 6929 /* image_load_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44475 { 6929 /* image_load_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44483 { 6929 /* image_load_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44491 { 6929 /* image_load_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44499 { 6929 /* image_load_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44507 { 6929 /* image_load_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44515 { 6929 /* image_load_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44523 { 6929 /* image_load_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44531 { 6929 /* image_load_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44540 { 6929 /* image_load_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44549 { 6929 /* image_load_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44558 { 6929 /* image_load_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44567 { 6929 /* image_load_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44576 { 6929 /* image_load_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44585 { 6929 /* image_load_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44594 { 6929 /* image_load_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44603 { 6929 /* image_load_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44612 { 6929 /* image_load_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44621 { 6929 /* image_load_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44630 { 6929 /* image_load_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44639 { 6929 /* image_load_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44648 { 6929 /* image_load_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44657 { 6929 /* image_load_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44666 { 6929 /* image_load_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44675 { 6929 /* image_load_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44684 { 6929 /* image_load_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44693 { 6929 /* image_load_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44702 { 6929 /* image_load_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44711 { 6929 /* image_load_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44720 { 6929 /* image_load_pck */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44729 { 6929 /* image_load_pck */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44738 { 6929 /* image_load_pck */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44747 { 6929 /* image_load_pck */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44756 { 6929 /* image_load_pck */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44765 { 6929 /* image_load_pck */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44774 { 6929 /* image_load_pck */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44783 { 6929 /* image_load_pck */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44792 { 6929 /* image_load_pck */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44801 { 6929 /* image_load_pck */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44810 { 6929 /* image_load_pck */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44819 { 6929 /* image_load_pck */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44828 { 6929 /* image_load_pck */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44837 { 6929 /* image_load_pck */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44846 { 6929 /* image_load_pck */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
44854 { 6944 /* image_load_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44862 { 6944 /* image_load_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44870 { 6944 /* image_load_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44878 { 6944 /* image_load_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44886 { 6944 /* image_load_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44894 { 6944 /* image_load_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44902 { 6944 /* image_load_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44910 { 6944 /* image_load_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44918 { 6944 /* image_load_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44926 { 6944 /* image_load_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44934 { 6944 /* image_load_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44942 { 6944 /* image_load_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44950 { 6944 /* image_load_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44958 { 6944 /* image_load_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44966 { 6944 /* image_load_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44974 { 6944 /* image_load_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44982 { 6944 /* image_load_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44990 { 6944 /* image_load_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44998 { 6944 /* image_load_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45006 { 6944 /* image_load_pck_sgn */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45015 { 6944 /* image_load_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45024 { 6944 /* image_load_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45033 { 6944 /* image_load_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45042 { 6944 /* image_load_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45051 { 6944 /* image_load_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45060 { 6944 /* image_load_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45069 { 6944 /* image_load_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45078 { 6944 /* image_load_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45087 { 6944 /* image_load_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45096 { 6944 /* image_load_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45105 { 6944 /* image_load_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45114 { 6944 /* image_load_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45123 { 6944 /* image_load_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45132 { 6944 /* image_load_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45141 { 6944 /* image_load_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45150 { 6944 /* image_load_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45159 { 6944 /* image_load_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45168 { 6944 /* image_load_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45177 { 6944 /* image_load_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45186 { 6944 /* image_load_pck_sgn */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45195 { 6944 /* image_load_pck_sgn */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45204 { 6944 /* image_load_pck_sgn */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45213 { 6944 /* image_load_pck_sgn */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45222 { 6944 /* image_load_pck_sgn */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45231 { 6944 /* image_load_pck_sgn */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45240 { 6944 /* image_load_pck_sgn */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45249 { 6944 /* image_load_pck_sgn */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45258 { 6944 /* image_load_pck_sgn */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45267 { 6944 /* image_load_pck_sgn */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45276 { 6944 /* image_load_pck_sgn */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45285 { 6944 /* image_load_pck_sgn */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45294 { 6944 /* image_load_pck_sgn */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45303 { 6944 /* image_load_pck_sgn */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45312 { 6944 /* image_load_pck_sgn */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45321 { 6944 /* image_load_pck_sgn */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45329 { 6963 /* image_sample */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45338 { 6963 /* image_sample */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45347 { 6963 /* image_sample */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45356 { 6963 /* image_sample */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45365 { 6963 /* image_sample */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45374 { 6963 /* image_sample */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45383 { 6963 /* image_sample */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45392 { 6963 /* image_sample */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45401 { 6963 /* image_sample */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45410 { 6963 /* image_sample */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45419 { 6963 /* image_sample */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45428 { 6963 /* image_sample */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45437 { 6963 /* image_sample */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45446 { 6963 /* image_sample */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45455 { 6963 /* image_sample */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45464 { 6963 /* image_sample */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45473 { 6963 /* image_sample */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45482 { 6963 /* image_sample */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45491 { 6963 /* image_sample */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45500 { 6963 /* image_sample */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45510 { 6963 /* image_sample */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45520 { 6963 /* image_sample */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45530 { 6963 /* image_sample */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45540 { 6963 /* image_sample */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45550 { 6963 /* image_sample */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45560 { 6963 /* image_sample */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45570 { 6963 /* image_sample */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45580 { 6963 /* image_sample */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45590 { 6963 /* image_sample */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45600 { 6963 /* image_sample */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45610 { 6963 /* image_sample */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45620 { 6963 /* image_sample */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45630 { 6963 /* image_sample */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45640 { 6963 /* image_sample */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45650 { 6963 /* image_sample */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45660 { 6963 /* image_sample */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45670 { 6963 /* image_sample */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45680 { 6963 /* image_sample */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45690 { 6963 /* image_sample */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45700 { 6963 /* image_sample */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45710 { 6963 /* image_sample */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45720 { 6963 /* image_sample */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45730 { 6963 /* image_sample */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45740 { 6963 /* image_sample */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45750 { 6963 /* image_sample */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45760 { 6963 /* image_sample */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45770 { 6963 /* image_sample */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45780 { 6963 /* image_sample */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45790 { 6963 /* image_sample */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45800 { 6963 /* image_sample */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45809 { 6976 /* image_sample_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45818 { 6976 /* image_sample_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45827 { 6976 /* image_sample_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45836 { 6976 /* image_sample_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45845 { 6976 /* image_sample_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45854 { 6976 /* image_sample_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45863 { 6976 /* image_sample_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45872 { 6976 /* image_sample_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45881 { 6976 /* image_sample_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45890 { 6976 /* image_sample_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45899 { 6976 /* image_sample_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45908 { 6976 /* image_sample_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45917 { 6976 /* image_sample_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45926 { 6976 /* image_sample_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45935 { 6976 /* image_sample_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45945 { 6976 /* image_sample_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45955 { 6976 /* image_sample_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45965 { 6976 /* image_sample_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45975 { 6976 /* image_sample_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45985 { 6976 /* image_sample_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
45995 { 6976 /* image_sample_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46005 { 6976 /* image_sample_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46015 { 6976 /* image_sample_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46025 { 6976 /* image_sample_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46035 { 6976 /* image_sample_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46045 { 6976 /* image_sample_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46055 { 6976 /* image_sample_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46065 { 6976 /* image_sample_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46075 { 6976 /* image_sample_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46085 { 6976 /* image_sample_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46095 { 6976 /* image_sample_b */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46105 { 6976 /* image_sample_b */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46115 { 6976 /* image_sample_b */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46125 { 6976 /* image_sample_b */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46135 { 6976 /* image_sample_b */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46145 { 6976 /* image_sample_b */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46155 { 6976 /* image_sample_b */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46165 { 6976 /* image_sample_b */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46175 { 6976 /* image_sample_b */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46185 { 6976 /* image_sample_b */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46195 { 6976 /* image_sample_b */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46205 { 6976 /* image_sample_b */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46215 { 6976 /* image_sample_b */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46225 { 6976 /* image_sample_b */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46235 { 6976 /* image_sample_b */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46244 { 6991 /* image_sample_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46253 { 6991 /* image_sample_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46262 { 6991 /* image_sample_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46271 { 6991 /* image_sample_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46280 { 6991 /* image_sample_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46289 { 6991 /* image_sample_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46298 { 6991 /* image_sample_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46307 { 6991 /* image_sample_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46316 { 6991 /* image_sample_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46325 { 6991 /* image_sample_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46334 { 6991 /* image_sample_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46343 { 6991 /* image_sample_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46352 { 6991 /* image_sample_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46361 { 6991 /* image_sample_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46370 { 6991 /* image_sample_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46379 { 6991 /* image_sample_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46388 { 6991 /* image_sample_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46397 { 6991 /* image_sample_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46406 { 6991 /* image_sample_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46415 { 6991 /* image_sample_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46425 { 6991 /* image_sample_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46435 { 6991 /* image_sample_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46445 { 6991 /* image_sample_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46455 { 6991 /* image_sample_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46465 { 6991 /* image_sample_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46475 { 6991 /* image_sample_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46485 { 6991 /* image_sample_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46495 { 6991 /* image_sample_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46505 { 6991 /* image_sample_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46515 { 6991 /* image_sample_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46525 { 6991 /* image_sample_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46535 { 6991 /* image_sample_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46545 { 6991 /* image_sample_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46555 { 6991 /* image_sample_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46565 { 6991 /* image_sample_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46575 { 6991 /* image_sample_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46585 { 6991 /* image_sample_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46595 { 6991 /* image_sample_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46605 { 6991 /* image_sample_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46615 { 6991 /* image_sample_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46625 { 6991 /* image_sample_b_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46635 { 6991 /* image_sample_b_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46645 { 6991 /* image_sample_b_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46655 { 6991 /* image_sample_b_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46665 { 6991 /* image_sample_b_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46675 { 6991 /* image_sample_b_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46685 { 6991 /* image_sample_b_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46695 { 6991 /* image_sample_b_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46705 { 6991 /* image_sample_b_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46715 { 6991 /* image_sample_b_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46725 { 6991 /* image_sample_b_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46735 { 6991 /* image_sample_b_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46745 { 6991 /* image_sample_b_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46755 { 6991 /* image_sample_b_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46765 { 6991 /* image_sample_b_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46775 { 6991 /* image_sample_b_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46785 { 6991 /* image_sample_b_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46795 { 6991 /* image_sample_b_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46805 { 6991 /* image_sample_b_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46815 { 6991 /* image_sample_b_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46824 { 7009 /* image_sample_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46833 { 7009 /* image_sample_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46842 { 7009 /* image_sample_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46851 { 7009 /* image_sample_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46860 { 7009 /* image_sample_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46869 { 7009 /* image_sample_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46878 { 7009 /* image_sample_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46887 { 7009 /* image_sample_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46896 { 7009 /* image_sample_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46905 { 7009 /* image_sample_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46914 { 7009 /* image_sample_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46923 { 7009 /* image_sample_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46932 { 7009 /* image_sample_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46941 { 7009 /* image_sample_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46950 { 7009 /* image_sample_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46960 { 7009 /* image_sample_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46970 { 7009 /* image_sample_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46980 { 7009 /* image_sample_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
46990 { 7009 /* image_sample_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47000 { 7009 /* image_sample_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47010 { 7009 /* image_sample_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47020 { 7009 /* image_sample_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47030 { 7009 /* image_sample_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47040 { 7009 /* image_sample_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47050 { 7009 /* image_sample_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47060 { 7009 /* image_sample_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47070 { 7009 /* image_sample_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47080 { 7009 /* image_sample_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47090 { 7009 /* image_sample_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47100 { 7009 /* image_sample_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47110 { 7009 /* image_sample_b_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47120 { 7009 /* image_sample_b_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47130 { 7009 /* image_sample_b_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47140 { 7009 /* image_sample_b_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47150 { 7009 /* image_sample_b_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47160 { 7009 /* image_sample_b_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47170 { 7009 /* image_sample_b_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47180 { 7009 /* image_sample_b_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47190 { 7009 /* image_sample_b_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47200 { 7009 /* image_sample_b_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47210 { 7009 /* image_sample_b_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47220 { 7009 /* image_sample_b_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47230 { 7009 /* image_sample_b_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47240 { 7009 /* image_sample_b_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47250 { 7009 /* image_sample_b_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47260 { 7009 /* image_sample_b_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47270 { 7009 /* image_sample_b_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47280 { 7009 /* image_sample_b_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47290 { 7009 /* image_sample_b_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47300 { 7009 /* image_sample_b_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47309 { 7029 /* image_sample_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47318 { 7029 /* image_sample_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47327 { 7029 /* image_sample_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47336 { 7029 /* image_sample_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47345 { 7029 /* image_sample_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47354 { 7029 /* image_sample_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47363 { 7029 /* image_sample_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47372 { 7029 /* image_sample_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47381 { 7029 /* image_sample_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47390 { 7029 /* image_sample_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47399 { 7029 /* image_sample_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47408 { 7029 /* image_sample_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47417 { 7029 /* image_sample_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47426 { 7029 /* image_sample_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47435 { 7029 /* image_sample_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47445 { 7029 /* image_sample_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47455 { 7029 /* image_sample_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47465 { 7029 /* image_sample_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47475 { 7029 /* image_sample_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47485 { 7029 /* image_sample_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47495 { 7029 /* image_sample_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47505 { 7029 /* image_sample_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47515 { 7029 /* image_sample_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47525 { 7029 /* image_sample_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47535 { 7029 /* image_sample_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47545 { 7029 /* image_sample_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47555 { 7029 /* image_sample_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47565 { 7029 /* image_sample_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47575 { 7029 /* image_sample_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47585 { 7029 /* image_sample_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47595 { 7029 /* image_sample_b_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47605 { 7029 /* image_sample_b_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47615 { 7029 /* image_sample_b_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47625 { 7029 /* image_sample_b_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47635 { 7029 /* image_sample_b_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47645 { 7029 /* image_sample_b_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47655 { 7029 /* image_sample_b_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47665 { 7029 /* image_sample_b_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47675 { 7029 /* image_sample_b_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47685 { 7029 /* image_sample_b_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47695 { 7029 /* image_sample_b_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47705 { 7029 /* image_sample_b_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47715 { 7029 /* image_sample_b_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47725 { 7029 /* image_sample_b_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47735 { 7029 /* image_sample_b_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47744 { 7046 /* image_sample_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47753 { 7046 /* image_sample_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47762 { 7046 /* image_sample_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47771 { 7046 /* image_sample_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47780 { 7046 /* image_sample_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47789 { 7046 /* image_sample_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47798 { 7046 /* image_sample_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47807 { 7046 /* image_sample_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47816 { 7046 /* image_sample_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47825 { 7046 /* image_sample_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47834 { 7046 /* image_sample_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47843 { 7046 /* image_sample_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47852 { 7046 /* image_sample_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47861 { 7046 /* image_sample_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47870 { 7046 /* image_sample_c */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47880 { 7046 /* image_sample_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47890 { 7046 /* image_sample_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47900 { 7046 /* image_sample_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47910 { 7046 /* image_sample_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47920 { 7046 /* image_sample_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47930 { 7046 /* image_sample_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47940 { 7046 /* image_sample_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47950 { 7046 /* image_sample_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47960 { 7046 /* image_sample_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47970 { 7046 /* image_sample_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47980 { 7046 /* image_sample_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
47990 { 7046 /* image_sample_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48000 { 7046 /* image_sample_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48010 { 7046 /* image_sample_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48020 { 7046 /* image_sample_c */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48030 { 7046 /* image_sample_c */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48040 { 7046 /* image_sample_c */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48050 { 7046 /* image_sample_c */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48060 { 7046 /* image_sample_c */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48070 { 7046 /* image_sample_c */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48080 { 7046 /* image_sample_c */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48090 { 7046 /* image_sample_c */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48100 { 7046 /* image_sample_c */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48110 { 7046 /* image_sample_c */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48120 { 7046 /* image_sample_c */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48130 { 7046 /* image_sample_c */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48140 { 7046 /* image_sample_c */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48150 { 7046 /* image_sample_c */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48160 { 7046 /* image_sample_c */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48170 { 7046 /* image_sample_c */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48179 { 7061 /* image_sample_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48188 { 7061 /* image_sample_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48197 { 7061 /* image_sample_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48206 { 7061 /* image_sample_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48215 { 7061 /* image_sample_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48224 { 7061 /* image_sample_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48233 { 7061 /* image_sample_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48242 { 7061 /* image_sample_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48251 { 7061 /* image_sample_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48260 { 7061 /* image_sample_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48269 { 7061 /* image_sample_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48278 { 7061 /* image_sample_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48287 { 7061 /* image_sample_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48296 { 7061 /* image_sample_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48305 { 7061 /* image_sample_c_b */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48315 { 7061 /* image_sample_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48325 { 7061 /* image_sample_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48335 { 7061 /* image_sample_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48345 { 7061 /* image_sample_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48355 { 7061 /* image_sample_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48365 { 7061 /* image_sample_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48375 { 7061 /* image_sample_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48385 { 7061 /* image_sample_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48395 { 7061 /* image_sample_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48405 { 7061 /* image_sample_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48415 { 7061 /* image_sample_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48425 { 7061 /* image_sample_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48435 { 7061 /* image_sample_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48445 { 7061 /* image_sample_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48455 { 7061 /* image_sample_c_b */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48465 { 7061 /* image_sample_c_b */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48475 { 7061 /* image_sample_c_b */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48485 { 7061 /* image_sample_c_b */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48495 { 7061 /* image_sample_c_b */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48505 { 7061 /* image_sample_c_b */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48515 { 7061 /* image_sample_c_b */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48525 { 7061 /* image_sample_c_b */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48535 { 7061 /* image_sample_c_b */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48545 { 7061 /* image_sample_c_b */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48555 { 7061 /* image_sample_c_b */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48565 { 7061 /* image_sample_c_b */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48575 { 7061 /* image_sample_c_b */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48585 { 7061 /* image_sample_c_b */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48595 { 7061 /* image_sample_c_b */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48605 { 7061 /* image_sample_c_b */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48614 { 7078 /* image_sample_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48623 { 7078 /* image_sample_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48632 { 7078 /* image_sample_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48641 { 7078 /* image_sample_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48650 { 7078 /* image_sample_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48659 { 7078 /* image_sample_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48668 { 7078 /* image_sample_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48677 { 7078 /* image_sample_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48686 { 7078 /* image_sample_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48695 { 7078 /* image_sample_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48704 { 7078 /* image_sample_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48713 { 7078 /* image_sample_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48722 { 7078 /* image_sample_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48731 { 7078 /* image_sample_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48740 { 7078 /* image_sample_c_b_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48750 { 7078 /* image_sample_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48760 { 7078 /* image_sample_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48770 { 7078 /* image_sample_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48780 { 7078 /* image_sample_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48790 { 7078 /* image_sample_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48800 { 7078 /* image_sample_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48810 { 7078 /* image_sample_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48820 { 7078 /* image_sample_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48830 { 7078 /* image_sample_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48840 { 7078 /* image_sample_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48850 { 7078 /* image_sample_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48860 { 7078 /* image_sample_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48870 { 7078 /* image_sample_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48880 { 7078 /* image_sample_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48890 { 7078 /* image_sample_c_b_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48900 { 7078 /* image_sample_c_b_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48910 { 7078 /* image_sample_c_b_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48920 { 7078 /* image_sample_c_b_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48930 { 7078 /* image_sample_c_b_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48940 { 7078 /* image_sample_c_b_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48950 { 7078 /* image_sample_c_b_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48960 { 7078 /* image_sample_c_b_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48970 { 7078 /* image_sample_c_b_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48980 { 7078 /* image_sample_c_b_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
48990 { 7078 /* image_sample_c_b_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49000 { 7078 /* image_sample_c_b_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49010 { 7078 /* image_sample_c_b_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49020 { 7078 /* image_sample_c_b_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49030 { 7078 /* image_sample_c_b_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49040 { 7078 /* image_sample_c_b_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49050 { 7078 /* image_sample_c_b_cl */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49060 { 7078 /* image_sample_c_b_cl */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49070 { 7078 /* image_sample_c_b_cl */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49080 { 7078 /* image_sample_c_b_cl */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49090 { 7078 /* image_sample_c_b_cl */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49099 { 7098 /* image_sample_c_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49108 { 7098 /* image_sample_c_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49117 { 7098 /* image_sample_c_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49126 { 7098 /* image_sample_c_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49135 { 7098 /* image_sample_c_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49144 { 7098 /* image_sample_c_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49153 { 7098 /* image_sample_c_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49162 { 7098 /* image_sample_c_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49171 { 7098 /* image_sample_c_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49180 { 7098 /* image_sample_c_b_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49190 { 7098 /* image_sample_c_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49200 { 7098 /* image_sample_c_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49210 { 7098 /* image_sample_c_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49220 { 7098 /* image_sample_c_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49230 { 7098 /* image_sample_c_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49240 { 7098 /* image_sample_c_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49250 { 7098 /* image_sample_c_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49260 { 7098 /* image_sample_c_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49270 { 7098 /* image_sample_c_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49280 { 7098 /* image_sample_c_b_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49290 { 7098 /* image_sample_c_b_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49300 { 7098 /* image_sample_c_b_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49310 { 7098 /* image_sample_c_b_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49320 { 7098 /* image_sample_c_b_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49330 { 7098 /* image_sample_c_b_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49340 { 7098 /* image_sample_c_b_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49350 { 7098 /* image_sample_c_b_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49360 { 7098 /* image_sample_c_b_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49370 { 7098 /* image_sample_c_b_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49380 { 7098 /* image_sample_c_b_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49390 { 7098 /* image_sample_c_b_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49400 { 7098 /* image_sample_c_b_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49410 { 7098 /* image_sample_c_b_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49420 { 7098 /* image_sample_c_b_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49430 { 7098 /* image_sample_c_b_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49440 { 7098 /* image_sample_c_b_cl_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49450 { 7098 /* image_sample_c_b_cl_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49460 { 7098 /* image_sample_c_b_cl_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49470 { 7098 /* image_sample_c_b_cl_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49480 { 7098 /* image_sample_c_b_cl_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49489 { 7120 /* image_sample_c_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49498 { 7120 /* image_sample_c_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49507 { 7120 /* image_sample_c_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49516 { 7120 /* image_sample_c_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49525 { 7120 /* image_sample_c_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49534 { 7120 /* image_sample_c_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49543 { 7120 /* image_sample_c_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49552 { 7120 /* image_sample_c_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49561 { 7120 /* image_sample_c_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49570 { 7120 /* image_sample_c_b_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49580 { 7120 /* image_sample_c_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49590 { 7120 /* image_sample_c_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49600 { 7120 /* image_sample_c_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49610 { 7120 /* image_sample_c_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49620 { 7120 /* image_sample_c_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49630 { 7120 /* image_sample_c_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49640 { 7120 /* image_sample_c_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49650 { 7120 /* image_sample_c_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49660 { 7120 /* image_sample_c_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49670 { 7120 /* image_sample_c_b_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49680 { 7120 /* image_sample_c_b_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49690 { 7120 /* image_sample_c_b_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49700 { 7120 /* image_sample_c_b_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49710 { 7120 /* image_sample_c_b_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49720 { 7120 /* image_sample_c_b_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49730 { 7120 /* image_sample_c_b_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49740 { 7120 /* image_sample_c_b_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49750 { 7120 /* image_sample_c_b_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49760 { 7120 /* image_sample_c_b_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49770 { 7120 /* image_sample_c_b_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49780 { 7120 /* image_sample_c_b_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49790 { 7120 /* image_sample_c_b_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49800 { 7120 /* image_sample_c_b_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49810 { 7120 /* image_sample_c_b_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49820 { 7120 /* image_sample_c_b_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
49829 { 7139 /* image_sample_c_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49838 { 7139 /* image_sample_c_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49847 { 7139 /* image_sample_c_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49856 { 7139 /* image_sample_c_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49865 { 7139 /* image_sample_c_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49874 { 7139 /* image_sample_c_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49883 { 7139 /* image_sample_c_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49892 { 7139 /* image_sample_c_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49901 { 7139 /* image_sample_c_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49910 { 7139 /* image_sample_c_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49919 { 7139 /* image_sample_c_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49928 { 7139 /* image_sample_c_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49937 { 7139 /* image_sample_c_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49946 { 7139 /* image_sample_c_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49955 { 7139 /* image_sample_c_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49964 { 7139 /* image_sample_c_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49973 { 7139 /* image_sample_c_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49982 { 7139 /* image_sample_c_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49991 { 7139 /* image_sample_c_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50000 { 7139 /* image_sample_c_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50010 { 7139 /* image_sample_c_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50020 { 7139 /* image_sample_c_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50030 { 7139 /* image_sample_c_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50040 { 7139 /* image_sample_c_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50050 { 7139 /* image_sample_c_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50060 { 7139 /* image_sample_c_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50070 { 7139 /* image_sample_c_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50080 { 7139 /* image_sample_c_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50090 { 7139 /* image_sample_c_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50100 { 7139 /* image_sample_c_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50110 { 7139 /* image_sample_c_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50120 { 7139 /* image_sample_c_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50130 { 7139 /* image_sample_c_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50140 { 7139 /* image_sample_c_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50150 { 7139 /* image_sample_c_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50160 { 7139 /* image_sample_c_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50170 { 7139 /* image_sample_c_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50180 { 7139 /* image_sample_c_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50190 { 7139 /* image_sample_c_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50200 { 7139 /* image_sample_c_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50210 { 7139 /* image_sample_c_cd */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50220 { 7139 /* image_sample_c_cd */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50230 { 7139 /* image_sample_c_cd */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50240 { 7139 /* image_sample_c_cd */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50250 { 7139 /* image_sample_c_cd */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50260 { 7139 /* image_sample_c_cd */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50270 { 7139 /* image_sample_c_cd */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50280 { 7139 /* image_sample_c_cd */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50290 { 7139 /* image_sample_c_cd */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50300 { 7139 /* image_sample_c_cd */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50310 { 7139 /* image_sample_c_cd */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50320 { 7139 /* image_sample_c_cd */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50330 { 7139 /* image_sample_c_cd */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50340 { 7139 /* image_sample_c_cd */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50350 { 7139 /* image_sample_c_cd */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50360 { 7139 /* image_sample_c_cd */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50370 { 7139 /* image_sample_c_cd */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50380 { 7139 /* image_sample_c_cd */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50390 { 7139 /* image_sample_c_cd */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50400 { 7139 /* image_sample_c_cd */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50410 { 7139 /* image_sample_c_cd */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50420 { 7139 /* image_sample_c_cd */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50430 { 7139 /* image_sample_c_cd */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50440 { 7139 /* image_sample_c_cd */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50450 { 7139 /* image_sample_c_cd */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50460 { 7139 /* image_sample_c_cd */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50470 { 7139 /* image_sample_c_cd */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50480 { 7139 /* image_sample_c_cd */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50490 { 7139 /* image_sample_c_cd */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50500 { 7139 /* image_sample_c_cd */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50510 { 7139 /* image_sample_c_cd */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50520 { 7139 /* image_sample_c_cd */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50530 { 7139 /* image_sample_c_cd */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50540 { 7139 /* image_sample_c_cd */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50550 { 7139 /* image_sample_c_cd */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50559 { 7157 /* image_sample_c_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50568 { 7157 /* image_sample_c_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50577 { 7157 /* image_sample_c_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50586 { 7157 /* image_sample_c_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50595 { 7157 /* image_sample_c_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50604 { 7157 /* image_sample_c_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50613 { 7157 /* image_sample_c_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50622 { 7157 /* image_sample_c_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50631 { 7157 /* image_sample_c_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50640 { 7157 /* image_sample_c_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50649 { 7157 /* image_sample_c_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50658 { 7157 /* image_sample_c_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50667 { 7157 /* image_sample_c_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50676 { 7157 /* image_sample_c_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50685 { 7157 /* image_sample_c_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50694 { 7157 /* image_sample_c_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50703 { 7157 /* image_sample_c_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50712 { 7157 /* image_sample_c_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50721 { 7157 /* image_sample_c_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50730 { 7157 /* image_sample_c_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50740 { 7157 /* image_sample_c_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50750 { 7157 /* image_sample_c_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50760 { 7157 /* image_sample_c_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50770 { 7157 /* image_sample_c_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50780 { 7157 /* image_sample_c_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50790 { 7157 /* image_sample_c_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50800 { 7157 /* image_sample_c_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50810 { 7157 /* image_sample_c_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50820 { 7157 /* image_sample_c_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50830 { 7157 /* image_sample_c_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50840 { 7157 /* image_sample_c_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50850 { 7157 /* image_sample_c_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50860 { 7157 /* image_sample_c_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50870 { 7157 /* image_sample_c_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50880 { 7157 /* image_sample_c_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50890 { 7157 /* image_sample_c_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50900 { 7157 /* image_sample_c_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50910 { 7157 /* image_sample_c_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50920 { 7157 /* image_sample_c_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50930 { 7157 /* image_sample_c_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50940 { 7157 /* image_sample_c_cd_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50950 { 7157 /* image_sample_c_cd_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50960 { 7157 /* image_sample_c_cd_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50970 { 7157 /* image_sample_c_cd_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50980 { 7157 /* image_sample_c_cd_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
50990 { 7157 /* image_sample_c_cd_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51000 { 7157 /* image_sample_c_cd_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51010 { 7157 /* image_sample_c_cd_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51020 { 7157 /* image_sample_c_cd_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51030 { 7157 /* image_sample_c_cd_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51040 { 7157 /* image_sample_c_cd_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51050 { 7157 /* image_sample_c_cd_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51060 { 7157 /* image_sample_c_cd_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51070 { 7157 /* image_sample_c_cd_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51080 { 7157 /* image_sample_c_cd_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51090 { 7157 /* image_sample_c_cd_cl */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51100 { 7157 /* image_sample_c_cd_cl */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51110 { 7157 /* image_sample_c_cd_cl */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51120 { 7157 /* image_sample_c_cd_cl */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51130 { 7157 /* image_sample_c_cd_cl */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51140 { 7157 /* image_sample_c_cd_cl */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51150 { 7157 /* image_sample_c_cd_cl */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51160 { 7157 /* image_sample_c_cd_cl */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51170 { 7157 /* image_sample_c_cd_cl */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51180 { 7157 /* image_sample_c_cd_cl */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51190 { 7157 /* image_sample_c_cd_cl */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51200 { 7157 /* image_sample_c_cd_cl */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51210 { 7157 /* image_sample_c_cd_cl */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51220 { 7157 /* image_sample_c_cd_cl */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51230 { 7157 /* image_sample_c_cd_cl */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51240 { 7157 /* image_sample_c_cd_cl */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51250 { 7157 /* image_sample_c_cd_cl */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51260 { 7157 /* image_sample_c_cd_cl */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51270 { 7157 /* image_sample_c_cd_cl */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51280 { 7157 /* image_sample_c_cd_cl */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51289 { 7178 /* image_sample_c_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51298 { 7178 /* image_sample_c_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51307 { 7178 /* image_sample_c_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51316 { 7178 /* image_sample_c_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51325 { 7178 /* image_sample_c_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51334 { 7178 /* image_sample_c_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51343 { 7178 /* image_sample_c_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51352 { 7178 /* image_sample_c_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51361 { 7178 /* image_sample_c_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51370 { 7178 /* image_sample_c_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51379 { 7178 /* image_sample_c_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51388 { 7178 /* image_sample_c_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51397 { 7178 /* image_sample_c_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51406 { 7178 /* image_sample_c_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51415 { 7178 /* image_sample_c_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51425 { 7178 /* image_sample_c_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51435 { 7178 /* image_sample_c_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51445 { 7178 /* image_sample_c_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51455 { 7178 /* image_sample_c_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51465 { 7178 /* image_sample_c_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51475 { 7178 /* image_sample_c_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51485 { 7178 /* image_sample_c_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51495 { 7178 /* image_sample_c_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51505 { 7178 /* image_sample_c_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51515 { 7178 /* image_sample_c_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51525 { 7178 /* image_sample_c_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51535 { 7178 /* image_sample_c_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51545 { 7178 /* image_sample_c_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51555 { 7178 /* image_sample_c_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51565 { 7178 /* image_sample_c_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51575 { 7178 /* image_sample_c_cd_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51585 { 7178 /* image_sample_c_cd_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51595 { 7178 /* image_sample_c_cd_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51605 { 7178 /* image_sample_c_cd_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51615 { 7178 /* image_sample_c_cd_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51625 { 7178 /* image_sample_c_cd_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51635 { 7178 /* image_sample_c_cd_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51645 { 7178 /* image_sample_c_cd_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51655 { 7178 /* image_sample_c_cd_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51665 { 7178 /* image_sample_c_cd_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51675 { 7178 /* image_sample_c_cd_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51685 { 7178 /* image_sample_c_cd_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51695 { 7178 /* image_sample_c_cd_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51705 { 7178 /* image_sample_c_cd_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51715 { 7178 /* image_sample_c_cd_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51725 { 7178 /* image_sample_c_cd_cl_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51735 { 7178 /* image_sample_c_cd_cl_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51745 { 7178 /* image_sample_c_cd_cl_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51755 { 7178 /* image_sample_c_cd_cl_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51765 { 7178 /* image_sample_c_cd_cl_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51775 { 7178 /* image_sample_c_cd_cl_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51785 { 7178 /* image_sample_c_cd_cl_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51795 { 7178 /* image_sample_c_cd_cl_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51805 { 7178 /* image_sample_c_cd_cl_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51815 { 7178 /* image_sample_c_cd_cl_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51825 { 7178 /* image_sample_c_cd_cl_o */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51835 { 7178 /* image_sample_c_cd_cl_o */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51845 { 7178 /* image_sample_c_cd_cl_o */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51855 { 7178 /* image_sample_c_cd_cl_o */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51865 { 7178 /* image_sample_c_cd_cl_o */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51875 { 7178 /* image_sample_c_cd_cl_o */, 4194304 /* 22 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51885 { 7178 /* image_sample_c_cd_cl_o */, 4194304 /* 22 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51895 { 7178 /* image_sample_c_cd_cl_o */, 4194304 /* 22 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51905 { 7178 /* image_sample_c_cd_cl_o */, 4194304 /* 22 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51915 { 7178 /* image_sample_c_cd_cl_o */, 4194304 /* 22 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
51924 { 7201 /* image_sample_c_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51933 { 7201 /* image_sample_c_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51942 { 7201 /* image_sample_c_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51951 { 7201 /* image_sample_c_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51960 { 7201 /* image_sample_c_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51969 { 7201 /* image_sample_c_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51978 { 7201 /* image_sample_c_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51987 { 7201 /* image_sample_c_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51996 { 7201 /* image_sample_c_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52005 { 7201 /* image_sample_c_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52014 { 7201 /* image_sample_c_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52023 { 7201 /* image_sample_c_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52032 { 7201 /* image_sample_c_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52041 { 7201 /* image_sample_c_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52050 { 7201 /* image_sample_c_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52060 { 7201 /* image_sample_c_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52070 { 7201 /* image_sample_c_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52080 { 7201 /* image_sample_c_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52090 { 7201 /* image_sample_c_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52100 { 7201 /* image_sample_c_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52110 { 7201 /* image_sample_c_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52120 { 7201 /* image_sample_c_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52130 { 7201 /* image_sample_c_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52140 { 7201 /* image_sample_c_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52150 { 7201 /* image_sample_c_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52160 { 7201 /* image_sample_c_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52170 { 7201 /* image_sample_c_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52180 { 7201 /* image_sample_c_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52190 { 7201 /* image_sample_c_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52200 { 7201 /* image_sample_c_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52210 { 7201 /* image_sample_c_cd_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52220 { 7201 /* image_sample_c_cd_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52230 { 7201 /* image_sample_c_cd_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52240 { 7201 /* image_sample_c_cd_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52250 { 7201 /* image_sample_c_cd_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52260 { 7201 /* image_sample_c_cd_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52270 { 7201 /* image_sample_c_cd_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52280 { 7201 /* image_sample_c_cd_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52290 { 7201 /* image_sample_c_cd_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52300 { 7201 /* image_sample_c_cd_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52310 { 7201 /* image_sample_c_cd_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52320 { 7201 /* image_sample_c_cd_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52330 { 7201 /* image_sample_c_cd_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52340 { 7201 /* image_sample_c_cd_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52350 { 7201 /* image_sample_c_cd_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52360 { 7201 /* image_sample_c_cd_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52370 { 7201 /* image_sample_c_cd_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52380 { 7201 /* image_sample_c_cd_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52390 { 7201 /* image_sample_c_cd_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52400 { 7201 /* image_sample_c_cd_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52410 { 7201 /* image_sample_c_cd_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52420 { 7201 /* image_sample_c_cd_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52430 { 7201 /* image_sample_c_cd_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52440 { 7201 /* image_sample_c_cd_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52450 { 7201 /* image_sample_c_cd_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52460 { 7201 /* image_sample_c_cd_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52470 { 7201 /* image_sample_c_cd_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52480 { 7201 /* image_sample_c_cd_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52490 { 7201 /* image_sample_c_cd_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52500 { 7201 /* image_sample_c_cd_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52510 { 7201 /* image_sample_c_cd_o */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52520 { 7201 /* image_sample_c_cd_o */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52530 { 7201 /* image_sample_c_cd_o */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52540 { 7201 /* image_sample_c_cd_o */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52550 { 7201 /* image_sample_c_cd_o */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52559 { 7221 /* image_sample_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52568 { 7221 /* image_sample_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52577 { 7221 /* image_sample_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52586 { 7221 /* image_sample_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52595 { 7221 /* image_sample_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52604 { 7221 /* image_sample_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52613 { 7221 /* image_sample_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52622 { 7221 /* image_sample_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52631 { 7221 /* image_sample_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52640 { 7221 /* image_sample_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52649 { 7221 /* image_sample_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52658 { 7221 /* image_sample_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52667 { 7221 /* image_sample_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52676 { 7221 /* image_sample_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52685 { 7221 /* image_sample_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52694 { 7221 /* image_sample_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52703 { 7221 /* image_sample_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52712 { 7221 /* image_sample_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52721 { 7221 /* image_sample_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52730 { 7221 /* image_sample_c_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52740 { 7221 /* image_sample_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52750 { 7221 /* image_sample_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52760 { 7221 /* image_sample_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52770 { 7221 /* image_sample_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52780 { 7221 /* image_sample_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52790 { 7221 /* image_sample_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52800 { 7221 /* image_sample_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52810 { 7221 /* image_sample_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52820 { 7221 /* image_sample_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52830 { 7221 /* image_sample_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52840 { 7221 /* image_sample_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52850 { 7221 /* image_sample_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52860 { 7221 /* image_sample_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52870 { 7221 /* image_sample_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52880 { 7221 /* image_sample_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52890 { 7221 /* image_sample_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52900 { 7221 /* image_sample_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52910 { 7221 /* image_sample_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52920 { 7221 /* image_sample_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52930 { 7221 /* image_sample_c_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52940 { 7221 /* image_sample_c_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52950 { 7221 /* image_sample_c_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52960 { 7221 /* image_sample_c_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52970 { 7221 /* image_sample_c_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52980 { 7221 /* image_sample_c_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
52990 { 7221 /* image_sample_c_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53000 { 7221 /* image_sample_c_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53010 { 7221 /* image_sample_c_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53020 { 7221 /* image_sample_c_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53030 { 7221 /* image_sample_c_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53040 { 7221 /* image_sample_c_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53050 { 7221 /* image_sample_c_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53060 { 7221 /* image_sample_c_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53070 { 7221 /* image_sample_c_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53080 { 7221 /* image_sample_c_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53090 { 7221 /* image_sample_c_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53100 { 7221 /* image_sample_c_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53110 { 7221 /* image_sample_c_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53120 { 7221 /* image_sample_c_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53130 { 7221 /* image_sample_c_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53139 { 7239 /* image_sample_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53148 { 7239 /* image_sample_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53157 { 7239 /* image_sample_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53166 { 7239 /* image_sample_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53175 { 7239 /* image_sample_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53184 { 7239 /* image_sample_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53193 { 7239 /* image_sample_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53202 { 7239 /* image_sample_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53211 { 7239 /* image_sample_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53220 { 7239 /* image_sample_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53229 { 7239 /* image_sample_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53238 { 7239 /* image_sample_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53247 { 7239 /* image_sample_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53256 { 7239 /* image_sample_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53265 { 7239 /* image_sample_c_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53275 { 7239 /* image_sample_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53285 { 7239 /* image_sample_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53295 { 7239 /* image_sample_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53305 { 7239 /* image_sample_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53315 { 7239 /* image_sample_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53325 { 7239 /* image_sample_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53335 { 7239 /* image_sample_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53345 { 7239 /* image_sample_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53355 { 7239 /* image_sample_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53365 { 7239 /* image_sample_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53375 { 7239 /* image_sample_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53385 { 7239 /* image_sample_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53395 { 7239 /* image_sample_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53405 { 7239 /* image_sample_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53415 { 7239 /* image_sample_c_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53425 { 7239 /* image_sample_c_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53435 { 7239 /* image_sample_c_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53445 { 7239 /* image_sample_c_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53455 { 7239 /* image_sample_c_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53465 { 7239 /* image_sample_c_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53475 { 7239 /* image_sample_c_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53485 { 7239 /* image_sample_c_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53495 { 7239 /* image_sample_c_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53505 { 7239 /* image_sample_c_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53515 { 7239 /* image_sample_c_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53525 { 7239 /* image_sample_c_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53535 { 7239 /* image_sample_c_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53545 { 7239 /* image_sample_c_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53555 { 7239 /* image_sample_c_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53565 { 7239 /* image_sample_c_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53575 { 7239 /* image_sample_c_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53585 { 7239 /* image_sample_c_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53595 { 7239 /* image_sample_c_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53605 { 7239 /* image_sample_c_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53615 { 7239 /* image_sample_c_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53624 { 7259 /* image_sample_c_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53633 { 7259 /* image_sample_c_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53642 { 7259 /* image_sample_c_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53651 { 7259 /* image_sample_c_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53660 { 7259 /* image_sample_c_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53669 { 7259 /* image_sample_c_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53678 { 7259 /* image_sample_c_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53687 { 7259 /* image_sample_c_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53696 { 7259 /* image_sample_c_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53705 { 7259 /* image_sample_c_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53714 { 7259 /* image_sample_c_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53723 { 7259 /* image_sample_c_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53732 { 7259 /* image_sample_c_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53741 { 7259 /* image_sample_c_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53750 { 7259 /* image_sample_c_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53759 { 7259 /* image_sample_c_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53768 { 7259 /* image_sample_c_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53777 { 7259 /* image_sample_c_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53786 { 7259 /* image_sample_c_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53795 { 7259 /* image_sample_c_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53805 { 7259 /* image_sample_c_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53815 { 7259 /* image_sample_c_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53825 { 7259 /* image_sample_c_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53835 { 7259 /* image_sample_c_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53845 { 7259 /* image_sample_c_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53855 { 7259 /* image_sample_c_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53865 { 7259 /* image_sample_c_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53875 { 7259 /* image_sample_c_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53885 { 7259 /* image_sample_c_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53895 { 7259 /* image_sample_c_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53905 { 7259 /* image_sample_c_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53915 { 7259 /* image_sample_c_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53925 { 7259 /* image_sample_c_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53935 { 7259 /* image_sample_c_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53945 { 7259 /* image_sample_c_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53955 { 7259 /* image_sample_c_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53965 { 7259 /* image_sample_c_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53975 { 7259 /* image_sample_c_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53985 { 7259 /* image_sample_c_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
53995 { 7259 /* image_sample_c_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54005 { 7259 /* image_sample_c_d */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54015 { 7259 /* image_sample_c_d */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54025 { 7259 /* image_sample_c_d */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54035 { 7259 /* image_sample_c_d */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54045 { 7259 /* image_sample_c_d */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54055 { 7259 /* image_sample_c_d */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54065 { 7259 /* image_sample_c_d */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54075 { 7259 /* image_sample_c_d */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54085 { 7259 /* image_sample_c_d */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54095 { 7259 /* image_sample_c_d */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54105 { 7259 /* image_sample_c_d */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54115 { 7259 /* image_sample_c_d */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54125 { 7259 /* image_sample_c_d */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54135 { 7259 /* image_sample_c_d */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54145 { 7259 /* image_sample_c_d */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54155 { 7259 /* image_sample_c_d */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54165 { 7259 /* image_sample_c_d */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54175 { 7259 /* image_sample_c_d */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54185 { 7259 /* image_sample_c_d */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54195 { 7259 /* image_sample_c_d */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54205 { 7259 /* image_sample_c_d */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54215 { 7259 /* image_sample_c_d */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54225 { 7259 /* image_sample_c_d */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54235 { 7259 /* image_sample_c_d */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54245 { 7259 /* image_sample_c_d */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54255 { 7259 /* image_sample_c_d */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54265 { 7259 /* image_sample_c_d */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54275 { 7259 /* image_sample_c_d */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54285 { 7259 /* image_sample_c_d */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54295 { 7259 /* image_sample_c_d */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54305 { 7259 /* image_sample_c_d */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54315 { 7259 /* image_sample_c_d */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54325 { 7259 /* image_sample_c_d */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54335 { 7259 /* image_sample_c_d */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54345 { 7259 /* image_sample_c_d */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54354 { 7276 /* image_sample_c_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54363 { 7276 /* image_sample_c_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54372 { 7276 /* image_sample_c_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54381 { 7276 /* image_sample_c_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54390 { 7276 /* image_sample_c_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54399 { 7276 /* image_sample_c_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54408 { 7276 /* image_sample_c_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54417 { 7276 /* image_sample_c_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54426 { 7276 /* image_sample_c_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54435 { 7276 /* image_sample_c_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54444 { 7276 /* image_sample_c_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54453 { 7276 /* image_sample_c_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54462 { 7276 /* image_sample_c_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54471 { 7276 /* image_sample_c_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54480 { 7276 /* image_sample_c_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54489 { 7276 /* image_sample_c_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54498 { 7276 /* image_sample_c_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54507 { 7276 /* image_sample_c_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54516 { 7276 /* image_sample_c_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54525 { 7276 /* image_sample_c_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54535 { 7276 /* image_sample_c_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54545 { 7276 /* image_sample_c_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54555 { 7276 /* image_sample_c_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54565 { 7276 /* image_sample_c_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54575 { 7276 /* image_sample_c_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54585 { 7276 /* image_sample_c_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54595 { 7276 /* image_sample_c_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54605 { 7276 /* image_sample_c_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54615 { 7276 /* image_sample_c_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54625 { 7276 /* image_sample_c_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54635 { 7276 /* image_sample_c_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54645 { 7276 /* image_sample_c_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54655 { 7276 /* image_sample_c_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54665 { 7276 /* image_sample_c_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54675 { 7276 /* image_sample_c_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54685 { 7276 /* image_sample_c_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54695 { 7276 /* image_sample_c_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54705 { 7276 /* image_sample_c_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54715 { 7276 /* image_sample_c_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54725 { 7276 /* image_sample_c_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54735 { 7276 /* image_sample_c_d_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54745 { 7276 /* image_sample_c_d_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54755 { 7276 /* image_sample_c_d_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54765 { 7276 /* image_sample_c_d_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54775 { 7276 /* image_sample_c_d_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54785 { 7276 /* image_sample_c_d_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54795 { 7276 /* image_sample_c_d_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54805 { 7276 /* image_sample_c_d_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54815 { 7276 /* image_sample_c_d_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54825 { 7276 /* image_sample_c_d_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54835 { 7276 /* image_sample_c_d_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54845 { 7276 /* image_sample_c_d_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54855 { 7276 /* image_sample_c_d_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54865 { 7276 /* image_sample_c_d_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54875 { 7276 /* image_sample_c_d_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54885 { 7276 /* image_sample_c_d_cl */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54895 { 7276 /* image_sample_c_d_cl */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54905 { 7276 /* image_sample_c_d_cl */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54915 { 7276 /* image_sample_c_d_cl */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54925 { 7276 /* image_sample_c_d_cl */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54935 { 7276 /* image_sample_c_d_cl */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54945 { 7276 /* image_sample_c_d_cl */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54955 { 7276 /* image_sample_c_d_cl */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54965 { 7276 /* image_sample_c_d_cl */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54975 { 7276 /* image_sample_c_d_cl */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54985 { 7276 /* image_sample_c_d_cl */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
54995 { 7276 /* image_sample_c_d_cl */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55005 { 7276 /* image_sample_c_d_cl */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55015 { 7276 /* image_sample_c_d_cl */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55025 { 7276 /* image_sample_c_d_cl */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55035 { 7276 /* image_sample_c_d_cl */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55045 { 7276 /* image_sample_c_d_cl */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55055 { 7276 /* image_sample_c_d_cl */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55065 { 7276 /* image_sample_c_d_cl */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55075 { 7276 /* image_sample_c_d_cl */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55084 { 7296 /* image_sample_c_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55093 { 7296 /* image_sample_c_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55102 { 7296 /* image_sample_c_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55111 { 7296 /* image_sample_c_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55120 { 7296 /* image_sample_c_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55129 { 7296 /* image_sample_c_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55138 { 7296 /* image_sample_c_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55147 { 7296 /* image_sample_c_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55156 { 7296 /* image_sample_c_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55165 { 7296 /* image_sample_c_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55174 { 7296 /* image_sample_c_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55183 { 7296 /* image_sample_c_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55192 { 7296 /* image_sample_c_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55201 { 7296 /* image_sample_c_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55210 { 7296 /* image_sample_c_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55220 { 7296 /* image_sample_c_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55230 { 7296 /* image_sample_c_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55240 { 7296 /* image_sample_c_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55250 { 7296 /* image_sample_c_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55260 { 7296 /* image_sample_c_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55270 { 7296 /* image_sample_c_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55280 { 7296 /* image_sample_c_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55290 { 7296 /* image_sample_c_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55300 { 7296 /* image_sample_c_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55310 { 7296 /* image_sample_c_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55320 { 7296 /* image_sample_c_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55330 { 7296 /* image_sample_c_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55340 { 7296 /* image_sample_c_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55350 { 7296 /* image_sample_c_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55360 { 7296 /* image_sample_c_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55370 { 7296 /* image_sample_c_d_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55380 { 7296 /* image_sample_c_d_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55390 { 7296 /* image_sample_c_d_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55400 { 7296 /* image_sample_c_d_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55410 { 7296 /* image_sample_c_d_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55420 { 7296 /* image_sample_c_d_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55430 { 7296 /* image_sample_c_d_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55440 { 7296 /* image_sample_c_d_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55450 { 7296 /* image_sample_c_d_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55460 { 7296 /* image_sample_c_d_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55470 { 7296 /* image_sample_c_d_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55480 { 7296 /* image_sample_c_d_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55490 { 7296 /* image_sample_c_d_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55500 { 7296 /* image_sample_c_d_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55510 { 7296 /* image_sample_c_d_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55520 { 7296 /* image_sample_c_d_cl_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55530 { 7296 /* image_sample_c_d_cl_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55540 { 7296 /* image_sample_c_d_cl_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55550 { 7296 /* image_sample_c_d_cl_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55560 { 7296 /* image_sample_c_d_cl_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55570 { 7296 /* image_sample_c_d_cl_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55580 { 7296 /* image_sample_c_d_cl_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55590 { 7296 /* image_sample_c_d_cl_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55600 { 7296 /* image_sample_c_d_cl_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55610 { 7296 /* image_sample_c_d_cl_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55620 { 7296 /* image_sample_c_d_cl_o */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55630 { 7296 /* image_sample_c_d_cl_o */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55640 { 7296 /* image_sample_c_d_cl_o */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55650 { 7296 /* image_sample_c_d_cl_o */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55660 { 7296 /* image_sample_c_d_cl_o */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55670 { 7296 /* image_sample_c_d_cl_o */, 4194304 /* 22 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55680 { 7296 /* image_sample_c_d_cl_o */, 4194304 /* 22 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55690 { 7296 /* image_sample_c_d_cl_o */, 4194304 /* 22 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55700 { 7296 /* image_sample_c_d_cl_o */, 4194304 /* 22 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55710 { 7296 /* image_sample_c_d_cl_o */, 4194304 /* 22 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55719 { 7318 /* image_sample_c_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55728 { 7318 /* image_sample_c_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55737 { 7318 /* image_sample_c_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55746 { 7318 /* image_sample_c_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55755 { 7318 /* image_sample_c_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55764 { 7318 /* image_sample_c_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55773 { 7318 /* image_sample_c_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55782 { 7318 /* image_sample_c_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55791 { 7318 /* image_sample_c_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55800 { 7318 /* image_sample_c_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55809 { 7318 /* image_sample_c_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55818 { 7318 /* image_sample_c_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55827 { 7318 /* image_sample_c_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55836 { 7318 /* image_sample_c_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55845 { 7318 /* image_sample_c_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55855 { 7318 /* image_sample_c_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55865 { 7318 /* image_sample_c_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55875 { 7318 /* image_sample_c_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55885 { 7318 /* image_sample_c_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55895 { 7318 /* image_sample_c_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55905 { 7318 /* image_sample_c_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55915 { 7318 /* image_sample_c_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55925 { 7318 /* image_sample_c_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55935 { 7318 /* image_sample_c_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55945 { 7318 /* image_sample_c_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55955 { 7318 /* image_sample_c_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55965 { 7318 /* image_sample_c_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55975 { 7318 /* image_sample_c_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55985 { 7318 /* image_sample_c_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
55995 { 7318 /* image_sample_c_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56005 { 7318 /* image_sample_c_d_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56015 { 7318 /* image_sample_c_d_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56025 { 7318 /* image_sample_c_d_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56035 { 7318 /* image_sample_c_d_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56045 { 7318 /* image_sample_c_d_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56055 { 7318 /* image_sample_c_d_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56065 { 7318 /* image_sample_c_d_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56075 { 7318 /* image_sample_c_d_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56085 { 7318 /* image_sample_c_d_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56095 { 7318 /* image_sample_c_d_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56105 { 7318 /* image_sample_c_d_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56115 { 7318 /* image_sample_c_d_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56125 { 7318 /* image_sample_c_d_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56135 { 7318 /* image_sample_c_d_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56145 { 7318 /* image_sample_c_d_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56155 { 7318 /* image_sample_c_d_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56165 { 7318 /* image_sample_c_d_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56175 { 7318 /* image_sample_c_d_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56185 { 7318 /* image_sample_c_d_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56195 { 7318 /* image_sample_c_d_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56205 { 7318 /* image_sample_c_d_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56215 { 7318 /* image_sample_c_d_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56225 { 7318 /* image_sample_c_d_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56235 { 7318 /* image_sample_c_d_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56245 { 7318 /* image_sample_c_d_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56255 { 7318 /* image_sample_c_d_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56265 { 7318 /* image_sample_c_d_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56275 { 7318 /* image_sample_c_d_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56285 { 7318 /* image_sample_c_d_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56295 { 7318 /* image_sample_c_d_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56305 { 7318 /* image_sample_c_d_o */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56315 { 7318 /* image_sample_c_d_o */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56325 { 7318 /* image_sample_c_d_o */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56335 { 7318 /* image_sample_c_d_o */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56345 { 7318 /* image_sample_c_d_o */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56354 { 7337 /* image_sample_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56363 { 7337 /* image_sample_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56372 { 7337 /* image_sample_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56381 { 7337 /* image_sample_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56390 { 7337 /* image_sample_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56399 { 7337 /* image_sample_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56408 { 7337 /* image_sample_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56417 { 7337 /* image_sample_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56426 { 7337 /* image_sample_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56435 { 7337 /* image_sample_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56444 { 7337 /* image_sample_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56453 { 7337 /* image_sample_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56462 { 7337 /* image_sample_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56471 { 7337 /* image_sample_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56480 { 7337 /* image_sample_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56489 { 7337 /* image_sample_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56498 { 7337 /* image_sample_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56507 { 7337 /* image_sample_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56516 { 7337 /* image_sample_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56525 { 7337 /* image_sample_c_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56535 { 7337 /* image_sample_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56545 { 7337 /* image_sample_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56555 { 7337 /* image_sample_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56565 { 7337 /* image_sample_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56575 { 7337 /* image_sample_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56585 { 7337 /* image_sample_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56595 { 7337 /* image_sample_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56605 { 7337 /* image_sample_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56615 { 7337 /* image_sample_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56625 { 7337 /* image_sample_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56635 { 7337 /* image_sample_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56645 { 7337 /* image_sample_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56655 { 7337 /* image_sample_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56665 { 7337 /* image_sample_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56675 { 7337 /* image_sample_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56685 { 7337 /* image_sample_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56695 { 7337 /* image_sample_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56705 { 7337 /* image_sample_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56715 { 7337 /* image_sample_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56725 { 7337 /* image_sample_c_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56735 { 7337 /* image_sample_c_l */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56745 { 7337 /* image_sample_c_l */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56755 { 7337 /* image_sample_c_l */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56765 { 7337 /* image_sample_c_l */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56775 { 7337 /* image_sample_c_l */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56785 { 7337 /* image_sample_c_l */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56795 { 7337 /* image_sample_c_l */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56805 { 7337 /* image_sample_c_l */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56815 { 7337 /* image_sample_c_l */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56825 { 7337 /* image_sample_c_l */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56835 { 7337 /* image_sample_c_l */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56845 { 7337 /* image_sample_c_l */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56855 { 7337 /* image_sample_c_l */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56865 { 7337 /* image_sample_c_l */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56875 { 7337 /* image_sample_c_l */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56885 { 7337 /* image_sample_c_l */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56895 { 7337 /* image_sample_c_l */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56905 { 7337 /* image_sample_c_l */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56915 { 7337 /* image_sample_c_l */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56925 { 7337 /* image_sample_c_l */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
56934 { 7354 /* image_sample_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56943 { 7354 /* image_sample_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56952 { 7354 /* image_sample_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56961 { 7354 /* image_sample_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56970 { 7354 /* image_sample_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56979 { 7354 /* image_sample_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56988 { 7354 /* image_sample_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56997 { 7354 /* image_sample_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57006 { 7354 /* image_sample_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57015 { 7354 /* image_sample_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57024 { 7354 /* image_sample_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57033 { 7354 /* image_sample_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57042 { 7354 /* image_sample_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57051 { 7354 /* image_sample_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57060 { 7354 /* image_sample_c_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57070 { 7354 /* image_sample_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57080 { 7354 /* image_sample_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57090 { 7354 /* image_sample_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57100 { 7354 /* image_sample_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57110 { 7354 /* image_sample_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57120 { 7354 /* image_sample_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57130 { 7354 /* image_sample_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57140 { 7354 /* image_sample_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57150 { 7354 /* image_sample_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57160 { 7354 /* image_sample_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57170 { 7354 /* image_sample_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57180 { 7354 /* image_sample_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57190 { 7354 /* image_sample_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57200 { 7354 /* image_sample_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57210 { 7354 /* image_sample_c_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57220 { 7354 /* image_sample_c_l_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57230 { 7354 /* image_sample_c_l_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57240 { 7354 /* image_sample_c_l_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57250 { 7354 /* image_sample_c_l_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57260 { 7354 /* image_sample_c_l_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57270 { 7354 /* image_sample_c_l_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57280 { 7354 /* image_sample_c_l_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57290 { 7354 /* image_sample_c_l_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57300 { 7354 /* image_sample_c_l_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57310 { 7354 /* image_sample_c_l_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57320 { 7354 /* image_sample_c_l_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57330 { 7354 /* image_sample_c_l_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57340 { 7354 /* image_sample_c_l_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57350 { 7354 /* image_sample_c_l_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57360 { 7354 /* image_sample_c_l_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57370 { 7354 /* image_sample_c_l_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57380 { 7354 /* image_sample_c_l_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57390 { 7354 /* image_sample_c_l_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57400 { 7354 /* image_sample_c_l_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57410 { 7354 /* image_sample_c_l_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57419 { 7373 /* image_sample_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57428 { 7373 /* image_sample_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57437 { 7373 /* image_sample_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57446 { 7373 /* image_sample_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57455 { 7373 /* image_sample_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57464 { 7373 /* image_sample_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57473 { 7373 /* image_sample_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57482 { 7373 /* image_sample_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57491 { 7373 /* image_sample_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57500 { 7373 /* image_sample_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57509 { 7373 /* image_sample_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57518 { 7373 /* image_sample_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57527 { 7373 /* image_sample_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57536 { 7373 /* image_sample_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57545 { 7373 /* image_sample_c_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57555 { 7373 /* image_sample_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57565 { 7373 /* image_sample_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57575 { 7373 /* image_sample_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57585 { 7373 /* image_sample_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57595 { 7373 /* image_sample_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57605 { 7373 /* image_sample_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57615 { 7373 /* image_sample_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57625 { 7373 /* image_sample_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57635 { 7373 /* image_sample_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57645 { 7373 /* image_sample_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57655 { 7373 /* image_sample_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57665 { 7373 /* image_sample_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57675 { 7373 /* image_sample_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57685 { 7373 /* image_sample_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57695 { 7373 /* image_sample_c_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57705 { 7373 /* image_sample_c_lz */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57715 { 7373 /* image_sample_c_lz */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57725 { 7373 /* image_sample_c_lz */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57735 { 7373 /* image_sample_c_lz */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57745 { 7373 /* image_sample_c_lz */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57755 { 7373 /* image_sample_c_lz */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57765 { 7373 /* image_sample_c_lz */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57775 { 7373 /* image_sample_c_lz */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57785 { 7373 /* image_sample_c_lz */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57795 { 7373 /* image_sample_c_lz */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57805 { 7373 /* image_sample_c_lz */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57815 { 7373 /* image_sample_c_lz */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57825 { 7373 /* image_sample_c_lz */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57835 { 7373 /* image_sample_c_lz */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57845 { 7373 /* image_sample_c_lz */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
57854 { 7391 /* image_sample_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57863 { 7391 /* image_sample_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57872 { 7391 /* image_sample_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57881 { 7391 /* image_sample_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57890 { 7391 /* image_sample_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57899 { 7391 /* image_sample_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57908 { 7391 /* image_sample_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57917 { 7391 /* image_sample_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57926 { 7391 /* image_sample_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57935 { 7391 /* image_sample_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57944 { 7391 /* image_sample_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57953 { 7391 /* image_sample_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57962 { 7391 /* image_sample_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57971 { 7391 /* image_sample_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57980 { 7391 /* image_sample_c_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57990 { 7391 /* image_sample_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58000 { 7391 /* image_sample_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58010 { 7391 /* image_sample_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58020 { 7391 /* image_sample_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58030 { 7391 /* image_sample_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58040 { 7391 /* image_sample_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58050 { 7391 /* image_sample_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58060 { 7391 /* image_sample_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58070 { 7391 /* image_sample_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58080 { 7391 /* image_sample_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58090 { 7391 /* image_sample_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58100 { 7391 /* image_sample_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58110 { 7391 /* image_sample_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58120 { 7391 /* image_sample_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58130 { 7391 /* image_sample_c_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58140 { 7391 /* image_sample_c_lz_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58150 { 7391 /* image_sample_c_lz_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58160 { 7391 /* image_sample_c_lz_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58170 { 7391 /* image_sample_c_lz_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58180 { 7391 /* image_sample_c_lz_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58190 { 7391 /* image_sample_c_lz_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58200 { 7391 /* image_sample_c_lz_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58210 { 7391 /* image_sample_c_lz_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58220 { 7391 /* image_sample_c_lz_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58230 { 7391 /* image_sample_c_lz_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58240 { 7391 /* image_sample_c_lz_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58250 { 7391 /* image_sample_c_lz_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58260 { 7391 /* image_sample_c_lz_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58270 { 7391 /* image_sample_c_lz_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58280 { 7391 /* image_sample_c_lz_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58289 { 7411 /* image_sample_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58298 { 7411 /* image_sample_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58307 { 7411 /* image_sample_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58316 { 7411 /* image_sample_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58325 { 7411 /* image_sample_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58334 { 7411 /* image_sample_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58343 { 7411 /* image_sample_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58352 { 7411 /* image_sample_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58361 { 7411 /* image_sample_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58370 { 7411 /* image_sample_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58379 { 7411 /* image_sample_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58388 { 7411 /* image_sample_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58397 { 7411 /* image_sample_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58406 { 7411 /* image_sample_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58415 { 7411 /* image_sample_c_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58425 { 7411 /* image_sample_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58435 { 7411 /* image_sample_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58445 { 7411 /* image_sample_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58455 { 7411 /* image_sample_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58465 { 7411 /* image_sample_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58475 { 7411 /* image_sample_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58485 { 7411 /* image_sample_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58495 { 7411 /* image_sample_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58505 { 7411 /* image_sample_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58515 { 7411 /* image_sample_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58525 { 7411 /* image_sample_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58535 { 7411 /* image_sample_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58545 { 7411 /* image_sample_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58555 { 7411 /* image_sample_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58565 { 7411 /* image_sample_c_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58575 { 7411 /* image_sample_c_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58585 { 7411 /* image_sample_c_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58595 { 7411 /* image_sample_c_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58605 { 7411 /* image_sample_c_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58615 { 7411 /* image_sample_c_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58625 { 7411 /* image_sample_c_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58635 { 7411 /* image_sample_c_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58645 { 7411 /* image_sample_c_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58655 { 7411 /* image_sample_c_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58665 { 7411 /* image_sample_c_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58675 { 7411 /* image_sample_c_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58685 { 7411 /* image_sample_c_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58695 { 7411 /* image_sample_c_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58705 { 7411 /* image_sample_c_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58715 { 7411 /* image_sample_c_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58724 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58733 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58742 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58751 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58760 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58769 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58778 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58787 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58796 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58805 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58814 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58823 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58832 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58841 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58850 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58859 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58868 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58877 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58886 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58895 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58904 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58913 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58922 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58931 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58940 { 7428 /* image_sample_cd */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58950 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58960 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58970 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58980 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
58990 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59000 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59010 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59020 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59030 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59040 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59050 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59060 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59070 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59080 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59090 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59100 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59110 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59120 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59130 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59140 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59150 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59160 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59170 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59180 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59190 { 7428 /* image_sample_cd */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59200 { 7428 /* image_sample_cd */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59210 { 7428 /* image_sample_cd */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59220 { 7428 /* image_sample_cd */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59230 { 7428 /* image_sample_cd */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59240 { 7428 /* image_sample_cd */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59250 { 7428 /* image_sample_cd */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59260 { 7428 /* image_sample_cd */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59270 { 7428 /* image_sample_cd */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59280 { 7428 /* image_sample_cd */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59290 { 7428 /* image_sample_cd */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59300 { 7428 /* image_sample_cd */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59310 { 7428 /* image_sample_cd */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59320 { 7428 /* image_sample_cd */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59330 { 7428 /* image_sample_cd */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59340 { 7428 /* image_sample_cd */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59350 { 7428 /* image_sample_cd */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59360 { 7428 /* image_sample_cd */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59370 { 7428 /* image_sample_cd */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59380 { 7428 /* image_sample_cd */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59390 { 7428 /* image_sample_cd */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59400 { 7428 /* image_sample_cd */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59410 { 7428 /* image_sample_cd */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59420 { 7428 /* image_sample_cd */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59430 { 7428 /* image_sample_cd */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59440 { 7428 /* image_sample_cd */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59450 { 7428 /* image_sample_cd */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59460 { 7428 /* image_sample_cd */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59470 { 7428 /* image_sample_cd */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59480 { 7428 /* image_sample_cd */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59490 { 7428 /* image_sample_cd */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59500 { 7428 /* image_sample_cd */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59510 { 7428 /* image_sample_cd */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59520 { 7428 /* image_sample_cd */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59530 { 7428 /* image_sample_cd */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59540 { 7428 /* image_sample_cd */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59549 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59558 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59567 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59576 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59585 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59594 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59603 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59612 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59621 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59630 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59639 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59648 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59657 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59666 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59675 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59684 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59693 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59702 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59711 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59720 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59729 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59738 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59747 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59756 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59765 { 7444 /* image_sample_cd_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59775 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59785 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59795 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59805 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59815 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59825 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59835 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59845 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59855 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59865 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59875 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59885 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59895 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59905 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59915 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59925 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59935 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59945 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59955 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59965 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59975 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59985 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
59995 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60005 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60015 { 7444 /* image_sample_cd_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60025 { 7444 /* image_sample_cd_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60035 { 7444 /* image_sample_cd_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60045 { 7444 /* image_sample_cd_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60055 { 7444 /* image_sample_cd_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60065 { 7444 /* image_sample_cd_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60075 { 7444 /* image_sample_cd_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60085 { 7444 /* image_sample_cd_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60095 { 7444 /* image_sample_cd_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60105 { 7444 /* image_sample_cd_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60115 { 7444 /* image_sample_cd_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60125 { 7444 /* image_sample_cd_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60135 { 7444 /* image_sample_cd_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60145 { 7444 /* image_sample_cd_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60155 { 7444 /* image_sample_cd_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60165 { 7444 /* image_sample_cd_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60175 { 7444 /* image_sample_cd_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60185 { 7444 /* image_sample_cd_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60195 { 7444 /* image_sample_cd_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60205 { 7444 /* image_sample_cd_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60215 { 7444 /* image_sample_cd_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60225 { 7444 /* image_sample_cd_cl */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60235 { 7444 /* image_sample_cd_cl */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60245 { 7444 /* image_sample_cd_cl */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60255 { 7444 /* image_sample_cd_cl */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60265 { 7444 /* image_sample_cd_cl */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60275 { 7444 /* image_sample_cd_cl */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60285 { 7444 /* image_sample_cd_cl */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60295 { 7444 /* image_sample_cd_cl */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60305 { 7444 /* image_sample_cd_cl */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60315 { 7444 /* image_sample_cd_cl */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60325 { 7444 /* image_sample_cd_cl */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60335 { 7444 /* image_sample_cd_cl */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60345 { 7444 /* image_sample_cd_cl */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60355 { 7444 /* image_sample_cd_cl */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60365 { 7444 /* image_sample_cd_cl */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60374 { 7463 /* image_sample_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60383 { 7463 /* image_sample_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60392 { 7463 /* image_sample_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60401 { 7463 /* image_sample_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60410 { 7463 /* image_sample_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60419 { 7463 /* image_sample_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60428 { 7463 /* image_sample_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60437 { 7463 /* image_sample_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60446 { 7463 /* image_sample_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60455 { 7463 /* image_sample_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60464 { 7463 /* image_sample_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60473 { 7463 /* image_sample_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60482 { 7463 /* image_sample_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60491 { 7463 /* image_sample_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60500 { 7463 /* image_sample_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60509 { 7463 /* image_sample_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60518 { 7463 /* image_sample_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60527 { 7463 /* image_sample_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60536 { 7463 /* image_sample_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60545 { 7463 /* image_sample_cd_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60555 { 7463 /* image_sample_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60565 { 7463 /* image_sample_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60575 { 7463 /* image_sample_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60585 { 7463 /* image_sample_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60595 { 7463 /* image_sample_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60605 { 7463 /* image_sample_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60615 { 7463 /* image_sample_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60625 { 7463 /* image_sample_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60635 { 7463 /* image_sample_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60645 { 7463 /* image_sample_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60655 { 7463 /* image_sample_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60665 { 7463 /* image_sample_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60675 { 7463 /* image_sample_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60685 { 7463 /* image_sample_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60695 { 7463 /* image_sample_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60705 { 7463 /* image_sample_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60715 { 7463 /* image_sample_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60725 { 7463 /* image_sample_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60735 { 7463 /* image_sample_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60745 { 7463 /* image_sample_cd_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60755 { 7463 /* image_sample_cd_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60765 { 7463 /* image_sample_cd_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60775 { 7463 /* image_sample_cd_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60785 { 7463 /* image_sample_cd_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60795 { 7463 /* image_sample_cd_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60805 { 7463 /* image_sample_cd_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60815 { 7463 /* image_sample_cd_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60825 { 7463 /* image_sample_cd_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60835 { 7463 /* image_sample_cd_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60845 { 7463 /* image_sample_cd_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60855 { 7463 /* image_sample_cd_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60865 { 7463 /* image_sample_cd_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60875 { 7463 /* image_sample_cd_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60885 { 7463 /* image_sample_cd_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60895 { 7463 /* image_sample_cd_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60905 { 7463 /* image_sample_cd_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60915 { 7463 /* image_sample_cd_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60925 { 7463 /* image_sample_cd_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60935 { 7463 /* image_sample_cd_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60945 { 7463 /* image_sample_cd_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60955 { 7463 /* image_sample_cd_cl_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60965 { 7463 /* image_sample_cd_cl_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60975 { 7463 /* image_sample_cd_cl_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60985 { 7463 /* image_sample_cd_cl_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
60995 { 7463 /* image_sample_cd_cl_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61005 { 7463 /* image_sample_cd_cl_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61015 { 7463 /* image_sample_cd_cl_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61025 { 7463 /* image_sample_cd_cl_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61035 { 7463 /* image_sample_cd_cl_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61045 { 7463 /* image_sample_cd_cl_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61055 { 7463 /* image_sample_cd_cl_o */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61065 { 7463 /* image_sample_cd_cl_o */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61075 { 7463 /* image_sample_cd_cl_o */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61085 { 7463 /* image_sample_cd_cl_o */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61095 { 7463 /* image_sample_cd_cl_o */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61104 { 7484 /* image_sample_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61113 { 7484 /* image_sample_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61122 { 7484 /* image_sample_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61131 { 7484 /* image_sample_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61140 { 7484 /* image_sample_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61149 { 7484 /* image_sample_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61158 { 7484 /* image_sample_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61167 { 7484 /* image_sample_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61176 { 7484 /* image_sample_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61185 { 7484 /* image_sample_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61194 { 7484 /* image_sample_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61203 { 7484 /* image_sample_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61212 { 7484 /* image_sample_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61221 { 7484 /* image_sample_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61230 { 7484 /* image_sample_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61239 { 7484 /* image_sample_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61248 { 7484 /* image_sample_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61257 { 7484 /* image_sample_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61266 { 7484 /* image_sample_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61275 { 7484 /* image_sample_cd_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61285 { 7484 /* image_sample_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61295 { 7484 /* image_sample_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61305 { 7484 /* image_sample_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61315 { 7484 /* image_sample_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61325 { 7484 /* image_sample_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61335 { 7484 /* image_sample_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61345 { 7484 /* image_sample_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61355 { 7484 /* image_sample_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61365 { 7484 /* image_sample_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61375 { 7484 /* image_sample_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61385 { 7484 /* image_sample_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61395 { 7484 /* image_sample_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61405 { 7484 /* image_sample_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61415 { 7484 /* image_sample_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61425 { 7484 /* image_sample_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61435 { 7484 /* image_sample_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61445 { 7484 /* image_sample_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61455 { 7484 /* image_sample_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61465 { 7484 /* image_sample_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61475 { 7484 /* image_sample_cd_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61485 { 7484 /* image_sample_cd_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61495 { 7484 /* image_sample_cd_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61505 { 7484 /* image_sample_cd_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61515 { 7484 /* image_sample_cd_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61525 { 7484 /* image_sample_cd_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61535 { 7484 /* image_sample_cd_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61545 { 7484 /* image_sample_cd_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61555 { 7484 /* image_sample_cd_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61565 { 7484 /* image_sample_cd_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61575 { 7484 /* image_sample_cd_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61585 { 7484 /* image_sample_cd_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61595 { 7484 /* image_sample_cd_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61605 { 7484 /* image_sample_cd_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61615 { 7484 /* image_sample_cd_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61625 { 7484 /* image_sample_cd_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61635 { 7484 /* image_sample_cd_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61645 { 7484 /* image_sample_cd_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61655 { 7484 /* image_sample_cd_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61665 { 7484 /* image_sample_cd_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61675 { 7484 /* image_sample_cd_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61685 { 7484 /* image_sample_cd_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61695 { 7484 /* image_sample_cd_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61705 { 7484 /* image_sample_cd_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61715 { 7484 /* image_sample_cd_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61725 { 7484 /* image_sample_cd_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61735 { 7484 /* image_sample_cd_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61745 { 7484 /* image_sample_cd_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61755 { 7484 /* image_sample_cd_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61765 { 7484 /* image_sample_cd_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61775 { 7484 /* image_sample_cd_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61785 { 7484 /* image_sample_cd_o */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61795 { 7484 /* image_sample_cd_o */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61805 { 7484 /* image_sample_cd_o */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61815 { 7484 /* image_sample_cd_o */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61825 { 7484 /* image_sample_cd_o */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
61834 { 7502 /* image_sample_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61843 { 7502 /* image_sample_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61852 { 7502 /* image_sample_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61861 { 7502 /* image_sample_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61870 { 7502 /* image_sample_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61879 { 7502 /* image_sample_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61888 { 7502 /* image_sample_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61897 { 7502 /* image_sample_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61906 { 7502 /* image_sample_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61915 { 7502 /* image_sample_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61924 { 7502 /* image_sample_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61933 { 7502 /* image_sample_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61942 { 7502 /* image_sample_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61951 { 7502 /* image_sample_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61960 { 7502 /* image_sample_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61969 { 7502 /* image_sample_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61978 { 7502 /* image_sample_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61987 { 7502 /* image_sample_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61996 { 7502 /* image_sample_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62005 { 7502 /* image_sample_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62015 { 7502 /* image_sample_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62025 { 7502 /* image_sample_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62035 { 7502 /* image_sample_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62045 { 7502 /* image_sample_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62055 { 7502 /* image_sample_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62065 { 7502 /* image_sample_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62075 { 7502 /* image_sample_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62085 { 7502 /* image_sample_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62095 { 7502 /* image_sample_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62105 { 7502 /* image_sample_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62115 { 7502 /* image_sample_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62125 { 7502 /* image_sample_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62135 { 7502 /* image_sample_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62145 { 7502 /* image_sample_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62155 { 7502 /* image_sample_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62165 { 7502 /* image_sample_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62175 { 7502 /* image_sample_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62185 { 7502 /* image_sample_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62195 { 7502 /* image_sample_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62205 { 7502 /* image_sample_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62215 { 7502 /* image_sample_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62225 { 7502 /* image_sample_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62235 { 7502 /* image_sample_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62245 { 7502 /* image_sample_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62255 { 7502 /* image_sample_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62265 { 7502 /* image_sample_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62275 { 7502 /* image_sample_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62285 { 7502 /* image_sample_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62295 { 7502 /* image_sample_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62305 { 7502 /* image_sample_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62315 { 7502 /* image_sample_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62325 { 7502 /* image_sample_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62335 { 7502 /* image_sample_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62345 { 7502 /* image_sample_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62355 { 7502 /* image_sample_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62364 { 7518 /* image_sample_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62373 { 7518 /* image_sample_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62382 { 7518 /* image_sample_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62391 { 7518 /* image_sample_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62400 { 7518 /* image_sample_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62409 { 7518 /* image_sample_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62418 { 7518 /* image_sample_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62427 { 7518 /* image_sample_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62436 { 7518 /* image_sample_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62445 { 7518 /* image_sample_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62454 { 7518 /* image_sample_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62463 { 7518 /* image_sample_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62472 { 7518 /* image_sample_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62481 { 7518 /* image_sample_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62490 { 7518 /* image_sample_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62499 { 7518 /* image_sample_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62508 { 7518 /* image_sample_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62517 { 7518 /* image_sample_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62526 { 7518 /* image_sample_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62535 { 7518 /* image_sample_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62545 { 7518 /* image_sample_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62555 { 7518 /* image_sample_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62565 { 7518 /* image_sample_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62575 { 7518 /* image_sample_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62585 { 7518 /* image_sample_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62595 { 7518 /* image_sample_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62605 { 7518 /* image_sample_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62615 { 7518 /* image_sample_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62625 { 7518 /* image_sample_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62635 { 7518 /* image_sample_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62645 { 7518 /* image_sample_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62655 { 7518 /* image_sample_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62665 { 7518 /* image_sample_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62675 { 7518 /* image_sample_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62685 { 7518 /* image_sample_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62695 { 7518 /* image_sample_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62705 { 7518 /* image_sample_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62715 { 7518 /* image_sample_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62725 { 7518 /* image_sample_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62735 { 7518 /* image_sample_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62745 { 7518 /* image_sample_cl_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62755 { 7518 /* image_sample_cl_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62765 { 7518 /* image_sample_cl_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62775 { 7518 /* image_sample_cl_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62785 { 7518 /* image_sample_cl_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62795 { 7518 /* image_sample_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62805 { 7518 /* image_sample_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62815 { 7518 /* image_sample_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62825 { 7518 /* image_sample_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62835 { 7518 /* image_sample_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62845 { 7518 /* image_sample_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62855 { 7518 /* image_sample_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62865 { 7518 /* image_sample_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62875 { 7518 /* image_sample_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62885 { 7518 /* image_sample_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62895 { 7518 /* image_sample_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62905 { 7518 /* image_sample_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62915 { 7518 /* image_sample_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62925 { 7518 /* image_sample_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62935 { 7518 /* image_sample_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
62944 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62953 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62962 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62971 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62980 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62989 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62998 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63007 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63016 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63025 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63034 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63043 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63052 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63061 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63070 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63079 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63088 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63097 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63106 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63115 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63124 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63133 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63142 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63151 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63160 { 7536 /* image_sample_d */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63170 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63180 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63190 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63200 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63210 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63220 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63230 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63240 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63250 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63260 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63270 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63280 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63290 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63300 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63310 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63320 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63330 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63340 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63350 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63360 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63370 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63380 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63390 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63400 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63410 { 7536 /* image_sample_d */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63420 { 7536 /* image_sample_d */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63430 { 7536 /* image_sample_d */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63440 { 7536 /* image_sample_d */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63450 { 7536 /* image_sample_d */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63460 { 7536 /* image_sample_d */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63470 { 7536 /* image_sample_d */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63480 { 7536 /* image_sample_d */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63490 { 7536 /* image_sample_d */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63500 { 7536 /* image_sample_d */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63510 { 7536 /* image_sample_d */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63520 { 7536 /* image_sample_d */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63530 { 7536 /* image_sample_d */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63540 { 7536 /* image_sample_d */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63550 { 7536 /* image_sample_d */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63560 { 7536 /* image_sample_d */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63570 { 7536 /* image_sample_d */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63580 { 7536 /* image_sample_d */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63590 { 7536 /* image_sample_d */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63600 { 7536 /* image_sample_d */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63610 { 7536 /* image_sample_d */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63620 { 7536 /* image_sample_d */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63630 { 7536 /* image_sample_d */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63640 { 7536 /* image_sample_d */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63650 { 7536 /* image_sample_d */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63660 { 7536 /* image_sample_d */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63670 { 7536 /* image_sample_d */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63680 { 7536 /* image_sample_d */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63690 { 7536 /* image_sample_d */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63700 { 7536 /* image_sample_d */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63710 { 7536 /* image_sample_d */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63720 { 7536 /* image_sample_d */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63730 { 7536 /* image_sample_d */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63740 { 7536 /* image_sample_d */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63750 { 7536 /* image_sample_d */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63760 { 7536 /* image_sample_d */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
63769 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63778 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63787 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63796 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63805 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63814 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63823 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63832 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63841 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63850 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63859 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63868 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63877 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63886 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63895 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63904 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63913 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63922 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63931 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63940 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63949 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63958 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63967 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63976 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63985 { 7551 /* image_sample_d_cl */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63995 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64005 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64015 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64025 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64035 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64045 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64055 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64065 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64075 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64085 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64095 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64105 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64115 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64125 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64135 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64145 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64155 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64165 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64175 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64185 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64195 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64205 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64215 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64225 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64235 { 7551 /* image_sample_d_cl */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64245 { 7551 /* image_sample_d_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64255 { 7551 /* image_sample_d_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64265 { 7551 /* image_sample_d_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64275 { 7551 /* image_sample_d_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64285 { 7551 /* image_sample_d_cl */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64295 { 7551 /* image_sample_d_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64305 { 7551 /* image_sample_d_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64315 { 7551 /* image_sample_d_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64325 { 7551 /* image_sample_d_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64335 { 7551 /* image_sample_d_cl */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64345 { 7551 /* image_sample_d_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64355 { 7551 /* image_sample_d_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64365 { 7551 /* image_sample_d_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64375 { 7551 /* image_sample_d_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64385 { 7551 /* image_sample_d_cl */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64395 { 7551 /* image_sample_d_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64405 { 7551 /* image_sample_d_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64415 { 7551 /* image_sample_d_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64425 { 7551 /* image_sample_d_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64435 { 7551 /* image_sample_d_cl */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64445 { 7551 /* image_sample_d_cl */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64455 { 7551 /* image_sample_d_cl */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64465 { 7551 /* image_sample_d_cl */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64475 { 7551 /* image_sample_d_cl */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64485 { 7551 /* image_sample_d_cl */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64495 { 7551 /* image_sample_d_cl */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64505 { 7551 /* image_sample_d_cl */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64515 { 7551 /* image_sample_d_cl */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64525 { 7551 /* image_sample_d_cl */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64535 { 7551 /* image_sample_d_cl */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64545 { 7551 /* image_sample_d_cl */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64555 { 7551 /* image_sample_d_cl */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64565 { 7551 /* image_sample_d_cl */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64575 { 7551 /* image_sample_d_cl */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64585 { 7551 /* image_sample_d_cl */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64594 { 7569 /* image_sample_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64603 { 7569 /* image_sample_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64612 { 7569 /* image_sample_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64621 { 7569 /* image_sample_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64630 { 7569 /* image_sample_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64639 { 7569 /* image_sample_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64648 { 7569 /* image_sample_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64657 { 7569 /* image_sample_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64666 { 7569 /* image_sample_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64675 { 7569 /* image_sample_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64684 { 7569 /* image_sample_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64693 { 7569 /* image_sample_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64702 { 7569 /* image_sample_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64711 { 7569 /* image_sample_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64720 { 7569 /* image_sample_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64729 { 7569 /* image_sample_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64738 { 7569 /* image_sample_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64747 { 7569 /* image_sample_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64756 { 7569 /* image_sample_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64765 { 7569 /* image_sample_d_cl_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64775 { 7569 /* image_sample_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64785 { 7569 /* image_sample_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64795 { 7569 /* image_sample_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64805 { 7569 /* image_sample_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64815 { 7569 /* image_sample_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64825 { 7569 /* image_sample_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64835 { 7569 /* image_sample_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64845 { 7569 /* image_sample_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64855 { 7569 /* image_sample_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64865 { 7569 /* image_sample_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64875 { 7569 /* image_sample_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64885 { 7569 /* image_sample_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64895 { 7569 /* image_sample_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64905 { 7569 /* image_sample_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64915 { 7569 /* image_sample_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64925 { 7569 /* image_sample_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64935 { 7569 /* image_sample_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64945 { 7569 /* image_sample_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64955 { 7569 /* image_sample_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64965 { 7569 /* image_sample_d_cl_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64975 { 7569 /* image_sample_d_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64985 { 7569 /* image_sample_d_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
64995 { 7569 /* image_sample_d_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65005 { 7569 /* image_sample_d_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65015 { 7569 /* image_sample_d_cl_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65025 { 7569 /* image_sample_d_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65035 { 7569 /* image_sample_d_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65045 { 7569 /* image_sample_d_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65055 { 7569 /* image_sample_d_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65065 { 7569 /* image_sample_d_cl_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65075 { 7569 /* image_sample_d_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65085 { 7569 /* image_sample_d_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65095 { 7569 /* image_sample_d_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65105 { 7569 /* image_sample_d_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65115 { 7569 /* image_sample_d_cl_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65125 { 7569 /* image_sample_d_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65135 { 7569 /* image_sample_d_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65145 { 7569 /* image_sample_d_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65155 { 7569 /* image_sample_d_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65165 { 7569 /* image_sample_d_cl_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65175 { 7569 /* image_sample_d_cl_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65185 { 7569 /* image_sample_d_cl_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65195 { 7569 /* image_sample_d_cl_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65205 { 7569 /* image_sample_d_cl_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65215 { 7569 /* image_sample_d_cl_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65225 { 7569 /* image_sample_d_cl_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65235 { 7569 /* image_sample_d_cl_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65245 { 7569 /* image_sample_d_cl_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65255 { 7569 /* image_sample_d_cl_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65265 { 7569 /* image_sample_d_cl_o */, 524288 /* 19 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65275 { 7569 /* image_sample_d_cl_o */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65285 { 7569 /* image_sample_d_cl_o */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65295 { 7569 /* image_sample_d_cl_o */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65305 { 7569 /* image_sample_d_cl_o */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65315 { 7569 /* image_sample_d_cl_o */, 2097152 /* 21 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65324 { 7589 /* image_sample_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65333 { 7589 /* image_sample_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65342 { 7589 /* image_sample_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65351 { 7589 /* image_sample_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65360 { 7589 /* image_sample_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65369 { 7589 /* image_sample_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65378 { 7589 /* image_sample_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65387 { 7589 /* image_sample_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65396 { 7589 /* image_sample_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65405 { 7589 /* image_sample_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65414 { 7589 /* image_sample_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65423 { 7589 /* image_sample_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65432 { 7589 /* image_sample_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65441 { 7589 /* image_sample_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65450 { 7589 /* image_sample_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65459 { 7589 /* image_sample_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65468 { 7589 /* image_sample_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65477 { 7589 /* image_sample_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65486 { 7589 /* image_sample_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65495 { 7589 /* image_sample_d_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65505 { 7589 /* image_sample_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65515 { 7589 /* image_sample_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65525 { 7589 /* image_sample_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65535 { 7589 /* image_sample_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65545 { 7589 /* image_sample_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65555 { 7589 /* image_sample_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65565 { 7589 /* image_sample_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65575 { 7589 /* image_sample_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65585 { 7589 /* image_sample_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65595 { 7589 /* image_sample_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65605 { 7589 /* image_sample_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65615 { 7589 /* image_sample_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65625 { 7589 /* image_sample_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65635 { 7589 /* image_sample_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65645 { 7589 /* image_sample_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65655 { 7589 /* image_sample_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65665 { 7589 /* image_sample_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65675 { 7589 /* image_sample_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65685 { 7589 /* image_sample_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65695 { 7589 /* image_sample_d_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65705 { 7589 /* image_sample_d_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65715 { 7589 /* image_sample_d_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65725 { 7589 /* image_sample_d_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65735 { 7589 /* image_sample_d_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65745 { 7589 /* image_sample_d_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65755 { 7589 /* image_sample_d_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65765 { 7589 /* image_sample_d_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65775 { 7589 /* image_sample_d_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65785 { 7589 /* image_sample_d_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65795 { 7589 /* image_sample_d_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65805 { 7589 /* image_sample_d_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65815 { 7589 /* image_sample_d_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65825 { 7589 /* image_sample_d_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65835 { 7589 /* image_sample_d_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65845 { 7589 /* image_sample_d_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65855 { 7589 /* image_sample_d_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65865 { 7589 /* image_sample_d_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65875 { 7589 /* image_sample_d_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65885 { 7589 /* image_sample_d_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65895 { 7589 /* image_sample_d_o */, 65536 /* 16 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65905 { 7589 /* image_sample_d_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65915 { 7589 /* image_sample_d_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65925 { 7589 /* image_sample_d_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65935 { 7589 /* image_sample_d_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65945 { 7589 /* image_sample_d_o */, 131072 /* 17 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65955 { 7589 /* image_sample_d_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65965 { 7589 /* image_sample_d_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65975 { 7589 /* image_sample_d_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65985 { 7589 /* image_sample_d_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
65995 { 7589 /* image_sample_d_o */, 262144 /* 18 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66005 { 7589 /* image_sample_d_o */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66015 { 7589 /* image_sample_d_o */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66025 { 7589 /* image_sample_d_o */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66035 { 7589 /* image_sample_d_o */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66045 { 7589 /* image_sample_d_o */, 1048576 /* 20 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66054 { 7606 /* image_sample_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66063 { 7606 /* image_sample_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66072 { 7606 /* image_sample_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66081 { 7606 /* image_sample_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66090 { 7606 /* image_sample_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66099 { 7606 /* image_sample_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66108 { 7606 /* image_sample_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66117 { 7606 /* image_sample_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66126 { 7606 /* image_sample_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66135 { 7606 /* image_sample_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66144 { 7606 /* image_sample_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66153 { 7606 /* image_sample_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66162 { 7606 /* image_sample_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66171 { 7606 /* image_sample_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66180 { 7606 /* image_sample_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66189 { 7606 /* image_sample_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66198 { 7606 /* image_sample_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66207 { 7606 /* image_sample_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66216 { 7606 /* image_sample_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66225 { 7606 /* image_sample_l */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66235 { 7606 /* image_sample_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66245 { 7606 /* image_sample_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66255 { 7606 /* image_sample_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66265 { 7606 /* image_sample_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66275 { 7606 /* image_sample_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66285 { 7606 /* image_sample_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66295 { 7606 /* image_sample_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66305 { 7606 /* image_sample_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66315 { 7606 /* image_sample_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66325 { 7606 /* image_sample_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66335 { 7606 /* image_sample_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66345 { 7606 /* image_sample_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66355 { 7606 /* image_sample_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66365 { 7606 /* image_sample_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66375 { 7606 /* image_sample_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66385 { 7606 /* image_sample_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66395 { 7606 /* image_sample_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66405 { 7606 /* image_sample_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66415 { 7606 /* image_sample_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66425 { 7606 /* image_sample_l */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66435 { 7606 /* image_sample_l */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66445 { 7606 /* image_sample_l */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66455 { 7606 /* image_sample_l */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66465 { 7606 /* image_sample_l */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66475 { 7606 /* image_sample_l */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66485 { 7606 /* image_sample_l */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66495 { 7606 /* image_sample_l */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66505 { 7606 /* image_sample_l */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66515 { 7606 /* image_sample_l */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66525 { 7606 /* image_sample_l */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66535 { 7606 /* image_sample_l */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66545 { 7606 /* image_sample_l */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66555 { 7606 /* image_sample_l */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66565 { 7606 /* image_sample_l */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66575 { 7606 /* image_sample_l */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66584 { 7621 /* image_sample_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66593 { 7621 /* image_sample_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66602 { 7621 /* image_sample_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66611 { 7621 /* image_sample_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66620 { 7621 /* image_sample_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66629 { 7621 /* image_sample_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66638 { 7621 /* image_sample_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66647 { 7621 /* image_sample_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66656 { 7621 /* image_sample_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66665 { 7621 /* image_sample_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66674 { 7621 /* image_sample_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66683 { 7621 /* image_sample_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66692 { 7621 /* image_sample_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66701 { 7621 /* image_sample_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66710 { 7621 /* image_sample_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66719 { 7621 /* image_sample_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66728 { 7621 /* image_sample_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66737 { 7621 /* image_sample_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66746 { 7621 /* image_sample_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66755 { 7621 /* image_sample_l_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66765 { 7621 /* image_sample_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66775 { 7621 /* image_sample_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66785 { 7621 /* image_sample_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66795 { 7621 /* image_sample_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66805 { 7621 /* image_sample_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66815 { 7621 /* image_sample_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66825 { 7621 /* image_sample_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66835 { 7621 /* image_sample_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66845 { 7621 /* image_sample_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66855 { 7621 /* image_sample_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66865 { 7621 /* image_sample_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66875 { 7621 /* image_sample_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66885 { 7621 /* image_sample_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66895 { 7621 /* image_sample_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66905 { 7621 /* image_sample_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66915 { 7621 /* image_sample_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66925 { 7621 /* image_sample_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66935 { 7621 /* image_sample_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66945 { 7621 /* image_sample_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66955 { 7621 /* image_sample_l_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66965 { 7621 /* image_sample_l_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66975 { 7621 /* image_sample_l_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66985 { 7621 /* image_sample_l_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
66995 { 7621 /* image_sample_l_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67005 { 7621 /* image_sample_l_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67015 { 7621 /* image_sample_l_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67025 { 7621 /* image_sample_l_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67035 { 7621 /* image_sample_l_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67045 { 7621 /* image_sample_l_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67055 { 7621 /* image_sample_l_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67065 { 7621 /* image_sample_l_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67075 { 7621 /* image_sample_l_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67085 { 7621 /* image_sample_l_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67095 { 7621 /* image_sample_l_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67105 { 7621 /* image_sample_l_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67115 { 7621 /* image_sample_l_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67125 { 7621 /* image_sample_l_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67135 { 7621 /* image_sample_l_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67145 { 7621 /* image_sample_l_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67155 { 7621 /* image_sample_l_o */, 32768 /* 15 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67164 { 7638 /* image_sample_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67173 { 7638 /* image_sample_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67182 { 7638 /* image_sample_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67191 { 7638 /* image_sample_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67200 { 7638 /* image_sample_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67209 { 7638 /* image_sample_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67218 { 7638 /* image_sample_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67227 { 7638 /* image_sample_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67236 { 7638 /* image_sample_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67245 { 7638 /* image_sample_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67254 { 7638 /* image_sample_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67263 { 7638 /* image_sample_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67272 { 7638 /* image_sample_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67281 { 7638 /* image_sample_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67290 { 7638 /* image_sample_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67299 { 7638 /* image_sample_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67308 { 7638 /* image_sample_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67317 { 7638 /* image_sample_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67326 { 7638 /* image_sample_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67335 { 7638 /* image_sample_lz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67345 { 7638 /* image_sample_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67355 { 7638 /* image_sample_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67365 { 7638 /* image_sample_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67375 { 7638 /* image_sample_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67385 { 7638 /* image_sample_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67395 { 7638 /* image_sample_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67405 { 7638 /* image_sample_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67415 { 7638 /* image_sample_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67425 { 7638 /* image_sample_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67435 { 7638 /* image_sample_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67445 { 7638 /* image_sample_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67455 { 7638 /* image_sample_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67465 { 7638 /* image_sample_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67475 { 7638 /* image_sample_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67485 { 7638 /* image_sample_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67495 { 7638 /* image_sample_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67505 { 7638 /* image_sample_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67515 { 7638 /* image_sample_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67525 { 7638 /* image_sample_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67535 { 7638 /* image_sample_lz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67545 { 7638 /* image_sample_lz */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67555 { 7638 /* image_sample_lz */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67565 { 7638 /* image_sample_lz */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67575 { 7638 /* image_sample_lz */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67585 { 7638 /* image_sample_lz */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67595 { 7638 /* image_sample_lz */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67605 { 7638 /* image_sample_lz */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67615 { 7638 /* image_sample_lz */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67625 { 7638 /* image_sample_lz */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67635 { 7638 /* image_sample_lz */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67644 { 7654 /* image_sample_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67653 { 7654 /* image_sample_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67662 { 7654 /* image_sample_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67671 { 7654 /* image_sample_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67680 { 7654 /* image_sample_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67689 { 7654 /* image_sample_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67698 { 7654 /* image_sample_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67707 { 7654 /* image_sample_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67716 { 7654 /* image_sample_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67725 { 7654 /* image_sample_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67734 { 7654 /* image_sample_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67743 { 7654 /* image_sample_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67752 { 7654 /* image_sample_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67761 { 7654 /* image_sample_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67770 { 7654 /* image_sample_lz_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67780 { 7654 /* image_sample_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67790 { 7654 /* image_sample_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67800 { 7654 /* image_sample_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67810 { 7654 /* image_sample_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67820 { 7654 /* image_sample_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67830 { 7654 /* image_sample_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67840 { 7654 /* image_sample_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67850 { 7654 /* image_sample_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67860 { 7654 /* image_sample_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67870 { 7654 /* image_sample_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67880 { 7654 /* image_sample_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67890 { 7654 /* image_sample_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67900 { 7654 /* image_sample_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67910 { 7654 /* image_sample_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67920 { 7654 /* image_sample_lz_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67930 { 7654 /* image_sample_lz_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67940 { 7654 /* image_sample_lz_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67950 { 7654 /* image_sample_lz_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67960 { 7654 /* image_sample_lz_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67970 { 7654 /* image_sample_lz_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67980 { 7654 /* image_sample_lz_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
67990 { 7654 /* image_sample_lz_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68000 { 7654 /* image_sample_lz_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68010 { 7654 /* image_sample_lz_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68020 { 7654 /* image_sample_lz_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68030 { 7654 /* image_sample_lz_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68040 { 7654 /* image_sample_lz_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68050 { 7654 /* image_sample_lz_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68060 { 7654 /* image_sample_lz_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68070 { 7654 /* image_sample_lz_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68079 { 7672 /* image_sample_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68088 { 7672 /* image_sample_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68097 { 7672 /* image_sample_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68106 { 7672 /* image_sample_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68115 { 7672 /* image_sample_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68124 { 7672 /* image_sample_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68133 { 7672 /* image_sample_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68142 { 7672 /* image_sample_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68151 { 7672 /* image_sample_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68160 { 7672 /* image_sample_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68169 { 7672 /* image_sample_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68178 { 7672 /* image_sample_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68187 { 7672 /* image_sample_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68196 { 7672 /* image_sample_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68205 { 7672 /* image_sample_o */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68215 { 7672 /* image_sample_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68225 { 7672 /* image_sample_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68235 { 7672 /* image_sample_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68245 { 7672 /* image_sample_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68255 { 7672 /* image_sample_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68265 { 7672 /* image_sample_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68275 { 7672 /* image_sample_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68285 { 7672 /* image_sample_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68295 { 7672 /* image_sample_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68305 { 7672 /* image_sample_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68315 { 7672 /* image_sample_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68325 { 7672 /* image_sample_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68335 { 7672 /* image_sample_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68345 { 7672 /* image_sample_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68355 { 7672 /* image_sample_o */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68365 { 7672 /* image_sample_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68375 { 7672 /* image_sample_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68385 { 7672 /* image_sample_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68395 { 7672 /* image_sample_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68405 { 7672 /* image_sample_o */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68415 { 7672 /* image_sample_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68425 { 7672 /* image_sample_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68435 { 7672 /* image_sample_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68445 { 7672 /* image_sample_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68455 { 7672 /* image_sample_o */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68465 { 7672 /* image_sample_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68475 { 7672 /* image_sample_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68485 { 7672 /* image_sample_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68495 { 7672 /* image_sample_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68505 { 7672 /* image_sample_o */, 16384 /* 14 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68514 { 7687 /* image_store */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68523 { 7687 /* image_store */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68532 { 7687 /* image_store */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68541 { 7687 /* image_store */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68550 { 7687 /* image_store */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68559 { 7687 /* image_store */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68568 { 7687 /* image_store */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68577 { 7687 /* image_store */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68586 { 7687 /* image_store */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68595 { 7687 /* image_store */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68604 { 7687 /* image_store */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68613 { 7687 /* image_store */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68622 { 7687 /* image_store */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68631 { 7687 /* image_store */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68640 { 7687 /* image_store */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68649 { 7687 /* image_store */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68659 { 7687 /* image_store */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68669 { 7687 /* image_store */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68679 { 7687 /* image_store */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68689 { 7687 /* image_store */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68699 { 7687 /* image_store */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68709 { 7687 /* image_store */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68719 { 7687 /* image_store */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68729 { 7687 /* image_store */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68739 { 7687 /* image_store */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68749 { 7687 /* image_store */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68759 { 7687 /* image_store */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68769 { 7687 /* image_store */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68779 { 7687 /* image_store */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68789 { 7687 /* image_store */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68799 { 7687 /* image_store */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68809 { 7687 /* image_store */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68819 { 7687 /* image_store */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68829 { 7687 /* image_store */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68839 { 7687 /* image_store */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68849 { 7687 /* image_store */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68859 { 7687 /* image_store */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68869 { 7687 /* image_store */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68879 { 7687 /* image_store */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68889 { 7687 /* image_store */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68899 { 7687 /* image_store */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68909 { 7687 /* image_store */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68919 { 7687 /* image_store */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68929 { 7687 /* image_store */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
68938 { 7699 /* image_store_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68947 { 7699 /* image_store_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68956 { 7699 /* image_store_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68965 { 7699 /* image_store_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68974 { 7699 /* image_store_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68983 { 7699 /* image_store_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68992 { 7699 /* image_store_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69001 { 7699 /* image_store_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69010 { 7699 /* image_store_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69019 { 7699 /* image_store_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69028 { 7699 /* image_store_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69037 { 7699 /* image_store_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69046 { 7699 /* image_store_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69055 { 7699 /* image_store_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69064 { 7699 /* image_store_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69073 { 7699 /* image_store_mip */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69083 { 7699 /* image_store_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69093 { 7699 /* image_store_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69103 { 7699 /* image_store_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69113 { 7699 /* image_store_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69123 { 7699 /* image_store_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69133 { 7699 /* image_store_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69143 { 7699 /* image_store_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69153 { 7699 /* image_store_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69163 { 7699 /* image_store_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69173 { 7699 /* image_store_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69183 { 7699 /* image_store_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69193 { 7699 /* image_store_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69203 { 7699 /* image_store_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69213 { 7699 /* image_store_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69223 { 7699 /* image_store_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69233 { 7699 /* image_store_mip */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69243 { 7699 /* image_store_mip */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69253 { 7699 /* image_store_mip */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69263 { 7699 /* image_store_mip */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69273 { 7699 /* image_store_mip */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69283 { 7699 /* image_store_mip */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69293 { 7699 /* image_store_mip */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69303 { 7699 /* image_store_mip */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69313 { 7699 /* image_store_mip */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69323 { 7699 /* image_store_mip */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69333 { 7699 /* image_store_mip */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69343 { 7699 /* image_store_mip */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69353 { 7699 /* image_store_mip */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69362 { 7715 /* image_store_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69370 { 7715 /* image_store_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69378 { 7715 /* image_store_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69386 { 7715 /* image_store_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69394 { 7715 /* image_store_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69402 { 7715 /* image_store_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69410 { 7715 /* image_store_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69418 { 7715 /* image_store_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69426 { 7715 /* image_store_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69434 { 7715 /* image_store_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69442 { 7715 /* image_store_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69450 { 7715 /* image_store_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69458 { 7715 /* image_store_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69466 { 7715 /* image_store_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69474 { 7715 /* image_store_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69482 { 7715 /* image_store_mip_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69491 { 7715 /* image_store_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69500 { 7715 /* image_store_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69509 { 7715 /* image_store_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69518 { 7715 /* image_store_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69527 { 7715 /* image_store_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69536 { 7715 /* image_store_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69545 { 7715 /* image_store_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69554 { 7715 /* image_store_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69563 { 7715 /* image_store_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69572 { 7715 /* image_store_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69581 { 7715 /* image_store_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69590 { 7715 /* image_store_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69599 { 7715 /* image_store_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69608 { 7715 /* image_store_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69617 { 7715 /* image_store_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69626 { 7715 /* image_store_mip_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69635 { 7715 /* image_store_mip_pck */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69644 { 7715 /* image_store_mip_pck */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69653 { 7715 /* image_store_mip_pck */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69662 { 7715 /* image_store_mip_pck */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69671 { 7715 /* image_store_mip_pck */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69680 { 7715 /* image_store_mip_pck */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69689 { 7715 /* image_store_mip_pck */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69698 { 7715 /* image_store_mip_pck */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69707 { 7715 /* image_store_mip_pck */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69716 { 7715 /* image_store_mip_pck */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69725 { 7715 /* image_store_mip_pck */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69734 { 7715 /* image_store_mip_pck */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69742 { 7735 /* image_store_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69750 { 7735 /* image_store_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69758 { 7735 /* image_store_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69766 { 7735 /* image_store_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69774 { 7735 /* image_store_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69782 { 7735 /* image_store_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69790 { 7735 /* image_store_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69798 { 7735 /* image_store_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69806 { 7735 /* image_store_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69814 { 7735 /* image_store_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69822 { 7735 /* image_store_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69830 { 7735 /* image_store_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69838 { 7735 /* image_store_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69846 { 7735 /* image_store_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69854 { 7735 /* image_store_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69862 { 7735 /* image_store_pck */, 64 /* 6 */, MCK_ImmSLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69871 { 7735 /* image_store_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69880 { 7735 /* image_store_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69889 { 7735 /* image_store_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69898 { 7735 /* image_store_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69907 { 7735 /* image_store_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69916 { 7735 /* image_store_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69925 { 7735 /* image_store_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69934 { 7735 /* image_store_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69943 { 7735 /* image_store_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69952 { 7735 /* image_store_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69961 { 7735 /* image_store_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69970 { 7735 /* image_store_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69979 { 7735 /* image_store_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69988 { 7735 /* image_store_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
69997 { 7735 /* image_store_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
70006 { 7735 /* image_store_pck */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
70015 { 7735 /* image_store_pck */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
70024 { 7735 /* image_store_pck */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
70033 { 7735 /* image_store_pck */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
70042 { 7735 /* image_store_pck */, 2048 /* 11 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
70051 { 7735 /* image_store_pck */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
70060 { 7735 /* image_store_pck */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
70069 { 7735 /* image_store_pck */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
70078 { 7735 /* image_store_pck */, 4096 /* 12 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
70087 { 7735 /* image_store_pck */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
70096 { 7735 /* image_store_pck */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
70105 { 7735 /* image_store_pck */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
70114 { 7735 /* image_store_pck */, 8192 /* 13 */, MCK_ImmSLC, AMFBS_isGFX10Plus_isGFX10Plus },
71099 { 12271 /* scratch_load_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71103 { 12271 /* scratch_load_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71107 { 12271 /* scratch_load_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71111 { 12271 /* scratch_load_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71115 { 12290 /* scratch_load_dwordx2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71119 { 12290 /* scratch_load_dwordx2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71123 { 12290 /* scratch_load_dwordx2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71127 { 12290 /* scratch_load_dwordx2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71131 { 12311 /* scratch_load_dwordx3 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71135 { 12311 /* scratch_load_dwordx3 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71139 { 12311 /* scratch_load_dwordx3 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71143 { 12311 /* scratch_load_dwordx3 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71147 { 12332 /* scratch_load_dwordx4 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71151 { 12332 /* scratch_load_dwordx4 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71155 { 12332 /* scratch_load_dwordx4 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71159 { 12332 /* scratch_load_dwordx4 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71163 { 12353 /* scratch_load_sbyte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71167 { 12353 /* scratch_load_sbyte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71171 { 12353 /* scratch_load_sbyte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71175 { 12353 /* scratch_load_sbyte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71179 { 12372 /* scratch_load_sbyte_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71183 { 12372 /* scratch_load_sbyte_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71187 { 12372 /* scratch_load_sbyte_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71191 { 12372 /* scratch_load_sbyte_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71195 { 12395 /* scratch_load_sbyte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71199 { 12395 /* scratch_load_sbyte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71203 { 12395 /* scratch_load_sbyte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71207 { 12395 /* scratch_load_sbyte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71211 { 12421 /* scratch_load_short_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71215 { 12421 /* scratch_load_short_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71219 { 12421 /* scratch_load_short_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71223 { 12421 /* scratch_load_short_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71227 { 12444 /* scratch_load_short_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71231 { 12444 /* scratch_load_short_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71235 { 12444 /* scratch_load_short_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71239 { 12444 /* scratch_load_short_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71243 { 12470 /* scratch_load_sshort */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71247 { 12470 /* scratch_load_sshort */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71251 { 12470 /* scratch_load_sshort */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71255 { 12470 /* scratch_load_sshort */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71259 { 12490 /* scratch_load_ubyte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71263 { 12490 /* scratch_load_ubyte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71267 { 12490 /* scratch_load_ubyte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71271 { 12490 /* scratch_load_ubyte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71275 { 12509 /* scratch_load_ubyte_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71279 { 12509 /* scratch_load_ubyte_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71283 { 12509 /* scratch_load_ubyte_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71287 { 12509 /* scratch_load_ubyte_d16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71291 { 12532 /* scratch_load_ubyte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71295 { 12532 /* scratch_load_ubyte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71299 { 12532 /* scratch_load_ubyte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71303 { 12532 /* scratch_load_ubyte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71307 { 12558 /* scratch_load_ushort */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71311 { 12558 /* scratch_load_ushort */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71315 { 12558 /* scratch_load_ushort */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71319 { 12558 /* scratch_load_ushort */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71323 { 12578 /* scratch_store_byte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71327 { 12578 /* scratch_store_byte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71331 { 12578 /* scratch_store_byte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71335 { 12578 /* scratch_store_byte */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71339 { 12597 /* scratch_store_byte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71343 { 12597 /* scratch_store_byte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71347 { 12597 /* scratch_store_byte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71351 { 12597 /* scratch_store_byte_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71355 { 12623 /* scratch_store_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71359 { 12623 /* scratch_store_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71363 { 12623 /* scratch_store_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71367 { 12623 /* scratch_store_dword */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71371 { 12643 /* scratch_store_dwordx2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71375 { 12643 /* scratch_store_dwordx2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71379 { 12643 /* scratch_store_dwordx2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71383 { 12643 /* scratch_store_dwordx2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71387 { 12665 /* scratch_store_dwordx3 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71391 { 12665 /* scratch_store_dwordx3 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71395 { 12665 /* scratch_store_dwordx3 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71399 { 12665 /* scratch_store_dwordx3 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71403 { 12687 /* scratch_store_dwordx4 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71407 { 12687 /* scratch_store_dwordx4 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71411 { 12687 /* scratch_store_dwordx4 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71415 { 12687 /* scratch_store_dwordx4 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71419 { 12709 /* scratch_store_short */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71423 { 12709 /* scratch_store_short */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71427 { 12709 /* scratch_store_short */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71431 { 12709 /* scratch_store_short */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71435 { 12729 /* scratch_store_short_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71439 { 12729 /* scratch_store_short_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71443 { 12729 /* scratch_store_short_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71447 { 12729 /* scratch_store_short_d16_hi */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71451 { 12756 /* tbuffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71458 { 12756 /* tbuffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71465 { 12756 /* tbuffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71472 { 12756 /* tbuffer_load_format_d16_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71479 { 12756 /* tbuffer_load_format_d16_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71486 { 12756 /* tbuffer_load_format_d16_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71493 { 12756 /* tbuffer_load_format_d16_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71500 { 12756 /* tbuffer_load_format_d16_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71507 { 12756 /* tbuffer_load_format_d16_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71514 { 12756 /* tbuffer_load_format_d16_x */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71521 { 12756 /* tbuffer_load_format_d16_x */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71528 { 12756 /* tbuffer_load_format_d16_x */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71535 { 12782 /* tbuffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71542 { 12782 /* tbuffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71549 { 12782 /* tbuffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71556 { 12782 /* tbuffer_load_format_d16_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71563 { 12782 /* tbuffer_load_format_d16_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71570 { 12782 /* tbuffer_load_format_d16_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71577 { 12782 /* tbuffer_load_format_d16_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71584 { 12782 /* tbuffer_load_format_d16_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71591 { 12782 /* tbuffer_load_format_d16_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71598 { 12782 /* tbuffer_load_format_d16_xy */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71605 { 12782 /* tbuffer_load_format_d16_xy */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71612 { 12782 /* tbuffer_load_format_d16_xy */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71619 { 12809 /* tbuffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71626 { 12809 /* tbuffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71633 { 12809 /* tbuffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71640 { 12809 /* tbuffer_load_format_d16_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71647 { 12809 /* tbuffer_load_format_d16_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71654 { 12809 /* tbuffer_load_format_d16_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71661 { 12809 /* tbuffer_load_format_d16_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71668 { 12809 /* tbuffer_load_format_d16_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71675 { 12809 /* tbuffer_load_format_d16_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71682 { 12809 /* tbuffer_load_format_d16_xyz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71689 { 12809 /* tbuffer_load_format_d16_xyz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71696 { 12809 /* tbuffer_load_format_d16_xyz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71703 { 12837 /* tbuffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71710 { 12837 /* tbuffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71717 { 12837 /* tbuffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71724 { 12837 /* tbuffer_load_format_d16_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71731 { 12837 /* tbuffer_load_format_d16_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71738 { 12837 /* tbuffer_load_format_d16_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71745 { 12837 /* tbuffer_load_format_d16_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71752 { 12837 /* tbuffer_load_format_d16_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71759 { 12837 /* tbuffer_load_format_d16_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71766 { 12837 /* tbuffer_load_format_d16_xyzw */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71773 { 12837 /* tbuffer_load_format_d16_xyzw */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71780 { 12837 /* tbuffer_load_format_d16_xyzw */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71787 { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
71794 { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71801 { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
71808 { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71815 { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
71822 { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71829 { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
71836 { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
71843 { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71850 { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
71857 { 12866 /* tbuffer_load_format_x */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
71864 { 12866 /* tbuffer_load_format_x */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71871 { 12866 /* tbuffer_load_format_x */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
71878 { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
71885 { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71892 { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
71899 { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71906 { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
71913 { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71920 { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
71927 { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
71934 { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71941 { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
71948 { 12888 /* tbuffer_load_format_xy */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
71955 { 12888 /* tbuffer_load_format_xy */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71962 { 12888 /* tbuffer_load_format_xy */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
71969 { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
71976 { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71983 { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
71990 { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
71997 { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72004 { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72011 { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72018 { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72025 { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72032 { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72039 { 12911 /* tbuffer_load_format_xyz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72046 { 12911 /* tbuffer_load_format_xyz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72053 { 12911 /* tbuffer_load_format_xyz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72060 { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72067 { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72074 { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72081 { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72088 { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72095 { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72102 { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72109 { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72116 { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72123 { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72130 { 12935 /* tbuffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72137 { 12935 /* tbuffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72144 { 12935 /* tbuffer_load_format_xyzw */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72151 { 12960 /* tbuffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72158 { 12960 /* tbuffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72165 { 12960 /* tbuffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72172 { 12960 /* tbuffer_store_format_d16_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72179 { 12960 /* tbuffer_store_format_d16_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72186 { 12960 /* tbuffer_store_format_d16_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72193 { 12960 /* tbuffer_store_format_d16_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72200 { 12960 /* tbuffer_store_format_d16_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72207 { 12960 /* tbuffer_store_format_d16_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72214 { 12960 /* tbuffer_store_format_d16_x */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72221 { 12960 /* tbuffer_store_format_d16_x */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72228 { 12960 /* tbuffer_store_format_d16_x */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72235 { 12987 /* tbuffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72242 { 12987 /* tbuffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72249 { 12987 /* tbuffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72256 { 12987 /* tbuffer_store_format_d16_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72263 { 12987 /* tbuffer_store_format_d16_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72270 { 12987 /* tbuffer_store_format_d16_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72277 { 12987 /* tbuffer_store_format_d16_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72284 { 12987 /* tbuffer_store_format_d16_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72291 { 12987 /* tbuffer_store_format_d16_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72298 { 12987 /* tbuffer_store_format_d16_xy */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72305 { 12987 /* tbuffer_store_format_d16_xy */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72312 { 12987 /* tbuffer_store_format_d16_xy */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72319 { 13015 /* tbuffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72326 { 13015 /* tbuffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72333 { 13015 /* tbuffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72340 { 13015 /* tbuffer_store_format_d16_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72347 { 13015 /* tbuffer_store_format_d16_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72354 { 13015 /* tbuffer_store_format_d16_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72361 { 13015 /* tbuffer_store_format_d16_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72368 { 13015 /* tbuffer_store_format_d16_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72375 { 13015 /* tbuffer_store_format_d16_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72382 { 13015 /* tbuffer_store_format_d16_xyz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72389 { 13015 /* tbuffer_store_format_d16_xyz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72396 { 13015 /* tbuffer_store_format_d16_xyz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72403 { 13044 /* tbuffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72410 { 13044 /* tbuffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72417 { 13044 /* tbuffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72424 { 13044 /* tbuffer_store_format_d16_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72431 { 13044 /* tbuffer_store_format_d16_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72438 { 13044 /* tbuffer_store_format_d16_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72445 { 13044 /* tbuffer_store_format_d16_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72452 { 13044 /* tbuffer_store_format_d16_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72459 { 13044 /* tbuffer_store_format_d16_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72466 { 13044 /* tbuffer_store_format_d16_xyzw */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72473 { 13044 /* tbuffer_store_format_d16_xyzw */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72480 { 13044 /* tbuffer_store_format_d16_xyzw */, 512 /* 9 */, MCK_ImmSLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72487 { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72494 { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72501 { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72508 { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72515 { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72522 { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72529 { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72536 { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72543 { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72550 { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72557 { 13074 /* tbuffer_store_format_x */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72564 { 13074 /* tbuffer_store_format_x */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72571 { 13074 /* tbuffer_store_format_x */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72578 { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72585 { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72592 { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72599 { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72606 { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72613 { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72620 { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72627 { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72634 { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72641 { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72648 { 13097 /* tbuffer_store_format_xy */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72655 { 13097 /* tbuffer_store_format_xy */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72662 { 13097 /* tbuffer_store_format_xy */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72669 { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72676 { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72683 { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72690 { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72697 { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72704 { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72711 { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72718 { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72725 { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72732 { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72739 { 13121 /* tbuffer_store_format_xyz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72746 { 13121 /* tbuffer_store_format_xyz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72753 { 13121 /* tbuffer_store_format_xyz */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72760 { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72767 { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72774 { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72781 { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72788 { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72795 { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72802 { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72809 { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72816 { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72823 { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
72830 { 13146 /* tbuffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX10Plus },
72837 { 13146 /* tbuffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX6GFX7 },
72844 { 13146 /* tbuffer_store_format_xyzw */, 512 /* 9 */, MCK_ImmSLC, AMFBS_isGFX8GFX9 },
80335 case MCK_ImmSLC: