reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

 5270   case MCK_ImmSDWASrc0Sel:
 6211   case MCK_ImmSDWASrc0Sel: {
10172   case MCK_ImmSDWASrc0Sel: return "MCK_ImmSDWASrc0Sel";
22797   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22798   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22799   { 13368 /* v_add_u16 */, AMDGPU::V_ADD_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22800   { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22803   { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22804   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22805   { 13489 /* v_ashrrev_i16 */, AMDGPU::V_ASHRREV_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22806   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22807   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22808   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22809   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22810   { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22811   { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22812   { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22813   { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22814   { 13839 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22815   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22816   { 13929 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22817   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22818   { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22819   { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22820   { 14103 /* v_cmp_f_i16 */, AMDGPU::V_CMP_F_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22821   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22822   { 14187 /* v_cmp_f_u16 */, AMDGPU::V_CMP_F_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22823   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22824   { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22825   { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22826   { 14361 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22827   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22828   { 14451 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22829   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22830   { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22831   { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22832   { 14631 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22833   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22834   { 14721 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22835   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22836   { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22837   { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22838   { 14901 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22839   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22840   { 14991 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22841   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22842   { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22843   { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22844   { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22845   { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22846   { 15261 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22847   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22848   { 15351 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22849   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22850   { 15441 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22851   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22852   { 15531 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22853   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22854   { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22855   { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22856   { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22857   { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22858   { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22859   { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22860   { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22861   { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22862   { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22863   { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22864   { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22865   { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22866   { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22867   { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22868   { 16281 /* v_cmp_t_i16 */, AMDGPU::V_CMP_T_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22869   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22870   { 16365 /* v_cmp_t_u16 */, AMDGPU::V_CMP_T_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22871   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22872   { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22873   { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22874   { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22875   { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22876   { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22877   { 18811 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22878   { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22879   { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22880   { 18983 /* v_cmpx_eq_i16 */, AMDGPU::V_CMPX_EQ_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22881   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22882   { 19079 /* v_cmpx_eq_u16 */, AMDGPU::V_CMPX_EQ_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22883   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22884   { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22885   { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22886   { 19265 /* v_cmpx_f_i16 */, AMDGPU::V_CMPX_F_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22887   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22888   { 19355 /* v_cmpx_f_u16 */, AMDGPU::V_CMPX_F_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22889   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22890   { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22891   { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22892   { 19541 /* v_cmpx_ge_i16 */, AMDGPU::V_CMPX_GE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22893   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22894   { 19637 /* v_cmpx_ge_u16 */, AMDGPU::V_CMPX_GE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22895   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22896   { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22897   { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22898   { 19829 /* v_cmpx_gt_i16 */, AMDGPU::V_CMPX_GT_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22899   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22900   { 19925 /* v_cmpx_gt_u16 */, AMDGPU::V_CMPX_GT_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22901   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22902   { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22903   { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22904   { 20117 /* v_cmpx_le_i16 */, AMDGPU::V_CMPX_LE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22905   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22906   { 20213 /* v_cmpx_le_u16 */, AMDGPU::V_CMPX_LE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22907   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22908   { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22909   { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22910   { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22911   { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22912   { 20501 /* v_cmpx_lt_i16 */, AMDGPU::V_CMPX_LT_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22913   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22914   { 20597 /* v_cmpx_lt_u16 */, AMDGPU::V_CMPX_LT_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22915   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22916   { 20693 /* v_cmpx_ne_i16 */, AMDGPU::V_CMPX_NE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22917   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22918   { 20789 /* v_cmpx_ne_u16 */, AMDGPU::V_CMPX_NE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22919   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22920   { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22921   { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22922   { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22923   { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22924   { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22925   { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22926   { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22927   { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22928   { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22929   { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22930   { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22931   { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22932   { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22933   { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22934   { 21587 /* v_cmpx_t_i16 */, AMDGPU::V_CMPX_T_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22935   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22936   { 21677 /* v_cmpx_t_u16 */, AMDGPU::V_CMPX_T_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22937   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22938   { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22939   { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22940   { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22941   { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22948   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2e, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22949   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22950   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22951   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22952   { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22953   { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22954   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22955   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22956   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22957   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22958   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22959   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22960   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22961   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22962   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22963   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22964   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_isGFX9Plus_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22965   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_isGFX9Plus_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22966   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22967   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22968   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22969   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22970   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22971   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22972   { 22919 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_isGFX7GFX8GFX9_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22973   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22974   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22975   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22976   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22977   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22978   { 23133 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasDLInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22979   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22980   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22981   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22982   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22983   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22984   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22985   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22986   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22987   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22988   { 23521 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_isGFX7GFX8GFX9_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22989   { 23589 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22990   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22991   { 23653 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22992   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22993   { 23695 /* v_mac_f16 */, AMDGPU::V_MAC_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22994   { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22995   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22996   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22997   { 24114 /* v_max_i16 */, AMDGPU::V_MAX_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22998   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22999   { 24151 /* v_max_u16 */, AMDGPU::V_MAX_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23000   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23001   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23002   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23003   { 24805 /* v_min_i16 */, AMDGPU::V_MIN_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23004   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23005   { 24842 /* v_min_u16 */, AMDGPU::V_MIN_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23006   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23007   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23008   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23009   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23010   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23011   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23012   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23013   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23014   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23015   { 25123 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23016   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23018   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23019   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23020   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23021   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23022   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23023   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23024   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23025   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23026   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23027   { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_isGFX9Plus_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23028   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23029   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23030   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23031   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23036   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23037   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23038   { 26080 /* v_sub_u16 */, AMDGPU::V_SUB_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23039   { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23042   { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23045   { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23050   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23051   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23052   { 26246 /* v_subrev_u16 */, AMDGPU::V_SUBREV_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23053   { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23054   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23055   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23056   { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasDLInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23057   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23063   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23064   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_sdwa_w64_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23065   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23068   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23069   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23070   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23071   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23072   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23073   { 13355 /* v_add_nc_u32 */, AMDGPU::V_ADD_NC_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23074   { 13368 /* v_add_u16 */, AMDGPU::V_ADD_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23075   { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23078   { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23079   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23080   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23081   { 13489 /* v_ashrrev_i16 */, AMDGPU::V_ASHRREV_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23082   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23083   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23084   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23085   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23086   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23087   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23088   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23089   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23090   { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23091   { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23092   { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23093   { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23094   { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23095   { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23096   { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23097   { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23098   { 13839 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23099   { 13839 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23100   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23101   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23102   { 13929 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23103   { 13929 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23104   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23105   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23106   { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23107   { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23108   { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23109   { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23110   { 14103 /* v_cmp_f_i16 */, AMDGPU::V_CMP_F_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23111   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23112   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23113   { 14187 /* v_cmp_f_u16 */, AMDGPU::V_CMP_F_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23114   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23115   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23116   { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23117   { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23118   { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23119   { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23120   { 14361 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23121   { 14361 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23122   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23123   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23124   { 14451 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23125   { 14451 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23126   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23127   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23128   { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23129   { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23130   { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23131   { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23132   { 14631 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23133   { 14631 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23134   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23135   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23136   { 14721 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23137   { 14721 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23138   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23139   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23140   { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23141   { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23142   { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23143   { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23144   { 14901 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23145   { 14901 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23146   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23147   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23148   { 14991 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23149   { 14991 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23150   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23151   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23152   { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23153   { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23154   { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23155   { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23156   { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23157   { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23158   { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23159   { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23160   { 15261 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23161   { 15261 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23162   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23163   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23164   { 15351 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23165   { 15351 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23166   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23167   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23168   { 15441 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23169   { 15441 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23170   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23171   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23172   { 15531 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23173   { 15531 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23174   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23175   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23176   { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23177   { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23178   { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23179   { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23180   { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23181   { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23182   { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23183   { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23184   { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23185   { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23186   { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23187   { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23188   { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23189   { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23190   { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23191   { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23192   { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23193   { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23194   { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23195   { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23196   { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23197   { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23198   { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23199   { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23200   { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23201   { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23202   { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23203   { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23204   { 16281 /* v_cmp_t_i16 */, AMDGPU::V_CMP_T_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23205   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23206   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23207   { 16365 /* v_cmp_t_u16 */, AMDGPU::V_CMP_T_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23208   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23209   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23210   { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23211   { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23212   { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23213   { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23214   { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23215   { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23216   { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23217   { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23218   { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23219   { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23220   { 18811 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23221   { 18811 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23222   { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23223   { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23224   { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23225   { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23226   { 18983 /* v_cmpx_eq_i16 */, AMDGPU::V_CMPX_EQ_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23227   { 18983 /* v_cmpx_eq_i16 */, AMDGPU::V_CMPX_EQ_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23228   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23229   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23230   { 19079 /* v_cmpx_eq_u16 */, AMDGPU::V_CMPX_EQ_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23231   { 19079 /* v_cmpx_eq_u16 */, AMDGPU::V_CMPX_EQ_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23232   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23233   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23234   { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23235   { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23236   { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23237   { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23238   { 19265 /* v_cmpx_f_i16 */, AMDGPU::V_CMPX_F_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23239   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23240   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23241   { 19355 /* v_cmpx_f_u16 */, AMDGPU::V_CMPX_F_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23242   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23243   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23244   { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23245   { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23246   { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23247   { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23248   { 19541 /* v_cmpx_ge_i16 */, AMDGPU::V_CMPX_GE_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23249   { 19541 /* v_cmpx_ge_i16 */, AMDGPU::V_CMPX_GE_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23250   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23251   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23252   { 19637 /* v_cmpx_ge_u16 */, AMDGPU::V_CMPX_GE_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23253   { 19637 /* v_cmpx_ge_u16 */, AMDGPU::V_CMPX_GE_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23254   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23255   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23256   { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23257   { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23258   { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23259   { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23260   { 19829 /* v_cmpx_gt_i16 */, AMDGPU::V_CMPX_GT_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23261   { 19829 /* v_cmpx_gt_i16 */, AMDGPU::V_CMPX_GT_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23262   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23263   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23264   { 19925 /* v_cmpx_gt_u16 */, AMDGPU::V_CMPX_GT_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23265   { 19925 /* v_cmpx_gt_u16 */, AMDGPU::V_CMPX_GT_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23266   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23267   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23268   { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23269   { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23270   { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23271   { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23272   { 20117 /* v_cmpx_le_i16 */, AMDGPU::V_CMPX_LE_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23273   { 20117 /* v_cmpx_le_i16 */, AMDGPU::V_CMPX_LE_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23274   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23275   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23276   { 20213 /* v_cmpx_le_u16 */, AMDGPU::V_CMPX_LE_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23277   { 20213 /* v_cmpx_le_u16 */, AMDGPU::V_CMPX_LE_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23278   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23279   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23280   { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23281   { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23282   { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23283   { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23284   { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23285   { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23286   { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23287   { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23288   { 20501 /* v_cmpx_lt_i16 */, AMDGPU::V_CMPX_LT_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23289   { 20501 /* v_cmpx_lt_i16 */, AMDGPU::V_CMPX_LT_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23290   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23291   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23292   { 20597 /* v_cmpx_lt_u16 */, AMDGPU::V_CMPX_LT_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23293   { 20597 /* v_cmpx_lt_u16 */, AMDGPU::V_CMPX_LT_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23294   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23295   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23296   { 20693 /* v_cmpx_ne_i16 */, AMDGPU::V_CMPX_NE_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23297   { 20693 /* v_cmpx_ne_i16 */, AMDGPU::V_CMPX_NE_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23298   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23299   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23300   { 20789 /* v_cmpx_ne_u16 */, AMDGPU::V_CMPX_NE_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23301   { 20789 /* v_cmpx_ne_u16 */, AMDGPU::V_CMPX_NE_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23302   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23303   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23304   { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23305   { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23306   { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23307   { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23308   { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23309   { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23310   { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23311   { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23312   { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23313   { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23314   { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23315   { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23316   { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23317   { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23318   { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23319   { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23320   { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23321   { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23322   { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23323   { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23324   { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23325   { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23326   { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23327   { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23328   { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23329   { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23330   { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23331   { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23332   { 21587 /* v_cmpx_t_i16 */, AMDGPU::V_CMPX_T_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23333   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23334   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23335   { 21677 /* v_cmpx_t_u16 */, AMDGPU::V_CMPX_T_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23336   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23337   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23338   { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23339   { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23340   { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23341   { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23342   { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23343   { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23344   { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA10_isGFX10Plus, { MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23345   { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA9_HasSDWA9, { MCK_BoolReg, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23352   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2e, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23353   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_w64_gfx10, ConvertCustom_cvtSdwaVOP2e, AMFBS_HasSDWA10_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23354   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2e, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23355   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2e, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23356   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23357   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23358   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23359   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23360   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23361   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23362   { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23363   { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23364   { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23365   { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23366   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23367   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23368   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23369   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23370   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23371   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23372   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23373   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23374   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23375   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23376   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23377   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23378   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23379   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23380   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23381   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23382   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23383   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23384   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23385   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23386   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23387   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23388   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23389   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23390   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23391   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23392   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23393   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23394   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23395   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23396   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23397   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23398   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23399   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23400   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23401   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23402   { 22919 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23403   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23404   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23405   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23406   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23407   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23408   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23409   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23410   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23411   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23412   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23413   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23414   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23415   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23416   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23417   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23418   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23419   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23420   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23421   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23422   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23423   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23424   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23425   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23426   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23427   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23428   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23429   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23430   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23431   { 23521 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23432   { 23589 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23433   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23434   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23435   { 23653 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23436   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23437   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23438   { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23439   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23440   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23441   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23442   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23443   { 24114 /* v_max_i16 */, AMDGPU::V_MAX_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23444   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23445   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23446   { 24151 /* v_max_u16 */, AMDGPU::V_MAX_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23447   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23448   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23449   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23450   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23451   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23452   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23453   { 24805 /* v_min_i16 */, AMDGPU::V_MIN_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23454   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23455   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23456   { 24842 /* v_min_u16 */, AMDGPU::V_MIN_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23457   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23458   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23459   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23460   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23461   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23462   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23463   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23464   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23465   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23466   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23467   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23468   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23469   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23470   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23471   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23472   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23473   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23474   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23475   { 25123 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23476   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23477   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23480   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23481   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23482   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23483   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23485   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23486   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23487   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23488   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23489   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23490   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23491   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23492   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23493   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23494   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23495   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23496   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23497   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23498   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23499   { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23500   { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23501   { 25879 /* v_screen_partition_4se_b32 */, AMDGPU::V_SCREEN_PARTITION_4SE_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23502   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23503   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23504   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23505   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23506   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23507   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23508   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23509   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23512   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23513   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_sdwa_w64_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23514   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23517   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23518   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23519   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23520   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23521   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23522   { 26067 /* v_sub_nc_u32 */, AMDGPU::V_SUB_NC_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23523   { 26080 /* v_sub_u16 */, AMDGPU::V_SUB_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23524   { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23527   { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23530   { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23533   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23534   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_sdwa_w64_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23535   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23538   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23539   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23540   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23541   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23542   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23543   { 26230 /* v_subrev_nc_u32 */, AMDGPU::V_SUBREV_NC_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23544   { 26246 /* v_subrev_u16 */, AMDGPU::V_SUBREV_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23545   { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23546   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23547   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23548   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23549   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23550   { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23551   { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasDLInsts_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23552   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23553   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
72864   { 13222 /* v_add_co_ci_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
72875   { 13222 /* v_add_co_ci_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus_isWave64 },
72886   { 13222 /* v_add_co_ci_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus_isWave32 },
72900   { 13238 /* v_add_co_u32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
72919   { 13251 /* v_add_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
72932   { 13251 /* v_add_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
72939   { 13251 /* v_add_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
72961   { 13261 /* v_add_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
72974   { 13261 /* v_add_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
72981   { 13261 /* v_add_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73010   { 13355 /* v_add_nc_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73020   { 13368 /* v_add_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73026   { 13368 /* v_add_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73043   { 13378 /* v_add_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
73049   { 13378 /* v_add_u32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA_isGFX8Only },
73061   { 13388 /* v_addc_co_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
73075   { 13402 /* v_addc_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA_isGFX8Only },
73092   { 13444 /* v_and_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73098   { 13444 /* v_and_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73104   { 13444 /* v_and_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73114   { 13489 /* v_ashrrev_i16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73120   { 13489 /* v_ashrrev_i16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73137   { 13503 /* v_ashrrev_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73143   { 13503 /* v_ashrrev_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73149   { 13503 /* v_ashrrev_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73161   { 13586 /* v_bfrev_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73166   { 13586 /* v_bfrev_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73171   { 13586 /* v_bfrev_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73189   { 13598 /* v_ceil_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73200   { 13598 /* v_ceil_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73206   { 13598 /* v_ceil_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73228   { 13609 /* v_ceil_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73239   { 13609 /* v_ceil_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73245   { 13609 /* v_ceil_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73269   { 13641 /* v_cmp_class_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73274   { 13641 /* v_cmp_class_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73279   { 13641 /* v_cmp_class_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73290   { 13677 /* v_cmp_class_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73295   { 13677 /* v_cmp_class_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73300   { 13677 /* v_cmp_class_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73316   { 13749 /* v_cmp_eq_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73320   { 13749 /* v_cmp_eq_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73324   { 13749 /* v_cmp_eq_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73337   { 13779 /* v_cmp_eq_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73341   { 13779 /* v_cmp_eq_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73345   { 13779 /* v_cmp_eq_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73360   { 13839 /* v_cmp_eq_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73364   { 13839 /* v_cmp_eq_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73368   { 13839 /* v_cmp_eq_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73375   { 13869 /* v_cmp_eq_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73379   { 13869 /* v_cmp_eq_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73383   { 13869 /* v_cmp_eq_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73392   { 13929 /* v_cmp_eq_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73396   { 13929 /* v_cmp_eq_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73400   { 13929 /* v_cmp_eq_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73407   { 13959 /* v_cmp_eq_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73411   { 13959 /* v_cmp_eq_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73415   { 13959 /* v_cmp_eq_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73428   { 14019 /* v_cmp_f_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73432   { 14019 /* v_cmp_f_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73436   { 14019 /* v_cmp_f_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73449   { 14047 /* v_cmp_f_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73453   { 14047 /* v_cmp_f_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73457   { 14047 /* v_cmp_f_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73471   { 14103 /* v_cmp_f_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73475   { 14103 /* v_cmp_f_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73482   { 14131 /* v_cmp_f_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73486   { 14131 /* v_cmp_f_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73490   { 14131 /* v_cmp_f_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73498   { 14187 /* v_cmp_f_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73502   { 14187 /* v_cmp_f_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73509   { 14215 /* v_cmp_f_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73513   { 14215 /* v_cmp_f_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73517   { 14215 /* v_cmp_f_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73530   { 14271 /* v_cmp_ge_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73534   { 14271 /* v_cmp_ge_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73538   { 14271 /* v_cmp_ge_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73551   { 14301 /* v_cmp_ge_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73555   { 14301 /* v_cmp_ge_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73559   { 14301 /* v_cmp_ge_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73574   { 14361 /* v_cmp_ge_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73578   { 14361 /* v_cmp_ge_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73582   { 14361 /* v_cmp_ge_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73589   { 14391 /* v_cmp_ge_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73593   { 14391 /* v_cmp_ge_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73597   { 14391 /* v_cmp_ge_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73606   { 14451 /* v_cmp_ge_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73610   { 14451 /* v_cmp_ge_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73614   { 14451 /* v_cmp_ge_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73621   { 14481 /* v_cmp_ge_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73625   { 14481 /* v_cmp_ge_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73629   { 14481 /* v_cmp_ge_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73642   { 14541 /* v_cmp_gt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73646   { 14541 /* v_cmp_gt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73650   { 14541 /* v_cmp_gt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73663   { 14571 /* v_cmp_gt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73667   { 14571 /* v_cmp_gt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73671   { 14571 /* v_cmp_gt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73686   { 14631 /* v_cmp_gt_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73690   { 14631 /* v_cmp_gt_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73694   { 14631 /* v_cmp_gt_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73701   { 14661 /* v_cmp_gt_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73705   { 14661 /* v_cmp_gt_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73709   { 14661 /* v_cmp_gt_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73718   { 14721 /* v_cmp_gt_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73722   { 14721 /* v_cmp_gt_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73726   { 14721 /* v_cmp_gt_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73733   { 14751 /* v_cmp_gt_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73737   { 14751 /* v_cmp_gt_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73741   { 14751 /* v_cmp_gt_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73754   { 14811 /* v_cmp_le_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73758   { 14811 /* v_cmp_le_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73762   { 14811 /* v_cmp_le_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73775   { 14841 /* v_cmp_le_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73779   { 14841 /* v_cmp_le_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73783   { 14841 /* v_cmp_le_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73798   { 14901 /* v_cmp_le_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73802   { 14901 /* v_cmp_le_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73806   { 14901 /* v_cmp_le_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73813   { 14931 /* v_cmp_le_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73817   { 14931 /* v_cmp_le_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73821   { 14931 /* v_cmp_le_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73830   { 14991 /* v_cmp_le_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73834   { 14991 /* v_cmp_le_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73838   { 14991 /* v_cmp_le_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73845   { 15021 /* v_cmp_le_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73849   { 15021 /* v_cmp_le_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73853   { 15021 /* v_cmp_le_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73866   { 15081 /* v_cmp_lg_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73870   { 15081 /* v_cmp_lg_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73874   { 15081 /* v_cmp_lg_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73887   { 15111 /* v_cmp_lg_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73891   { 15111 /* v_cmp_lg_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73895   { 15111 /* v_cmp_lg_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73914   { 15171 /* v_cmp_lt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73918   { 15171 /* v_cmp_lt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73922   { 15171 /* v_cmp_lt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73935   { 15201 /* v_cmp_lt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73939   { 15201 /* v_cmp_lt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73943   { 15201 /* v_cmp_lt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73958   { 15261 /* v_cmp_lt_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73962   { 15261 /* v_cmp_lt_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73966   { 15261 /* v_cmp_lt_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73973   { 15291 /* v_cmp_lt_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73977   { 15291 /* v_cmp_lt_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73981   { 15291 /* v_cmp_lt_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
73990   { 15351 /* v_cmp_lt_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
73994   { 15351 /* v_cmp_lt_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
73998   { 15351 /* v_cmp_lt_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74005   { 15381 /* v_cmp_lt_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74009   { 15381 /* v_cmp_lt_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74013   { 15381 /* v_cmp_lt_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74022   { 15441 /* v_cmp_ne_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74026   { 15441 /* v_cmp_ne_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74030   { 15441 /* v_cmp_ne_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74037   { 15471 /* v_cmp_ne_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74041   { 15471 /* v_cmp_ne_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74045   { 15471 /* v_cmp_ne_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74054   { 15531 /* v_cmp_ne_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74058   { 15531 /* v_cmp_ne_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74062   { 15531 /* v_cmp_ne_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74069   { 15561 /* v_cmp_ne_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74073   { 15561 /* v_cmp_ne_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74077   { 15561 /* v_cmp_ne_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74090   { 15621 /* v_cmp_neq_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74094   { 15621 /* v_cmp_neq_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74098   { 15621 /* v_cmp_neq_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74111   { 15653 /* v_cmp_neq_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74115   { 15653 /* v_cmp_neq_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74119   { 15653 /* v_cmp_neq_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74138   { 15717 /* v_cmp_nge_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74142   { 15717 /* v_cmp_nge_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74146   { 15717 /* v_cmp_nge_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74159   { 15749 /* v_cmp_nge_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74163   { 15749 /* v_cmp_nge_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74167   { 15749 /* v_cmp_nge_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74186   { 15813 /* v_cmp_ngt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74190   { 15813 /* v_cmp_ngt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74194   { 15813 /* v_cmp_ngt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74207   { 15845 /* v_cmp_ngt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74211   { 15845 /* v_cmp_ngt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74215   { 15845 /* v_cmp_ngt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74234   { 15909 /* v_cmp_nle_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74238   { 15909 /* v_cmp_nle_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74242   { 15909 /* v_cmp_nle_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74255   { 15941 /* v_cmp_nle_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74259   { 15941 /* v_cmp_nle_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74263   { 15941 /* v_cmp_nle_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74282   { 16005 /* v_cmp_nlg_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74286   { 16005 /* v_cmp_nlg_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74290   { 16005 /* v_cmp_nlg_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74303   { 16037 /* v_cmp_nlg_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74307   { 16037 /* v_cmp_nlg_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74311   { 16037 /* v_cmp_nlg_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74330   { 16101 /* v_cmp_nlt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74334   { 16101 /* v_cmp_nlt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74338   { 16101 /* v_cmp_nlt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74351   { 16133 /* v_cmp_nlt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74355   { 16133 /* v_cmp_nlt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74359   { 16133 /* v_cmp_nlt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74378   { 16197 /* v_cmp_o_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74382   { 16197 /* v_cmp_o_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74386   { 16197 /* v_cmp_o_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74399   { 16225 /* v_cmp_o_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74403   { 16225 /* v_cmp_o_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74407   { 16225 /* v_cmp_o_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74421   { 16281 /* v_cmp_t_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74425   { 16281 /* v_cmp_t_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74432   { 16309 /* v_cmp_t_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74436   { 16309 /* v_cmp_t_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74440   { 16309 /* v_cmp_t_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74448   { 16365 /* v_cmp_t_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74452   { 16365 /* v_cmp_t_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74459   { 16393 /* v_cmp_t_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74463   { 16393 /* v_cmp_t_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74467   { 16393 /* v_cmp_t_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74480   { 16449 /* v_cmp_tru_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74484   { 16449 /* v_cmp_tru_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74488   { 16449 /* v_cmp_tru_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74501   { 16481 /* v_cmp_tru_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74505   { 16481 /* v_cmp_tru_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74509   { 16481 /* v_cmp_tru_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74528   { 16545 /* v_cmp_u_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74532   { 16545 /* v_cmp_u_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74536   { 16545 /* v_cmp_u_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74549   { 16573 /* v_cmp_u_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74553   { 16573 /* v_cmp_u_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74557   { 16573 /* v_cmp_u_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74765   { 18773 /* v_cmpx_class_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74770   { 18773 /* v_cmpx_class_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74775   { 18773 /* v_cmpx_class_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74784   { 18811 /* v_cmpx_class_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74789   { 18811 /* v_cmpx_class_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74794   { 18811 /* v_cmpx_class_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74807   { 18887 /* v_cmpx_eq_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74811   { 18887 /* v_cmpx_eq_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74815   { 18887 /* v_cmpx_eq_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74826   { 18919 /* v_cmpx_eq_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74830   { 18919 /* v_cmpx_eq_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74834   { 18919 /* v_cmpx_eq_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74846   { 18983 /* v_cmpx_eq_i16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74850   { 18983 /* v_cmpx_eq_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74854   { 18983 /* v_cmpx_eq_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74859   { 19015 /* v_cmpx_eq_i32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74863   { 19015 /* v_cmpx_eq_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74867   { 19015 /* v_cmpx_eq_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74873   { 19079 /* v_cmpx_eq_u16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74877   { 19079 /* v_cmpx_eq_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74881   { 19079 /* v_cmpx_eq_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74886   { 19111 /* v_cmpx_eq_u32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74890   { 19111 /* v_cmpx_eq_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74894   { 19111 /* v_cmpx_eq_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74904   { 19175 /* v_cmpx_f_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74908   { 19175 /* v_cmpx_f_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74912   { 19175 /* v_cmpx_f_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74923   { 19205 /* v_cmpx_f_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74927   { 19205 /* v_cmpx_f_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74931   { 19205 /* v_cmpx_f_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74944   { 19265 /* v_cmpx_f_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74948   { 19265 /* v_cmpx_f_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74953   { 19295 /* v_cmpx_f_i32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74957   { 19295 /* v_cmpx_f_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74961   { 19295 /* v_cmpx_f_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74968   { 19355 /* v_cmpx_f_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74972   { 19355 /* v_cmpx_f_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74977   { 19385 /* v_cmpx_f_u32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74981   { 19385 /* v_cmpx_f_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
74985   { 19385 /* v_cmpx_f_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
74995   { 19445 /* v_cmpx_ge_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
74999   { 19445 /* v_cmpx_ge_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75003   { 19445 /* v_cmpx_ge_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75014   { 19477 /* v_cmpx_ge_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75018   { 19477 /* v_cmpx_ge_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75022   { 19477 /* v_cmpx_ge_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75034   { 19541 /* v_cmpx_ge_i16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75038   { 19541 /* v_cmpx_ge_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75042   { 19541 /* v_cmpx_ge_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75047   { 19573 /* v_cmpx_ge_i32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75051   { 19573 /* v_cmpx_ge_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75055   { 19573 /* v_cmpx_ge_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75061   { 19637 /* v_cmpx_ge_u16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75065   { 19637 /* v_cmpx_ge_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75069   { 19637 /* v_cmpx_ge_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75074   { 19669 /* v_cmpx_ge_u32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75078   { 19669 /* v_cmpx_ge_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75082   { 19669 /* v_cmpx_ge_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75092   { 19733 /* v_cmpx_gt_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75096   { 19733 /* v_cmpx_gt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75100   { 19733 /* v_cmpx_gt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75111   { 19765 /* v_cmpx_gt_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75115   { 19765 /* v_cmpx_gt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75119   { 19765 /* v_cmpx_gt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75131   { 19829 /* v_cmpx_gt_i16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75135   { 19829 /* v_cmpx_gt_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75139   { 19829 /* v_cmpx_gt_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75144   { 19861 /* v_cmpx_gt_i32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75148   { 19861 /* v_cmpx_gt_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75152   { 19861 /* v_cmpx_gt_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75158   { 19925 /* v_cmpx_gt_u16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75162   { 19925 /* v_cmpx_gt_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75166   { 19925 /* v_cmpx_gt_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75171   { 19957 /* v_cmpx_gt_u32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75175   { 19957 /* v_cmpx_gt_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75179   { 19957 /* v_cmpx_gt_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75189   { 20021 /* v_cmpx_le_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75193   { 20021 /* v_cmpx_le_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75197   { 20021 /* v_cmpx_le_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75208   { 20053 /* v_cmpx_le_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75212   { 20053 /* v_cmpx_le_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75216   { 20053 /* v_cmpx_le_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75228   { 20117 /* v_cmpx_le_i16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75232   { 20117 /* v_cmpx_le_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75236   { 20117 /* v_cmpx_le_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75241   { 20149 /* v_cmpx_le_i32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75245   { 20149 /* v_cmpx_le_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75249   { 20149 /* v_cmpx_le_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75255   { 20213 /* v_cmpx_le_u16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75259   { 20213 /* v_cmpx_le_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75263   { 20213 /* v_cmpx_le_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75268   { 20245 /* v_cmpx_le_u32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75272   { 20245 /* v_cmpx_le_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75276   { 20245 /* v_cmpx_le_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75286   { 20309 /* v_cmpx_lg_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75290   { 20309 /* v_cmpx_lg_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75294   { 20309 /* v_cmpx_lg_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75305   { 20341 /* v_cmpx_lg_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75309   { 20341 /* v_cmpx_lg_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75313   { 20341 /* v_cmpx_lg_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75329   { 20405 /* v_cmpx_lt_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75333   { 20405 /* v_cmpx_lt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75337   { 20405 /* v_cmpx_lt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75348   { 20437 /* v_cmpx_lt_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75352   { 20437 /* v_cmpx_lt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75356   { 20437 /* v_cmpx_lt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75368   { 20501 /* v_cmpx_lt_i16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75372   { 20501 /* v_cmpx_lt_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75376   { 20501 /* v_cmpx_lt_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75381   { 20533 /* v_cmpx_lt_i32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75385   { 20533 /* v_cmpx_lt_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75389   { 20533 /* v_cmpx_lt_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75395   { 20597 /* v_cmpx_lt_u16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75399   { 20597 /* v_cmpx_lt_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75403   { 20597 /* v_cmpx_lt_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75408   { 20629 /* v_cmpx_lt_u32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75412   { 20629 /* v_cmpx_lt_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75416   { 20629 /* v_cmpx_lt_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75422   { 20693 /* v_cmpx_ne_i16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75426   { 20693 /* v_cmpx_ne_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75430   { 20693 /* v_cmpx_ne_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75435   { 20725 /* v_cmpx_ne_i32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75439   { 20725 /* v_cmpx_ne_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75443   { 20725 /* v_cmpx_ne_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75449   { 20789 /* v_cmpx_ne_u16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75453   { 20789 /* v_cmpx_ne_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75457   { 20789 /* v_cmpx_ne_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75462   { 20821 /* v_cmpx_ne_u32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75466   { 20821 /* v_cmpx_ne_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75470   { 20821 /* v_cmpx_ne_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75480   { 20885 /* v_cmpx_neq_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75484   { 20885 /* v_cmpx_neq_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75488   { 20885 /* v_cmpx_neq_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75499   { 20919 /* v_cmpx_neq_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75503   { 20919 /* v_cmpx_neq_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75507   { 20919 /* v_cmpx_neq_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75523   { 20987 /* v_cmpx_nge_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75527   { 20987 /* v_cmpx_nge_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75531   { 20987 /* v_cmpx_nge_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75542   { 21021 /* v_cmpx_nge_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75546   { 21021 /* v_cmpx_nge_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75550   { 21021 /* v_cmpx_nge_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75566   { 21089 /* v_cmpx_ngt_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75570   { 21089 /* v_cmpx_ngt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75574   { 21089 /* v_cmpx_ngt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75585   { 21123 /* v_cmpx_ngt_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75589   { 21123 /* v_cmpx_ngt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75593   { 21123 /* v_cmpx_ngt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75609   { 21191 /* v_cmpx_nle_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75613   { 21191 /* v_cmpx_nle_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75617   { 21191 /* v_cmpx_nle_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75628   { 21225 /* v_cmpx_nle_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75632   { 21225 /* v_cmpx_nle_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75636   { 21225 /* v_cmpx_nle_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75652   { 21293 /* v_cmpx_nlg_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75656   { 21293 /* v_cmpx_nlg_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75660   { 21293 /* v_cmpx_nlg_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75671   { 21327 /* v_cmpx_nlg_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75675   { 21327 /* v_cmpx_nlg_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75679   { 21327 /* v_cmpx_nlg_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75695   { 21395 /* v_cmpx_nlt_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75699   { 21395 /* v_cmpx_nlt_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75703   { 21395 /* v_cmpx_nlt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75714   { 21429 /* v_cmpx_nlt_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75718   { 21429 /* v_cmpx_nlt_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75722   { 21429 /* v_cmpx_nlt_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75738   { 21497 /* v_cmpx_o_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75742   { 21497 /* v_cmpx_o_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75746   { 21497 /* v_cmpx_o_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75757   { 21527 /* v_cmpx_o_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75761   { 21527 /* v_cmpx_o_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75765   { 21527 /* v_cmpx_o_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75778   { 21587 /* v_cmpx_t_i16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75782   { 21587 /* v_cmpx_t_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75787   { 21617 /* v_cmpx_t_i32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75791   { 21617 /* v_cmpx_t_i32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75795   { 21617 /* v_cmpx_t_i32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75802   { 21677 /* v_cmpx_t_u16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75806   { 21677 /* v_cmpx_t_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75811   { 21707 /* v_cmpx_t_u32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75815   { 21707 /* v_cmpx_t_u32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75819   { 21707 /* v_cmpx_t_u32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75829   { 21767 /* v_cmpx_tru_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75833   { 21767 /* v_cmpx_tru_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75837   { 21767 /* v_cmpx_tru_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75848   { 21801 /* v_cmpx_tru_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75852   { 21801 /* v_cmpx_tru_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75856   { 21801 /* v_cmpx_tru_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75872   { 21869 /* v_cmpx_u_f16 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75876   { 21869 /* v_cmpx_u_f16 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75880   { 21869 /* v_cmpx_u_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75891   { 21899 /* v_cmpx_u_f32 */, 4 /* 2 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75895   { 21899 /* v_cmpx_u_f32 */, 8 /* 3 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75899   { 21899 /* v_cmpx_u_f32 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75933   { 21959 /* v_cndmask_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75949   { 21959 /* v_cndmask_b32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus_isWave64 },
75955   { 21959 /* v_cndmask_b32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
75961   { 21959 /* v_cndmask_b32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
75967   { 21959 /* v_cndmask_b32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus_isWave32 },
75981   { 21973 /* v_cos_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75992   { 21973 /* v_cos_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
75998   { 21973 /* v_cos_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76020   { 21983 /* v_cos_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76031   { 21983 /* v_cos_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76037   { 21983 /* v_cos_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76095   { 22045 /* v_cvt_f16_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76106   { 22045 /* v_cvt_f16_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76112   { 22045 /* v_cvt_f16_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76133   { 22059 /* v_cvt_f16_i16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
76144   { 22059 /* v_cvt_f16_i16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76150   { 22059 /* v_cvt_f16_i16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76165   { 22073 /* v_cvt_f16_u16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
76176   { 22073 /* v_cvt_f16_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76182   { 22073 /* v_cvt_f16_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76198   { 22087 /* v_cvt_f32_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76209   { 22087 /* v_cvt_f32_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76215   { 22087 /* v_cvt_f32_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76247   { 22115 /* v_cvt_f32_i32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76258   { 22115 /* v_cvt_f32_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76264   { 22115 /* v_cvt_f32_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76281   { 22129 /* v_cvt_f32_u32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76292   { 22129 /* v_cvt_f32_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76298   { 22129 /* v_cvt_f32_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76315   { 22143 /* v_cvt_f32_ubyte0 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76326   { 22143 /* v_cvt_f32_ubyte0 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76332   { 22143 /* v_cvt_f32_ubyte0 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76349   { 22160 /* v_cvt_f32_ubyte1 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76360   { 22160 /* v_cvt_f32_ubyte1 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76366   { 22160 /* v_cvt_f32_ubyte1 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76383   { 22177 /* v_cvt_f32_ubyte2 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76394   { 22177 /* v_cvt_f32_ubyte2 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76400   { 22177 /* v_cvt_f32_ubyte2 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76417   { 22194 /* v_cvt_f32_ubyte3 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76428   { 22194 /* v_cvt_f32_ubyte3 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76434   { 22194 /* v_cvt_f32_ubyte3 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76468   { 22253 /* v_cvt_flr_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76473   { 22253 /* v_cvt_flr_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76478   { 22253 /* v_cvt_flr_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76500   { 22271 /* v_cvt_i16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
76505   { 22271 /* v_cvt_i16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76510   { 22271 /* v_cvt_i16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76534   { 22285 /* v_cvt_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76539   { 22285 /* v_cvt_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76544   { 22285 /* v_cvt_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76572   { 22313 /* v_cvt_norm_i16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_isGFX9Plus_HasSDWA },
76577   { 22313 /* v_cvt_norm_i16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76582   { 22313 /* v_cvt_norm_i16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76604   { 22332 /* v_cvt_norm_u16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_isGFX9Plus_HasSDWA },
76609   { 22332 /* v_cvt_norm_u16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76614   { 22332 /* v_cvt_norm_u16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76642   { 22351 /* v_cvt_off_f32_i4 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76653   { 22351 /* v_cvt_off_f32_i4 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76659   { 22351 /* v_cvt_off_f32_i4 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76720   { 22543 /* v_cvt_rpi_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76725   { 22543 /* v_cvt_rpi_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76730   { 22543 /* v_cvt_rpi_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76752   { 22561 /* v_cvt_u16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
76757   { 22561 /* v_cvt_u16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76762   { 22561 /* v_cvt_u16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76786   { 22575 /* v_cvt_u32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
76791   { 22575 /* v_cvt_u32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
76796   { 22575 /* v_cvt_u32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
76986   { 22899 /* v_exp_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
76997   { 22899 /* v_exp_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77003   { 22899 /* v_exp_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77025   { 22909 /* v_exp_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77036   { 22909 /* v_exp_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77042   { 22909 /* v_exp_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77059   { 22919 /* v_exp_legacy_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_isGFX7GFX8GFX9_HasSDWA },
77070   { 22919 /* v_exp_legacy_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77081   { 22936 /* v_ffbh_i32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77086   { 22936 /* v_ffbh_i32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77091   { 22936 /* v_ffbh_i32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77107   { 22947 /* v_ffbh_u32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77112   { 22947 /* v_ffbh_u32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77117   { 22947 /* v_ffbh_u32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77133   { 22958 /* v_ffbl_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77138   { 22958 /* v_ffbl_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77143   { 22958 /* v_ffbl_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77161   { 22969 /* v_floor_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
77172   { 22969 /* v_floor_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77178   { 22969 /* v_floor_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77200   { 22981 /* v_floor_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77211   { 22981 /* v_floor_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77217   { 22981 /* v_floor_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77317   { 23133 /* v_fmac_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasDLInsts_HasSDWA },
77339   { 23168 /* v_fract_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
77350   { 23168 /* v_fract_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77356   { 23168 /* v_fract_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77378   { 23180 /* v_fract_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77389   { 23180 /* v_fract_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77395   { 23180 /* v_fract_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77421   { 23204 /* v_frexp_exp_i16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
77426   { 23204 /* v_frexp_exp_i16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77431   { 23204 /* v_frexp_exp_i16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77455   { 23224 /* v_frexp_exp_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77460   { 23224 /* v_frexp_exp_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77465   { 23224 /* v_frexp_exp_i32_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77495   { 23264 /* v_frexp_mant_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
77506   { 23264 /* v_frexp_mant_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77512   { 23264 /* v_frexp_mant_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77534   { 23281 /* v_frexp_mant_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77545   { 23281 /* v_frexp_mant_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77551   { 23281 /* v_frexp_mant_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77665   { 23439 /* v_ldexp_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
77680   { 23439 /* v_ldexp_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77688   { 23439 /* v_ldexp_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77729   { 23501 /* v_log_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
77740   { 23501 /* v_log_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77746   { 23501 /* v_log_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77768   { 23511 /* v_log_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77779   { 23511 /* v_log_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77785   { 23511 /* v_log_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77802   { 23521 /* v_log_legacy_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_isGFX7GFX8GFX9_HasSDWA },
77813   { 23521 /* v_log_legacy_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77822   { 23589 /* v_lshlrev_b16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
77828   { 23589 /* v_lshlrev_b16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77845   { 23603 /* v_lshlrev_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77851   { 23603 /* v_lshlrev_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77857   { 23603 /* v_lshlrev_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77867   { 23653 /* v_lshrrev_b16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
77873   { 23653 /* v_lshrrev_b16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77890   { 23667 /* v_lshrrev_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77896   { 23667 /* v_lshrrev_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
77902   { 23667 /* v_lshrrev_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
77916   { 23695 /* v_mac_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
77938   { 23705 /* v_mac_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
77965   { 23715 /* v_mac_legacy_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78092   { 24084 /* v_max_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
78105   { 24084 /* v_max_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78112   { 24084 /* v_max_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78134   { 24094 /* v_max_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78147   { 24094 /* v_max_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78154   { 24094 /* v_max_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78173   { 24114 /* v_max_i16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
78179   { 24114 /* v_max_i16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78196   { 24124 /* v_max_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78202   { 24124 /* v_max_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78208   { 24124 /* v_max_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78221   { 24151 /* v_max_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
78227   { 24151 /* v_max_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78244   { 24161 /* v_max_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78250   { 24161 /* v_max_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78256   { 24161 /* v_max_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78381   { 24775 /* v_min_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
78394   { 24775 /* v_min_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78401   { 24775 /* v_min_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78423   { 24785 /* v_min_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78436   { 24785 /* v_min_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78443   { 24785 /* v_min_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78462   { 24805 /* v_min_i16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
78468   { 24805 /* v_min_i16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78485   { 24815 /* v_min_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78491   { 24815 /* v_min_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78497   { 24815 /* v_min_i32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78510   { 24842 /* v_min_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
78516   { 24842 /* v_min_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78533   { 24852 /* v_min_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78539   { 24852 /* v_min_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78545   { 24852 /* v_min_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78557   { 24862 /* v_mov_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78562   { 24862 /* v_mov_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78567   { 24862 /* v_mov_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78583   { 24872 /* v_mov_fed_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78588   { 24872 /* v_mov_fed_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78593   { 24872 /* v_mov_fed_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78625   { 24989 /* v_mul_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
78638   { 24989 /* v_mul_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78645   { 24989 /* v_mul_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78667   { 24999 /* v_mul_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78680   { 24999 /* v_mul_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78687   { 24999 /* v_mul_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78713   { 25032 /* v_mul_hi_i32_i24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78719   { 25032 /* v_mul_hi_i32_i24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78725   { 25032 /* v_mul_hi_i32_i24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78742   { 25062 /* v_mul_hi_u32_u24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78748   { 25062 /* v_mul_hi_u32_u24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78754   { 25062 /* v_mul_hi_u32_u24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78771   { 25079 /* v_mul_i32_i24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78777   { 25079 /* v_mul_i32_i24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78783   { 25079 /* v_mul_i32_i24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78805   { 25093 /* v_mul_legacy_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78818   { 25093 /* v_mul_legacy_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78825   { 25093 /* v_mul_legacy_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78835   { 25123 /* v_mul_lo_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
78841   { 25123 /* v_mul_lo_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78858   { 25149 /* v_mul_u32_u24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78864   { 25149 /* v_mul_u32_u24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78870   { 25149 /* v_mul_u32_u24 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78888   { 25182 /* v_not_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78893   { 25182 /* v_not_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78898   { 25182 /* v_not_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
78919   { 25202 /* v_or_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
78925   { 25202 /* v_or_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
78931   { 25202 /* v_or_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79152   { 25609 /* v_rcp_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
79163   { 25609 /* v_rcp_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79169   { 25609 /* v_rcp_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79191   { 25619 /* v_rcp_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
79202   { 25619 /* v_rcp_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79208   { 25619 /* v_rcp_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79239   { 25639 /* v_rcp_iflag_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
79250   { 25639 /* v_rcp_iflag_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79256   { 25639 /* v_rcp_iflag_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79278   { 25707 /* v_rndne_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
79289   { 25707 /* v_rndne_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79295   { 25707 /* v_rndne_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79317   { 25719 /* v_rndne_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
79328   { 25719 /* v_rndne_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79334   { 25719 /* v_rndne_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79368   { 25775 /* v_rsq_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
79379   { 25775 /* v_rsq_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79385   { 25775 /* v_rsq_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79407   { 25785 /* v_rsq_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
79418   { 25785 /* v_rsq_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79424   { 25785 /* v_rsq_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79465   { 25863 /* v_sat_pk_u8_i16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_isGFX9Plus_HasSDWA },
79470   { 25863 /* v_sat_pk_u8_i16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79475   { 25863 /* v_sat_pk_u8_i16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79489   { 25879 /* v_screen_partition_4se_b32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79502   { 25906 /* v_sin_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
79513   { 25906 /* v_sin_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79519   { 25906 /* v_sin_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79541   { 25916 /* v_sin_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
79552   { 25916 /* v_sin_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79558   { 25916 /* v_sin_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79577   { 25926 /* v_sqrt_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
79588   { 25926 /* v_sqrt_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79594   { 25926 /* v_sqrt_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79616   { 25937 /* v_sqrt_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
79627   { 25937 /* v_sqrt_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79633   { 25937 /* v_sqrt_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79666   { 25959 /* v_sub_co_ci_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79677   { 25959 /* v_sub_co_ci_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus_isWave64 },
79688   { 25959 /* v_sub_co_ci_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus_isWave32 },
79702   { 25975 /* v_sub_co_u32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79721   { 25988 /* v_sub_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
79734   { 25988 /* v_sub_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79741   { 25988 /* v_sub_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79763   { 25998 /* v_sub_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
79776   { 25998 /* v_sub_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79783   { 25998 /* v_sub_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79803   { 26067 /* v_sub_nc_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79813   { 26080 /* v_sub_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
79819   { 26080 /* v_sub_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
79836   { 26090 /* v_sub_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79842   { 26090 /* v_sub_u32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA_isGFX8Only },
79854   { 26100 /* v_subb_co_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79868   { 26114 /* v_subb_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA_isGFX8Only },
79880   { 26125 /* v_subbrev_co_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79894   { 26142 /* v_subbrev_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA_isGFX8Only },
79913   { 26156 /* v_subrev_co_ci_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79924   { 26156 /* v_subrev_co_ci_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus_isWave64 },
79935   { 26156 /* v_subrev_co_ci_u32 */, 256 /* 8 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus_isWave32 },
79949   { 26175 /* v_subrev_co_u32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79968   { 26191 /* v_subrev_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
79981   { 26191 /* v_subrev_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
79988   { 26191 /* v_subrev_f16 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
80010   { 26204 /* v_subrev_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
80023   { 26204 /* v_subrev_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
80030   { 26204 /* v_subrev_f32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
80046   { 26230 /* v_subrev_nc_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
80056   { 26246 /* v_subrev_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
80062   { 26246 /* v_subrev_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
80079   { 26259 /* v_subrev_u32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
80085   { 26259 /* v_subrev_u32 */, 128 /* 7 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA_isGFX8Only },
80111   { 26314 /* v_trunc_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
80122   { 26314 /* v_trunc_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
80128   { 26314 /* v_trunc_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
80150   { 26326 /* v_trunc_f32 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
80161   { 26326 /* v_trunc_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
80167   { 26326 /* v_trunc_f32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
80198   { 26376 /* v_xnor_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasDLInsts_HasSDWA },
80204   { 26376 /* v_xnor_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
80210   { 26376 /* v_xnor_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasDLInsts_HasSDWA9 },
80227   { 26398 /* v_xor_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA_HasSDWA },
80233   { 26398 /* v_xor_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA10_isGFX10Plus },
80239   { 26398 /* v_xor_b32 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_HasSDWA9_HasSDWA9 },
80375   case MCK_ImmSDWASrc0Sel: