reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

 5267   case MCK_ImmSDWADstSel:
 6204   case MCK_ImmSDWADstSel: {
10171   case MCK_ImmSDWADstSel: return "MCK_ImmSDWADstSel";
22797   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22798   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22799   { 13368 /* v_add_u16 */, AMDGPU::V_ADD_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22800   { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22803   { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22804   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22805   { 13489 /* v_ashrrev_i16 */, AMDGPU::V_ASHRREV_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22806   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22807   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22808   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22809   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22948   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2e, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22949   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22950   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22951   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22952   { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22953   { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22954   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22955   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22956   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22957   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22958   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22959   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22960   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22961   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22962   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22963   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22964   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_isGFX9Plus_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22965   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_isGFX9Plus_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22966   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22967   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22968   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22969   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22970   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22971   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22972   { 22919 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_isGFX7GFX8GFX9_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22973   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22974   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22975   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22976   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22977   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22978   { 23133 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasDLInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22979   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22980   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22981   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22982   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22983   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22984   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22985   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22986   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22987   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22988   { 23521 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_isGFX7GFX8GFX9_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22989   { 23589 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22990   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22991   { 23653 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22992   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22993   { 23695 /* v_mac_f16 */, AMDGPU::V_MAC_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22994   { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22995   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22996   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22997   { 24114 /* v_max_i16 */, AMDGPU::V_MAX_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22998   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22999   { 24151 /* v_max_u16 */, AMDGPU::V_MAX_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23000   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23001   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23002   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23003   { 24805 /* v_min_i16 */, AMDGPU::V_MIN_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23004   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23005   { 24842 /* v_min_u16 */, AMDGPU::V_MIN_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23006   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23007   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23008   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23009   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23010   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23011   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23012   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23013   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23014   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23015   { 25123 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23016   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23018   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23019   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23020   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23021   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23022   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23023   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23024   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23025   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23026   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23027   { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_isGFX9Plus_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23028   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23029   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23030   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23031   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23036   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23037   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23038   { 26080 /* v_sub_u16 */, AMDGPU::V_SUB_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23039   { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23042   { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23045   { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23050   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23051   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23052   { 26246 /* v_subrev_u16 */, AMDGPU::V_SUBREV_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23053   { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23054   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23055   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23056   { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasDLInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23057   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23063   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23064   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_sdwa_w64_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23065   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23068   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23069   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23070   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23071   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23072   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23073   { 13355 /* v_add_nc_u32 */, AMDGPU::V_ADD_NC_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23074   { 13368 /* v_add_u16 */, AMDGPU::V_ADD_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23075   { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23078   { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23079   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23080   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23081   { 13489 /* v_ashrrev_i16 */, AMDGPU::V_ASHRREV_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23082   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23083   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23084   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23085   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23086   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23087   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23088   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23089   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23352   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2e, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23353   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_w64_gfx10, ConvertCustom_cvtSdwaVOP2e, AMFBS_HasSDWA10_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23354   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2e, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23355   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2e, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23356   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23357   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23358   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23359   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23360   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23361   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23362   { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23363   { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23364   { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23365   { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23366   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23367   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23368   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23369   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23370   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23371   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23372   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23373   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23374   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23375   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23376   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23377   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23378   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23379   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23380   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23381   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23382   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23383   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23384   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23385   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23386   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23387   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23388   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23389   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23390   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23391   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23392   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23393   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23394   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23395   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23396   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23397   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23398   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23399   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23400   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23401   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23402   { 22919 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23403   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23404   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23405   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23406   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23407   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23408   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23409   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23410   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23411   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23412   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23413   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23414   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23415   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23416   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23417   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23418   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23419   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23420   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23421   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23422   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23423   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23424   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23425   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23426   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23427   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23428   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23429   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23430   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23431   { 23521 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23432   { 23589 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23433   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23434   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23435   { 23653 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23436   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23437   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23438   { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23439   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23440   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23441   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23442   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23443   { 24114 /* v_max_i16 */, AMDGPU::V_MAX_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23444   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23445   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23446   { 24151 /* v_max_u16 */, AMDGPU::V_MAX_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23447   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23448   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23449   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23450   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23451   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23452   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23453   { 24805 /* v_min_i16 */, AMDGPU::V_MIN_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23454   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23455   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23456   { 24842 /* v_min_u16 */, AMDGPU::V_MIN_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23457   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23458   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23459   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23460   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23461   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23462   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23463   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23464   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23465   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23466   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23467   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23468   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23469   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23470   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23471   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23472   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23473   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23474   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23475   { 25123 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23476   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23477   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23480   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23481   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23482   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23483   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23485   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23486   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23487   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23488   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23489   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23490   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23491   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23492   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23493   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23494   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23495   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23496   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23497   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23498   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23499   { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23500   { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23501   { 25879 /* v_screen_partition_4se_b32 */, AMDGPU::V_SCREEN_PARTITION_4SE_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23502   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23503   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23504   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23505   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23506   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23507   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23508   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23509   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23512   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23513   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_sdwa_w64_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23514   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23517   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23518   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23519   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23520   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23521   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23522   { 26067 /* v_sub_nc_u32 */, AMDGPU::V_SUB_NC_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23523   { 26080 /* v_sub_u16 */, AMDGPU::V_SUB_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23524   { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23527   { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23530   { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23533   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23534   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_sdwa_w64_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23535   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23538   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23539   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23540   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23541   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23542   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23543   { 26230 /* v_subrev_nc_u32 */, AMDGPU::V_SUBREV_NC_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23544   { 26246 /* v_subrev_u16 */, AMDGPU::V_SUBREV_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23545   { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23546   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23547   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23548   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23549   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23550   { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23551   { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasDLInsts_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23552   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23553   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
72863   { 13222 /* v_add_co_ci_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
72874   { 13222 /* v_add_co_ci_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus_isWave64 },
72885   { 13222 /* v_add_co_ci_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus_isWave32 },
72899   { 13238 /* v_add_co_u32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
72918   { 13251 /* v_add_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
72931   { 13251 /* v_add_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
72938   { 13251 /* v_add_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
72960   { 13261 /* v_add_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
72973   { 13261 /* v_add_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
72980   { 13261 /* v_add_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
73009   { 13355 /* v_add_nc_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
73019   { 13368 /* v_add_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
73025   { 13368 /* v_add_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
73042   { 13378 /* v_add_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
73048   { 13378 /* v_add_u32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA_isGFX8Only },
73060   { 13388 /* v_addc_co_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
73074   { 13402 /* v_addc_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA_isGFX8Only },
73091   { 13444 /* v_and_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
73097   { 13444 /* v_and_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
73103   { 13444 /* v_and_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
73113   { 13489 /* v_ashrrev_i16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
73119   { 13489 /* v_ashrrev_i16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
73136   { 13503 /* v_ashrrev_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
73142   { 13503 /* v_ashrrev_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
73148   { 13503 /* v_ashrrev_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
73160   { 13586 /* v_bfrev_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
73165   { 13586 /* v_bfrev_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
73170   { 13586 /* v_bfrev_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
73188   { 13598 /* v_ceil_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
73199   { 13598 /* v_ceil_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
73205   { 13598 /* v_ceil_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
73227   { 13609 /* v_ceil_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
73238   { 13609 /* v_ceil_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
73244   { 13609 /* v_ceil_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
75932   { 21959 /* v_cndmask_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
75948   { 21959 /* v_cndmask_b32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus_isWave64 },
75954   { 21959 /* v_cndmask_b32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
75960   { 21959 /* v_cndmask_b32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
75966   { 21959 /* v_cndmask_b32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus_isWave32 },
75980   { 21973 /* v_cos_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
75991   { 21973 /* v_cos_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
75997   { 21973 /* v_cos_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76019   { 21983 /* v_cos_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76030   { 21983 /* v_cos_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76036   { 21983 /* v_cos_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76094   { 22045 /* v_cvt_f16_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76105   { 22045 /* v_cvt_f16_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76111   { 22045 /* v_cvt_f16_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76132   { 22059 /* v_cvt_f16_i16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
76143   { 22059 /* v_cvt_f16_i16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76149   { 22059 /* v_cvt_f16_i16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76164   { 22073 /* v_cvt_f16_u16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
76175   { 22073 /* v_cvt_f16_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76181   { 22073 /* v_cvt_f16_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76197   { 22087 /* v_cvt_f32_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76208   { 22087 /* v_cvt_f32_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76214   { 22087 /* v_cvt_f32_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76246   { 22115 /* v_cvt_f32_i32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76257   { 22115 /* v_cvt_f32_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76263   { 22115 /* v_cvt_f32_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76280   { 22129 /* v_cvt_f32_u32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76291   { 22129 /* v_cvt_f32_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76297   { 22129 /* v_cvt_f32_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76314   { 22143 /* v_cvt_f32_ubyte0 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76325   { 22143 /* v_cvt_f32_ubyte0 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76331   { 22143 /* v_cvt_f32_ubyte0 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76348   { 22160 /* v_cvt_f32_ubyte1 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76359   { 22160 /* v_cvt_f32_ubyte1 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76365   { 22160 /* v_cvt_f32_ubyte1 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76382   { 22177 /* v_cvt_f32_ubyte2 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76393   { 22177 /* v_cvt_f32_ubyte2 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76399   { 22177 /* v_cvt_f32_ubyte2 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76416   { 22194 /* v_cvt_f32_ubyte3 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76427   { 22194 /* v_cvt_f32_ubyte3 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76433   { 22194 /* v_cvt_f32_ubyte3 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76467   { 22253 /* v_cvt_flr_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76472   { 22253 /* v_cvt_flr_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76477   { 22253 /* v_cvt_flr_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76499   { 22271 /* v_cvt_i16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
76504   { 22271 /* v_cvt_i16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76509   { 22271 /* v_cvt_i16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76533   { 22285 /* v_cvt_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76538   { 22285 /* v_cvt_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76543   { 22285 /* v_cvt_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76571   { 22313 /* v_cvt_norm_i16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_isGFX9Plus_HasSDWA },
76576   { 22313 /* v_cvt_norm_i16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76581   { 22313 /* v_cvt_norm_i16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76603   { 22332 /* v_cvt_norm_u16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_isGFX9Plus_HasSDWA },
76608   { 22332 /* v_cvt_norm_u16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76613   { 22332 /* v_cvt_norm_u16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76641   { 22351 /* v_cvt_off_f32_i4 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76652   { 22351 /* v_cvt_off_f32_i4 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76658   { 22351 /* v_cvt_off_f32_i4 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76719   { 22543 /* v_cvt_rpi_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76724   { 22543 /* v_cvt_rpi_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76729   { 22543 /* v_cvt_rpi_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76751   { 22561 /* v_cvt_u16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
76756   { 22561 /* v_cvt_u16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76761   { 22561 /* v_cvt_u16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76785   { 22575 /* v_cvt_u32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
76790   { 22575 /* v_cvt_u32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
76795   { 22575 /* v_cvt_u32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
76985   { 22899 /* v_exp_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
76996   { 22899 /* v_exp_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77002   { 22899 /* v_exp_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77024   { 22909 /* v_exp_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77035   { 22909 /* v_exp_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77041   { 22909 /* v_exp_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77058   { 22919 /* v_exp_legacy_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_isGFX7GFX8GFX9_HasSDWA },
77069   { 22919 /* v_exp_legacy_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77080   { 22936 /* v_ffbh_i32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77085   { 22936 /* v_ffbh_i32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77090   { 22936 /* v_ffbh_i32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77106   { 22947 /* v_ffbh_u32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77111   { 22947 /* v_ffbh_u32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77116   { 22947 /* v_ffbh_u32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77132   { 22958 /* v_ffbl_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77137   { 22958 /* v_ffbl_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77142   { 22958 /* v_ffbl_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77160   { 22969 /* v_floor_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
77171   { 22969 /* v_floor_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77177   { 22969 /* v_floor_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77199   { 22981 /* v_floor_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77210   { 22981 /* v_floor_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77216   { 22981 /* v_floor_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77316   { 23133 /* v_fmac_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasDLInsts_HasSDWA },
77338   { 23168 /* v_fract_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
77349   { 23168 /* v_fract_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77355   { 23168 /* v_fract_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77377   { 23180 /* v_fract_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77388   { 23180 /* v_fract_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77394   { 23180 /* v_fract_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77420   { 23204 /* v_frexp_exp_i16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
77425   { 23204 /* v_frexp_exp_i16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77430   { 23204 /* v_frexp_exp_i16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77454   { 23224 /* v_frexp_exp_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77459   { 23224 /* v_frexp_exp_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77464   { 23224 /* v_frexp_exp_i32_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77494   { 23264 /* v_frexp_mant_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
77505   { 23264 /* v_frexp_mant_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77511   { 23264 /* v_frexp_mant_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77533   { 23281 /* v_frexp_mant_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77544   { 23281 /* v_frexp_mant_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77550   { 23281 /* v_frexp_mant_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77664   { 23439 /* v_ldexp_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
77679   { 23439 /* v_ldexp_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77687   { 23439 /* v_ldexp_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77728   { 23501 /* v_log_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
77739   { 23501 /* v_log_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77745   { 23501 /* v_log_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77767   { 23511 /* v_log_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77778   { 23511 /* v_log_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77784   { 23511 /* v_log_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77801   { 23521 /* v_log_legacy_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_isGFX7GFX8GFX9_HasSDWA },
77812   { 23521 /* v_log_legacy_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77821   { 23589 /* v_lshlrev_b16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
77827   { 23589 /* v_lshlrev_b16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77844   { 23603 /* v_lshlrev_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77850   { 23603 /* v_lshlrev_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77856   { 23603 /* v_lshlrev_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77866   { 23653 /* v_lshrrev_b16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
77872   { 23653 /* v_lshrrev_b16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77889   { 23667 /* v_lshrrev_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77895   { 23667 /* v_lshrrev_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
77901   { 23667 /* v_lshrrev_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
77915   { 23695 /* v_mac_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
77937   { 23705 /* v_mac_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
77964   { 23715 /* v_mac_legacy_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78091   { 24084 /* v_max_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
78104   { 24084 /* v_max_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78111   { 24084 /* v_max_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78133   { 24094 /* v_max_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78146   { 24094 /* v_max_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78153   { 24094 /* v_max_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78172   { 24114 /* v_max_i16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
78178   { 24114 /* v_max_i16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78195   { 24124 /* v_max_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78201   { 24124 /* v_max_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78207   { 24124 /* v_max_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78220   { 24151 /* v_max_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
78226   { 24151 /* v_max_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78243   { 24161 /* v_max_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78249   { 24161 /* v_max_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78255   { 24161 /* v_max_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78380   { 24775 /* v_min_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
78393   { 24775 /* v_min_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78400   { 24775 /* v_min_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78422   { 24785 /* v_min_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78435   { 24785 /* v_min_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78442   { 24785 /* v_min_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78461   { 24805 /* v_min_i16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
78467   { 24805 /* v_min_i16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78484   { 24815 /* v_min_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78490   { 24815 /* v_min_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78496   { 24815 /* v_min_i32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78509   { 24842 /* v_min_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
78515   { 24842 /* v_min_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78532   { 24852 /* v_min_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78538   { 24852 /* v_min_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78544   { 24852 /* v_min_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78556   { 24862 /* v_mov_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78561   { 24862 /* v_mov_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78566   { 24862 /* v_mov_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78582   { 24872 /* v_mov_fed_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78587   { 24872 /* v_mov_fed_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78592   { 24872 /* v_mov_fed_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78624   { 24989 /* v_mul_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
78637   { 24989 /* v_mul_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78644   { 24989 /* v_mul_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78666   { 24999 /* v_mul_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78679   { 24999 /* v_mul_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78686   { 24999 /* v_mul_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78712   { 25032 /* v_mul_hi_i32_i24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78718   { 25032 /* v_mul_hi_i32_i24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78724   { 25032 /* v_mul_hi_i32_i24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78741   { 25062 /* v_mul_hi_u32_u24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78747   { 25062 /* v_mul_hi_u32_u24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78753   { 25062 /* v_mul_hi_u32_u24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78770   { 25079 /* v_mul_i32_i24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78776   { 25079 /* v_mul_i32_i24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78782   { 25079 /* v_mul_i32_i24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78804   { 25093 /* v_mul_legacy_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78817   { 25093 /* v_mul_legacy_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78824   { 25093 /* v_mul_legacy_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78834   { 25123 /* v_mul_lo_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
78840   { 25123 /* v_mul_lo_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78857   { 25149 /* v_mul_u32_u24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78863   { 25149 /* v_mul_u32_u24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78869   { 25149 /* v_mul_u32_u24 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78887   { 25182 /* v_not_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78892   { 25182 /* v_not_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78897   { 25182 /* v_not_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
78918   { 25202 /* v_or_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
78924   { 25202 /* v_or_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
78930   { 25202 /* v_or_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79151   { 25609 /* v_rcp_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
79162   { 25609 /* v_rcp_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79168   { 25609 /* v_rcp_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79190   { 25619 /* v_rcp_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
79201   { 25619 /* v_rcp_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79207   { 25619 /* v_rcp_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79238   { 25639 /* v_rcp_iflag_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
79249   { 25639 /* v_rcp_iflag_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79255   { 25639 /* v_rcp_iflag_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79277   { 25707 /* v_rndne_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
79288   { 25707 /* v_rndne_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79294   { 25707 /* v_rndne_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79316   { 25719 /* v_rndne_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
79327   { 25719 /* v_rndne_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79333   { 25719 /* v_rndne_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79367   { 25775 /* v_rsq_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
79378   { 25775 /* v_rsq_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79384   { 25775 /* v_rsq_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79406   { 25785 /* v_rsq_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
79417   { 25785 /* v_rsq_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79423   { 25785 /* v_rsq_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79464   { 25863 /* v_sat_pk_u8_i16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_isGFX9Plus_HasSDWA },
79469   { 25863 /* v_sat_pk_u8_i16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79474   { 25863 /* v_sat_pk_u8_i16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79488   { 25879 /* v_screen_partition_4se_b32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79501   { 25906 /* v_sin_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
79512   { 25906 /* v_sin_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79518   { 25906 /* v_sin_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79540   { 25916 /* v_sin_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
79551   { 25916 /* v_sin_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79557   { 25916 /* v_sin_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79576   { 25926 /* v_sqrt_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
79587   { 25926 /* v_sqrt_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79593   { 25926 /* v_sqrt_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79615   { 25937 /* v_sqrt_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
79626   { 25937 /* v_sqrt_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79632   { 25937 /* v_sqrt_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79665   { 25959 /* v_sub_co_ci_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79676   { 25959 /* v_sub_co_ci_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus_isWave64 },
79687   { 25959 /* v_sub_co_ci_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus_isWave32 },
79701   { 25975 /* v_sub_co_u32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79720   { 25988 /* v_sub_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
79733   { 25988 /* v_sub_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79740   { 25988 /* v_sub_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79762   { 25998 /* v_sub_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
79775   { 25998 /* v_sub_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79782   { 25998 /* v_sub_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79802   { 26067 /* v_sub_nc_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79812   { 26080 /* v_sub_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
79818   { 26080 /* v_sub_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
79835   { 26090 /* v_sub_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79841   { 26090 /* v_sub_u32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA_isGFX8Only },
79853   { 26100 /* v_subb_co_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79867   { 26114 /* v_subb_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA_isGFX8Only },
79879   { 26125 /* v_subbrev_co_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79893   { 26142 /* v_subbrev_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA_isGFX8Only },
79912   { 26156 /* v_subrev_co_ci_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79923   { 26156 /* v_subrev_co_ci_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus_isWave64 },
79934   { 26156 /* v_subrev_co_ci_u32 */, 64 /* 6 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus_isWave32 },
79948   { 26175 /* v_subrev_co_u32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79967   { 26191 /* v_subrev_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
79980   { 26191 /* v_subrev_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
79987   { 26191 /* v_subrev_f16 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
80009   { 26204 /* v_subrev_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
80022   { 26204 /* v_subrev_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
80029   { 26204 /* v_subrev_f32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
80045   { 26230 /* v_subrev_nc_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
80055   { 26246 /* v_subrev_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
80061   { 26246 /* v_subrev_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
80078   { 26259 /* v_subrev_u32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
80084   { 26259 /* v_subrev_u32 */, 32 /* 5 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA_isGFX8Only },
80110   { 26314 /* v_trunc_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
80121   { 26314 /* v_trunc_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
80127   { 26314 /* v_trunc_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
80149   { 26326 /* v_trunc_f32 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
80160   { 26326 /* v_trunc_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
80166   { 26326 /* v_trunc_f32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
80197   { 26376 /* v_xnor_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasDLInsts_HasSDWA },
80203   { 26376 /* v_xnor_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
80209   { 26376 /* v_xnor_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasDLInsts_HasSDWA9 },
80226   { 26398 /* v_xor_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA_HasSDWA },
80232   { 26398 /* v_xor_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA10_isGFX10Plus },
80238   { 26398 /* v_xor_b32 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_HasSDWA9_HasSDWA9 },
80373   case MCK_ImmSDWADstSel: