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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 5279 case MCK_ImmOpSel:
6232 case MCK_ImmOpSel: {
10175 case MCK_ImmOpSel: return "MCK_ImmOpSel";
21455 { 13281 /* v_add_i16 */, AMDGPU::V_ADD_I16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
21460 { 13316 /* v_add_nc_i16 */, AMDGPU::V_ADD_NC_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22201 { 22439 /* v_cvt_pknorm_i16_f16 */, AMDGPU::V_CVT_PKNORM_I16_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22202 { 22439 /* v_cvt_pknorm_i16_f16 */, AMDGPU::V_CVT_PKNORM_I16_F16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22207 { 22481 /* v_cvt_pknorm_u16_f16 */, AMDGPU::V_CVT_PKNORM_U16_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22208 { 22481 /* v_cvt_pknorm_u16_f16 */, AMDGPU::V_CVT_PKNORM_U16_F16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22229 { 22603 /* v_div_fixup_f16 */, AMDGPU::V_DIV_FIXUP_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22230 { 22603 /* v_div_fixup_f16 */, AMDGPU::V_DIV_FIXUP_F16_gfx9_gfx9, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22250 { 22736 /* v_dot2_f32_f16 */, AMDGPU::V_DOT2_F32_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_VSrcF32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22251 { 22736 /* v_dot2_f32_f16 */, AMDGPU::V_DOT2_F32_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_VSrcF32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22252 { 22751 /* v_dot2_i32_i16 */, AMDGPU::V_DOT2_I32_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22253 { 22751 /* v_dot2_i32_i16 */, AMDGPU::V_DOT2_I32_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22254 { 22766 /* v_dot2_u32_u16 */, AMDGPU::V_DOT2_U32_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22255 { 22766 /* v_dot2_u32_u16 */, AMDGPU::V_DOT2_U32_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22256 { 22813 /* v_dot4_i32_i8 */, AMDGPU::V_DOT4_I32_I8_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot1Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22257 { 22813 /* v_dot4_i32_i8 */, AMDGPU::V_DOT4_I32_I8_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot1Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22258 { 22827 /* v_dot4_u32_u8 */, AMDGPU::V_DOT4_U32_U8_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22259 { 22827 /* v_dot4_u32_u8 */, AMDGPU::V_DOT4_U32_U8_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22260 { 22856 /* v_dot8_i32_i4 */, AMDGPU::V_DOT8_I32_I4_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot1Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22261 { 22856 /* v_dot8_i32_i4 */, AMDGPU::V_DOT8_I32_I4_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot1Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22262 { 22870 /* v_dot8_u32_u4 */, AMDGPU::V_DOT8_U32_U4_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22263 { 22870 /* v_dot8_u32_u4 */, AMDGPU::V_DOT8_U32_U4_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22289 { 23005 /* v_fma_f16 */, AMDGPU::V_FMA_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22290 { 23005 /* v_fma_f16 */, AMDGPU::V_FMA_F16_gfx9_gfx9, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22298 { 23052 /* v_fma_mix_f32 */, AMDGPU::V_FMA_MIX_F32_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasFmaMixInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
22299 { 23052 /* v_fma_mix_f32 */, AMDGPU::V_FMA_MIX_F32_vi, ConvertCustom_cvtVOP3P, AMFBS_HasFmaMixInsts_HasVOP3PInsts, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
22300 { 23066 /* v_fma_mixhi_f16 */, AMDGPU::V_FMA_MIXHI_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasFmaMixInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
22301 { 23066 /* v_fma_mixhi_f16 */, AMDGPU::V_FMA_MIXHI_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasFmaMixInsts_HasVOP3PInsts, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
22302 { 23082 /* v_fma_mixlo_f16 */, AMDGPU::V_FMA_MIXLO_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasFmaMixInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
22303 { 23082 /* v_fma_mixlo_f16 */, AMDGPU::V_FMA_MIXLO_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasFmaMixInsts_HasVOP3PInsts, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
22394 { 23732 /* v_mad_f16 */, AMDGPU::V_MAD_F16_gfx9_gfx9, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Only_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22399 { 23752 /* v_mad_i16 */, AMDGPU::V_MAD_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22400 { 23752 /* v_mad_i16 */, AMDGPU::V_MAD_I16_gfx9_gfx9, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22401 { 23762 /* v_mad_i32_i16 */, AMDGPU::V_MAD_I32_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmClampSI }, },
22402 { 23762 /* v_mad_i32_i16 */, AMDGPU::V_MAD_I32_I16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmClampSI }, },
22415 { 23872 /* v_mad_mix_f32 */, AMDGPU::V_MAD_MIX_F32_vi, ConvertCustom_cvtVOP3P, AMFBS_HasMadMixInsts_HasVOP3PInsts, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
22416 { 23886 /* v_mad_mixhi_f16 */, AMDGPU::V_MAD_MIXHI_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasMadMixInsts_HasVOP3PInsts, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
22417 { 23902 /* v_mad_mixlo_f16 */, AMDGPU::V_MAD_MIXLO_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasMadMixInsts_HasVOP3PInsts, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
22419 { 23918 /* v_mad_u16 */, AMDGPU::V_MAD_U16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22420 { 23918 /* v_mad_u16 */, AMDGPU::V_MAD_U16_gfx9_gfx9, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22421 { 23928 /* v_mad_u32_u16 */, AMDGPU::V_MAD_U32_U16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmClampSI }, },
22422 { 23928 /* v_mad_u32_u16 */, AMDGPU::V_MAD_U32_U16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmClampSI }, },
22429 { 24018 /* v_max3_f16 */, AMDGPU::V_MAX3_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22430 { 24018 /* v_max3_f16 */, AMDGPU::V_MAX3_F16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22434 { 24040 /* v_max3_i16 */, AMDGPU::V_MAX3_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22435 { 24040 /* v_max3_i16 */, AMDGPU::V_MAX3_I16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22439 { 24062 /* v_max3_u16 */, AMDGPU::V_MAX3_U16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22440 { 24062 /* v_max3_u16 */, AMDGPU::V_MAX3_U16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22469 { 24209 /* v_med3_f16 */, AMDGPU::V_MED3_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22470 { 24209 /* v_med3_f16 */, AMDGPU::V_MED3_F16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22474 { 24231 /* v_med3_i16 */, AMDGPU::V_MED3_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22475 { 24231 /* v_med3_i16 */, AMDGPU::V_MED3_I16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22479 { 24253 /* v_med3_u16 */, AMDGPU::V_MED3_U16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22480 { 24253 /* v_med3_u16 */, AMDGPU::V_MED3_U16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22504 { 24709 /* v_min3_f16 */, AMDGPU::V_MIN3_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22505 { 24709 /* v_min3_f16 */, AMDGPU::V_MIN3_F16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22509 { 24731 /* v_min3_i16 */, AMDGPU::V_MIN3_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22510 { 24731 /* v_min3_i16 */, AMDGPU::V_MIN3_I16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22514 { 24753 /* v_min3_u16 */, AMDGPU::V_MIN3_U16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22515 { 24753 /* v_min3_u16 */, AMDGPU::V_MIN3_U16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22613 { 25211 /* v_pack_b32_f16 */, AMDGPU::V_PACK_B32_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22614 { 25211 /* v_pack_b32_f16 */, AMDGPU::V_PACK_B32_F16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22617 { 25237 /* v_permlane16_b32 */, AMDGPU::V_PERMLANE16_B32_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SCSrcB32, MCK_SCSrcB32, MCK_ImmOpSel }, },
22618 { 25254 /* v_permlanex16_b32 */, AMDGPU::V_PERMLANEX16_B32_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SCSrcB32, MCK_SCSrcB32, MCK_ImmOpSel }, },
22620 { 25284 /* v_pk_add_f16 */, AMDGPU::V_PK_ADD_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22621 { 25284 /* v_pk_add_f16 */, AMDGPU::V_PK_ADD_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22622 { 25297 /* v_pk_add_i16 */, AMDGPU::V_PK_ADD_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22623 { 25297 /* v_pk_add_i16 */, AMDGPU::V_PK_ADD_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22624 { 25310 /* v_pk_add_u16 */, AMDGPU::V_PK_ADD_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22625 { 25310 /* v_pk_add_u16 */, AMDGPU::V_PK_ADD_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22626 { 25323 /* v_pk_ashrrev_i16 */, AMDGPU::V_PK_ASHRREV_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22627 { 25323 /* v_pk_ashrrev_i16 */, AMDGPU::V_PK_ASHRREV_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22628 { 25340 /* v_pk_fma_f16 */, AMDGPU::V_PK_FMA_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22629 { 25340 /* v_pk_fma_f16 */, AMDGPU::V_PK_FMA_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22630 { 25367 /* v_pk_lshlrev_b16 */, AMDGPU::V_PK_LSHLREV_B16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22631 { 25367 /* v_pk_lshlrev_b16 */, AMDGPU::V_PK_LSHLREV_B16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22632 { 25384 /* v_pk_lshrrev_b16 */, AMDGPU::V_PK_LSHRREV_B16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22633 { 25384 /* v_pk_lshrrev_b16 */, AMDGPU::V_PK_LSHRREV_B16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22634 { 25401 /* v_pk_mad_i16 */, AMDGPU::V_PK_MAD_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22635 { 25401 /* v_pk_mad_i16 */, AMDGPU::V_PK_MAD_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22636 { 25414 /* v_pk_mad_u16 */, AMDGPU::V_PK_MAD_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22637 { 25414 /* v_pk_mad_u16 */, AMDGPU::V_PK_MAD_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22638 { 25427 /* v_pk_max_f16 */, AMDGPU::V_PK_MAX_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22639 { 25427 /* v_pk_max_f16 */, AMDGPU::V_PK_MAX_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22640 { 25440 /* v_pk_max_i16 */, AMDGPU::V_PK_MAX_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22641 { 25440 /* v_pk_max_i16 */, AMDGPU::V_PK_MAX_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22642 { 25453 /* v_pk_max_u16 */, AMDGPU::V_PK_MAX_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22643 { 25453 /* v_pk_max_u16 */, AMDGPU::V_PK_MAX_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22644 { 25466 /* v_pk_min_f16 */, AMDGPU::V_PK_MIN_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22645 { 25466 /* v_pk_min_f16 */, AMDGPU::V_PK_MIN_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22646 { 25479 /* v_pk_min_i16 */, AMDGPU::V_PK_MIN_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22647 { 25479 /* v_pk_min_i16 */, AMDGPU::V_PK_MIN_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22648 { 25492 /* v_pk_min_u16 */, AMDGPU::V_PK_MIN_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22649 { 25492 /* v_pk_min_u16 */, AMDGPU::V_PK_MIN_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22650 { 25505 /* v_pk_mul_f16 */, AMDGPU::V_PK_MUL_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22651 { 25505 /* v_pk_mul_f16 */, AMDGPU::V_PK_MUL_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22652 { 25518 /* v_pk_mul_lo_u16 */, AMDGPU::V_PK_MUL_LO_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22653 { 25518 /* v_pk_mul_lo_u16 */, AMDGPU::V_PK_MUL_LO_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22654 { 25534 /* v_pk_sub_i16 */, AMDGPU::V_PK_SUB_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22655 { 25534 /* v_pk_sub_i16 */, AMDGPU::V_PK_SUB_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22656 { 25547 /* v_pk_sub_u16 */, AMDGPU::V_PK_SUB_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22657 { 25547 /* v_pk_sub_u16 */, AMDGPU::V_PK_SUB_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22734 { 26008 /* v_sub_i16 */, AMDGPU::V_SUB_I16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22737 { 26028 /* v_sub_nc_i16 */, AMDGPU::V_SUB_NC_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
72994 { 13281 /* v_add_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
72998 { 13316 /* v_add_nc_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
76678 { 22439 /* v_cvt_pknorm_i16_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
76681 { 22439 /* v_cvt_pknorm_i16_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
76690 { 22481 /* v_cvt_pknorm_u16_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
76693 { 22481 /* v_cvt_pknorm_u16_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
76820 { 22603 /* v_div_fixup_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
76823 { 22603 /* v_div_fixup_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Only },
76870 { 22736 /* v_dot2_f32_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasDot2Insts_isGFX10Plus },
76875 { 22736 /* v_dot2_f32_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasDot2Insts_HasVOP3PInsts },
76880 { 22751 /* v_dot2_i32_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasDot2Insts_isGFX10Plus },
76885 { 22751 /* v_dot2_i32_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasDot2Insts_HasVOP3PInsts },
76890 { 22766 /* v_dot2_u32_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasDot2Insts_isGFX10Plus },
76895 { 22766 /* v_dot2_u32_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasDot2Insts_HasVOP3PInsts },
76918 { 22813 /* v_dot4_i32_i8 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasDot1Insts_isGFX10Plus },
76923 { 22813 /* v_dot4_i32_i8 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasDot1Insts_HasVOP3PInsts },
76928 { 22827 /* v_dot4_u32_u8 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasDot2Insts_isGFX10Plus },
76933 { 22827 /* v_dot4_u32_u8 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasDot2Insts_HasVOP3PInsts },
76951 { 22856 /* v_dot8_i32_i4 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasDot1Insts_isGFX10Plus },
76956 { 22856 /* v_dot8_i32_i4 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasDot1Insts_HasVOP3PInsts },
76961 { 22870 /* v_dot8_u32_u4 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasDot2Insts_isGFX10Plus },
76966 { 22870 /* v_dot8_u32_u4 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasDot2Insts_HasVOP3PInsts },
77239 { 23005 /* v_fma_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
77242 { 23005 /* v_fma_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Only },
77266 { 23052 /* v_fma_mix_f32 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasFmaMixInsts_isGFX10Plus },
77270 { 23052 /* v_fma_mix_f32 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasFmaMixInsts_HasVOP3PInsts },
77274 { 23066 /* v_fma_mixhi_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasFmaMixInsts_isGFX10Plus },
77278 { 23066 /* v_fma_mixhi_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasFmaMixInsts_HasVOP3PInsts },
77282 { 23082 /* v_fma_mixlo_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasFmaMixInsts_isGFX10Plus },
77286 { 23082 /* v_fma_mixlo_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasFmaMixInsts_HasVOP3PInsts },
77973 { 23732 /* v_mad_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Only_isGFX9Only },
77985 { 23752 /* v_mad_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
77987 { 23752 /* v_mad_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX9Only },
77989 { 23762 /* v_mad_i32_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
77991 { 23762 /* v_mad_i32_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78017 { 23872 /* v_mad_mix_f32 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasMadMixInsts_HasVOP3PInsts },
78021 { 23886 /* v_mad_mixhi_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasMadMixInsts_HasVOP3PInsts },
78025 { 23902 /* v_mad_mixlo_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasMadMixInsts_HasVOP3PInsts },
78029 { 23918 /* v_mad_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78031 { 23918 /* v_mad_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX9Only },
78033 { 23928 /* v_mad_u32_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78035 { 23928 /* v_mad_u32_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78055 { 24018 /* v_max3_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78058 { 24018 /* v_max3_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78069 { 24040 /* v_max3_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78071 { 24040 /* v_max3_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78073 { 24062 /* v_max3_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78075 { 24062 /* v_max3_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78261 { 24209 /* v_med3_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78264 { 24209 /* v_med3_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78275 { 24231 /* v_med3_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78277 { 24231 /* v_med3_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78279 { 24253 /* v_med3_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78281 { 24253 /* v_med3_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78344 { 24709 /* v_min3_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78347 { 24709 /* v_min3_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78358 { 24731 /* v_min3_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78360 { 24731 /* v_min3_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78362 { 24753 /* v_min3_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78364 { 24753 /* v_min3_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78936 { 25211 /* v_pack_b32_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
78939 { 25211 /* v_pack_b32_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
78940 { 25237 /* v_permlane16_b32 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX10Plus_isGFX10Plus },
78941 { 25254 /* v_permlanex16_b32 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX10Plus_isGFX10Plus },
78943 { 25284 /* v_pk_add_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
78948 { 25284 /* v_pk_add_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
78953 { 25297 /* v_pk_add_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
78958 { 25297 /* v_pk_add_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
78963 { 25310 /* v_pk_add_u16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
78968 { 25310 /* v_pk_add_u16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
78973 { 25323 /* v_pk_ashrrev_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
78978 { 25323 /* v_pk_ashrrev_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
78983 { 25340 /* v_pk_fma_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
78988 { 25340 /* v_pk_fma_f16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
78993 { 25367 /* v_pk_lshlrev_b16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
78998 { 25367 /* v_pk_lshlrev_b16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79003 { 25384 /* v_pk_lshrrev_b16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79008 { 25384 /* v_pk_lshrrev_b16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79013 { 25401 /* v_pk_mad_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79018 { 25401 /* v_pk_mad_i16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79023 { 25414 /* v_pk_mad_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79028 { 25414 /* v_pk_mad_u16 */, 16 /* 4 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79033 { 25427 /* v_pk_max_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79038 { 25427 /* v_pk_max_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79043 { 25440 /* v_pk_max_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79048 { 25440 /* v_pk_max_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79053 { 25453 /* v_pk_max_u16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79058 { 25453 /* v_pk_max_u16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79063 { 25466 /* v_pk_min_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79068 { 25466 /* v_pk_min_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79073 { 25479 /* v_pk_min_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79078 { 25479 /* v_pk_min_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79083 { 25492 /* v_pk_min_u16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79088 { 25492 /* v_pk_min_u16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79093 { 25505 /* v_pk_mul_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79098 { 25505 /* v_pk_mul_f16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79103 { 25518 /* v_pk_mul_lo_u16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79108 { 25518 /* v_pk_mul_lo_u16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79113 { 25534 /* v_pk_sub_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79118 { 25534 /* v_pk_sub_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79123 { 25547 /* v_pk_sub_u16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX10Plus },
79128 { 25547 /* v_pk_sub_u16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_HasVOP3PInsts },
79787 { 26008 /* v_sub_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX8GFX9 },
79791 { 26028 /* v_sub_nc_i16 */, 8 /* 3 */, MCK_ImmOpSel, AMFBS_isGFX9Plus_isGFX10Plus },
80381 case MCK_ImmOpSel: