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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 5198 case MCK_ImmOffset1:
6022 case MCK_ImmOffset1: {
10145 case MCK_ImmOffset1: return "MCK_ImmOffset1";
12698 { 3058 /* ds_read2_b32 */, AMDGPU::DS_READ2_B32_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12699 { 3058 /* ds_read2_b32 */, AMDGPU::DS_READ2_B32_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12700 { 3058 /* ds_read2_b32 */, AMDGPU::DS_READ2_B32_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12701 { 3071 /* ds_read2_b64 */, AMDGPU::DS_READ2_B64_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12702 { 3071 /* ds_read2_b64 */, AMDGPU::DS_READ2_B64_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12703 { 3071 /* ds_read2_b64 */, AMDGPU::DS_READ2_B64_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12704 { 3084 /* ds_read2st64_b32 */, AMDGPU::DS_READ2ST64_B32_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12705 { 3084 /* ds_read2st64_b32 */, AMDGPU::DS_READ2ST64_B32_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12706 { 3084 /* ds_read2st64_b32 */, AMDGPU::DS_READ2ST64_B32_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12707 { 3101 /* ds_read2st64_b64 */, AMDGPU::DS_READ2ST64_B64_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12708 { 3101 /* ds_read2st64_b64 */, AMDGPU::DS_READ2ST64_B64_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12709 { 3101 /* ds_read2st64_b64 */, AMDGPU::DS_READ2ST64_B64_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12790 { 3538 /* ds_write2_b32 */, AMDGPU::DS_WRITE2_B32_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12791 { 3538 /* ds_write2_b32 */, AMDGPU::DS_WRITE2_B32_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12792 { 3538 /* ds_write2_b32 */, AMDGPU::DS_WRITE2_B32_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12793 { 3552 /* ds_write2_b64 */, AMDGPU::DS_WRITE2_B64_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12794 { 3552 /* ds_write2_b64 */, AMDGPU::DS_WRITE2_B64_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12795 { 3552 /* ds_write2_b64 */, AMDGPU::DS_WRITE2_B64_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12796 { 3566 /* ds_write2st64_b32 */, AMDGPU::DS_WRITE2ST64_B32_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12797 { 3566 /* ds_write2st64_b32 */, AMDGPU::DS_WRITE2ST64_B32_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12798 { 3566 /* ds_write2st64_b32 */, AMDGPU::DS_WRITE2ST64_B32_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12799 { 3584 /* ds_write2st64_b64 */, AMDGPU::DS_WRITE2ST64_B64_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12800 { 3584 /* ds_write2st64_b64 */, AMDGPU::DS_WRITE2ST64_B64_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12801 { 3584 /* ds_write2st64_b64 */, AMDGPU::DS_WRITE2ST64_B64_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12832 { 3775 /* ds_wrxchg2_rtn_b32 */, AMDGPU::DS_WRXCHG2_RTN_B32_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12833 { 3775 /* ds_wrxchg2_rtn_b32 */, AMDGPU::DS_WRXCHG2_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12834 { 3775 /* ds_wrxchg2_rtn_b32 */, AMDGPU::DS_WRXCHG2_RTN_B32_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12835 { 3794 /* ds_wrxchg2_rtn_b64 */, AMDGPU::DS_WRXCHG2_RTN_B64_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12836 { 3794 /* ds_wrxchg2_rtn_b64 */, AMDGPU::DS_WRXCHG2_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12837 { 3794 /* ds_wrxchg2_rtn_b64 */, AMDGPU::DS_WRXCHG2_RTN_B64_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12838 { 3813 /* ds_wrxchg2st64_rtn_b32 */, AMDGPU::DS_WRXCHG2ST64_RTN_B32_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12839 { 3813 /* ds_wrxchg2st64_rtn_b32 */, AMDGPU::DS_WRXCHG2ST64_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12840 { 3813 /* ds_wrxchg2st64_rtn_b32 */, AMDGPU::DS_WRXCHG2ST64_RTN_B32_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12841 { 3836 /* ds_wrxchg2st64_rtn_b64 */, AMDGPU::DS_WRXCHG2ST64_RTN_B64_gfx10, ConvertCustom_cvtDSOffset01, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12842 { 3836 /* ds_wrxchg2st64_rtn_b64 */, AMDGPU::DS_WRXCHG2ST64_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDSOffset01, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
12843 { 3836 /* ds_wrxchg2st64_rtn_b64 */, AMDGPU::DS_WRXCHG2ST64_RTN_B64_vi, ConvertCustom_cvtDSOffset01, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
29443 { 3058 /* ds_read2_b32 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29446 { 3058 /* ds_read2_b32 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29449 { 3058 /* ds_read2_b32 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29452 { 3071 /* ds_read2_b64 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29455 { 3071 /* ds_read2_b64 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29458 { 3071 /* ds_read2_b64 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29461 { 3084 /* ds_read2st64_b32 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29464 { 3084 /* ds_read2st64_b32 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29467 { 3084 /* ds_read2st64_b32 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29470 { 3101 /* ds_read2st64_b64 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29473 { 3101 /* ds_read2st64_b64 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29476 { 3101 /* ds_read2st64_b64 */, 8 /* 3 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29639 { 3538 /* ds_write2_b32 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29642 { 3538 /* ds_write2_b32 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29645 { 3538 /* ds_write2_b32 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29648 { 3552 /* ds_write2_b64 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29651 { 3552 /* ds_write2_b64 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29654 { 3552 /* ds_write2_b64 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29657 { 3566 /* ds_write2st64_b32 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29660 { 3566 /* ds_write2st64_b32 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29663 { 3566 /* ds_write2st64_b32 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29666 { 3584 /* ds_write2st64_b64 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29669 { 3584 /* ds_write2st64_b64 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29672 { 3584 /* ds_write2st64_b64 */, 16 /* 4 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29735 { 3775 /* ds_wrxchg2_rtn_b32 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29738 { 3775 /* ds_wrxchg2_rtn_b32 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29741 { 3775 /* ds_wrxchg2_rtn_b32 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29744 { 3794 /* ds_wrxchg2_rtn_b64 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29747 { 3794 /* ds_wrxchg2_rtn_b64 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29750 { 3794 /* ds_wrxchg2_rtn_b64 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29753 { 3813 /* ds_wrxchg2st64_rtn_b32 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29756 { 3813 /* ds_wrxchg2st64_rtn_b32 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29759 { 3813 /* ds_wrxchg2st64_rtn_b32 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
29762 { 3836 /* ds_wrxchg2st64_rtn_b64 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX10Plus },
29765 { 3836 /* ds_wrxchg2st64_rtn_b64 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX6GFX7 },
29768 { 3836 /* ds_wrxchg2st64_rtn_b64 */, 32 /* 5 */, MCK_ImmOffset1, AMFBS_isGFX8GFX9 },
80321 case MCK_ImmOffset1: