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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 5192 case MCK_ImmOffset:
6008 case MCK_ImmOffset: {
10143 case MCK_ImmOffset: return "MCK_ImmOffset";
11077 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11078 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11079 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11080 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11081 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11082 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11083 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11084 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11085 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11086 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11087 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11088 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11089 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11090 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11091 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11092 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11093 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11094 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11095 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11096 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11097 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11098 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11099 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11100 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11101 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11102 { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11103 { 18 /* buffer_atomic_add_f32 */, AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11104 { 18 /* buffer_atomic_add_f32 */, AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11105 { 18 /* buffer_atomic_add_f32 */, AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11106 { 18 /* buffer_atomic_add_f32 */, AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11107 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11108 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11109 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11110 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11111 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11112 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11113 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11114 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11115 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11116 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11117 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11118 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11119 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11120 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11121 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11122 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11123 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11124 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11125 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11126 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11127 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11128 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11129 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11130 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11131 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11132 { 40 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11133 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11134 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11135 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11136 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11137 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11138 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11139 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11140 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11141 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11142 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11143 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11144 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11145 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11146 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11147 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11148 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11149 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11150 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11151 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11152 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11153 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11154 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11155 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11156 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11157 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11158 { 61 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11159 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11160 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11161 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11162 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11163 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11164 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11165 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11166 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11167 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11168 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11169 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11170 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11171 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11172 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11173 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11174 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11175 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11176 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11177 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11178 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11179 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11180 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11181 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11182 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11183 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11184 { 79 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11185 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11186 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11187 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11188 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11189 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11190 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11191 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11192 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11193 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11194 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11195 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11196 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11197 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11198 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11199 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11200 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11201 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11202 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11203 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11204 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11205 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11206 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11207 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11208 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11209 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11210 { 100 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11211 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11212 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11213 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11214 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11215 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11216 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11217 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11218 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11219 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11220 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11221 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11222 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11223 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11224 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11225 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11226 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11227 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11228 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11229 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11230 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11231 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11232 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11233 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11234 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11235 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11236 { 122 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11237 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11238 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11239 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11240 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11241 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11242 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11243 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11244 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11245 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11246 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11247 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11248 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11249 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11250 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11251 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11252 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11253 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11254 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11255 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11256 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11257 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11258 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11259 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11260 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11261 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11262 { 147 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11263 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11264 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11265 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11266 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11267 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11268 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11269 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11270 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11271 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11272 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11273 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11274 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11275 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11276 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11277 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11278 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11279 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11280 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11281 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11282 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11283 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11284 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11285 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11286 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11287 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11288 { 165 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11289 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11290 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11291 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11292 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11293 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11294 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11295 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11296 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11297 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11298 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11299 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11300 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11301 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11302 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11303 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11304 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11305 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11306 { 186 /* buffer_atomic_fcmpswap */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11307 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11308 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11309 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11310 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11311 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11312 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11313 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11314 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11315 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11316 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11317 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11318 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11319 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11320 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11321 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11322 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11323 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11324 { 209 /* buffer_atomic_fcmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11325 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11326 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11327 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11328 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11329 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11330 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11331 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11332 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11333 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11334 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11335 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11336 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11337 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11338 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11339 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11340 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11341 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11342 { 235 /* buffer_atomic_fmax */, AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11343 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11344 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11345 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11346 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11347 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11348 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11349 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11350 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11351 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11352 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11353 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11354 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11355 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11356 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11357 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11358 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11359 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11360 { 254 /* buffer_atomic_fmax_x2 */, AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11361 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11362 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11363 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11364 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11365 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11366 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11367 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11368 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11369 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11370 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11371 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11372 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11373 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11374 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11375 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11376 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11377 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11378 { 276 /* buffer_atomic_fmin */, AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11379 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11380 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11381 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11382 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11383 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11384 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11385 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11386 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11387 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11388 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11389 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11390 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11391 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11392 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11393 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11394 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11395 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11396 { 295 /* buffer_atomic_fmin_x2 */, AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11397 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11398 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11399 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11400 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11401 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11402 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11403 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11404 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11405 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11406 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11407 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11408 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11409 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11410 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11411 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11412 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11413 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11414 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11415 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11416 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11417 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11418 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11419 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11420 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11421 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11422 { 317 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11423 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11424 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11425 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11426 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11427 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11428 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11429 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11430 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11431 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11432 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11433 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11434 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11435 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11436 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11437 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11438 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11439 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11440 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11441 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11442 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11443 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11444 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11445 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11446 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11447 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11448 { 335 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11449 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11450 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11451 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11452 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11453 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11454 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11455 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11456 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11457 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11458 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11459 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11460 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11461 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11462 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11463 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11464 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11465 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11466 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11467 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11468 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11469 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11470 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11471 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11472 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11473 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11474 { 356 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11475 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11476 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11477 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11478 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11479 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11480 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11481 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11482 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11483 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11484 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11485 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11486 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11487 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11488 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11489 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11490 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11491 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11492 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11493 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11494 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11495 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11496 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11497 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11498 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11499 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11500 { 373 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11501 { 393 /* buffer_atomic_pk_add_f16 */, AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11502 { 393 /* buffer_atomic_pk_add_f16 */, AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11503 { 393 /* buffer_atomic_pk_add_f16 */, AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11504 { 393 /* buffer_atomic_pk_add_f16 */, AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11505 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11506 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11507 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11508 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11509 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11510 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11511 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11512 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11513 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11514 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11515 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11516 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11517 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11518 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11519 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11520 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11521 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11522 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11523 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11524 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11525 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11526 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11527 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11528 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11529 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11530 { 418 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11531 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11532 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11533 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11534 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11535 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11536 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11537 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11538 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11539 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11540 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11541 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11542 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11543 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11544 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11545 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11546 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11547 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11548 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11549 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11550 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11551 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11552 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11553 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11554 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11555 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11556 { 437 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11557 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11558 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11559 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11560 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11561 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11562 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11563 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11564 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11565 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11566 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11567 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11568 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11569 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11570 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11571 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11572 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11573 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11574 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11575 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11576 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11577 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11578 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11579 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11580 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11581 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11582 { 459 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11583 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11584 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11585 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11586 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11587 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11588 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11589 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11590 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11591 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11592 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11593 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11594 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11595 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11596 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11597 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11598 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11599 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11600 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11601 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11602 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11603 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11604 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11605 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11606 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11607 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11608 { 478 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11609 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11610 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11611 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11612 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11613 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11614 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11615 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11616 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11617 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11618 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11619 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11620 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11621 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11622 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11623 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11624 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11625 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11626 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11627 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11628 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11629 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11630 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11631 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11632 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11633 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11634 { 500 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11635 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11636 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11637 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11638 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11639 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11640 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11641 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11642 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11643 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11644 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11645 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11646 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11647 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11648 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11649 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11650 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11651 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11652 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11653 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11654 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11655 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11656 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11657 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11658 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11659 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11660 { 518 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11661 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11662 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11663 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11664 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11665 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11666 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11667 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11668 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11669 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11670 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11671 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11672 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11673 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11674 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11675 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11676 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11677 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11678 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11679 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11680 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11681 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11682 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11683 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11684 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11685 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11686 { 539 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11687 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11688 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11689 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11690 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11691 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11692 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11693 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11694 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11695 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11696 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11697 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11698 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11699 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11700 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11701 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11702 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11703 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11704 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11705 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11706 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11707 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11708 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11709 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11710 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11711 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11712 { 558 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11713 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11714 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11715 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11716 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11717 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11718 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11719 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11720 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11721 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11722 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11723 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11724 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11725 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11726 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11727 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11728 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11729 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11730 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11731 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11732 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11733 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11734 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11735 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11736 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11737 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11738 { 580 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11739 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11740 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11741 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11742 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11743 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11744 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11745 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11746 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11747 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11748 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11749 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11750 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11751 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11752 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11753 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11754 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11755 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11756 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11757 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11758 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11759 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11760 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11761 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11762 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11763 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11764 { 599 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11765 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11766 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11767 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11768 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11769 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11770 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11771 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11772 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11773 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11774 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11775 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11776 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11777 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11778 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11779 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11780 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11781 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11782 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11783 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11784 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11785 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11786 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11787 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11788 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11789 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11790 { 621 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11791 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11792 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11793 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11794 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11795 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11796 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11797 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11798 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11799 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11800 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11801 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11802 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11803 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11804 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11805 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11806 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11807 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11808 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11809 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11810 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11811 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11812 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11813 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11814 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11815 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11816 { 640 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11817 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11818 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11819 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11820 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11821 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11822 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11823 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11824 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11825 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11826 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11827 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11828 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11829 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11830 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11831 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11832 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11833 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11834 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11835 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11836 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11837 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11838 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11839 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11840 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11841 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11842 { 662 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11843 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11844 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11845 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
11846 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11847 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11848 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11849 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
11850 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11851 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11852 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
11853 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11854 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11855 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11856 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11857 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_gfx10, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11858 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11859 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
11860 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11861 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11862 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11863 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11864 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11865 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11866 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx10, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11867 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx6_gfx7, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11868 { 680 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
11871 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11872 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11873 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11874 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11875 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11876 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11877 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11878 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11879 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11880 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11881 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11882 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11883 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11884 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11885 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11886 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11887 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11888 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11889 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11890 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11891 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11892 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11893 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11894 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11895 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11896 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11897 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11898 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11899 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11900 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11901 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11902 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11903 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11904 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11905 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11906 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11907 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11908 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11909 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11910 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11911 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11912 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11913 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11914 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11915 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11916 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11917 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11918 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11919 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11920 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11921 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11922 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11923 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11924 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11925 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11926 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11927 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11928 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11929 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11930 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11931 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11932 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11933 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11934 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11935 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11936 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11937 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11938 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11939 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11940 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11941 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11942 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11943 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11944 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11945 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11946 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11947 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11948 { 809 /* buffer_load_format_d16_hi_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11949 { 809 /* buffer_load_format_d16_hi_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11950 { 809 /* buffer_load_format_d16_hi_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11951 { 809 /* buffer_load_format_d16_hi_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11952 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11953 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11954 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11955 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11956 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11957 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11958 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11959 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11960 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11961 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11962 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11963 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11964 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11965 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11966 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11967 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11968 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11969 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11970 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11971 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11972 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11973 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11974 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11975 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11976 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11977 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11978 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11979 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11980 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11981 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11982 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11983 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11984 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11985 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11986 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11987 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11988 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11989 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11990 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11991 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11992 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11993 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11994 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11995 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11996 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11997 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11998 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11999 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12000 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12001 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12002 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12003 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12004 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12005 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12006 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12007 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12008 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12009 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12010 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12011 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12012 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12013 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12014 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12015 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12016 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12017 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12018 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12019 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12020 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12021 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12022 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12023 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12024 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12025 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12026 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12027 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12028 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12029 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12030 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12031 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12032 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12033 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12034 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12035 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12036 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12037 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12038 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12039 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12040 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12041 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12042 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12043 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12044 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12045 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12046 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12047 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12048 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12049 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12050 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12051 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12052 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12053 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12054 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12055 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12056 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12057 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12058 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12059 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12060 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12061 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12062 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12063 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12064 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12065 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12066 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12067 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12068 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12069 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12070 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12071 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12072 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12073 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12074 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12075 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12076 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12077 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12078 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12079 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12080 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12081 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12082 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12083 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12084 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12085 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12086 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12087 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12088 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12089 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12090 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12091 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12092 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12093 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12094 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12095 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12096 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12097 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12098 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12099 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12100 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12101 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12102 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12103 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12104 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12105 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12106 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12107 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12108 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12109 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12110 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12111 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12112 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12113 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12114 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12115 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12116 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12117 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12118 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12119 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12120 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12121 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12122 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12123 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12124 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12125 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12126 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12127 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12128 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12129 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12130 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12131 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12132 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12133 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12134 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12135 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12136 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12137 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12138 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12139 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12140 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12141 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12142 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12143 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12144 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12145 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12146 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12147 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12148 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12149 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12150 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12151 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12152 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12153 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12154 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12155 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12156 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12157 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12158 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12159 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12160 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12161 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12162 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12163 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12164 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12165 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12166 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12167 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12168 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12169 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12170 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12171 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12172 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12173 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12174 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12175 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12176 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12177 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12178 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12179 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12180 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12181 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12182 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12183 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12184 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12185 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12186 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12187 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12188 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12189 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12190 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12191 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12192 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12193 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12194 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12195 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12196 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12197 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12198 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12199 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12200 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12201 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12202 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12203 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12204 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12205 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12206 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12207 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12208 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12209 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12210 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12211 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12212 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12213 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12214 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12215 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12216 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12217 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12218 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12219 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12220 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12221 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12222 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12223 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12224 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12225 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12226 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12227 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12228 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12229 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12230 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12231 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12232 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12233 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12234 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12235 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12236 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12237 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12238 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12239 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12240 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12241 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12242 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12243 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12244 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12245 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12246 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12247 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12248 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12249 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12250 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12251 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12252 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12253 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12254 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12255 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12256 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12257 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12258 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12259 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12260 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12261 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12262 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12263 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12264 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12265 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12266 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12267 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12268 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12269 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12270 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12271 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12272 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12273 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12274 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12275 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12276 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12277 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12278 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12279 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12280 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12281 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12282 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12283 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12284 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12285 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12286 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12287 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12288 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12289 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12290 { 1373 /* buffer_store_format_d16_hi_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12291 { 1373 /* buffer_store_format_d16_hi_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12292 { 1373 /* buffer_store_format_d16_hi_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12293 { 1373 /* buffer_store_format_d16_hi_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12294 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12295 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12296 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12297 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12298 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12299 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12300 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12301 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12302 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12303 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12304 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12305 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12306 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12307 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12308 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12309 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12310 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12311 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12312 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12313 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12314 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12315 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12316 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12317 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12318 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12319 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12320 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12321 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12322 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12323 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12324 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12325 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12326 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12327 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12328 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12329 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12330 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12331 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12332 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12333 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12334 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12335 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12336 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12337 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12338 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12339 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12340 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12341 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12342 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12343 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12344 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12345 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12346 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12347 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12348 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12349 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12350 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12351 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12352 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12353 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12354 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12355 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12356 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12357 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12358 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12359 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12360 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12361 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12362 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12363 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12364 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12365 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12366 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12367 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12368 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12369 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12370 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12371 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12372 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12373 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12374 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12375 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12376 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12377 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12378 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12379 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12380 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12381 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12382 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12383 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12384 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12385 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12386 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12387 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12388 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12389 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12390 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12391 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12392 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12393 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12394 { 1606 /* buffer_store_lds_dword */, AMDGPU::BUFFER_STORE_LDS_DWORD_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_lds, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmSWZ }, },
12395 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12396 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12397 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12398 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12399 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12400 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12401 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12402 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12403 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12404 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12405 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12406 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12407 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12408 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12409 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12410 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12411 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12412 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12413 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12414 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12415 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12421 { 1726 /* ds_add_f32 */, AMDGPU::DS_ADD_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12422 { 1726 /* ds_add_f32 */, AMDGPU::DS_ADD_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12423 { 1737 /* ds_add_rtn_f32 */, AMDGPU::DS_ADD_RTN_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12424 { 1737 /* ds_add_rtn_f32 */, AMDGPU::DS_ADD_RTN_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12425 { 1752 /* ds_add_rtn_u32 */, AMDGPU::DS_ADD_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12426 { 1752 /* ds_add_rtn_u32 */, AMDGPU::DS_ADD_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12427 { 1752 /* ds_add_rtn_u32 */, AMDGPU::DS_ADD_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12428 { 1767 /* ds_add_rtn_u64 */, AMDGPU::DS_ADD_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12429 { 1767 /* ds_add_rtn_u64 */, AMDGPU::DS_ADD_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12430 { 1767 /* ds_add_rtn_u64 */, AMDGPU::DS_ADD_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12431 { 1782 /* ds_add_src2_f32 */, AMDGPU::DS_ADD_SRC2_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12432 { 1782 /* ds_add_src2_f32 */, AMDGPU::DS_ADD_SRC2_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12433 { 1798 /* ds_add_src2_u32 */, AMDGPU::DS_ADD_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12434 { 1798 /* ds_add_src2_u32 */, AMDGPU::DS_ADD_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12435 { 1798 /* ds_add_src2_u32 */, AMDGPU::DS_ADD_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12436 { 1814 /* ds_add_src2_u64 */, AMDGPU::DS_ADD_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12437 { 1814 /* ds_add_src2_u64 */, AMDGPU::DS_ADD_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12438 { 1814 /* ds_add_src2_u64 */, AMDGPU::DS_ADD_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12439 { 1830 /* ds_add_u32 */, AMDGPU::DS_ADD_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12440 { 1830 /* ds_add_u32 */, AMDGPU::DS_ADD_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12441 { 1830 /* ds_add_u32 */, AMDGPU::DS_ADD_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12442 { 1841 /* ds_add_u64 */, AMDGPU::DS_ADD_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12443 { 1841 /* ds_add_u64 */, AMDGPU::DS_ADD_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12444 { 1841 /* ds_add_u64 */, AMDGPU::DS_ADD_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12445 { 1852 /* ds_and_b32 */, AMDGPU::DS_AND_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12446 { 1852 /* ds_and_b32 */, AMDGPU::DS_AND_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12447 { 1852 /* ds_and_b32 */, AMDGPU::DS_AND_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12448 { 1863 /* ds_and_b64 */, AMDGPU::DS_AND_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12449 { 1863 /* ds_and_b64 */, AMDGPU::DS_AND_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12450 { 1863 /* ds_and_b64 */, AMDGPU::DS_AND_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12451 { 1874 /* ds_and_rtn_b32 */, AMDGPU::DS_AND_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12452 { 1874 /* ds_and_rtn_b32 */, AMDGPU::DS_AND_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12453 { 1874 /* ds_and_rtn_b32 */, AMDGPU::DS_AND_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12454 { 1889 /* ds_and_rtn_b64 */, AMDGPU::DS_AND_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12455 { 1889 /* ds_and_rtn_b64 */, AMDGPU::DS_AND_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12456 { 1889 /* ds_and_rtn_b64 */, AMDGPU::DS_AND_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12457 { 1904 /* ds_and_src2_b32 */, AMDGPU::DS_AND_SRC2_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12458 { 1904 /* ds_and_src2_b32 */, AMDGPU::DS_AND_SRC2_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12459 { 1904 /* ds_and_src2_b32 */, AMDGPU::DS_AND_SRC2_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12460 { 1920 /* ds_and_src2_b64 */, AMDGPU::DS_AND_SRC2_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12461 { 1920 /* ds_and_src2_b64 */, AMDGPU::DS_AND_SRC2_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12462 { 1920 /* ds_and_src2_b64 */, AMDGPU::DS_AND_SRC2_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12463 { 1936 /* ds_append */, AMDGPU::DS_APPEND_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12464 { 1936 /* ds_append */, AMDGPU::DS_APPEND_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12465 { 1936 /* ds_append */, AMDGPU::DS_APPEND_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12466 { 1946 /* ds_bpermute_b32 */, AMDGPU::DS_BPERMUTE_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset }, },
12467 { 1946 /* ds_bpermute_b32 */, AMDGPU::DS_BPERMUTE_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset }, },
12468 { 1962 /* ds_cmpst_b32 */, AMDGPU::DS_CMPST_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12469 { 1962 /* ds_cmpst_b32 */, AMDGPU::DS_CMPST_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12470 { 1962 /* ds_cmpst_b32 */, AMDGPU::DS_CMPST_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12471 { 1975 /* ds_cmpst_b64 */, AMDGPU::DS_CMPST_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12472 { 1975 /* ds_cmpst_b64 */, AMDGPU::DS_CMPST_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12473 { 1975 /* ds_cmpst_b64 */, AMDGPU::DS_CMPST_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12474 { 1988 /* ds_cmpst_f32 */, AMDGPU::DS_CMPST_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12475 { 1988 /* ds_cmpst_f32 */, AMDGPU::DS_CMPST_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12476 { 1988 /* ds_cmpst_f32 */, AMDGPU::DS_CMPST_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12477 { 2001 /* ds_cmpst_f64 */, AMDGPU::DS_CMPST_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12478 { 2001 /* ds_cmpst_f64 */, AMDGPU::DS_CMPST_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12479 { 2001 /* ds_cmpst_f64 */, AMDGPU::DS_CMPST_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12480 { 2014 /* ds_cmpst_rtn_b32 */, AMDGPU::DS_CMPST_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12481 { 2014 /* ds_cmpst_rtn_b32 */, AMDGPU::DS_CMPST_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12482 { 2014 /* ds_cmpst_rtn_b32 */, AMDGPU::DS_CMPST_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12483 { 2031 /* ds_cmpst_rtn_b64 */, AMDGPU::DS_CMPST_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12484 { 2031 /* ds_cmpst_rtn_b64 */, AMDGPU::DS_CMPST_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12485 { 2031 /* ds_cmpst_rtn_b64 */, AMDGPU::DS_CMPST_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12486 { 2048 /* ds_cmpst_rtn_f32 */, AMDGPU::DS_CMPST_RTN_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12487 { 2048 /* ds_cmpst_rtn_f32 */, AMDGPU::DS_CMPST_RTN_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12488 { 2048 /* ds_cmpst_rtn_f32 */, AMDGPU::DS_CMPST_RTN_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12489 { 2065 /* ds_cmpst_rtn_f64 */, AMDGPU::DS_CMPST_RTN_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12490 { 2065 /* ds_cmpst_rtn_f64 */, AMDGPU::DS_CMPST_RTN_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12491 { 2065 /* ds_cmpst_rtn_f64 */, AMDGPU::DS_CMPST_RTN_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12492 { 2082 /* ds_condxchg32_rtn_b64 */, AMDGPU::DS_CONDXCHG32_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12493 { 2082 /* ds_condxchg32_rtn_b64 */, AMDGPU::DS_CONDXCHG32_RTN_B64_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12494 { 2082 /* ds_condxchg32_rtn_b64 */, AMDGPU::DS_CONDXCHG32_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12495 { 2104 /* ds_consume */, AMDGPU::DS_CONSUME_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12496 { 2104 /* ds_consume */, AMDGPU::DS_CONSUME_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12497 { 2104 /* ds_consume */, AMDGPU::DS_CONSUME_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12498 { 2115 /* ds_dec_rtn_u32 */, AMDGPU::DS_DEC_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12499 { 2115 /* ds_dec_rtn_u32 */, AMDGPU::DS_DEC_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12500 { 2115 /* ds_dec_rtn_u32 */, AMDGPU::DS_DEC_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12501 { 2130 /* ds_dec_rtn_u64 */, AMDGPU::DS_DEC_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12502 { 2130 /* ds_dec_rtn_u64 */, AMDGPU::DS_DEC_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12503 { 2130 /* ds_dec_rtn_u64 */, AMDGPU::DS_DEC_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12504 { 2145 /* ds_dec_src2_u32 */, AMDGPU::DS_DEC_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12505 { 2145 /* ds_dec_src2_u32 */, AMDGPU::DS_DEC_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12506 { 2145 /* ds_dec_src2_u32 */, AMDGPU::DS_DEC_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12507 { 2161 /* ds_dec_src2_u64 */, AMDGPU::DS_DEC_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12508 { 2161 /* ds_dec_src2_u64 */, AMDGPU::DS_DEC_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12509 { 2161 /* ds_dec_src2_u64 */, AMDGPU::DS_DEC_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12510 { 2177 /* ds_dec_u32 */, AMDGPU::DS_DEC_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12511 { 2177 /* ds_dec_u32 */, AMDGPU::DS_DEC_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12512 { 2177 /* ds_dec_u32 */, AMDGPU::DS_DEC_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12513 { 2188 /* ds_dec_u64 */, AMDGPU::DS_DEC_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12514 { 2188 /* ds_dec_u64 */, AMDGPU::DS_DEC_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12515 { 2188 /* ds_dec_u64 */, AMDGPU::DS_DEC_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12516 { 2199 /* ds_gws_barrier */, AMDGPU::DS_GWS_BARRIER_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12517 { 2199 /* ds_gws_barrier */, AMDGPU::DS_GWS_BARRIER_gfx6_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12518 { 2199 /* ds_gws_barrier */, AMDGPU::DS_GWS_BARRIER_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12519 { 2214 /* ds_gws_init */, AMDGPU::DS_GWS_INIT_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12520 { 2214 /* ds_gws_init */, AMDGPU::DS_GWS_INIT_gfx6_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12521 { 2214 /* ds_gws_init */, AMDGPU::DS_GWS_INIT_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12522 { 2226 /* ds_gws_sema_br */, AMDGPU::DS_GWS_SEMA_BR_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12523 { 2226 /* ds_gws_sema_br */, AMDGPU::DS_GWS_SEMA_BR_gfx6_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12524 { 2226 /* ds_gws_sema_br */, AMDGPU::DS_GWS_SEMA_BR_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12525 { 2241 /* ds_gws_sema_p */, AMDGPU::DS_GWS_SEMA_P_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX10Plus, { MCK_ImmOffset, MCK_gds }, },
12526 { 2241 /* ds_gws_sema_p */, AMDGPU::DS_GWS_SEMA_P_gfx6_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX6GFX7, { MCK_ImmOffset, MCK_gds }, },
12527 { 2241 /* ds_gws_sema_p */, AMDGPU::DS_GWS_SEMA_P_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX8GFX9, { MCK_ImmOffset, MCK_gds }, },
12528 { 2255 /* ds_gws_sema_release_all */, AMDGPU::DS_GWS_SEMA_RELEASE_ALL_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_ImmOffset, MCK_gds }, },
12529 { 2255 /* ds_gws_sema_release_all */, AMDGPU::DS_GWS_SEMA_RELEASE_ALL_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX7Plus_isGFX7Only, { MCK_ImmOffset, MCK_gds }, },
12530 { 2255 /* ds_gws_sema_release_all */, AMDGPU::DS_GWS_SEMA_RELEASE_ALL_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_ImmOffset, MCK_gds }, },
12531 { 2279 /* ds_gws_sema_v */, AMDGPU::DS_GWS_SEMA_V_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX10Plus, { MCK_ImmOffset, MCK_gds }, },
12532 { 2279 /* ds_gws_sema_v */, AMDGPU::DS_GWS_SEMA_V_gfx6_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX6GFX7, { MCK_ImmOffset, MCK_gds }, },
12533 { 2279 /* ds_gws_sema_v */, AMDGPU::DS_GWS_SEMA_V_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX8GFX9, { MCK_ImmOffset, MCK_gds }, },
12534 { 2293 /* ds_inc_rtn_u32 */, AMDGPU::DS_INC_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12535 { 2293 /* ds_inc_rtn_u32 */, AMDGPU::DS_INC_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12536 { 2293 /* ds_inc_rtn_u32 */, AMDGPU::DS_INC_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12537 { 2308 /* ds_inc_rtn_u64 */, AMDGPU::DS_INC_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12538 { 2308 /* ds_inc_rtn_u64 */, AMDGPU::DS_INC_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12539 { 2308 /* ds_inc_rtn_u64 */, AMDGPU::DS_INC_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12540 { 2323 /* ds_inc_src2_u32 */, AMDGPU::DS_INC_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12541 { 2323 /* ds_inc_src2_u32 */, AMDGPU::DS_INC_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12542 { 2323 /* ds_inc_src2_u32 */, AMDGPU::DS_INC_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12543 { 2339 /* ds_inc_src2_u64 */, AMDGPU::DS_INC_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12544 { 2339 /* ds_inc_src2_u64 */, AMDGPU::DS_INC_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12545 { 2339 /* ds_inc_src2_u64 */, AMDGPU::DS_INC_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12546 { 2355 /* ds_inc_u32 */, AMDGPU::DS_INC_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12547 { 2355 /* ds_inc_u32 */, AMDGPU::DS_INC_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12548 { 2355 /* ds_inc_u32 */, AMDGPU::DS_INC_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12549 { 2366 /* ds_inc_u64 */, AMDGPU::DS_INC_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12550 { 2366 /* ds_inc_u64 */, AMDGPU::DS_INC_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12551 { 2366 /* ds_inc_u64 */, AMDGPU::DS_INC_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12552 { 2377 /* ds_max_f32 */, AMDGPU::DS_MAX_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12553 { 2377 /* ds_max_f32 */, AMDGPU::DS_MAX_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12554 { 2377 /* ds_max_f32 */, AMDGPU::DS_MAX_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12555 { 2388 /* ds_max_f64 */, AMDGPU::DS_MAX_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12556 { 2388 /* ds_max_f64 */, AMDGPU::DS_MAX_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12557 { 2388 /* ds_max_f64 */, AMDGPU::DS_MAX_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12558 { 2399 /* ds_max_i32 */, AMDGPU::DS_MAX_I32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12559 { 2399 /* ds_max_i32 */, AMDGPU::DS_MAX_I32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12560 { 2399 /* ds_max_i32 */, AMDGPU::DS_MAX_I32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12561 { 2410 /* ds_max_i64 */, AMDGPU::DS_MAX_I64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12562 { 2410 /* ds_max_i64 */, AMDGPU::DS_MAX_I64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12563 { 2410 /* ds_max_i64 */, AMDGPU::DS_MAX_I64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12564 { 2421 /* ds_max_rtn_f32 */, AMDGPU::DS_MAX_RTN_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12565 { 2421 /* ds_max_rtn_f32 */, AMDGPU::DS_MAX_RTN_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12566 { 2421 /* ds_max_rtn_f32 */, AMDGPU::DS_MAX_RTN_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12567 { 2436 /* ds_max_rtn_f64 */, AMDGPU::DS_MAX_RTN_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12568 { 2436 /* ds_max_rtn_f64 */, AMDGPU::DS_MAX_RTN_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12569 { 2436 /* ds_max_rtn_f64 */, AMDGPU::DS_MAX_RTN_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12570 { 2451 /* ds_max_rtn_i32 */, AMDGPU::DS_MAX_RTN_I32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12571 { 2451 /* ds_max_rtn_i32 */, AMDGPU::DS_MAX_RTN_I32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12572 { 2451 /* ds_max_rtn_i32 */, AMDGPU::DS_MAX_RTN_I32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12573 { 2466 /* ds_max_rtn_i64 */, AMDGPU::DS_MAX_RTN_I64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12574 { 2466 /* ds_max_rtn_i64 */, AMDGPU::DS_MAX_RTN_I64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12575 { 2466 /* ds_max_rtn_i64 */, AMDGPU::DS_MAX_RTN_I64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12576 { 2481 /* ds_max_rtn_u32 */, AMDGPU::DS_MAX_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12577 { 2481 /* ds_max_rtn_u32 */, AMDGPU::DS_MAX_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12578 { 2481 /* ds_max_rtn_u32 */, AMDGPU::DS_MAX_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12579 { 2496 /* ds_max_rtn_u64 */, AMDGPU::DS_MAX_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12580 { 2496 /* ds_max_rtn_u64 */, AMDGPU::DS_MAX_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12581 { 2496 /* ds_max_rtn_u64 */, AMDGPU::DS_MAX_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12582 { 2511 /* ds_max_src2_f32 */, AMDGPU::DS_MAX_SRC2_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12583 { 2511 /* ds_max_src2_f32 */, AMDGPU::DS_MAX_SRC2_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12584 { 2511 /* ds_max_src2_f32 */, AMDGPU::DS_MAX_SRC2_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12585 { 2527 /* ds_max_src2_f64 */, AMDGPU::DS_MAX_SRC2_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12586 { 2527 /* ds_max_src2_f64 */, AMDGPU::DS_MAX_SRC2_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12587 { 2527 /* ds_max_src2_f64 */, AMDGPU::DS_MAX_SRC2_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12588 { 2543 /* ds_max_src2_i32 */, AMDGPU::DS_MAX_SRC2_I32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12589 { 2543 /* ds_max_src2_i32 */, AMDGPU::DS_MAX_SRC2_I32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12590 { 2543 /* ds_max_src2_i32 */, AMDGPU::DS_MAX_SRC2_I32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12591 { 2559 /* ds_max_src2_i64 */, AMDGPU::DS_MAX_SRC2_I64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12592 { 2559 /* ds_max_src2_i64 */, AMDGPU::DS_MAX_SRC2_I64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12593 { 2559 /* ds_max_src2_i64 */, AMDGPU::DS_MAX_SRC2_I64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12594 { 2575 /* ds_max_src2_u32 */, AMDGPU::DS_MAX_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12595 { 2575 /* ds_max_src2_u32 */, AMDGPU::DS_MAX_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12596 { 2575 /* ds_max_src2_u32 */, AMDGPU::DS_MAX_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12597 { 2591 /* ds_max_src2_u64 */, AMDGPU::DS_MAX_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12598 { 2591 /* ds_max_src2_u64 */, AMDGPU::DS_MAX_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12599 { 2591 /* ds_max_src2_u64 */, AMDGPU::DS_MAX_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12600 { 2607 /* ds_max_u32 */, AMDGPU::DS_MAX_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12601 { 2607 /* ds_max_u32 */, AMDGPU::DS_MAX_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12602 { 2607 /* ds_max_u32 */, AMDGPU::DS_MAX_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12603 { 2618 /* ds_max_u64 */, AMDGPU::DS_MAX_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12604 { 2618 /* ds_max_u64 */, AMDGPU::DS_MAX_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12605 { 2618 /* ds_max_u64 */, AMDGPU::DS_MAX_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12606 { 2629 /* ds_min_f32 */, AMDGPU::DS_MIN_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12607 { 2629 /* ds_min_f32 */, AMDGPU::DS_MIN_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12608 { 2629 /* ds_min_f32 */, AMDGPU::DS_MIN_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12609 { 2640 /* ds_min_f64 */, AMDGPU::DS_MIN_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12610 { 2640 /* ds_min_f64 */, AMDGPU::DS_MIN_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12611 { 2640 /* ds_min_f64 */, AMDGPU::DS_MIN_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12612 { 2651 /* ds_min_i32 */, AMDGPU::DS_MIN_I32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12613 { 2651 /* ds_min_i32 */, AMDGPU::DS_MIN_I32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12614 { 2651 /* ds_min_i32 */, AMDGPU::DS_MIN_I32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12615 { 2662 /* ds_min_i64 */, AMDGPU::DS_MIN_I64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12616 { 2662 /* ds_min_i64 */, AMDGPU::DS_MIN_I64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12617 { 2662 /* ds_min_i64 */, AMDGPU::DS_MIN_I64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12618 { 2673 /* ds_min_rtn_f32 */, AMDGPU::DS_MIN_RTN_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12619 { 2673 /* ds_min_rtn_f32 */, AMDGPU::DS_MIN_RTN_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12620 { 2673 /* ds_min_rtn_f32 */, AMDGPU::DS_MIN_RTN_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12621 { 2688 /* ds_min_rtn_f64 */, AMDGPU::DS_MIN_RTN_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12622 { 2688 /* ds_min_rtn_f64 */, AMDGPU::DS_MIN_RTN_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12623 { 2688 /* ds_min_rtn_f64 */, AMDGPU::DS_MIN_RTN_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12624 { 2703 /* ds_min_rtn_i32 */, AMDGPU::DS_MIN_RTN_I32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12625 { 2703 /* ds_min_rtn_i32 */, AMDGPU::DS_MIN_RTN_I32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12626 { 2703 /* ds_min_rtn_i32 */, AMDGPU::DS_MIN_RTN_I32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12627 { 2718 /* ds_min_rtn_i64 */, AMDGPU::DS_MIN_RTN_I64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12628 { 2718 /* ds_min_rtn_i64 */, AMDGPU::DS_MIN_RTN_I64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12629 { 2718 /* ds_min_rtn_i64 */, AMDGPU::DS_MIN_RTN_I64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12630 { 2733 /* ds_min_rtn_u32 */, AMDGPU::DS_MIN_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12631 { 2733 /* ds_min_rtn_u32 */, AMDGPU::DS_MIN_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12632 { 2733 /* ds_min_rtn_u32 */, AMDGPU::DS_MIN_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12633 { 2748 /* ds_min_rtn_u64 */, AMDGPU::DS_MIN_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12634 { 2748 /* ds_min_rtn_u64 */, AMDGPU::DS_MIN_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12635 { 2748 /* ds_min_rtn_u64 */, AMDGPU::DS_MIN_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12636 { 2763 /* ds_min_src2_f32 */, AMDGPU::DS_MIN_SRC2_F32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12637 { 2763 /* ds_min_src2_f32 */, AMDGPU::DS_MIN_SRC2_F32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12638 { 2763 /* ds_min_src2_f32 */, AMDGPU::DS_MIN_SRC2_F32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12639 { 2779 /* ds_min_src2_f64 */, AMDGPU::DS_MIN_SRC2_F64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12640 { 2779 /* ds_min_src2_f64 */, AMDGPU::DS_MIN_SRC2_F64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12641 { 2779 /* ds_min_src2_f64 */, AMDGPU::DS_MIN_SRC2_F64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12642 { 2795 /* ds_min_src2_i32 */, AMDGPU::DS_MIN_SRC2_I32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12643 { 2795 /* ds_min_src2_i32 */, AMDGPU::DS_MIN_SRC2_I32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12644 { 2795 /* ds_min_src2_i32 */, AMDGPU::DS_MIN_SRC2_I32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12645 { 2811 /* ds_min_src2_i64 */, AMDGPU::DS_MIN_SRC2_I64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12646 { 2811 /* ds_min_src2_i64 */, AMDGPU::DS_MIN_SRC2_I64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12647 { 2811 /* ds_min_src2_i64 */, AMDGPU::DS_MIN_SRC2_I64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12648 { 2827 /* ds_min_src2_u32 */, AMDGPU::DS_MIN_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12649 { 2827 /* ds_min_src2_u32 */, AMDGPU::DS_MIN_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12650 { 2827 /* ds_min_src2_u32 */, AMDGPU::DS_MIN_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12651 { 2843 /* ds_min_src2_u64 */, AMDGPU::DS_MIN_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12652 { 2843 /* ds_min_src2_u64 */, AMDGPU::DS_MIN_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12653 { 2843 /* ds_min_src2_u64 */, AMDGPU::DS_MIN_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12654 { 2859 /* ds_min_u32 */, AMDGPU::DS_MIN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12655 { 2859 /* ds_min_u32 */, AMDGPU::DS_MIN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12656 { 2859 /* ds_min_u32 */, AMDGPU::DS_MIN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12657 { 2870 /* ds_min_u64 */, AMDGPU::DS_MIN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12658 { 2870 /* ds_min_u64 */, AMDGPU::DS_MIN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12659 { 2870 /* ds_min_u64 */, AMDGPU::DS_MIN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12660 { 2881 /* ds_mskor_b32 */, AMDGPU::DS_MSKOR_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12661 { 2881 /* ds_mskor_b32 */, AMDGPU::DS_MSKOR_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12662 { 2881 /* ds_mskor_b32 */, AMDGPU::DS_MSKOR_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12663 { 2894 /* ds_mskor_b64 */, AMDGPU::DS_MSKOR_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12664 { 2894 /* ds_mskor_b64 */, AMDGPU::DS_MSKOR_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12665 { 2894 /* ds_mskor_b64 */, AMDGPU::DS_MSKOR_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12666 { 2907 /* ds_mskor_rtn_b32 */, AMDGPU::DS_MSKOR_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12667 { 2907 /* ds_mskor_rtn_b32 */, AMDGPU::DS_MSKOR_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12668 { 2907 /* ds_mskor_rtn_b32 */, AMDGPU::DS_MSKOR_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12669 { 2924 /* ds_mskor_rtn_b64 */, AMDGPU::DS_MSKOR_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12670 { 2924 /* ds_mskor_rtn_b64 */, AMDGPU::DS_MSKOR_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12671 { 2924 /* ds_mskor_rtn_b64 */, AMDGPU::DS_MSKOR_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12675 { 2948 /* ds_or_b32 */, AMDGPU::DS_OR_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12676 { 2948 /* ds_or_b32 */, AMDGPU::DS_OR_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12677 { 2948 /* ds_or_b32 */, AMDGPU::DS_OR_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12678 { 2958 /* ds_or_b64 */, AMDGPU::DS_OR_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12679 { 2958 /* ds_or_b64 */, AMDGPU::DS_OR_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12680 { 2958 /* ds_or_b64 */, AMDGPU::DS_OR_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12681 { 2968 /* ds_or_rtn_b32 */, AMDGPU::DS_OR_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12682 { 2968 /* ds_or_rtn_b32 */, AMDGPU::DS_OR_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12683 { 2968 /* ds_or_rtn_b32 */, AMDGPU::DS_OR_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12684 { 2982 /* ds_or_rtn_b64 */, AMDGPU::DS_OR_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12685 { 2982 /* ds_or_rtn_b64 */, AMDGPU::DS_OR_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12686 { 2982 /* ds_or_rtn_b64 */, AMDGPU::DS_OR_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12687 { 2996 /* ds_or_src2_b32 */, AMDGPU::DS_OR_SRC2_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12688 { 2996 /* ds_or_src2_b32 */, AMDGPU::DS_OR_SRC2_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12689 { 2996 /* ds_or_src2_b32 */, AMDGPU::DS_OR_SRC2_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12690 { 3011 /* ds_or_src2_b64 */, AMDGPU::DS_OR_SRC2_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12691 { 3011 /* ds_or_src2_b64 */, AMDGPU::DS_OR_SRC2_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12692 { 3011 /* ds_or_src2_b64 */, AMDGPU::DS_OR_SRC2_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12693 { 3026 /* ds_ordered_count */, AMDGPU::DS_ORDERED_COUNT_gfx10, ConvertCustom_cvtDSGds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12694 { 3026 /* ds_ordered_count */, AMDGPU::DS_ORDERED_COUNT_gfx6_gfx7, ConvertCustom_cvtDSGds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12695 { 3026 /* ds_ordered_count */, AMDGPU::DS_ORDERED_COUNT_vi, ConvertCustom_cvtDSGds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
12696 { 3043 /* ds_permute_b32 */, AMDGPU::DS_PERMUTE_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset }, },
12697 { 3043 /* ds_permute_b32 */, AMDGPU::DS_PERMUTE_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset }, },
12710 { 3118 /* ds_read_addtid_b32 */, AMDGPU::DS_READ_ADDTID_B32_gfx10, ConvertCustom_cvtDS, AMFBS_HasDSAddTid_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12711 { 3118 /* ds_read_addtid_b32 */, AMDGPU::DS_READ_ADDTID_B32_vi, ConvertCustom_cvtDS, AMFBS_HasDSAddTid_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12712 { 3137 /* ds_read_b128 */, AMDGPU::DS_READ_B128_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12713 { 3137 /* ds_read_b128 */, AMDGPU::DS_READ_B128_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12714 { 3137 /* ds_read_b128 */, AMDGPU::DS_READ_B128_vi, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12715 { 3150 /* ds_read_b32 */, AMDGPU::DS_READ_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12716 { 3150 /* ds_read_b32 */, AMDGPU::DS_READ_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12717 { 3150 /* ds_read_b32 */, AMDGPU::DS_READ_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12718 { 3162 /* ds_read_b64 */, AMDGPU::DS_READ_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12719 { 3162 /* ds_read_b64 */, AMDGPU::DS_READ_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12720 { 3162 /* ds_read_b64 */, AMDGPU::DS_READ_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12721 { 3174 /* ds_read_b96 */, AMDGPU::DS_READ_B96_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12722 { 3174 /* ds_read_b96 */, AMDGPU::DS_READ_B96_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_96, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12723 { 3174 /* ds_read_b96 */, AMDGPU::DS_READ_B96_vi, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12724 { 3186 /* ds_read_i16 */, AMDGPU::DS_READ_I16_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12725 { 3186 /* ds_read_i16 */, AMDGPU::DS_READ_I16_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12726 { 3186 /* ds_read_i16 */, AMDGPU::DS_READ_I16_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12727 { 3198 /* ds_read_i8 */, AMDGPU::DS_READ_I8_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12728 { 3198 /* ds_read_i8 */, AMDGPU::DS_READ_I8_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12729 { 3198 /* ds_read_i8 */, AMDGPU::DS_READ_I8_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12730 { 3209 /* ds_read_i8_d16 */, AMDGPU::DS_READ_I8_D16_gfx10, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12731 { 3209 /* ds_read_i8_d16 */, AMDGPU::DS_READ_I8_D16_vi, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12732 { 3224 /* ds_read_i8_d16_hi */, AMDGPU::DS_READ_I8_D16_HI_gfx10, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12733 { 3224 /* ds_read_i8_d16_hi */, AMDGPU::DS_READ_I8_D16_HI_vi, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12734 { 3242 /* ds_read_u16 */, AMDGPU::DS_READ_U16_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12735 { 3242 /* ds_read_u16 */, AMDGPU::DS_READ_U16_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12736 { 3242 /* ds_read_u16 */, AMDGPU::DS_READ_U16_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12737 { 3254 /* ds_read_u16_d16 */, AMDGPU::DS_READ_U16_D16_gfx10, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12738 { 3254 /* ds_read_u16_d16 */, AMDGPU::DS_READ_U16_D16_vi, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12739 { 3270 /* ds_read_u16_d16_hi */, AMDGPU::DS_READ_U16_D16_HI_gfx10, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12740 { 3270 /* ds_read_u16_d16_hi */, AMDGPU::DS_READ_U16_D16_HI_vi, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12741 { 3289 /* ds_read_u8 */, AMDGPU::DS_READ_U8_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12742 { 3289 /* ds_read_u8 */, AMDGPU::DS_READ_U8_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12743 { 3289 /* ds_read_u8 */, AMDGPU::DS_READ_U8_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12744 { 3300 /* ds_read_u8_d16 */, AMDGPU::DS_READ_U8_D16_gfx10, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12745 { 3300 /* ds_read_u8_d16 */, AMDGPU::DS_READ_U8_D16_vi, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12746 { 3315 /* ds_read_u8_d16_hi */, AMDGPU::DS_READ_U8_D16_HI_gfx10, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12747 { 3315 /* ds_read_u8_d16_hi */, AMDGPU::DS_READ_U8_D16_HI_vi, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12748 { 3333 /* ds_rsub_rtn_u32 */, AMDGPU::DS_RSUB_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12749 { 3333 /* ds_rsub_rtn_u32 */, AMDGPU::DS_RSUB_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12750 { 3333 /* ds_rsub_rtn_u32 */, AMDGPU::DS_RSUB_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12751 { 3349 /* ds_rsub_rtn_u64 */, AMDGPU::DS_RSUB_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12752 { 3349 /* ds_rsub_rtn_u64 */, AMDGPU::DS_RSUB_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12753 { 3349 /* ds_rsub_rtn_u64 */, AMDGPU::DS_RSUB_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12754 { 3365 /* ds_rsub_src2_u32 */, AMDGPU::DS_RSUB_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12755 { 3365 /* ds_rsub_src2_u32 */, AMDGPU::DS_RSUB_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12756 { 3365 /* ds_rsub_src2_u32 */, AMDGPU::DS_RSUB_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12757 { 3382 /* ds_rsub_src2_u64 */, AMDGPU::DS_RSUB_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12758 { 3382 /* ds_rsub_src2_u64 */, AMDGPU::DS_RSUB_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12759 { 3382 /* ds_rsub_src2_u64 */, AMDGPU::DS_RSUB_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12760 { 3399 /* ds_rsub_u32 */, AMDGPU::DS_RSUB_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12761 { 3399 /* ds_rsub_u32 */, AMDGPU::DS_RSUB_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12762 { 3399 /* ds_rsub_u32 */, AMDGPU::DS_RSUB_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12763 { 3411 /* ds_rsub_u64 */, AMDGPU::DS_RSUB_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12764 { 3411 /* ds_rsub_u64 */, AMDGPU::DS_RSUB_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12765 { 3411 /* ds_rsub_u64 */, AMDGPU::DS_RSUB_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12766 { 3423 /* ds_sub_rtn_u32 */, AMDGPU::DS_SUB_RTN_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12767 { 3423 /* ds_sub_rtn_u32 */, AMDGPU::DS_SUB_RTN_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12768 { 3423 /* ds_sub_rtn_u32 */, AMDGPU::DS_SUB_RTN_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12769 { 3438 /* ds_sub_rtn_u64 */, AMDGPU::DS_SUB_RTN_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12770 { 3438 /* ds_sub_rtn_u64 */, AMDGPU::DS_SUB_RTN_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12771 { 3438 /* ds_sub_rtn_u64 */, AMDGPU::DS_SUB_RTN_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12772 { 3453 /* ds_sub_src2_u32 */, AMDGPU::DS_SUB_SRC2_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12773 { 3453 /* ds_sub_src2_u32 */, AMDGPU::DS_SUB_SRC2_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12774 { 3453 /* ds_sub_src2_u32 */, AMDGPU::DS_SUB_SRC2_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12775 { 3469 /* ds_sub_src2_u64 */, AMDGPU::DS_SUB_SRC2_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12776 { 3469 /* ds_sub_src2_u64 */, AMDGPU::DS_SUB_SRC2_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12777 { 3469 /* ds_sub_src2_u64 */, AMDGPU::DS_SUB_SRC2_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12778 { 3485 /* ds_sub_u32 */, AMDGPU::DS_SUB_U32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12779 { 3485 /* ds_sub_u32 */, AMDGPU::DS_SUB_U32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12780 { 3485 /* ds_sub_u32 */, AMDGPU::DS_SUB_U32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12781 { 3496 /* ds_sub_u64 */, AMDGPU::DS_SUB_U64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12782 { 3496 /* ds_sub_u64 */, AMDGPU::DS_SUB_U64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12783 { 3496 /* ds_sub_u64 */, AMDGPU::DS_SUB_U64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12787 { 3522 /* ds_wrap_rtn_b32 */, AMDGPU::DS_WRAP_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12788 { 3522 /* ds_wrap_rtn_b32 */, AMDGPU::DS_WRAP_RTN_B32_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12789 { 3522 /* ds_wrap_rtn_b32 */, AMDGPU::DS_WRAP_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12802 { 3602 /* ds_write_addtid_b32 */, AMDGPU::DS_WRITE_ADDTID_B32_gfx10, ConvertCustom_cvtDS, AMFBS_HasDSAddTid_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12803 { 3602 /* ds_write_addtid_b32 */, AMDGPU::DS_WRITE_ADDTID_B32_vi, ConvertCustom_cvtDS, AMFBS_HasDSAddTid_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12804 { 3622 /* ds_write_b128 */, AMDGPU::DS_WRITE_B128_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_ImmOffset, MCK_ImmGDS }, },
12805 { 3622 /* ds_write_b128 */, AMDGPU::DS_WRITE_B128_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VGPR_32, MCK_VReg_128, MCK_ImmOffset, MCK_ImmGDS }, },
12806 { 3622 /* ds_write_b128 */, AMDGPU::DS_WRITE_B128_vi, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_ImmOffset, MCK_ImmGDS }, },
12807 { 3636 /* ds_write_b16 */, AMDGPU::DS_WRITE_B16_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12808 { 3636 /* ds_write_b16 */, AMDGPU::DS_WRITE_B16_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12809 { 3636 /* ds_write_b16 */, AMDGPU::DS_WRITE_B16_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12810 { 3649 /* ds_write_b16_d16_hi */, AMDGPU::DS_WRITE_B16_D16_HI_gfx10, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12811 { 3649 /* ds_write_b16_d16_hi */, AMDGPU::DS_WRITE_B16_D16_HI_vi, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12812 { 3669 /* ds_write_b32 */, AMDGPU::DS_WRITE_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12813 { 3669 /* ds_write_b32 */, AMDGPU::DS_WRITE_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12814 { 3669 /* ds_write_b32 */, AMDGPU::DS_WRITE_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12815 { 3682 /* ds_write_b64 */, AMDGPU::DS_WRITE_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12816 { 3682 /* ds_write_b64 */, AMDGPU::DS_WRITE_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12817 { 3682 /* ds_write_b64 */, AMDGPU::DS_WRITE_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12818 { 3695 /* ds_write_b8 */, AMDGPU::DS_WRITE_B8_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12819 { 3695 /* ds_write_b8 */, AMDGPU::DS_WRITE_B8_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12820 { 3695 /* ds_write_b8 */, AMDGPU::DS_WRITE_B8_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12821 { 3707 /* ds_write_b8_d16_hi */, AMDGPU::DS_WRITE_B8_D16_HI_gfx10, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12822 { 3707 /* ds_write_b8_d16_hi */, AMDGPU::DS_WRITE_B8_D16_HI_vi, ConvertCustom_cvtDS, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12823 { 3726 /* ds_write_b96 */, AMDGPU::DS_WRITE_B96_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_ImmOffset, MCK_ImmGDS }, },
12824 { 3726 /* ds_write_b96 */, AMDGPU::DS_WRITE_B96_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VGPR_32, MCK_VReg_96, MCK_ImmOffset, MCK_ImmGDS }, },
12825 { 3726 /* ds_write_b96 */, AMDGPU::DS_WRITE_B96_vi, ConvertCustom_cvtDS, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_ImmOffset, MCK_ImmGDS }, },
12826 { 3739 /* ds_write_src2_b32 */, AMDGPU::DS_WRITE_SRC2_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12827 { 3739 /* ds_write_src2_b32 */, AMDGPU::DS_WRITE_SRC2_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12828 { 3739 /* ds_write_src2_b32 */, AMDGPU::DS_WRITE_SRC2_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12829 { 3757 /* ds_write_src2_b64 */, AMDGPU::DS_WRITE_SRC2_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12830 { 3757 /* ds_write_src2_b64 */, AMDGPU::DS_WRITE_SRC2_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12831 { 3757 /* ds_write_src2_b64 */, AMDGPU::DS_WRITE_SRC2_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12844 { 3859 /* ds_wrxchg_rtn_b32 */, AMDGPU::DS_WRXCHG_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12845 { 3859 /* ds_wrxchg_rtn_b32 */, AMDGPU::DS_WRXCHG_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12846 { 3859 /* ds_wrxchg_rtn_b32 */, AMDGPU::DS_WRXCHG_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12847 { 3877 /* ds_wrxchg_rtn_b64 */, AMDGPU::DS_WRXCHG_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12848 { 3877 /* ds_wrxchg_rtn_b64 */, AMDGPU::DS_WRXCHG_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12849 { 3877 /* ds_wrxchg_rtn_b64 */, AMDGPU::DS_WRXCHG_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12850 { 3895 /* ds_xor_b32 */, AMDGPU::DS_XOR_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12851 { 3895 /* ds_xor_b32 */, AMDGPU::DS_XOR_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12852 { 3895 /* ds_xor_b32 */, AMDGPU::DS_XOR_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12853 { 3906 /* ds_xor_b64 */, AMDGPU::DS_XOR_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12854 { 3906 /* ds_xor_b64 */, AMDGPU::DS_XOR_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12855 { 3906 /* ds_xor_b64 */, AMDGPU::DS_XOR_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12856 { 3917 /* ds_xor_rtn_b32 */, AMDGPU::DS_XOR_RTN_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12857 { 3917 /* ds_xor_rtn_b32 */, AMDGPU::DS_XOR_RTN_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12858 { 3917 /* ds_xor_rtn_b32 */, AMDGPU::DS_XOR_RTN_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12859 { 3932 /* ds_xor_rtn_b64 */, AMDGPU::DS_XOR_RTN_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12860 { 3932 /* ds_xor_rtn_b64 */, AMDGPU::DS_XOR_RTN_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12861 { 3932 /* ds_xor_rtn_b64 */, AMDGPU::DS_XOR_RTN_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
12862 { 3947 /* ds_xor_src2_b32 */, AMDGPU::DS_XOR_SRC2_B32_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12863 { 3947 /* ds_xor_src2_b32 */, AMDGPU::DS_XOR_SRC2_B32_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12864 { 3947 /* ds_xor_src2_b32 */, AMDGPU::DS_XOR_SRC2_B32_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12865 { 3963 /* ds_xor_src2_b64 */, AMDGPU::DS_XOR_SRC2_B64_gfx10, ConvertCustom_cvtDS, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12866 { 3963 /* ds_xor_src2_b64 */, AMDGPU::DS_XOR_SRC2_B64_gfx6_gfx7, ConvertCustom_cvtDS, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
12867 { 3963 /* ds_xor_src2_b64 */, AMDGPU::DS_XOR_SRC2_B64_vi, ConvertCustom_cvtDS, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
18651 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18652 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18653 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18654 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18655 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18656 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18657 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18658 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18659 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18660 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18661 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18662 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18663 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18664 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18665 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18666 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18667 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18668 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18669 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18670 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18671 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18672 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18673 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18674 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18675 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18676 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18677 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18678 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18679 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18680 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18681 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18682 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18683 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18684 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18685 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18686 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18687 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18688 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18689 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18690 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18691 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18692 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18693 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18694 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18695 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18696 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18697 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18698 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18699 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18700 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18701 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18702 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18703 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18704 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18705 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18706 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18707 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18708 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18709 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18710 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18711 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18712 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18713 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18714 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18715 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18716 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18717 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18718 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18719 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18720 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18721 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18722 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18723 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18724 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18725 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18726 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18727 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18728 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18729 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18730 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18731 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18732 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18733 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18734 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18735 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18736 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18737 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18738 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18739 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18740 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18741 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18742 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18743 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18744 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18745 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18746 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18747 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18748 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18749 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18750 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18751 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18752 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18753 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18754 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18755 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18756 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18757 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18758 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18759 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18760 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18761 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18762 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18763 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18764 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18765 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18766 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18767 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18768 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18769 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18770 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18771 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18772 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18773 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18774 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18775 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18776 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18777 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18778 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18779 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18780 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18781 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18782 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18783 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18784 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18785 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18786 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18787 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18788 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18789 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18790 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18791 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18792 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18793 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18794 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18795 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18796 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18797 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18798 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18799 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18800 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18801 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18802 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18803 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18804 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18805 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18806 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18807 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18808 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18809 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18810 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18811 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18812 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18813 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18814 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18815 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18816 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18817 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18818 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18819 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18820 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18821 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18822 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18823 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18824 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18825 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18826 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18827 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18828 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18829 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18830 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18831 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18832 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18833 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18834 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18835 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18836 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18837 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18838 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18839 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18840 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18841 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18842 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18843 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18844 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18845 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18846 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18847 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18848 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18849 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18850 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
24157 { 0 /* buffer_atomic_add */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24159 { 0 /* buffer_atomic_add */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24161 { 0 /* buffer_atomic_add */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24163 { 0 /* buffer_atomic_add */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24165 { 0 /* buffer_atomic_add */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24167 { 0 /* buffer_atomic_add */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24169 { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24171 { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24173 { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24175 { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24177 { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24179 { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24181 { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24183 { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24185 { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24187 { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24189 { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24191 { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24193 { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24195 { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24197 { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24199 { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24201 { 0 /* buffer_atomic_add */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24203 { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24205 { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24207 { 0 /* buffer_atomic_add */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24209 { 18 /* buffer_atomic_add_f32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
24211 { 18 /* buffer_atomic_add_f32 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
24213 { 18 /* buffer_atomic_add_f32 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
24215 { 18 /* buffer_atomic_add_f32 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
24217 { 40 /* buffer_atomic_add_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24219 { 40 /* buffer_atomic_add_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24221 { 40 /* buffer_atomic_add_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24223 { 40 /* buffer_atomic_add_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24225 { 40 /* buffer_atomic_add_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24227 { 40 /* buffer_atomic_add_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24229 { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24231 { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24233 { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24235 { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24237 { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24239 { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24241 { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24243 { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24245 { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24247 { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24249 { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24251 { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24253 { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24255 { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24257 { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24259 { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24261 { 40 /* buffer_atomic_add_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24263 { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24265 { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24267 { 40 /* buffer_atomic_add_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24269 { 61 /* buffer_atomic_and */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24271 { 61 /* buffer_atomic_and */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24273 { 61 /* buffer_atomic_and */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24275 { 61 /* buffer_atomic_and */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24277 { 61 /* buffer_atomic_and */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24279 { 61 /* buffer_atomic_and */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24281 { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24283 { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24285 { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24287 { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24289 { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24291 { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24293 { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24295 { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24297 { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24299 { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24301 { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24303 { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24305 { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24307 { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24309 { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24311 { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24313 { 61 /* buffer_atomic_and */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24315 { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24317 { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24319 { 61 /* buffer_atomic_and */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24321 { 79 /* buffer_atomic_and_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24323 { 79 /* buffer_atomic_and_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24325 { 79 /* buffer_atomic_and_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24327 { 79 /* buffer_atomic_and_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24329 { 79 /* buffer_atomic_and_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24331 { 79 /* buffer_atomic_and_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24333 { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24335 { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24337 { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24339 { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24341 { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24343 { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24345 { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24347 { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24349 { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24351 { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24353 { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24355 { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24357 { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24359 { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24361 { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24363 { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24365 { 79 /* buffer_atomic_and_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24367 { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24369 { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24371 { 79 /* buffer_atomic_and_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24373 { 100 /* buffer_atomic_cmpswap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24375 { 100 /* buffer_atomic_cmpswap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24377 { 100 /* buffer_atomic_cmpswap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24379 { 100 /* buffer_atomic_cmpswap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24381 { 100 /* buffer_atomic_cmpswap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24383 { 100 /* buffer_atomic_cmpswap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24385 { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24387 { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24389 { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24391 { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24393 { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24395 { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24397 { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24399 { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24401 { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24403 { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24405 { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24407 { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24409 { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24411 { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24413 { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24415 { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24417 { 100 /* buffer_atomic_cmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24419 { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24421 { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24423 { 100 /* buffer_atomic_cmpswap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24425 { 122 /* buffer_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24427 { 122 /* buffer_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24429 { 122 /* buffer_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24431 { 122 /* buffer_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24433 { 122 /* buffer_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24435 { 122 /* buffer_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24437 { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24439 { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24441 { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24443 { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24445 { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24447 { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24449 { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24451 { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24453 { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24455 { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24457 { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24459 { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24461 { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24463 { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24465 { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24467 { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24469 { 122 /* buffer_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24471 { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24473 { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24475 { 122 /* buffer_atomic_cmpswap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24477 { 147 /* buffer_atomic_dec */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24479 { 147 /* buffer_atomic_dec */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24481 { 147 /* buffer_atomic_dec */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24483 { 147 /* buffer_atomic_dec */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24485 { 147 /* buffer_atomic_dec */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24487 { 147 /* buffer_atomic_dec */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24489 { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24491 { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24493 { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24495 { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24497 { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24499 { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24501 { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24503 { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24505 { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24507 { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24509 { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24511 { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24513 { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24515 { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24517 { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24519 { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24521 { 147 /* buffer_atomic_dec */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24523 { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24525 { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24527 { 147 /* buffer_atomic_dec */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24529 { 165 /* buffer_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24531 { 165 /* buffer_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24533 { 165 /* buffer_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24535 { 165 /* buffer_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24537 { 165 /* buffer_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24539 { 165 /* buffer_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24541 { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24543 { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24545 { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24547 { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24549 { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24551 { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24553 { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24555 { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24557 { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24559 { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24561 { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24563 { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24565 { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24567 { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24569 { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24571 { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24573 { 165 /* buffer_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24575 { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24577 { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24579 { 165 /* buffer_atomic_dec_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24581 { 186 /* buffer_atomic_fcmpswap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24583 { 186 /* buffer_atomic_fcmpswap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24585 { 186 /* buffer_atomic_fcmpswap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24587 { 186 /* buffer_atomic_fcmpswap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24589 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24591 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24593 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24595 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24597 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24599 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24601 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24603 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24605 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24607 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24609 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24611 { 186 /* buffer_atomic_fcmpswap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24613 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24615 { 186 /* buffer_atomic_fcmpswap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24617 { 209 /* buffer_atomic_fcmpswap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24619 { 209 /* buffer_atomic_fcmpswap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24621 { 209 /* buffer_atomic_fcmpswap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24623 { 209 /* buffer_atomic_fcmpswap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24625 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24627 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24629 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24631 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24633 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24635 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24637 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24639 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24641 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24643 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24645 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24647 { 209 /* buffer_atomic_fcmpswap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24649 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24651 { 209 /* buffer_atomic_fcmpswap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24653 { 235 /* buffer_atomic_fmax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24655 { 235 /* buffer_atomic_fmax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24657 { 235 /* buffer_atomic_fmax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24659 { 235 /* buffer_atomic_fmax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24661 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24663 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24665 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24667 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24669 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24671 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24673 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24675 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24677 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24679 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24681 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24683 { 235 /* buffer_atomic_fmax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24685 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24687 { 235 /* buffer_atomic_fmax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24689 { 254 /* buffer_atomic_fmax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24691 { 254 /* buffer_atomic_fmax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24693 { 254 /* buffer_atomic_fmax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24695 { 254 /* buffer_atomic_fmax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24697 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24699 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24701 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24703 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24705 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24707 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24709 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24711 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24713 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24715 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24717 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24719 { 254 /* buffer_atomic_fmax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24721 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24723 { 254 /* buffer_atomic_fmax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24725 { 276 /* buffer_atomic_fmin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24727 { 276 /* buffer_atomic_fmin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24729 { 276 /* buffer_atomic_fmin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24731 { 276 /* buffer_atomic_fmin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24733 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24735 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24737 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24739 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24741 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24743 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24745 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24747 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24749 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24751 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24753 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24755 { 276 /* buffer_atomic_fmin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24757 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24759 { 276 /* buffer_atomic_fmin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24761 { 295 /* buffer_atomic_fmin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24763 { 295 /* buffer_atomic_fmin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24765 { 295 /* buffer_atomic_fmin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24767 { 295 /* buffer_atomic_fmin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24769 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24771 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24773 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24775 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24777 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24779 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24781 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24783 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24785 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24787 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24789 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24791 { 295 /* buffer_atomic_fmin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24793 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
24795 { 295 /* buffer_atomic_fmin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
24797 { 317 /* buffer_atomic_inc */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24799 { 317 /* buffer_atomic_inc */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24801 { 317 /* buffer_atomic_inc */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24803 { 317 /* buffer_atomic_inc */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24805 { 317 /* buffer_atomic_inc */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24807 { 317 /* buffer_atomic_inc */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24809 { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24811 { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24813 { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24815 { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24817 { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24819 { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24821 { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24823 { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24825 { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24827 { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24829 { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24831 { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24833 { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24835 { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24837 { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24839 { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24841 { 317 /* buffer_atomic_inc */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24843 { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24845 { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24847 { 317 /* buffer_atomic_inc */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24849 { 335 /* buffer_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24851 { 335 /* buffer_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24853 { 335 /* buffer_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24855 { 335 /* buffer_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24857 { 335 /* buffer_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24859 { 335 /* buffer_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24861 { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24863 { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24865 { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24867 { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24869 { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24871 { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24873 { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24875 { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24877 { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24879 { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24881 { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24883 { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24885 { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24887 { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24889 { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24891 { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24893 { 335 /* buffer_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24895 { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24897 { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24899 { 335 /* buffer_atomic_inc_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24901 { 356 /* buffer_atomic_or */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24903 { 356 /* buffer_atomic_or */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24905 { 356 /* buffer_atomic_or */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24907 { 356 /* buffer_atomic_or */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24909 { 356 /* buffer_atomic_or */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24911 { 356 /* buffer_atomic_or */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24913 { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24915 { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24917 { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24919 { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24921 { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24923 { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24925 { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24927 { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24929 { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24931 { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24933 { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24935 { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24937 { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24939 { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24941 { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24943 { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24945 { 356 /* buffer_atomic_or */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24947 { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24949 { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24951 { 356 /* buffer_atomic_or */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24953 { 373 /* buffer_atomic_or_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24955 { 373 /* buffer_atomic_or_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24957 { 373 /* buffer_atomic_or_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24959 { 373 /* buffer_atomic_or_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24961 { 373 /* buffer_atomic_or_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24963 { 373 /* buffer_atomic_or_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24965 { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24967 { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24969 { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24971 { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24973 { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24975 { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24977 { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24979 { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24981 { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24983 { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24985 { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24987 { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24989 { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24991 { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24993 { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
24995 { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
24997 { 373 /* buffer_atomic_or_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
24999 { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25001 { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25003 { 373 /* buffer_atomic_or_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25005 { 393 /* buffer_atomic_pk_add_f16 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
25007 { 393 /* buffer_atomic_pk_add_f16 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
25009 { 393 /* buffer_atomic_pk_add_f16 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
25011 { 393 /* buffer_atomic_pk_add_f16 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
25013 { 418 /* buffer_atomic_smax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25015 { 418 /* buffer_atomic_smax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25017 { 418 /* buffer_atomic_smax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25019 { 418 /* buffer_atomic_smax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25021 { 418 /* buffer_atomic_smax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25023 { 418 /* buffer_atomic_smax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25025 { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25027 { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25029 { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25031 { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25033 { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25035 { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25037 { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25039 { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25041 { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25043 { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25045 { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25047 { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25049 { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25051 { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25053 { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25055 { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25057 { 418 /* buffer_atomic_smax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25059 { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25061 { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25063 { 418 /* buffer_atomic_smax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25065 { 437 /* buffer_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25067 { 437 /* buffer_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25069 { 437 /* buffer_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25071 { 437 /* buffer_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25073 { 437 /* buffer_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25075 { 437 /* buffer_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25077 { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25079 { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25081 { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25083 { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25085 { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25087 { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25089 { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25091 { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25093 { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25095 { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25097 { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25099 { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25101 { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25103 { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25105 { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25107 { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25109 { 437 /* buffer_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25111 { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25113 { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25115 { 437 /* buffer_atomic_smax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25117 { 459 /* buffer_atomic_smin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25119 { 459 /* buffer_atomic_smin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25121 { 459 /* buffer_atomic_smin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25123 { 459 /* buffer_atomic_smin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25125 { 459 /* buffer_atomic_smin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25127 { 459 /* buffer_atomic_smin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25129 { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25131 { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25133 { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25135 { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25137 { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25139 { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25141 { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25143 { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25145 { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25147 { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25149 { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25151 { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25153 { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25155 { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25157 { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25159 { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25161 { 459 /* buffer_atomic_smin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25163 { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25165 { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25167 { 459 /* buffer_atomic_smin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25169 { 478 /* buffer_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25171 { 478 /* buffer_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25173 { 478 /* buffer_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25175 { 478 /* buffer_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25177 { 478 /* buffer_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25179 { 478 /* buffer_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25181 { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25183 { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25185 { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25187 { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25189 { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25191 { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25193 { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25195 { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25197 { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25199 { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25201 { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25203 { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25205 { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25207 { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25209 { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25211 { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25213 { 478 /* buffer_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25215 { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25217 { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25219 { 478 /* buffer_atomic_smin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25221 { 500 /* buffer_atomic_sub */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25223 { 500 /* buffer_atomic_sub */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25225 { 500 /* buffer_atomic_sub */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25227 { 500 /* buffer_atomic_sub */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25229 { 500 /* buffer_atomic_sub */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25231 { 500 /* buffer_atomic_sub */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25233 { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25235 { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25237 { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25239 { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25241 { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25243 { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25245 { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25247 { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25249 { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25251 { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25253 { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25255 { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25257 { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25259 { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25261 { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25263 { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25265 { 500 /* buffer_atomic_sub */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25267 { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25269 { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25271 { 500 /* buffer_atomic_sub */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25273 { 518 /* buffer_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25275 { 518 /* buffer_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25277 { 518 /* buffer_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25279 { 518 /* buffer_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25281 { 518 /* buffer_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25283 { 518 /* buffer_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25285 { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25287 { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25289 { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25291 { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25293 { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25295 { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25297 { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25299 { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25301 { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25303 { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25305 { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25307 { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25309 { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25311 { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25313 { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25315 { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25317 { 518 /* buffer_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25319 { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25321 { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25323 { 518 /* buffer_atomic_sub_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25325 { 539 /* buffer_atomic_swap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25327 { 539 /* buffer_atomic_swap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25329 { 539 /* buffer_atomic_swap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25331 { 539 /* buffer_atomic_swap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25333 { 539 /* buffer_atomic_swap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25335 { 539 /* buffer_atomic_swap */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25337 { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25339 { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25341 { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25343 { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25345 { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25347 { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25349 { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25351 { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25353 { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25355 { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25357 { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25359 { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25361 { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25363 { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25365 { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25367 { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25369 { 539 /* buffer_atomic_swap */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25371 { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25373 { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25375 { 539 /* buffer_atomic_swap */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25377 { 558 /* buffer_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25379 { 558 /* buffer_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25381 { 558 /* buffer_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25383 { 558 /* buffer_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25385 { 558 /* buffer_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25387 { 558 /* buffer_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25389 { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25391 { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25393 { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25395 { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25397 { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25399 { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25401 { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25403 { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25405 { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25407 { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25409 { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25411 { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25413 { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25415 { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25417 { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25419 { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25421 { 558 /* buffer_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25423 { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25425 { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25427 { 558 /* buffer_atomic_swap_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25429 { 580 /* buffer_atomic_umax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25431 { 580 /* buffer_atomic_umax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25433 { 580 /* buffer_atomic_umax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25435 { 580 /* buffer_atomic_umax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25437 { 580 /* buffer_atomic_umax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25439 { 580 /* buffer_atomic_umax */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25441 { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25443 { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25445 { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25447 { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25449 { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25451 { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25453 { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25455 { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25457 { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25459 { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25461 { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25463 { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25465 { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25467 { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25469 { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25471 { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25473 { 580 /* buffer_atomic_umax */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25475 { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25477 { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25479 { 580 /* buffer_atomic_umax */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25481 { 599 /* buffer_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25483 { 599 /* buffer_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25485 { 599 /* buffer_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25487 { 599 /* buffer_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25489 { 599 /* buffer_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25491 { 599 /* buffer_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25493 { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25495 { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25497 { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25499 { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25501 { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25503 { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25505 { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25507 { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25509 { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25511 { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25513 { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25515 { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25517 { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25519 { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25521 { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25523 { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25525 { 599 /* buffer_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25527 { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25529 { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25531 { 599 /* buffer_atomic_umax_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25533 { 621 /* buffer_atomic_umin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25535 { 621 /* buffer_atomic_umin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25537 { 621 /* buffer_atomic_umin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25539 { 621 /* buffer_atomic_umin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25541 { 621 /* buffer_atomic_umin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25543 { 621 /* buffer_atomic_umin */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25545 { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25547 { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25549 { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25551 { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25553 { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25555 { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25557 { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25559 { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25561 { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25563 { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25565 { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25567 { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25569 { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25571 { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25573 { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25575 { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25577 { 621 /* buffer_atomic_umin */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25579 { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25581 { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25583 { 621 /* buffer_atomic_umin */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25585 { 640 /* buffer_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25587 { 640 /* buffer_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25589 { 640 /* buffer_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25591 { 640 /* buffer_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25593 { 640 /* buffer_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25595 { 640 /* buffer_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25597 { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25599 { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25601 { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25603 { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25605 { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25607 { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25609 { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25611 { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25613 { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25615 { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25617 { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25619 { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25621 { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25623 { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25625 { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25627 { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25629 { 640 /* buffer_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25631 { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25633 { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25635 { 640 /* buffer_atomic_umin_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25637 { 662 /* buffer_atomic_xor */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25639 { 662 /* buffer_atomic_xor */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25641 { 662 /* buffer_atomic_xor */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25643 { 662 /* buffer_atomic_xor */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25645 { 662 /* buffer_atomic_xor */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25647 { 662 /* buffer_atomic_xor */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25649 { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25651 { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25653 { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25655 { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25657 { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25659 { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25661 { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25663 { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25665 { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25667 { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25669 { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25671 { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25673 { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25675 { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25677 { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25679 { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25681 { 662 /* buffer_atomic_xor */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25683 { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25685 { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25687 { 662 /* buffer_atomic_xor */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25689 { 680 /* buffer_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25691 { 680 /* buffer_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25693 { 680 /* buffer_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25695 { 680 /* buffer_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25697 { 680 /* buffer_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25699 { 680 /* buffer_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25701 { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25703 { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25705 { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25707 { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25709 { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25711 { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25713 { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25715 { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25717 { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25719 { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25721 { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25723 { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25725 { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25727 { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25729 { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25731 { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25733 { 680 /* buffer_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25735 { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25737 { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25739 { 680 /* buffer_atomic_xor_x2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25741 { 731 /* buffer_load_dword */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25746 { 731 /* buffer_load_dword */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25751 { 731 /* buffer_load_dword */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25756 { 731 /* buffer_load_dword */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25762 { 731 /* buffer_load_dword */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25768 { 731 /* buffer_load_dword */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25774 { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25779 { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25785 { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25790 { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25795 { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25800 { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25806 { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25812 { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25818 { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25823 { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25828 { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25833 { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25839 { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25845 { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25851 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25856 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25861 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25866 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25872 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25878 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25884 { 749 /* buffer_load_dwordx2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9_isGFX8GFX9 },
25889 { 749 /* buffer_load_dwordx2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25895 { 749 /* buffer_load_dwordx2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25901 { 749 /* buffer_load_dwordx2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25907 { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25913 { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9_isGFX8GFX9 },
25918 { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25924 { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25930 { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25936 { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9_isGFX8GFX9 },
25941 { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25947 { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25953 { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25959 { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9_isGFX8GFX9 },
25964 { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25970 { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25976 { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
25982 { 769 /* buffer_load_dwordx3 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9_isGFX8GFX9 },
25987 { 769 /* buffer_load_dwordx3 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
25993 { 769 /* buffer_load_dwordx3 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
25999 { 769 /* buffer_load_dwordx3 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26005 { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26011 { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26016 { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26022 { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26028 { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26034 { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26039 { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26045 { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26051 { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26057 { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26062 { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26068 { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26074 { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26080 { 789 /* buffer_load_dwordx4 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26085 { 789 /* buffer_load_dwordx4 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26091 { 789 /* buffer_load_dwordx4 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26097 { 789 /* buffer_load_dwordx4 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26103 { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26109 { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26114 { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26120 { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26126 { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26132 { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26137 { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26143 { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26149 { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26155 { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26160 { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26166 { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26172 { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26178 { 809 /* buffer_load_format_d16_hi_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
26184 { 809 /* buffer_load_format_d16_hi_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
26190 { 809 /* buffer_load_format_d16_hi_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
26196 { 809 /* buffer_load_format_d16_hi_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
26202 { 837 /* buffer_load_format_d16_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
26208 { 837 /* buffer_load_format_d16_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26214 { 837 /* buffer_load_format_d16_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26220 { 837 /* buffer_load_format_d16_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
26226 { 837 /* buffer_load_format_d16_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26232 { 837 /* buffer_load_format_d16_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26238 { 837 /* buffer_load_format_d16_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
26244 { 837 /* buffer_load_format_d16_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26250 { 837 /* buffer_load_format_d16_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26256 { 837 /* buffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
26262 { 837 /* buffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26268 { 837 /* buffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26274 { 862 /* buffer_load_format_d16_xy */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26280 { 862 /* buffer_load_format_d16_xy */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
26286 { 862 /* buffer_load_format_d16_xy */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26292 { 862 /* buffer_load_format_d16_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26298 { 862 /* buffer_load_format_d16_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26304 { 862 /* buffer_load_format_d16_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
26310 { 862 /* buffer_load_format_d16_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26316 { 862 /* buffer_load_format_d16_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
26322 { 862 /* buffer_load_format_d16_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26328 { 862 /* buffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26334 { 862 /* buffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
26340 { 862 /* buffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26346 { 888 /* buffer_load_format_d16_xyz */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26352 { 888 /* buffer_load_format_d16_xyz */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
26358 { 888 /* buffer_load_format_d16_xyz */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26364 { 888 /* buffer_load_format_d16_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26370 { 888 /* buffer_load_format_d16_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26376 { 888 /* buffer_load_format_d16_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
26382 { 888 /* buffer_load_format_d16_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26388 { 888 /* buffer_load_format_d16_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
26394 { 888 /* buffer_load_format_d16_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26400 { 888 /* buffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26406 { 888 /* buffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
26412 { 888 /* buffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26418 { 915 /* buffer_load_format_d16_xyzw */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26424 { 915 /* buffer_load_format_d16_xyzw */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
26430 { 915 /* buffer_load_format_d16_xyzw */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26436 { 915 /* buffer_load_format_d16_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26442 { 915 /* buffer_load_format_d16_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26448 { 915 /* buffer_load_format_d16_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
26454 { 915 /* buffer_load_format_d16_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26460 { 915 /* buffer_load_format_d16_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
26466 { 915 /* buffer_load_format_d16_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26472 { 915 /* buffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26478 { 915 /* buffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
26484 { 915 /* buffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26490 { 943 /* buffer_load_format_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26495 { 943 /* buffer_load_format_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26500 { 943 /* buffer_load_format_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26505 { 943 /* buffer_load_format_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26511 { 943 /* buffer_load_format_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26517 { 943 /* buffer_load_format_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26523 { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26528 { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26534 { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26539 { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26544 { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26549 { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26555 { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26561 { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26567 { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26572 { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26577 { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26582 { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26588 { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26594 { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26600 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26605 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26610 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26615 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26621 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26627 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26633 { 964 /* buffer_load_format_xy */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26639 { 964 /* buffer_load_format_xy */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26645 { 964 /* buffer_load_format_xy */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26651 { 964 /* buffer_load_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26657 { 964 /* buffer_load_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26663 { 964 /* buffer_load_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26669 { 964 /* buffer_load_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26675 { 964 /* buffer_load_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26681 { 964 /* buffer_load_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26687 { 964 /* buffer_load_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26693 { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26699 { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26705 { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26711 { 986 /* buffer_load_format_xyz */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26717 { 986 /* buffer_load_format_xyz */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26723 { 986 /* buffer_load_format_xyz */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26729 { 986 /* buffer_load_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26735 { 986 /* buffer_load_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26741 { 986 /* buffer_load_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26747 { 986 /* buffer_load_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26753 { 986 /* buffer_load_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26759 { 986 /* buffer_load_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26765 { 986 /* buffer_load_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26771 { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26777 { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26783 { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26789 { 1009 /* buffer_load_format_xyzw */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26795 { 1009 /* buffer_load_format_xyzw */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26801 { 1009 /* buffer_load_format_xyzw */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26807 { 1009 /* buffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26813 { 1009 /* buffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26819 { 1009 /* buffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26825 { 1009 /* buffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26831 { 1009 /* buffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26837 { 1009 /* buffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26843 { 1009 /* buffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26849 { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26855 { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26861 { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26867 { 1033 /* buffer_load_sbyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26872 { 1033 /* buffer_load_sbyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26877 { 1033 /* buffer_load_sbyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26882 { 1033 /* buffer_load_sbyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26888 { 1033 /* buffer_load_sbyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26894 { 1033 /* buffer_load_sbyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26900 { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26905 { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26911 { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26916 { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26921 { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26926 { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26932 { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26938 { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26944 { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26949 { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26954 { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26959 { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26965 { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26971 { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26977 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26982 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
26987 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
26992 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
26998 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27004 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27010 { 1051 /* buffer_load_sbyte_d16 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27016 { 1051 /* buffer_load_sbyte_d16 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27022 { 1051 /* buffer_load_sbyte_d16 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27028 { 1051 /* buffer_load_sbyte_d16 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27034 { 1051 /* buffer_load_sbyte_d16 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27040 { 1051 /* buffer_load_sbyte_d16 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27046 { 1051 /* buffer_load_sbyte_d16 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27052 { 1051 /* buffer_load_sbyte_d16 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27058 { 1073 /* buffer_load_sbyte_d16_hi */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27064 { 1073 /* buffer_load_sbyte_d16_hi */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27070 { 1073 /* buffer_load_sbyte_d16_hi */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27076 { 1073 /* buffer_load_sbyte_d16_hi */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27082 { 1073 /* buffer_load_sbyte_d16_hi */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27088 { 1073 /* buffer_load_sbyte_d16_hi */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27094 { 1073 /* buffer_load_sbyte_d16_hi */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27100 { 1073 /* buffer_load_sbyte_d16_hi */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27106 { 1098 /* buffer_load_short_d16 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27112 { 1098 /* buffer_load_short_d16 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27118 { 1098 /* buffer_load_short_d16 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27124 { 1098 /* buffer_load_short_d16 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27130 { 1098 /* buffer_load_short_d16 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27136 { 1098 /* buffer_load_short_d16 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27142 { 1098 /* buffer_load_short_d16 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27148 { 1098 /* buffer_load_short_d16 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27154 { 1120 /* buffer_load_short_d16_hi */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27160 { 1120 /* buffer_load_short_d16_hi */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27166 { 1120 /* buffer_load_short_d16_hi */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27172 { 1120 /* buffer_load_short_d16_hi */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27178 { 1120 /* buffer_load_short_d16_hi */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27184 { 1120 /* buffer_load_short_d16_hi */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27190 { 1120 /* buffer_load_short_d16_hi */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27196 { 1120 /* buffer_load_short_d16_hi */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27202 { 1145 /* buffer_load_sshort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27207 { 1145 /* buffer_load_sshort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27212 { 1145 /* buffer_load_sshort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27217 { 1145 /* buffer_load_sshort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27223 { 1145 /* buffer_load_sshort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27229 { 1145 /* buffer_load_sshort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27235 { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27240 { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27246 { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27251 { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27256 { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27261 { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27267 { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27273 { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27279 { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27284 { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27289 { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27294 { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27300 { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27306 { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27312 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27317 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27322 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27327 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27333 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27339 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27345 { 1164 /* buffer_load_ubyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27350 { 1164 /* buffer_load_ubyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27355 { 1164 /* buffer_load_ubyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27360 { 1164 /* buffer_load_ubyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27366 { 1164 /* buffer_load_ubyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27372 { 1164 /* buffer_load_ubyte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27378 { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27383 { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27389 { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27394 { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27399 { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27404 { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27410 { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27416 { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27422 { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27427 { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27432 { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27437 { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27443 { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27449 { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27455 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27460 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27465 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27470 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27476 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27482 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27488 { 1182 /* buffer_load_ubyte_d16 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27494 { 1182 /* buffer_load_ubyte_d16 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27500 { 1182 /* buffer_load_ubyte_d16 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27506 { 1182 /* buffer_load_ubyte_d16 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27512 { 1182 /* buffer_load_ubyte_d16 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27518 { 1182 /* buffer_load_ubyte_d16 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27524 { 1182 /* buffer_load_ubyte_d16 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27530 { 1182 /* buffer_load_ubyte_d16 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27536 { 1204 /* buffer_load_ubyte_d16_hi */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27542 { 1204 /* buffer_load_ubyte_d16_hi */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27548 { 1204 /* buffer_load_ubyte_d16_hi */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27554 { 1204 /* buffer_load_ubyte_d16_hi */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27560 { 1204 /* buffer_load_ubyte_d16_hi */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27566 { 1204 /* buffer_load_ubyte_d16_hi */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27572 { 1204 /* buffer_load_ubyte_d16_hi */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27578 { 1204 /* buffer_load_ubyte_d16_hi */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27584 { 1229 /* buffer_load_ushort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27589 { 1229 /* buffer_load_ushort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27594 { 1229 /* buffer_load_ushort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27599 { 1229 /* buffer_load_ushort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27605 { 1229 /* buffer_load_ushort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27611 { 1229 /* buffer_load_ushort */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27617 { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27622 { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27628 { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27633 { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27638 { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27643 { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27649 { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27655 { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27661 { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27666 { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27671 { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27676 { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27682 { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27688 { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27694 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27699 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27704 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27709 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27715 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27721 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27727 { 1248 /* buffer_store_byte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27733 { 1248 /* buffer_store_byte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27739 { 1248 /* buffer_store_byte */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27745 { 1248 /* buffer_store_byte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27751 { 1248 /* buffer_store_byte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27757 { 1248 /* buffer_store_byte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27763 { 1248 /* buffer_store_byte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27769 { 1248 /* buffer_store_byte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27775 { 1248 /* buffer_store_byte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27781 { 1248 /* buffer_store_byte */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27787 { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27793 { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27799 { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27805 { 1266 /* buffer_store_byte_d16_hi */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27811 { 1266 /* buffer_store_byte_d16_hi */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27817 { 1266 /* buffer_store_byte_d16_hi */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27823 { 1266 /* buffer_store_byte_d16_hi */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27829 { 1266 /* buffer_store_byte_d16_hi */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27835 { 1266 /* buffer_store_byte_d16_hi */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27841 { 1266 /* buffer_store_byte_d16_hi */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
27847 { 1266 /* buffer_store_byte_d16_hi */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27853 { 1291 /* buffer_store_dword */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27859 { 1291 /* buffer_store_dword */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27865 { 1291 /* buffer_store_dword */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27871 { 1291 /* buffer_store_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27877 { 1291 /* buffer_store_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27883 { 1291 /* buffer_store_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27889 { 1291 /* buffer_store_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27895 { 1291 /* buffer_store_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27901 { 1291 /* buffer_store_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27907 { 1291 /* buffer_store_dword */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27913 { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27919 { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27925 { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27931 { 1310 /* buffer_store_dwordx2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27937 { 1310 /* buffer_store_dwordx2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27943 { 1310 /* buffer_store_dwordx2 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27949 { 1310 /* buffer_store_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27955 { 1310 /* buffer_store_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27961 { 1310 /* buffer_store_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27967 { 1310 /* buffer_store_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27973 { 1310 /* buffer_store_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27979 { 1310 /* buffer_store_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
27985 { 1310 /* buffer_store_dwordx2 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
27991 { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
27997 { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28003 { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28009 { 1331 /* buffer_store_dwordx3 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28015 { 1331 /* buffer_store_dwordx3 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28021 { 1331 /* buffer_store_dwordx3 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28027 { 1331 /* buffer_store_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28033 { 1331 /* buffer_store_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28039 { 1331 /* buffer_store_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28045 { 1331 /* buffer_store_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28051 { 1331 /* buffer_store_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28057 { 1331 /* buffer_store_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28063 { 1331 /* buffer_store_dwordx3 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28069 { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28075 { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28081 { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28087 { 1352 /* buffer_store_dwordx4 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28093 { 1352 /* buffer_store_dwordx4 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28099 { 1352 /* buffer_store_dwordx4 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28105 { 1352 /* buffer_store_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28111 { 1352 /* buffer_store_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28117 { 1352 /* buffer_store_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28123 { 1352 /* buffer_store_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28129 { 1352 /* buffer_store_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28135 { 1352 /* buffer_store_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28141 { 1352 /* buffer_store_dwordx4 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28147 { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28153 { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28159 { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28165 { 1373 /* buffer_store_format_d16_hi_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28171 { 1373 /* buffer_store_format_d16_hi_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28177 { 1373 /* buffer_store_format_d16_hi_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28183 { 1373 /* buffer_store_format_d16_hi_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28189 { 1402 /* buffer_store_format_d16_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
28195 { 1402 /* buffer_store_format_d16_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28201 { 1402 /* buffer_store_format_d16_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28207 { 1402 /* buffer_store_format_d16_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
28213 { 1402 /* buffer_store_format_d16_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28219 { 1402 /* buffer_store_format_d16_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28225 { 1402 /* buffer_store_format_d16_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
28231 { 1402 /* buffer_store_format_d16_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28237 { 1402 /* buffer_store_format_d16_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28243 { 1402 /* buffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
28249 { 1402 /* buffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28255 { 1402 /* buffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28261 { 1428 /* buffer_store_format_d16_xy */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28267 { 1428 /* buffer_store_format_d16_xy */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
28273 { 1428 /* buffer_store_format_d16_xy */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28279 { 1428 /* buffer_store_format_d16_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28285 { 1428 /* buffer_store_format_d16_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28291 { 1428 /* buffer_store_format_d16_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
28297 { 1428 /* buffer_store_format_d16_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28303 { 1428 /* buffer_store_format_d16_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
28309 { 1428 /* buffer_store_format_d16_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28315 { 1428 /* buffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28321 { 1428 /* buffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
28327 { 1428 /* buffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28333 { 1455 /* buffer_store_format_d16_xyz */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28339 { 1455 /* buffer_store_format_d16_xyz */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
28345 { 1455 /* buffer_store_format_d16_xyz */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28351 { 1455 /* buffer_store_format_d16_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28357 { 1455 /* buffer_store_format_d16_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28363 { 1455 /* buffer_store_format_d16_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
28369 { 1455 /* buffer_store_format_d16_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28375 { 1455 /* buffer_store_format_d16_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
28381 { 1455 /* buffer_store_format_d16_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28387 { 1455 /* buffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28393 { 1455 /* buffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
28399 { 1455 /* buffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28405 { 1483 /* buffer_store_format_d16_xyzw */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28411 { 1483 /* buffer_store_format_d16_xyzw */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
28417 { 1483 /* buffer_store_format_d16_xyzw */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28423 { 1483 /* buffer_store_format_d16_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28429 { 1483 /* buffer_store_format_d16_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28435 { 1483 /* buffer_store_format_d16_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
28441 { 1483 /* buffer_store_format_d16_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28447 { 1483 /* buffer_store_format_d16_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
28453 { 1483 /* buffer_store_format_d16_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28459 { 1483 /* buffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28465 { 1483 /* buffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
28471 { 1483 /* buffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28477 { 1512 /* buffer_store_format_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28483 { 1512 /* buffer_store_format_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28489 { 1512 /* buffer_store_format_x */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28495 { 1512 /* buffer_store_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28501 { 1512 /* buffer_store_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28507 { 1512 /* buffer_store_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28513 { 1512 /* buffer_store_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28519 { 1512 /* buffer_store_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28525 { 1512 /* buffer_store_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28531 { 1512 /* buffer_store_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28537 { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28543 { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28549 { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28555 { 1534 /* buffer_store_format_xy */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28561 { 1534 /* buffer_store_format_xy */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28567 { 1534 /* buffer_store_format_xy */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28573 { 1534 /* buffer_store_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28579 { 1534 /* buffer_store_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28585 { 1534 /* buffer_store_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28591 { 1534 /* buffer_store_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28597 { 1534 /* buffer_store_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28603 { 1534 /* buffer_store_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28609 { 1534 /* buffer_store_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28615 { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28621 { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28627 { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28633 { 1557 /* buffer_store_format_xyz */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28639 { 1557 /* buffer_store_format_xyz */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28645 { 1557 /* buffer_store_format_xyz */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28651 { 1557 /* buffer_store_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28657 { 1557 /* buffer_store_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28663 { 1557 /* buffer_store_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28669 { 1557 /* buffer_store_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28675 { 1557 /* buffer_store_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28681 { 1557 /* buffer_store_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28687 { 1557 /* buffer_store_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28693 { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28699 { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28705 { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28711 { 1581 /* buffer_store_format_xyzw */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28717 { 1581 /* buffer_store_format_xyzw */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28723 { 1581 /* buffer_store_format_xyzw */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28729 { 1581 /* buffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28735 { 1581 /* buffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28741 { 1581 /* buffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28747 { 1581 /* buffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28753 { 1581 /* buffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28759 { 1581 /* buffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28765 { 1581 /* buffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28771 { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28777 { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28783 { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28789 { 1606 /* buffer_store_lds_dword */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9_isGFX8GFX9 },
28793 { 1629 /* buffer_store_short */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28799 { 1629 /* buffer_store_short */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28805 { 1629 /* buffer_store_short */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28811 { 1629 /* buffer_store_short */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28817 { 1629 /* buffer_store_short */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28823 { 1629 /* buffer_store_short */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28829 { 1629 /* buffer_store_short */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28835 { 1629 /* buffer_store_short */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28841 { 1629 /* buffer_store_short */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28847 { 1629 /* buffer_store_short */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28853 { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28859 { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28865 { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28871 { 1648 /* buffer_store_short_d16_hi */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
28877 { 1648 /* buffer_store_short_d16_hi */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28883 { 1648 /* buffer_store_short_d16_hi */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
28889 { 1648 /* buffer_store_short_d16_hi */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28895 { 1648 /* buffer_store_short_d16_hi */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
28901 { 1648 /* buffer_store_short_d16_hi */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28907 { 1648 /* buffer_store_short_d16_hi */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
28913 { 1648 /* buffer_store_short_d16_hi */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28919 { 1726 /* ds_add_f32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28921 { 1726 /* ds_add_f32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28923 { 1737 /* ds_add_rtn_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28925 { 1737 /* ds_add_rtn_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28927 { 1752 /* ds_add_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28929 { 1752 /* ds_add_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28931 { 1752 /* ds_add_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28933 { 1767 /* ds_add_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28935 { 1767 /* ds_add_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28937 { 1767 /* ds_add_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28939 { 1782 /* ds_add_src2_f32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8Plus_isGFX10Plus },
28941 { 1782 /* ds_add_src2_f32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8Plus_isGFX8GFX9 },
28943 { 1798 /* ds_add_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28945 { 1798 /* ds_add_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28947 { 1798 /* ds_add_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28949 { 1814 /* ds_add_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28951 { 1814 /* ds_add_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28953 { 1814 /* ds_add_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28955 { 1830 /* ds_add_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28957 { 1830 /* ds_add_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28959 { 1830 /* ds_add_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28961 { 1841 /* ds_add_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28963 { 1841 /* ds_add_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28965 { 1841 /* ds_add_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28967 { 1852 /* ds_and_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28969 { 1852 /* ds_and_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28971 { 1852 /* ds_and_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28973 { 1863 /* ds_and_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28975 { 1863 /* ds_and_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28977 { 1863 /* ds_and_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28979 { 1874 /* ds_and_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28981 { 1874 /* ds_and_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28983 { 1874 /* ds_and_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28985 { 1889 /* ds_and_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28987 { 1889 /* ds_and_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28989 { 1889 /* ds_and_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28991 { 1904 /* ds_and_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28993 { 1904 /* ds_and_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
28995 { 1904 /* ds_and_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
28997 { 1920 /* ds_and_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
28999 { 1920 /* ds_and_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29001 { 1920 /* ds_and_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29003 { 1936 /* ds_append */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29005 { 1936 /* ds_append */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29007 { 1936 /* ds_append */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29009 { 1946 /* ds_bpermute_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8Plus_isGFX10Plus },
29010 { 1946 /* ds_bpermute_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8Plus_isGFX8GFX9 },
29011 { 1962 /* ds_cmpst_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29013 { 1962 /* ds_cmpst_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29015 { 1962 /* ds_cmpst_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29017 { 1975 /* ds_cmpst_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29019 { 1975 /* ds_cmpst_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29021 { 1975 /* ds_cmpst_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29023 { 1988 /* ds_cmpst_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29025 { 1988 /* ds_cmpst_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29027 { 1988 /* ds_cmpst_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29029 { 2001 /* ds_cmpst_f64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29031 { 2001 /* ds_cmpst_f64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29033 { 2001 /* ds_cmpst_f64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29035 { 2014 /* ds_cmpst_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29037 { 2014 /* ds_cmpst_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29039 { 2014 /* ds_cmpst_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29041 { 2031 /* ds_cmpst_rtn_b64 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29043 { 2031 /* ds_cmpst_rtn_b64 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29045 { 2031 /* ds_cmpst_rtn_b64 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29047 { 2048 /* ds_cmpst_rtn_f32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29049 { 2048 /* ds_cmpst_rtn_f32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29051 { 2048 /* ds_cmpst_rtn_f32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29053 { 2065 /* ds_cmpst_rtn_f64 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29055 { 2065 /* ds_cmpst_rtn_f64 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29057 { 2065 /* ds_cmpst_rtn_f64 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29059 { 2082 /* ds_condxchg32_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX10Plus },
29061 { 2082 /* ds_condxchg32_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX7Only },
29063 { 2082 /* ds_condxchg32_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX8GFX9 },
29065 { 2104 /* ds_consume */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29067 { 2104 /* ds_consume */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29069 { 2104 /* ds_consume */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29071 { 2115 /* ds_dec_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29073 { 2115 /* ds_dec_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29075 { 2115 /* ds_dec_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29077 { 2130 /* ds_dec_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29079 { 2130 /* ds_dec_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29081 { 2130 /* ds_dec_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29083 { 2145 /* ds_dec_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29085 { 2145 /* ds_dec_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29087 { 2145 /* ds_dec_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29089 { 2161 /* ds_dec_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29091 { 2161 /* ds_dec_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29093 { 2161 /* ds_dec_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29095 { 2177 /* ds_dec_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29097 { 2177 /* ds_dec_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29099 { 2177 /* ds_dec_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29101 { 2188 /* ds_dec_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29103 { 2188 /* ds_dec_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29105 { 2188 /* ds_dec_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29107 { 2199 /* ds_gws_barrier */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29108 { 2199 /* ds_gws_barrier */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29109 { 2199 /* ds_gws_barrier */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29110 { 2214 /* ds_gws_init */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29111 { 2214 /* ds_gws_init */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29112 { 2214 /* ds_gws_init */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29113 { 2226 /* ds_gws_sema_br */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29114 { 2226 /* ds_gws_sema_br */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29115 { 2226 /* ds_gws_sema_br */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29116 { 2241 /* ds_gws_sema_p */, 1 /* 0 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29117 { 2241 /* ds_gws_sema_p */, 1 /* 0 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29118 { 2241 /* ds_gws_sema_p */, 1 /* 0 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29119 { 2255 /* ds_gws_sema_release_all */, 1 /* 0 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX10Plus },
29120 { 2255 /* ds_gws_sema_release_all */, 1 /* 0 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX7Only },
29121 { 2255 /* ds_gws_sema_release_all */, 1 /* 0 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX8GFX9 },
29122 { 2279 /* ds_gws_sema_v */, 1 /* 0 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29123 { 2279 /* ds_gws_sema_v */, 1 /* 0 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29124 { 2279 /* ds_gws_sema_v */, 1 /* 0 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29125 { 2293 /* ds_inc_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29127 { 2293 /* ds_inc_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29129 { 2293 /* ds_inc_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29131 { 2308 /* ds_inc_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29133 { 2308 /* ds_inc_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29135 { 2308 /* ds_inc_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29137 { 2323 /* ds_inc_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29139 { 2323 /* ds_inc_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29141 { 2323 /* ds_inc_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29143 { 2339 /* ds_inc_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29145 { 2339 /* ds_inc_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29147 { 2339 /* ds_inc_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29149 { 2355 /* ds_inc_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29151 { 2355 /* ds_inc_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29153 { 2355 /* ds_inc_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29155 { 2366 /* ds_inc_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29157 { 2366 /* ds_inc_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29159 { 2366 /* ds_inc_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29161 { 2377 /* ds_max_f32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29163 { 2377 /* ds_max_f32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29165 { 2377 /* ds_max_f32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29167 { 2388 /* ds_max_f64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29169 { 2388 /* ds_max_f64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29171 { 2388 /* ds_max_f64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29173 { 2399 /* ds_max_i32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29175 { 2399 /* ds_max_i32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29177 { 2399 /* ds_max_i32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29179 { 2410 /* ds_max_i64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29181 { 2410 /* ds_max_i64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29183 { 2410 /* ds_max_i64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29185 { 2421 /* ds_max_rtn_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29187 { 2421 /* ds_max_rtn_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29189 { 2421 /* ds_max_rtn_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29191 { 2436 /* ds_max_rtn_f64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29193 { 2436 /* ds_max_rtn_f64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29195 { 2436 /* ds_max_rtn_f64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29197 { 2451 /* ds_max_rtn_i32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29199 { 2451 /* ds_max_rtn_i32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29201 { 2451 /* ds_max_rtn_i32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29203 { 2466 /* ds_max_rtn_i64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29205 { 2466 /* ds_max_rtn_i64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29207 { 2466 /* ds_max_rtn_i64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29209 { 2481 /* ds_max_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29211 { 2481 /* ds_max_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29213 { 2481 /* ds_max_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29215 { 2496 /* ds_max_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29217 { 2496 /* ds_max_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29219 { 2496 /* ds_max_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29221 { 2511 /* ds_max_src2_f32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29223 { 2511 /* ds_max_src2_f32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29225 { 2511 /* ds_max_src2_f32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29227 { 2527 /* ds_max_src2_f64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29229 { 2527 /* ds_max_src2_f64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29231 { 2527 /* ds_max_src2_f64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29233 { 2543 /* ds_max_src2_i32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29235 { 2543 /* ds_max_src2_i32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29237 { 2543 /* ds_max_src2_i32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29239 { 2559 /* ds_max_src2_i64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29241 { 2559 /* ds_max_src2_i64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29243 { 2559 /* ds_max_src2_i64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29245 { 2575 /* ds_max_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29247 { 2575 /* ds_max_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29249 { 2575 /* ds_max_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29251 { 2591 /* ds_max_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29253 { 2591 /* ds_max_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29255 { 2591 /* ds_max_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29257 { 2607 /* ds_max_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29259 { 2607 /* ds_max_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29261 { 2607 /* ds_max_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29263 { 2618 /* ds_max_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29265 { 2618 /* ds_max_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29267 { 2618 /* ds_max_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29269 { 2629 /* ds_min_f32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29271 { 2629 /* ds_min_f32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29273 { 2629 /* ds_min_f32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29275 { 2640 /* ds_min_f64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29277 { 2640 /* ds_min_f64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29279 { 2640 /* ds_min_f64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29281 { 2651 /* ds_min_i32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29283 { 2651 /* ds_min_i32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29285 { 2651 /* ds_min_i32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29287 { 2662 /* ds_min_i64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29289 { 2662 /* ds_min_i64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29291 { 2662 /* ds_min_i64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29293 { 2673 /* ds_min_rtn_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29295 { 2673 /* ds_min_rtn_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29297 { 2673 /* ds_min_rtn_f32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29299 { 2688 /* ds_min_rtn_f64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29301 { 2688 /* ds_min_rtn_f64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29303 { 2688 /* ds_min_rtn_f64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29305 { 2703 /* ds_min_rtn_i32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29307 { 2703 /* ds_min_rtn_i32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29309 { 2703 /* ds_min_rtn_i32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29311 { 2718 /* ds_min_rtn_i64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29313 { 2718 /* ds_min_rtn_i64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29315 { 2718 /* ds_min_rtn_i64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29317 { 2733 /* ds_min_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29319 { 2733 /* ds_min_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29321 { 2733 /* ds_min_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29323 { 2748 /* ds_min_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29325 { 2748 /* ds_min_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29327 { 2748 /* ds_min_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29329 { 2763 /* ds_min_src2_f32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29331 { 2763 /* ds_min_src2_f32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29333 { 2763 /* ds_min_src2_f32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29335 { 2779 /* ds_min_src2_f64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29337 { 2779 /* ds_min_src2_f64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29339 { 2779 /* ds_min_src2_f64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29341 { 2795 /* ds_min_src2_i32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29343 { 2795 /* ds_min_src2_i32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29345 { 2795 /* ds_min_src2_i32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29347 { 2811 /* ds_min_src2_i64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29349 { 2811 /* ds_min_src2_i64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29351 { 2811 /* ds_min_src2_i64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29353 { 2827 /* ds_min_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29355 { 2827 /* ds_min_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29357 { 2827 /* ds_min_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29359 { 2843 /* ds_min_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29361 { 2843 /* ds_min_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29363 { 2843 /* ds_min_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29365 { 2859 /* ds_min_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29367 { 2859 /* ds_min_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29369 { 2859 /* ds_min_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29371 { 2870 /* ds_min_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29373 { 2870 /* ds_min_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29375 { 2870 /* ds_min_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29377 { 2881 /* ds_mskor_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29379 { 2881 /* ds_mskor_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29381 { 2881 /* ds_mskor_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29383 { 2894 /* ds_mskor_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29385 { 2894 /* ds_mskor_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29387 { 2894 /* ds_mskor_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29389 { 2907 /* ds_mskor_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29391 { 2907 /* ds_mskor_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29393 { 2907 /* ds_mskor_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29395 { 2924 /* ds_mskor_rtn_b64 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29397 { 2924 /* ds_mskor_rtn_b64 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29399 { 2924 /* ds_mskor_rtn_b64 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29401 { 2948 /* ds_or_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29403 { 2948 /* ds_or_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29405 { 2948 /* ds_or_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29407 { 2958 /* ds_or_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29409 { 2958 /* ds_or_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29411 { 2958 /* ds_or_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29413 { 2968 /* ds_or_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29415 { 2968 /* ds_or_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29417 { 2968 /* ds_or_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29419 { 2982 /* ds_or_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29421 { 2982 /* ds_or_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29423 { 2982 /* ds_or_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29425 { 2996 /* ds_or_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29427 { 2996 /* ds_or_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29429 { 2996 /* ds_or_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29431 { 3011 /* ds_or_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29433 { 3011 /* ds_or_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29435 { 3011 /* ds_or_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29437 { 3026 /* ds_ordered_count */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29438 { 3026 /* ds_ordered_count */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29439 { 3026 /* ds_ordered_count */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29440 { 3043 /* ds_permute_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8Plus_isGFX10Plus },
29441 { 3043 /* ds_permute_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8Plus_isGFX8GFX9 },
29478 { 3118 /* ds_read_addtid_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_HasDSAddTid_isGFX10Plus },
29480 { 3118 /* ds_read_addtid_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_HasDSAddTid_isGFX8GFX9 },
29482 { 3137 /* ds_read_b128 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX10Plus },
29484 { 3137 /* ds_read_b128 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX7Only },
29486 { 3137 /* ds_read_b128 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX8GFX9 },
29488 { 3150 /* ds_read_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29490 { 3150 /* ds_read_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29492 { 3150 /* ds_read_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29494 { 3162 /* ds_read_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29496 { 3162 /* ds_read_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29498 { 3162 /* ds_read_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29500 { 3174 /* ds_read_b96 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX10Plus },
29502 { 3174 /* ds_read_b96 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX7Only },
29504 { 3174 /* ds_read_b96 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX8GFX9 },
29506 { 3186 /* ds_read_i16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29508 { 3186 /* ds_read_i16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29510 { 3186 /* ds_read_i16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29512 { 3198 /* ds_read_i8 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29514 { 3198 /* ds_read_i8 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29516 { 3198 /* ds_read_i8 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29518 { 3209 /* ds_read_i8_d16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
29520 { 3209 /* ds_read_i8_d16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
29522 { 3224 /* ds_read_i8_d16_hi */, 4 /* 2 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
29524 { 3224 /* ds_read_i8_d16_hi */, 4 /* 2 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
29526 { 3242 /* ds_read_u16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29528 { 3242 /* ds_read_u16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29530 { 3242 /* ds_read_u16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29532 { 3254 /* ds_read_u16_d16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
29534 { 3254 /* ds_read_u16_d16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
29536 { 3270 /* ds_read_u16_d16_hi */, 4 /* 2 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
29538 { 3270 /* ds_read_u16_d16_hi */, 4 /* 2 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
29540 { 3289 /* ds_read_u8 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29542 { 3289 /* ds_read_u8 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29544 { 3289 /* ds_read_u8 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29546 { 3300 /* ds_read_u8_d16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
29548 { 3300 /* ds_read_u8_d16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
29550 { 3315 /* ds_read_u8_d16_hi */, 4 /* 2 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
29552 { 3315 /* ds_read_u8_d16_hi */, 4 /* 2 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
29554 { 3333 /* ds_rsub_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29556 { 3333 /* ds_rsub_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29558 { 3333 /* ds_rsub_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29560 { 3349 /* ds_rsub_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29562 { 3349 /* ds_rsub_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29564 { 3349 /* ds_rsub_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29566 { 3365 /* ds_rsub_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29568 { 3365 /* ds_rsub_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29570 { 3365 /* ds_rsub_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29572 { 3382 /* ds_rsub_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29574 { 3382 /* ds_rsub_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29576 { 3382 /* ds_rsub_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29578 { 3399 /* ds_rsub_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29580 { 3399 /* ds_rsub_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29582 { 3399 /* ds_rsub_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29584 { 3411 /* ds_rsub_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29586 { 3411 /* ds_rsub_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29588 { 3411 /* ds_rsub_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29590 { 3423 /* ds_sub_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29592 { 3423 /* ds_sub_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29594 { 3423 /* ds_sub_rtn_u32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29596 { 3438 /* ds_sub_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29598 { 3438 /* ds_sub_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29600 { 3438 /* ds_sub_rtn_u64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29602 { 3453 /* ds_sub_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29604 { 3453 /* ds_sub_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29606 { 3453 /* ds_sub_src2_u32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29608 { 3469 /* ds_sub_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29610 { 3469 /* ds_sub_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29612 { 3469 /* ds_sub_src2_u64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29614 { 3485 /* ds_sub_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29616 { 3485 /* ds_sub_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29618 { 3485 /* ds_sub_u32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29620 { 3496 /* ds_sub_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29622 { 3496 /* ds_sub_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29624 { 3496 /* ds_sub_u64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29632 { 3522 /* ds_wrap_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX10Plus },
29634 { 3522 /* ds_wrap_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX7Only },
29636 { 3522 /* ds_wrap_rtn_b32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX8GFX9 },
29674 { 3602 /* ds_write_addtid_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_HasDSAddTid_isGFX10Plus },
29676 { 3602 /* ds_write_addtid_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_HasDSAddTid_isGFX8GFX9 },
29678 { 3622 /* ds_write_b128 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX10Plus },
29680 { 3622 /* ds_write_b128 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX7Only },
29682 { 3622 /* ds_write_b128 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX8GFX9 },
29684 { 3636 /* ds_write_b16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29686 { 3636 /* ds_write_b16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29688 { 3636 /* ds_write_b16 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29690 { 3649 /* ds_write_b16_d16_hi */, 4 /* 2 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
29692 { 3649 /* ds_write_b16_d16_hi */, 4 /* 2 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
29694 { 3669 /* ds_write_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29696 { 3669 /* ds_write_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29698 { 3669 /* ds_write_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29700 { 3682 /* ds_write_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29702 { 3682 /* ds_write_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29704 { 3682 /* ds_write_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29706 { 3695 /* ds_write_b8 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29708 { 3695 /* ds_write_b8 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29710 { 3695 /* ds_write_b8 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29712 { 3707 /* ds_write_b8_d16_hi */, 4 /* 2 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
29714 { 3707 /* ds_write_b8_d16_hi */, 4 /* 2 */, MCK_ImmOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
29716 { 3726 /* ds_write_b96 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX10Plus },
29718 { 3726 /* ds_write_b96 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX7Only },
29720 { 3726 /* ds_write_b96 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX7Plus_isGFX8GFX9 },
29722 { 3739 /* ds_write_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29724 { 3739 /* ds_write_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29726 { 3739 /* ds_write_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29728 { 3757 /* ds_write_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29730 { 3757 /* ds_write_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29732 { 3757 /* ds_write_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29770 { 3859 /* ds_wrxchg_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29772 { 3859 /* ds_wrxchg_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29774 { 3859 /* ds_wrxchg_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29776 { 3877 /* ds_wrxchg_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29778 { 3877 /* ds_wrxchg_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29780 { 3877 /* ds_wrxchg_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29782 { 3895 /* ds_xor_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29784 { 3895 /* ds_xor_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29786 { 3895 /* ds_xor_b32 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29788 { 3906 /* ds_xor_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29790 { 3906 /* ds_xor_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29792 { 3906 /* ds_xor_b64 */, 4 /* 2 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29794 { 3917 /* ds_xor_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29796 { 3917 /* ds_xor_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29798 { 3917 /* ds_xor_rtn_b32 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29800 { 3932 /* ds_xor_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29802 { 3932 /* ds_xor_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29804 { 3932 /* ds_xor_rtn_b64 */, 8 /* 3 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29806 { 3947 /* ds_xor_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29808 { 3947 /* ds_xor_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29810 { 3947 /* ds_xor_src2_b32 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
29812 { 3963 /* ds_xor_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
29814 { 3963 /* ds_xor_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
29816 { 3963 /* ds_xor_src2_b64 */, 2 /* 1 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
71448 { 12756 /* tbuffer_load_format_d16_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
71455 { 12756 /* tbuffer_load_format_d16_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71462 { 12756 /* tbuffer_load_format_d16_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71469 { 12756 /* tbuffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
71476 { 12756 /* tbuffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71483 { 12756 /* tbuffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71490 { 12756 /* tbuffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
71497 { 12756 /* tbuffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71504 { 12756 /* tbuffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71511 { 12756 /* tbuffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
71518 { 12756 /* tbuffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71525 { 12756 /* tbuffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71532 { 12782 /* tbuffer_load_format_d16_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71539 { 12782 /* tbuffer_load_format_d16_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
71546 { 12782 /* tbuffer_load_format_d16_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71553 { 12782 /* tbuffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71560 { 12782 /* tbuffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71567 { 12782 /* tbuffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
71574 { 12782 /* tbuffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71581 { 12782 /* tbuffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
71588 { 12782 /* tbuffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71595 { 12782 /* tbuffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71602 { 12782 /* tbuffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
71609 { 12782 /* tbuffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71616 { 12809 /* tbuffer_load_format_d16_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71623 { 12809 /* tbuffer_load_format_d16_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
71630 { 12809 /* tbuffer_load_format_d16_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71637 { 12809 /* tbuffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71644 { 12809 /* tbuffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71651 { 12809 /* tbuffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
71658 { 12809 /* tbuffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71665 { 12809 /* tbuffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
71672 { 12809 /* tbuffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71679 { 12809 /* tbuffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71686 { 12809 /* tbuffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
71693 { 12809 /* tbuffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71700 { 12837 /* tbuffer_load_format_d16_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71707 { 12837 /* tbuffer_load_format_d16_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
71714 { 12837 /* tbuffer_load_format_d16_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71721 { 12837 /* tbuffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71728 { 12837 /* tbuffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71735 { 12837 /* tbuffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
71742 { 12837 /* tbuffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71749 { 12837 /* tbuffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
71756 { 12837 /* tbuffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71763 { 12837 /* tbuffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71770 { 12837 /* tbuffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
71777 { 12837 /* tbuffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71784 { 12866 /* tbuffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
71791 { 12866 /* tbuffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71798 { 12866 /* tbuffer_load_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
71805 { 12866 /* tbuffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71812 { 12866 /* tbuffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
71819 { 12866 /* tbuffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71826 { 12866 /* tbuffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
71833 { 12866 /* tbuffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
71840 { 12866 /* tbuffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71847 { 12866 /* tbuffer_load_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
71854 { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
71861 { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71868 { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
71875 { 12888 /* tbuffer_load_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
71882 { 12888 /* tbuffer_load_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71889 { 12888 /* tbuffer_load_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
71896 { 12888 /* tbuffer_load_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71903 { 12888 /* tbuffer_load_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
71910 { 12888 /* tbuffer_load_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71917 { 12888 /* tbuffer_load_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
71924 { 12888 /* tbuffer_load_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
71931 { 12888 /* tbuffer_load_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71938 { 12888 /* tbuffer_load_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
71945 { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
71952 { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71959 { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
71966 { 12911 /* tbuffer_load_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
71973 { 12911 /* tbuffer_load_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71980 { 12911 /* tbuffer_load_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
71987 { 12911 /* tbuffer_load_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
71994 { 12911 /* tbuffer_load_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72001 { 12911 /* tbuffer_load_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72008 { 12911 /* tbuffer_load_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72015 { 12911 /* tbuffer_load_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72022 { 12911 /* tbuffer_load_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72029 { 12911 /* tbuffer_load_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72036 { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72043 { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72050 { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72057 { 12935 /* tbuffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72064 { 12935 /* tbuffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72071 { 12935 /* tbuffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72078 { 12935 /* tbuffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72085 { 12935 /* tbuffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72092 { 12935 /* tbuffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72099 { 12935 /* tbuffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72106 { 12935 /* tbuffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72113 { 12935 /* tbuffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72120 { 12935 /* tbuffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72127 { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72134 { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72141 { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72148 { 12960 /* tbuffer_store_format_d16_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
72155 { 12960 /* tbuffer_store_format_d16_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72162 { 12960 /* tbuffer_store_format_d16_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72169 { 12960 /* tbuffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
72176 { 12960 /* tbuffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72183 { 12960 /* tbuffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72190 { 12960 /* tbuffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
72197 { 12960 /* tbuffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72204 { 12960 /* tbuffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72211 { 12960 /* tbuffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
72218 { 12960 /* tbuffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72225 { 12960 /* tbuffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72232 { 12987 /* tbuffer_store_format_d16_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72239 { 12987 /* tbuffer_store_format_d16_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
72246 { 12987 /* tbuffer_store_format_d16_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72253 { 12987 /* tbuffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72260 { 12987 /* tbuffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72267 { 12987 /* tbuffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
72274 { 12987 /* tbuffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72281 { 12987 /* tbuffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
72288 { 12987 /* tbuffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72295 { 12987 /* tbuffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72302 { 12987 /* tbuffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
72309 { 12987 /* tbuffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72316 { 13015 /* tbuffer_store_format_d16_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72323 { 13015 /* tbuffer_store_format_d16_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
72330 { 13015 /* tbuffer_store_format_d16_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72337 { 13015 /* tbuffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72344 { 13015 /* tbuffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72351 { 13015 /* tbuffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
72358 { 13015 /* tbuffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72365 { 13015 /* tbuffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
72372 { 13015 /* tbuffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72379 { 13015 /* tbuffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72386 { 13015 /* tbuffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
72393 { 13015 /* tbuffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72400 { 13044 /* tbuffer_store_format_d16_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72407 { 13044 /* tbuffer_store_format_d16_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
72414 { 13044 /* tbuffer_store_format_d16_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72421 { 13044 /* tbuffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72428 { 13044 /* tbuffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72435 { 13044 /* tbuffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
72442 { 13044 /* tbuffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72449 { 13044 /* tbuffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
72456 { 13044 /* tbuffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72463 { 13044 /* tbuffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72470 { 13044 /* tbuffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX10Plus },
72477 { 13044 /* tbuffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmOffset, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72484 { 13074 /* tbuffer_store_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72491 { 13074 /* tbuffer_store_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72498 { 13074 /* tbuffer_store_format_x */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72505 { 13074 /* tbuffer_store_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72512 { 13074 /* tbuffer_store_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72519 { 13074 /* tbuffer_store_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72526 { 13074 /* tbuffer_store_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72533 { 13074 /* tbuffer_store_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72540 { 13074 /* tbuffer_store_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72547 { 13074 /* tbuffer_store_format_x */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72554 { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72561 { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72568 { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72575 { 13097 /* tbuffer_store_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72582 { 13097 /* tbuffer_store_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72589 { 13097 /* tbuffer_store_format_xy */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72596 { 13097 /* tbuffer_store_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72603 { 13097 /* tbuffer_store_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72610 { 13097 /* tbuffer_store_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72617 { 13097 /* tbuffer_store_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72624 { 13097 /* tbuffer_store_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72631 { 13097 /* tbuffer_store_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72638 { 13097 /* tbuffer_store_format_xy */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72645 { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72652 { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72659 { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72666 { 13121 /* tbuffer_store_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72673 { 13121 /* tbuffer_store_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72680 { 13121 /* tbuffer_store_format_xyz */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72687 { 13121 /* tbuffer_store_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72694 { 13121 /* tbuffer_store_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72701 { 13121 /* tbuffer_store_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72708 { 13121 /* tbuffer_store_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72715 { 13121 /* tbuffer_store_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72722 { 13121 /* tbuffer_store_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72729 { 13121 /* tbuffer_store_format_xyz */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72736 { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72743 { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72750 { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72757 { 13146 /* tbuffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72764 { 13146 /* tbuffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72771 { 13146 /* tbuffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72778 { 13146 /* tbuffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72785 { 13146 /* tbuffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72792 { 13146 /* tbuffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72799 { 13146 /* tbuffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72806 { 13146 /* tbuffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72813 { 13146 /* tbuffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72820 { 13146 /* tbuffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
72827 { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX10Plus },
72834 { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX6GFX7 },
72841 { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmOffset, AMFBS_isGFX8GFX9 },
80317 case MCK_ImmOffset: