reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
5210 case MCK_ImmHigh: 6050 case MCK_ImmHigh: { 10149 case MCK_ImmHigh: return "MCK_ImmHigh"; 22335 { 23348 /* v_interp_p1ll_f16 */, AMDGPU::V_INTERP_P1LL_F16_gfx10, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmHigh, MCK_ImmClampSI, MCK_ImmOModSI }, }, 22336 { 23348 /* v_interp_p1ll_f16 */, AMDGPU::V_INTERP_P1LL_F16_vi, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmHigh, MCK_ImmClampSI, MCK_ImmOModSI }, }, 22337 { 23366 /* v_interp_p1lv_f16 */, AMDGPU::V_INTERP_P1LV_F16_gfx10, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP16InputMods, MCK_ImmHigh, MCK_ImmClampSI, MCK_ImmOModSI }, }, 22338 { 23366 /* v_interp_p1lv_f16 */, AMDGPU::V_INTERP_P1LV_F16_vi, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP16InputMods, MCK_ImmHigh, MCK_ImmClampSI, MCK_ImmOModSI }, }, 22339 { 23384 /* v_interp_p2_f16 */, AMDGPU::V_INTERP_P2_F16_gfx10, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP32InputMods, MCK_ImmHigh, MCK_ImmClampSI }, }, 22340 { 23384 /* v_interp_p2_f16 */, AMDGPU::V_INTERP_P2_F16_gfx9_gfx9, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX9Plus_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP32InputMods, MCK_ImmHigh, MCK_ImmClampSI }, }, 22341 { 23384 /* v_interp_p2_f16 */, AMDGPU::V_INTERP_P2_F16_vi, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX8Only, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP32InputMods, MCK_ImmHigh, MCK_ImmClampSI }, }, 22344 { 23416 /* v_interp_p2_legacy_f16 */, AMDGPU::V_INTERP_P2_LEGACY_F16_gfx9, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP32InputMods, MCK_ImmHigh, MCK_ImmClampSI }, }, 77600 { 23348 /* v_interp_p1ll_f16 */, 16 /* 4 */, MCK_ImmHigh, AMFBS_Has16BitInsts_isGFX10Plus }, 77605 { 23348 /* v_interp_p1ll_f16 */, 16 /* 4 */, MCK_ImmHigh, AMFBS_Has16BitInsts_isGFX8GFX9 }, 77611 { 23366 /* v_interp_p1lv_f16 */, 32 /* 5 */, MCK_ImmHigh, AMFBS_Has16BitInsts_isGFX10Plus }, 77617 { 23366 /* v_interp_p1lv_f16 */, 32 /* 5 */, MCK_ImmHigh, AMFBS_Has16BitInsts_isGFX8GFX9 }, 77621 { 23384 /* v_interp_p2_f16 */, 32 /* 5 */, MCK_ImmHigh, AMFBS_Has16BitInsts_isGFX10Plus }, 77625 { 23384 /* v_interp_p2_f16 */, 32 /* 5 */, MCK_ImmHigh, AMFBS_isGFX9Plus_isGFX9Only }, 77629 { 23384 /* v_interp_p2_f16 */, 32 /* 5 */, MCK_ImmHigh, AMFBS_Has16BitInsts_isGFX8Only }, 77644 { 23416 /* v_interp_p2_legacy_f16 */, 32 /* 5 */, MCK_ImmHigh, AMFBS_Has16BitInsts_isGFX9Only }, 80329 case MCK_ImmHigh: