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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 5216 case MCK_ImmGLC:
6064 case MCK_ImmGLC: {
10151 case MCK_ImmGLC: return "MCK_ImmGLC";
11871 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11872 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11873 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11874 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11875 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11876 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11877 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11878 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11879 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11880 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11881 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11882 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11883 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11884 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11885 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11886 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11887 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11888 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11889 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11890 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11891 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11892 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11893 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11894 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11895 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11896 { 731 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11897 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11898 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11899 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11900 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11901 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11902 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11903 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11904 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11905 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11906 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11907 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11908 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11909 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11910 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11911 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11912 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11913 { 749 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11914 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11915 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11916 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11917 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11918 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11919 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11920 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11921 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11922 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11923 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11924 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11925 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11926 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11927 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11928 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11929 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11930 { 769 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11931 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11932 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11933 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11934 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11935 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11936 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11937 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11938 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11939 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11940 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11941 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11942 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11943 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11944 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
11945 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11946 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11947 { 789 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11948 { 809 /* buffer_load_format_d16_hi_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11949 { 809 /* buffer_load_format_d16_hi_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11950 { 809 /* buffer_load_format_d16_hi_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11951 { 809 /* buffer_load_format_d16_hi_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11952 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11953 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11954 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11955 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11956 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11957 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11958 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11959 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11960 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11961 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11962 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11963 { 837 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11964 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11965 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11966 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11967 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11968 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11969 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11970 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11971 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11972 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11973 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11974 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11975 { 862 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11976 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11977 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11978 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11979 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11980 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11981 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11982 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11983 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11984 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11985 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11986 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11987 { 888 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11988 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11989 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11990 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11991 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11992 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11993 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11994 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11995 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11996 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11997 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11998 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
11999 { 915 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12000 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12001 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12002 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12003 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12004 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12005 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12006 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12007 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12008 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12009 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12010 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12011 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12012 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12013 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12014 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12015 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12016 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12017 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12018 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12019 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12020 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12021 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12022 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12023 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12024 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12025 { 943 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12026 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12027 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12028 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12029 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12030 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12031 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12032 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12033 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12034 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12035 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12036 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12037 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12038 { 964 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12039 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12040 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12041 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12042 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12043 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12044 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12045 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12046 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12047 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12048 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12049 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12050 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12051 { 986 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12052 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12053 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12054 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12055 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12056 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12057 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12058 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12059 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12060 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12061 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12062 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12063 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12064 { 1009 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12065 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12066 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12067 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12068 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12069 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12070 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12071 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12072 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12073 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12074 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12075 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12076 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12077 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12078 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12079 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12080 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12081 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12082 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12083 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12084 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12085 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12086 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12087 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12088 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12089 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12090 { 1033 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12091 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12092 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12093 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12094 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12095 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12096 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12097 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12098 { 1051 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12099 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12100 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12101 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12102 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12103 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12104 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12105 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12106 { 1073 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12107 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12108 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12109 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12110 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12111 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12112 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12113 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12114 { 1098 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12115 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12116 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12117 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12118 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12119 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12120 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12121 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12122 { 1120 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12123 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12124 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12125 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12126 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12127 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12128 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12129 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12130 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12131 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12132 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12133 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12134 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12135 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12136 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12137 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12138 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12139 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12140 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12141 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12142 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12143 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12144 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12145 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12146 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12147 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12148 { 1145 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12149 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12150 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12151 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12152 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12153 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12154 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12155 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12156 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12157 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12158 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12159 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12160 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12161 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12162 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12163 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12164 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12165 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12166 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12167 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12168 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12169 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12170 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12171 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12172 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12173 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12174 { 1164 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12175 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12176 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12177 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12178 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12179 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12180 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12181 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12182 { 1182 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12183 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12184 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12185 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12186 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12187 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12188 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12189 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12190 { 1204 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12191 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12192 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12193 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12194 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12195 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12196 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12197 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12198 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12199 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12200 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12201 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12202 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12203 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12204 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12205 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12206 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12207 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12208 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12209 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12210 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12211 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_gfx10, ConvertCustom_cvtMubufLds, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12212 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubufLds, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12213 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds, MCK_ImmDLC, MCK_ImmSWZ }, },
12214 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12215 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12216 { 1229 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12217 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12218 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12219 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12220 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12221 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12222 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12223 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12224 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12225 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12226 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12227 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12228 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12229 { 1248 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12230 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12231 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12232 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12233 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12234 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12235 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12236 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12237 { 1266 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12238 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12239 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12240 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12241 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12242 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12243 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12244 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12245 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12246 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12247 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12248 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12249 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12250 { 1291 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12251 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12252 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12253 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12254 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12255 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12256 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12257 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12258 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12259 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12260 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12261 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12262 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12263 { 1310 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12264 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12265 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12266 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12267 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12268 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12269 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12270 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12271 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12272 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12273 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12274 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12275 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12276 { 1331 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12277 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12278 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12279 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12280 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12281 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12282 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12283 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12284 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12285 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12286 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12287 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12288 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12289 { 1352 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12290 { 1373 /* buffer_store_format_d16_hi_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12291 { 1373 /* buffer_store_format_d16_hi_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12292 { 1373 /* buffer_store_format_d16_hi_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12293 { 1373 /* buffer_store_format_d16_hi_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12294 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12295 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12296 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12297 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12298 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12299 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12300 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12301 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12302 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12303 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12304 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12305 { 1402 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12306 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12307 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12308 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12309 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12310 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12311 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12312 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12313 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12314 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12315 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12316 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12317 { 1428 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12318 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12319 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12320 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12321 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12322 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12323 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12324 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12325 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12326 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12327 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12328 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12329 { 1455 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12330 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12331 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12332 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12333 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12334 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12335 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12336 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12337 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12338 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12339 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12340 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12341 { 1483 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12342 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12343 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12344 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12345 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12346 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12347 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12348 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12349 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12350 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12351 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12352 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12353 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12354 { 1512 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12355 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12356 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12357 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12358 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12359 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12360 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12361 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12362 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12363 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12364 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12365 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12366 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12367 { 1534 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12368 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12369 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12370 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12371 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12372 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12373 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12374 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12375 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12376 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12377 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12378 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12379 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12380 { 1557 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12381 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12382 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12383 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12384 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12385 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12386 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12387 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12388 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12389 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12390 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12391 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12392 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12393 { 1581 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12394 { 1606 /* buffer_store_lds_dword */, AMDGPU::BUFFER_STORE_LDS_DWORD_vi, ConvertCustom_cvtMubufLds, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_lds, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmSWZ }, },
12395 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12396 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFSET_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12397 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12398 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_ADDR64_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12399 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12400 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_IDXEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12401 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12402 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12403 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12404 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12405 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12406 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMubuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12407 { 1629 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12408 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12409 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12410 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_IDXEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12411 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12412 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12413 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12414 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_BOTHEN_gfx10, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
12415 { 1648 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
13054 { 4573 /* flat_load_dword */, AMDGPU::FLAT_LOAD_DWORD_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13055 { 4573 /* flat_load_dword */, AMDGPU::FLAT_LOAD_DWORD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13056 { 4573 /* flat_load_dword */, AMDGPU::FLAT_LOAD_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13057 { 4589 /* flat_load_dwordx2 */, AMDGPU::FLAT_LOAD_DWORDX2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13058 { 4589 /* flat_load_dwordx2 */, AMDGPU::FLAT_LOAD_DWORDX2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13059 { 4589 /* flat_load_dwordx2 */, AMDGPU::FLAT_LOAD_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13060 { 4607 /* flat_load_dwordx3 */, AMDGPU::FLAT_LOAD_DWORDX3_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_96, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13061 { 4607 /* flat_load_dwordx3 */, AMDGPU::FLAT_LOAD_DWORDX3_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13062 { 4607 /* flat_load_dwordx3 */, AMDGPU::FLAT_LOAD_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13063 { 4625 /* flat_load_dwordx4 */, AMDGPU::FLAT_LOAD_DWORDX4_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_128, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13064 { 4625 /* flat_load_dwordx4 */, AMDGPU::FLAT_LOAD_DWORDX4_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13065 { 4625 /* flat_load_dwordx4 */, AMDGPU::FLAT_LOAD_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13066 { 4643 /* flat_load_sbyte */, AMDGPU::FLAT_LOAD_SBYTE_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13067 { 4643 /* flat_load_sbyte */, AMDGPU::FLAT_LOAD_SBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13068 { 4643 /* flat_load_sbyte */, AMDGPU::FLAT_LOAD_SBYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13069 { 4659 /* flat_load_sbyte_d16 */, AMDGPU::FLAT_LOAD_SBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13070 { 4659 /* flat_load_sbyte_d16 */, AMDGPU::FLAT_LOAD_SBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13071 { 4679 /* flat_load_sbyte_d16_hi */, AMDGPU::FLAT_LOAD_SBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13072 { 4679 /* flat_load_sbyte_d16_hi */, AMDGPU::FLAT_LOAD_SBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13073 { 4702 /* flat_load_short_d16 */, AMDGPU::FLAT_LOAD_SHORT_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13074 { 4702 /* flat_load_short_d16 */, AMDGPU::FLAT_LOAD_SHORT_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13075 { 4722 /* flat_load_short_d16_hi */, AMDGPU::FLAT_LOAD_SHORT_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13076 { 4722 /* flat_load_short_d16_hi */, AMDGPU::FLAT_LOAD_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13077 { 4745 /* flat_load_sshort */, AMDGPU::FLAT_LOAD_SSHORT_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13078 { 4745 /* flat_load_sshort */, AMDGPU::FLAT_LOAD_SSHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13079 { 4745 /* flat_load_sshort */, AMDGPU::FLAT_LOAD_SSHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13080 { 4762 /* flat_load_ubyte */, AMDGPU::FLAT_LOAD_UBYTE_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13081 { 4762 /* flat_load_ubyte */, AMDGPU::FLAT_LOAD_UBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13082 { 4762 /* flat_load_ubyte */, AMDGPU::FLAT_LOAD_UBYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13083 { 4778 /* flat_load_ubyte_d16 */, AMDGPU::FLAT_LOAD_UBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13084 { 4778 /* flat_load_ubyte_d16 */, AMDGPU::FLAT_LOAD_UBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13085 { 4798 /* flat_load_ubyte_d16_hi */, AMDGPU::FLAT_LOAD_UBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13086 { 4798 /* flat_load_ubyte_d16_hi */, AMDGPU::FLAT_LOAD_UBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13087 { 4821 /* flat_load_ushort */, AMDGPU::FLAT_LOAD_USHORT_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13088 { 4821 /* flat_load_ushort */, AMDGPU::FLAT_LOAD_USHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13089 { 4821 /* flat_load_ushort */, AMDGPU::FLAT_LOAD_USHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13090 { 4838 /* flat_store_byte */, AMDGPU::FLAT_STORE_BYTE_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13091 { 4838 /* flat_store_byte */, AMDGPU::FLAT_STORE_BYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13092 { 4838 /* flat_store_byte */, AMDGPU::FLAT_STORE_BYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13093 { 4854 /* flat_store_byte_d16_hi */, AMDGPU::FLAT_STORE_BYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13094 { 4854 /* flat_store_byte_d16_hi */, AMDGPU::FLAT_STORE_BYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13095 { 4877 /* flat_store_dword */, AMDGPU::FLAT_STORE_DWORD_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13096 { 4877 /* flat_store_dword */, AMDGPU::FLAT_STORE_DWORD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13097 { 4877 /* flat_store_dword */, AMDGPU::FLAT_STORE_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13098 { 4894 /* flat_store_dwordx2 */, AMDGPU::FLAT_STORE_DWORDX2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13099 { 4894 /* flat_store_dwordx2 */, AMDGPU::FLAT_STORE_DWORDX2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13100 { 4894 /* flat_store_dwordx2 */, AMDGPU::FLAT_STORE_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13101 { 4913 /* flat_store_dwordx3 */, AMDGPU::FLAT_STORE_DWORDX3_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_96, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13102 { 4913 /* flat_store_dwordx3 */, AMDGPU::FLAT_STORE_DWORDX3_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13103 { 4913 /* flat_store_dwordx3 */, AMDGPU::FLAT_STORE_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13104 { 4932 /* flat_store_dwordx4 */, AMDGPU::FLAT_STORE_DWORDX4_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13105 { 4932 /* flat_store_dwordx4 */, AMDGPU::FLAT_STORE_DWORDX4_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13106 { 4932 /* flat_store_dwordx4 */, AMDGPU::FLAT_STORE_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13107 { 4951 /* flat_store_short */, AMDGPU::FLAT_STORE_SHORT_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13108 { 4951 /* flat_store_short */, AMDGPU::FLAT_STORE_SHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13109 { 4951 /* flat_store_short */, AMDGPU::FLAT_STORE_SHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13110 { 4968 /* flat_store_short_d16_hi */, AMDGPU::FLAT_STORE_SHORT_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13111 { 4968 /* flat_store_short_d16_hi */, AMDGPU::FLAT_STORE_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13348 { 5693 /* global_load_dword */, AMDGPU::GLOBAL_LOAD_DWORD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13349 { 5693 /* global_load_dword */, AMDGPU::GLOBAL_LOAD_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13350 { 5693 /* global_load_dword */, AMDGPU::GLOBAL_LOAD_DWORD_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13351 { 5693 /* global_load_dword */, AMDGPU::GLOBAL_LOAD_DWORD_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13352 { 5711 /* global_load_dwordx2 */, AMDGPU::GLOBAL_LOAD_DWORDX2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13353 { 5711 /* global_load_dwordx2 */, AMDGPU::GLOBAL_LOAD_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13354 { 5711 /* global_load_dwordx2 */, AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13355 { 5711 /* global_load_dwordx2 */, AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13356 { 5731 /* global_load_dwordx3 */, AMDGPU::GLOBAL_LOAD_DWORDX3_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13357 { 5731 /* global_load_dwordx3 */, AMDGPU::GLOBAL_LOAD_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13358 { 5731 /* global_load_dwordx3 */, AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13359 { 5731 /* global_load_dwordx3 */, AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13360 { 5751 /* global_load_dwordx4 */, AMDGPU::GLOBAL_LOAD_DWORDX4_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13361 { 5751 /* global_load_dwordx4 */, AMDGPU::GLOBAL_LOAD_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13362 { 5751 /* global_load_dwordx4 */, AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13363 { 5751 /* global_load_dwordx4 */, AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13364 { 5771 /* global_load_sbyte */, AMDGPU::GLOBAL_LOAD_SBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13365 { 5771 /* global_load_sbyte */, AMDGPU::GLOBAL_LOAD_SBYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13366 { 5771 /* global_load_sbyte */, AMDGPU::GLOBAL_LOAD_SBYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13367 { 5771 /* global_load_sbyte */, AMDGPU::GLOBAL_LOAD_SBYTE_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13368 { 5789 /* global_load_sbyte_d16 */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13369 { 5789 /* global_load_sbyte_d16 */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13370 { 5789 /* global_load_sbyte_d16 */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13371 { 5789 /* global_load_sbyte_d16 */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13372 { 5811 /* global_load_sbyte_d16_hi */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13373 { 5811 /* global_load_sbyte_d16_hi */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13374 { 5811 /* global_load_sbyte_d16_hi */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13375 { 5811 /* global_load_sbyte_d16_hi */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13376 { 5836 /* global_load_short_d16 */, AMDGPU::GLOBAL_LOAD_SHORT_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13377 { 5836 /* global_load_short_d16 */, AMDGPU::GLOBAL_LOAD_SHORT_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13378 { 5836 /* global_load_short_d16 */, AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13379 { 5836 /* global_load_short_d16 */, AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13380 { 5858 /* global_load_short_d16_hi */, AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13381 { 5858 /* global_load_short_d16_hi */, AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13382 { 5858 /* global_load_short_d16_hi */, AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13383 { 5858 /* global_load_short_d16_hi */, AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13384 { 5883 /* global_load_sshort */, AMDGPU::GLOBAL_LOAD_SSHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13385 { 5883 /* global_load_sshort */, AMDGPU::GLOBAL_LOAD_SSHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13386 { 5883 /* global_load_sshort */, AMDGPU::GLOBAL_LOAD_SSHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13387 { 5883 /* global_load_sshort */, AMDGPU::GLOBAL_LOAD_SSHORT_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13388 { 5902 /* global_load_ubyte */, AMDGPU::GLOBAL_LOAD_UBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13389 { 5902 /* global_load_ubyte */, AMDGPU::GLOBAL_LOAD_UBYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13390 { 5902 /* global_load_ubyte */, AMDGPU::GLOBAL_LOAD_UBYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13391 { 5902 /* global_load_ubyte */, AMDGPU::GLOBAL_LOAD_UBYTE_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13392 { 5920 /* global_load_ubyte_d16 */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13393 { 5920 /* global_load_ubyte_d16 */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13394 { 5920 /* global_load_ubyte_d16 */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13395 { 5920 /* global_load_ubyte_d16 */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13396 { 5942 /* global_load_ubyte_d16_hi */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13397 { 5942 /* global_load_ubyte_d16_hi */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13398 { 5942 /* global_load_ubyte_d16_hi */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13399 { 5942 /* global_load_ubyte_d16_hi */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13400 { 5967 /* global_load_ushort */, AMDGPU::GLOBAL_LOAD_USHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13401 { 5967 /* global_load_ushort */, AMDGPU::GLOBAL_LOAD_USHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13402 { 5967 /* global_load_ushort */, AMDGPU::GLOBAL_LOAD_USHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13403 { 5967 /* global_load_ushort */, AMDGPU::GLOBAL_LOAD_USHORT_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13404 { 5986 /* global_store_byte */, AMDGPU::GLOBAL_STORE_BYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13405 { 5986 /* global_store_byte */, AMDGPU::GLOBAL_STORE_BYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13406 { 5986 /* global_store_byte */, AMDGPU::GLOBAL_STORE_BYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13407 { 5986 /* global_store_byte */, AMDGPU::GLOBAL_STORE_BYTE_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13408 { 6004 /* global_store_byte_d16_hi */, AMDGPU::GLOBAL_STORE_BYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13409 { 6004 /* global_store_byte_d16_hi */, AMDGPU::GLOBAL_STORE_BYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13410 { 6004 /* global_store_byte_d16_hi */, AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13411 { 6004 /* global_store_byte_d16_hi */, AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13412 { 6029 /* global_store_dword */, AMDGPU::GLOBAL_STORE_DWORD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13413 { 6029 /* global_store_dword */, AMDGPU::GLOBAL_STORE_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13414 { 6029 /* global_store_dword */, AMDGPU::GLOBAL_STORE_DWORD_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13415 { 6029 /* global_store_dword */, AMDGPU::GLOBAL_STORE_DWORD_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13416 { 6048 /* global_store_dwordx2 */, AMDGPU::GLOBAL_STORE_DWORDX2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13417 { 6048 /* global_store_dwordx2 */, AMDGPU::GLOBAL_STORE_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13418 { 6048 /* global_store_dwordx2 */, AMDGPU::GLOBAL_STORE_DWORDX2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13419 { 6048 /* global_store_dwordx2 */, AMDGPU::GLOBAL_STORE_DWORDX2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13420 { 6069 /* global_store_dwordx3 */, AMDGPU::GLOBAL_STORE_DWORDX3_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13421 { 6069 /* global_store_dwordx3 */, AMDGPU::GLOBAL_STORE_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13422 { 6069 /* global_store_dwordx3 */, AMDGPU::GLOBAL_STORE_DWORDX3_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13423 { 6069 /* global_store_dwordx3 */, AMDGPU::GLOBAL_STORE_DWORDX3_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13424 { 6090 /* global_store_dwordx4 */, AMDGPU::GLOBAL_STORE_DWORDX4_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13425 { 6090 /* global_store_dwordx4 */, AMDGPU::GLOBAL_STORE_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13426 { 6090 /* global_store_dwordx4 */, AMDGPU::GLOBAL_STORE_DWORDX4_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13427 { 6090 /* global_store_dwordx4 */, AMDGPU::GLOBAL_STORE_DWORDX4_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13428 { 6111 /* global_store_short */, AMDGPU::GLOBAL_STORE_SHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13429 { 6111 /* global_store_short */, AMDGPU::GLOBAL_STORE_SHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13430 { 6111 /* global_store_short */, AMDGPU::GLOBAL_STORE_SHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13431 { 6111 /* global_store_short */, AMDGPU::GLOBAL_STORE_SHORT_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13432 { 6130 /* global_store_short_d16_hi */, AMDGPU::GLOBAL_STORE_SHORT_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13433 { 6130 /* global_store_short_d16_hi */, AMDGPU::GLOBAL_STORE_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13434 { 6130 /* global_store_short_d16_hi */, AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13435 { 6130 /* global_store_short_d16_hi */, AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13436 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13437 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13438 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13439 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13440 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13441 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13442 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13443 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13444 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13445 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13446 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13447 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13448 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13449 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13450 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13451 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13452 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13453 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13454 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13455 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13456 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13457 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13458 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13459 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13460 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13461 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13462 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13463 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13464 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13465 { 6156 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13466 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13467 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13468 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13469 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13470 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13471 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13472 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13473 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13474 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13475 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13476 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13477 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13478 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13479 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13480 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13481 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13482 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13483 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13484 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13485 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13486 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13487 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13488 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13489 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13490 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13491 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13492 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13493 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13494 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13495 { 6173 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13496 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13497 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13498 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13499 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13500 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13501 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13502 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13503 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13504 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13505 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13506 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13507 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13508 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13509 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13510 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13511 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13512 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13513 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13514 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13515 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13516 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13517 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13518 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13519 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13520 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13521 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13522 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13523 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13524 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13525 { 6190 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13526 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13527 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13528 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13529 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13530 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13531 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13532 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13533 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13534 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13535 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13536 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13537 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13538 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13539 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13540 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13541 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13542 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13543 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13544 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13545 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13546 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13547 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13548 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13549 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13550 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13551 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13552 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13553 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13554 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13555 { 6211 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13556 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13557 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13558 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13559 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13560 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13561 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13562 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13563 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13564 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13565 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13566 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13567 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13568 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13569 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13570 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13571 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13572 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13573 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13574 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13575 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13576 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13577 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13578 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13579 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13580 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13581 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13582 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13583 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13584 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13585 { 6228 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13586 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13587 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13588 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13589 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13590 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13591 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13592 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13593 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13594 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13595 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13596 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13597 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13598 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13599 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13600 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13601 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13602 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13603 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13604 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13605 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13606 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13607 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13608 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13609 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13610 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13611 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13612 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13613 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13614 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13615 { 6245 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13616 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13617 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13618 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13619 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13620 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13621 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13622 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13623 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13624 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13625 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13626 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13627 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13628 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13629 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13630 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13631 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13632 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13633 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13634 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13635 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13636 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13637 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13638 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13639 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13640 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13641 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13642 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13643 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13644 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13645 { 6261 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13646 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13647 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13648 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13649 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13650 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13651 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13652 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13653 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13654 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13655 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13656 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13657 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13658 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13659 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13660 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13661 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13662 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13663 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13664 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13665 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13666 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13667 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13668 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13669 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13670 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13671 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13672 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13673 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13674 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13675 { 6279 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13676 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13677 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13678 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13679 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13680 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13681 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13682 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13683 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13684 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13685 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13686 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13687 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13688 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13689 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13690 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13691 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13692 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13693 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13694 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13695 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13696 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13697 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13698 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13699 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13700 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13701 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13702 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13703 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13704 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13705 { 6297 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13706 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13707 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13708 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13709 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13710 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13711 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13712 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13713 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13714 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13715 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13716 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13717 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13718 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13719 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13720 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13721 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13722 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13723 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13724 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13725 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13726 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13727 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13728 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13729 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13730 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13731 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13732 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13733 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13734 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13735 { 6314 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13736 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13737 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13738 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13739 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13740 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13741 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13742 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13743 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13744 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13745 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13746 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13747 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13748 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13749 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13750 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13751 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13752 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13753 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13754 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13755 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13756 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13757 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13758 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13759 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13760 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13761 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13762 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13763 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13764 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13765 { 6332 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13766 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13767 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13768 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13769 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13770 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13771 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13772 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13773 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13774 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13775 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13776 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13777 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13778 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13779 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13780 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13781 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13782 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13783 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13784 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13785 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13786 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13787 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13788 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13789 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13790 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13791 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13792 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13793 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13794 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13795 { 6350 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13796 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13797 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13798 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13799 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13800 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13801 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13802 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13803 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13804 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13805 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13806 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13807 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13808 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13809 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13810 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V1_si, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13811 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
13812 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13813 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13814 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13815 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13816 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13817 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13818 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13819 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V1_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13820 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13821 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13822 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13823 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13824 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13825 { 6368 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMGAtomic, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
13826 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13827 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13828 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13829 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13830 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13831 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13832 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13833 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13834 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13835 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13836 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13837 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13838 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13839 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13840 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13841 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13842 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13843 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13844 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13845 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13846 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13847 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13848 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13849 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13850 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13851 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13852 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13853 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13854 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13855 { 6385 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13856 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13857 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13858 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13859 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13860 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13861 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13862 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13863 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13864 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13865 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13866 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13867 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13868 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13869 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13870 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13871 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13872 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13873 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13874 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13875 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13876 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13877 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13878 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13879 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13880 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13881 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13882 { 6399 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13883 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13884 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13885 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13886 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13887 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13888 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13889 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13890 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13891 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13892 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13893 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13894 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13895 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13896 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13897 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13898 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13899 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13900 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13901 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13902 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13903 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13904 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13905 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13906 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13907 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13908 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13909 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13910 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13911 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13912 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13913 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13914 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13915 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13916 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13917 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13918 { 6415 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13919 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13920 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13921 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13922 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13923 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13924 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13925 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13926 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13927 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13928 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13929 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13930 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13931 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13932 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13933 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13934 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13935 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13936 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13937 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13938 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13939 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13940 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13941 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13942 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13943 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13944 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13945 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13946 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13947 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13948 { 6434 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13949 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13950 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13951 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13952 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13953 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13954 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13955 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13956 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13957 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13958 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13959 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13960 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13961 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13962 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13963 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13964 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13965 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13966 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13967 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13968 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13969 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13970 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13971 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13972 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13973 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13974 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13975 { 6455 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13976 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13977 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13978 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13979 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13980 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13981 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13982 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13983 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13984 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
13985 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13986 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13987 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13988 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13989 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13990 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13991 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13992 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13993 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13994 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13995 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13996 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13997 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13998 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
13999 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14000 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14001 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14002 { 6473 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14003 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14004 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14005 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14006 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14007 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14008 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14009 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14010 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14011 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14012 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14013 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14014 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14015 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14016 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14017 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14018 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14019 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14020 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14021 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14022 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14023 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14024 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14025 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14026 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14027 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14028 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14029 { 6489 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14030 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14031 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14032 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14033 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14034 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14035 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14036 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14037 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14038 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14039 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14040 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14041 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14042 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14043 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14044 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14045 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14046 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14047 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14048 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14049 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14050 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14051 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14052 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14053 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14054 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14055 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14056 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14057 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14058 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14059 { 6507 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14060 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14061 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14062 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14063 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14064 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14065 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14066 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14067 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14068 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14069 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14070 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14071 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14072 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14073 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14074 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14075 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14076 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14077 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14078 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14079 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14080 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14081 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14082 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14083 { 6528 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14084 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14085 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14086 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14087 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14088 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14089 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14090 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14091 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14092 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14093 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14094 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14095 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14096 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14097 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14098 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14099 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14100 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14101 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14102 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14103 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14104 { 6551 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14105 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14106 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14107 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14108 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14109 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14110 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14111 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14112 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14113 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14114 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14115 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14116 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14117 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14118 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14119 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14120 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14121 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14122 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14123 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14124 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14125 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14126 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14127 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14128 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14129 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14130 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14131 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14132 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14133 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14134 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14135 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14136 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14137 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14138 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14139 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14140 { 6571 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14141 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14142 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14143 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14144 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14145 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14146 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14147 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14148 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14149 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14150 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14151 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14152 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14153 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14154 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14155 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14156 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14157 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14158 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14159 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14160 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14161 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14162 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14163 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14164 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14165 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14166 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14167 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14168 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14169 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14170 { 6590 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14171 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14172 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14173 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14174 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14175 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14176 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14177 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14178 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14179 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14180 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14181 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14182 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14183 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14184 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14185 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14186 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14187 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14188 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14189 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14190 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14191 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14192 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14193 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14194 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14195 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14196 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14197 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14198 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14199 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14200 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14201 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14202 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14203 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14204 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14205 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14206 { 6611 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14207 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14208 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14209 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14210 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14211 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14212 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14213 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14214 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14215 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14216 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14217 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14218 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14219 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14220 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14221 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14222 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14223 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14224 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14225 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14226 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14227 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14228 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14229 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14230 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14231 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14232 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14233 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14234 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14235 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14236 { 6629 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14237 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14238 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14239 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14240 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14241 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14242 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14243 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14244 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14245 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14246 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14247 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14248 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14249 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14250 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14251 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14252 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14253 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14254 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14255 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14256 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14257 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14258 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14259 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14260 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14261 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14262 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14263 { 6649 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14264 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14265 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14266 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14267 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14268 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14269 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14270 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14271 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14272 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14273 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14274 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14275 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14276 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14277 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14278 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14279 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14280 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14281 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14282 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14283 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14284 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14285 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14286 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14287 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14288 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14289 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14290 { 6668 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14291 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14292 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14293 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14294 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14295 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14296 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14297 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14298 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14299 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14300 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14301 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14302 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14303 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14304 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14305 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14306 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14307 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14308 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14309 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14310 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14311 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14312 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14313 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14314 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14315 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14316 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14317 { 6689 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14318 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14319 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14320 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14321 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14322 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14323 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14324 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14325 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14326 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14327 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14328 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14329 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14330 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14331 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14332 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14333 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14334 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14335 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14336 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14337 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14338 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14339 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14340 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14341 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14342 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14343 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14344 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14345 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14346 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14347 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14348 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14349 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14350 { 6707 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14351 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14352 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14353 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14354 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14355 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14356 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14357 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14358 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14359 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14360 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14361 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14362 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14363 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14364 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14365 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14366 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14367 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14368 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14369 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14370 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14371 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14372 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14373 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14374 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14375 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14376 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14377 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14378 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14379 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14380 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14381 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14382 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14383 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14384 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14385 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14386 { 6724 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14387 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14388 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14389 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14390 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14391 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14392 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14393 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14394 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14395 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14396 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14397 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14398 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14399 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14400 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14401 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14402 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14403 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14404 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14405 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14406 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14407 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14408 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14409 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14410 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14411 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14412 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14413 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14414 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14415 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14416 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14417 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14418 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14419 { 6743 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14420 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14421 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14422 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14423 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14424 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14425 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14426 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14427 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14428 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14429 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14430 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14431 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14432 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14433 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14434 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14435 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14436 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14437 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14438 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14439 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14440 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14441 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14442 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14443 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14444 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14445 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14446 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14447 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14448 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14449 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14450 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14451 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14452 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14453 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14454 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14455 { 6759 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14456 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14457 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14458 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14459 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14460 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14461 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14462 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14463 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14464 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14465 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14466 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14467 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14468 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14469 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14470 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14471 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14472 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14473 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14474 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14475 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14476 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14477 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14478 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14479 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14480 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14481 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14482 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14483 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14484 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14485 { 6777 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14486 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14487 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14488 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14489 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14490 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14491 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14492 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14493 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14494 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14495 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14496 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14497 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14498 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14499 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14500 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14501 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14502 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14503 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14504 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14505 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14506 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14507 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14508 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14509 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14510 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14511 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14512 { 6794 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14513 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14514 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14515 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14516 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14517 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14518 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14519 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14520 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14521 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14522 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14523 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14524 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14525 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14526 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14527 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14528 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14529 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14530 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14531 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14532 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14533 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14534 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14535 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14536 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14537 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14538 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14539 { 6813 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14540 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14541 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14542 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14543 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14544 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14545 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14546 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14547 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14548 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14549 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14550 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14551 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14552 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14553 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14554 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14555 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14556 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14557 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14558 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14559 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14560 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14561 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14562 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14563 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14564 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14565 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14566 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14567 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14568 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14569 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14570 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14571 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14572 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14573 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14574 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14575 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14576 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14577 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14578 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14579 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14580 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14581 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14582 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14583 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14584 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14585 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14586 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14587 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14588 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14589 { 6829 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14590 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14591 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14592 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14593 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14594 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14595 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14596 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14597 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14598 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14599 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14600 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14601 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14602 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14603 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14604 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14605 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14606 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14607 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14608 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14609 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14610 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14611 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14612 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14613 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14614 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14615 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14616 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14617 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14618 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14619 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14620 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14621 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14622 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14623 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14624 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14625 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14626 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14627 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14628 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14629 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14630 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14631 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14632 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14633 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14634 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14635 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14636 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14637 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14638 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14639 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14640 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14641 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14642 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14643 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14644 { 6843 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14645 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14646 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14647 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14648 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14649 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14650 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14651 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14652 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14653 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14654 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14655 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14656 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14657 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14658 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14659 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14660 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14661 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14662 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14663 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14664 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14665 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14666 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14667 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14668 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14669 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14670 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14671 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14672 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14673 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14674 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14675 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14676 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14677 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14678 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14679 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14680 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14681 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14682 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14683 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14684 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14685 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14686 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14687 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14688 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14689 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14690 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14691 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14692 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14693 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14694 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14695 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14696 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14697 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14698 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14699 { 6861 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14700 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14701 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14702 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14703 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14704 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14705 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14706 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14707 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14708 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14709 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14710 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14711 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14712 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14713 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14714 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14715 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14716 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14717 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14718 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14719 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14720 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14721 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14722 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14723 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14724 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14725 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14726 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14727 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14728 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14729 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14730 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14731 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14732 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14733 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14734 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14735 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14736 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14737 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14738 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14739 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14740 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14741 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14742 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14743 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14744 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14745 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14746 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14747 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14748 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14749 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14750 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14751 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14752 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14753 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14754 { 6872 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14755 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14756 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14757 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14758 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14759 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14760 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14761 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14762 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14763 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14764 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14765 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14766 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14767 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14768 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14769 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14770 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14771 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14772 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14773 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14774 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14775 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14776 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14777 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14778 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14779 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14780 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14781 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14782 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14783 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14784 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14785 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14786 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14787 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14788 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14789 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14790 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14791 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14792 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14793 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14794 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14795 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14796 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14797 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14798 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14799 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14800 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14801 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14802 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14803 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14804 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14805 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14806 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14807 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14808 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14809 { 6887 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14810 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14811 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14812 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14813 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14814 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14815 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14816 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14817 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14818 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14819 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14820 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14821 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14822 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14823 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14824 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14825 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14826 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14827 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14828 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14829 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14830 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14831 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14832 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14833 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14834 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14835 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14836 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14837 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14838 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14839 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14840 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14841 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14842 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14843 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14844 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14845 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14846 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14847 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14848 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14849 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14850 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14851 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14852 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14853 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14854 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14855 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14856 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14857 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14858 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14859 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14860 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14861 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14862 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14863 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14864 { 6906 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14865 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14866 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14867 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14868 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14869 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14870 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14871 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14872 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14873 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14874 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14875 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14876 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14877 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14878 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14879 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14880 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14881 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14882 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14883 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14884 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14885 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14886 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14887 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14888 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14889 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14890 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14891 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14892 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14893 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14894 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14895 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14896 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14897 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14898 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14899 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14900 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14901 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14902 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14903 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14904 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14905 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14906 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14907 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14908 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14909 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14910 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14911 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14912 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14913 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14914 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14915 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14916 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14917 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14918 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14919 { 6929 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14920 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14921 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14922 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14923 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14924 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14925 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14926 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14927 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14928 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14929 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14930 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14931 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14932 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14933 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14934 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14935 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14936 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14937 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14938 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14939 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
14940 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14941 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14942 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14943 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14944 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14945 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14946 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14947 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14948 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14949 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14950 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14951 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14952 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14953 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14954 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14955 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14956 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14957 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14958 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14959 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14960 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14961 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14962 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14963 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14964 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14965 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14966 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14967 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14968 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14969 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14970 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14971 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14972 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14973 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14974 { 6944 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
14975 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14976 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14977 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14978 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14979 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14980 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14981 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14982 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14983 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14984 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14985 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14986 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14987 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14988 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14989 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14990 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14991 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14992 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14993 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14994 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
14995 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14996 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14997 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14998 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
14999 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15000 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15001 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15002 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15003 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15004 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15005 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15006 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15007 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15008 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15009 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15010 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15011 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15012 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15013 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15014 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15015 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15016 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15017 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15018 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15019 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15020 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15021 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15022 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15023 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15024 { 6963 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15025 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15026 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15027 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15028 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15029 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15030 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15031 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15032 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15033 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15034 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15035 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15036 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15037 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15038 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15039 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15040 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15041 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15042 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15043 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15044 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15045 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15046 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15047 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15048 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15049 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15050 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15051 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15052 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15053 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15054 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15055 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15056 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15057 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15058 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15059 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15060 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15061 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15062 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15063 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15064 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15065 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15066 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15067 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15068 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15069 { 6976 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15070 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15071 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15072 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15073 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15074 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15075 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15076 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15077 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15078 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15079 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15080 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15081 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15082 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15083 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15084 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15085 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15086 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15087 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15088 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15089 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15090 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15091 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15092 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15093 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15094 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15095 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15096 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15097 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15098 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15099 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15100 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15101 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15102 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15103 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15104 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15105 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15106 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15107 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15108 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15109 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15110 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15111 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15112 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15113 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15114 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15115 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15116 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15117 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15118 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15119 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15120 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15121 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15122 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15123 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15124 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15125 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15126 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15127 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15128 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15129 { 6991 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15130 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15131 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15132 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15133 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15134 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15135 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15136 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15137 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15138 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15139 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15140 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15141 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15142 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15143 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15144 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15145 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15146 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15147 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15148 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15149 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15150 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15151 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15152 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15153 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15154 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15155 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15156 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15157 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15158 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15159 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15160 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15161 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15162 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15163 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15164 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15165 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15166 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15167 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15168 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15169 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15170 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15171 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15172 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15173 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15174 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15175 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15176 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15177 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15178 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15179 { 7009 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15180 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15181 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15182 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15183 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15184 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15185 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15186 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15187 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15188 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15189 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15190 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15191 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15192 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15193 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15194 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15195 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15196 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15197 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15198 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15199 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15200 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15201 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15202 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15203 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15204 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15205 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15206 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15207 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15208 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15209 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15210 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15211 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15212 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15213 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15214 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15215 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15216 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15217 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15218 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15219 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15220 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15221 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15222 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15223 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15224 { 7029 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15225 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15226 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15227 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15228 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15229 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15230 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15231 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15232 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15233 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15234 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15235 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15236 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15237 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15238 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15239 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15240 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15241 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15242 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15243 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15244 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15245 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15246 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15247 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15248 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15249 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15250 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15251 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15252 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15253 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15254 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15255 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15256 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15257 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15258 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15259 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15260 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15261 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15262 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15263 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15264 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15265 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15266 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15267 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15268 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15269 { 7046 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15270 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15271 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15272 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15273 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15274 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15275 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15276 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15277 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15278 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15279 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15280 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15281 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15282 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15283 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15284 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15285 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15286 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15287 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15288 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15289 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15290 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15291 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15292 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15293 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15294 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15295 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15296 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15297 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15298 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15299 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15300 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15301 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15302 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15303 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15304 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15305 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15306 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15307 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15308 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15309 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15310 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15311 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15312 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15313 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15314 { 7061 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15315 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15316 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15317 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15318 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15319 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15320 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15321 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15322 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15323 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15324 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15325 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15326 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15327 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15328 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15329 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15330 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15331 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15332 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15333 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15334 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15335 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15336 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15337 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15338 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15339 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15340 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15341 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15342 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15343 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15344 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15345 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15346 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15347 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15348 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15349 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15350 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15351 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15352 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15353 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15354 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15355 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15356 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15357 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15358 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15359 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15360 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15361 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15362 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15363 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15364 { 7078 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15365 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15366 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15367 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15368 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15369 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15370 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15371 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15372 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15373 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15374 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15375 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15376 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15377 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15378 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15379 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15380 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15381 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15382 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15383 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15384 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15385 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15386 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15387 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15388 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15389 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15390 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15391 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15392 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15393 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15394 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15395 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15396 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15397 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15398 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15399 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15400 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15401 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15402 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15403 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15404 { 7098 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15405 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15406 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15407 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15408 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15409 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15410 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15411 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15412 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15413 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15414 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15415 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15416 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15417 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15418 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15419 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15420 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15421 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15422 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15423 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15424 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15425 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15426 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15427 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15428 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15429 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15430 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15431 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15432 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15433 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15434 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15435 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15436 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15437 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15438 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15439 { 7120 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15440 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15441 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15442 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15443 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15444 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15445 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15446 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15447 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15448 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15449 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15450 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15451 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15452 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15453 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15454 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15455 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15456 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15457 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15458 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15459 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15460 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15461 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15462 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15463 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15464 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15465 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15466 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15467 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15468 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15469 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15470 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15471 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15472 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15473 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15474 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15475 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15476 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15477 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15478 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15479 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15480 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15481 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15482 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15483 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15484 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15485 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15486 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15487 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15488 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15489 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15490 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15491 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15492 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15493 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15494 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15495 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15496 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15497 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15498 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15499 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15500 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15501 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15502 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15503 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15504 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15505 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15506 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15507 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15508 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15509 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15510 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V5_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15511 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15512 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15513 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15514 { 7139 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15515 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15516 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15517 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15518 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15519 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15520 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15521 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15522 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15523 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15524 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15525 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15526 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15527 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15528 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15529 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15530 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15531 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15532 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15533 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15534 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15535 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15536 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15537 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15538 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15539 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15540 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15541 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15542 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15543 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15544 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15545 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15546 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15547 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15548 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15549 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15550 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15551 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15552 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15553 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15554 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15555 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15556 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15557 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15558 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15559 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15560 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15561 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15562 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15563 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15564 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15565 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15566 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15567 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15568 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15569 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15570 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15571 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15572 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15573 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15574 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15575 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15576 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15577 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15578 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15579 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15580 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15581 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15582 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15583 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15584 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15585 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V5_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15586 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15587 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15588 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15589 { 7157 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15590 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15591 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15592 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15593 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15594 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15595 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15596 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15597 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15598 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15599 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15600 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15601 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15602 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15603 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15604 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15605 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15606 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15607 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15608 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15609 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15610 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15611 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15612 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15613 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15614 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15615 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15616 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15617 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15618 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15619 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15620 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15621 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15622 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15623 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15624 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15625 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15626 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15627 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15628 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15629 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15630 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15631 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15632 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15633 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15634 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15635 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15636 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15637 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15638 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15639 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15640 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15641 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15642 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15643 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15644 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15645 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15646 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15647 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15648 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15649 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15650 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V5_V12_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15651 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V12_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15652 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V12_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15653 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V12_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15654 { 7178 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V12_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15655 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15656 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15657 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15658 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15659 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15660 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15661 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15662 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15663 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15664 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15665 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15666 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15667 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15668 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15669 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15670 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15671 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15672 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15673 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15674 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15675 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15676 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15677 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15678 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15679 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15680 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15681 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15682 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15683 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15684 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15685 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15686 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15687 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15688 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15689 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15690 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15691 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15692 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15693 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15694 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15695 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15696 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15697 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15698 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15699 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15700 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15701 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15702 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15703 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15704 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15705 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15706 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15707 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15708 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15709 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15710 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15711 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15712 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15713 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15714 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15715 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V5_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15716 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15717 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15718 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15719 { 7201 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15720 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15721 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15722 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15723 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15724 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15725 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15726 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15727 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15728 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15729 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15730 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15731 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15732 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15733 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15734 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15735 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15736 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15737 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15738 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15739 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15740 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15741 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15742 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15743 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15744 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15745 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15746 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15747 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15748 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15749 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15750 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15751 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15752 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15753 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15754 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15755 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15756 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15757 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15758 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15759 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15760 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15761 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15762 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15763 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15764 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15765 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15766 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15767 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15768 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15769 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15770 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15771 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15772 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15773 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15774 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15775 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15776 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15777 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15778 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15779 { 7221 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15780 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15781 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15782 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15783 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15784 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15785 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15786 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15787 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15788 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15789 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15790 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15791 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15792 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15793 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15794 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15795 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15796 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15797 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15798 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15799 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15800 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15801 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15802 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15803 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15804 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15805 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15806 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15807 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15808 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15809 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15810 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15811 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15812 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15813 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15814 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15815 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15816 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15817 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15818 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15819 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15820 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15821 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15822 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15823 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15824 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15825 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15826 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15827 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15828 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15829 { 7239 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15830 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15831 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15832 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15833 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15834 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15835 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15836 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15837 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15838 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15839 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15840 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15841 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15842 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15843 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15844 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15845 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15846 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15847 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15848 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15849 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15850 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15851 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15852 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15853 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15854 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15855 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15856 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15857 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15858 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15859 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15860 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15861 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15862 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15863 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15864 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15865 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15866 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15867 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15868 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15869 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15870 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15871 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15872 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15873 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15874 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15875 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15876 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15877 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15878 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15879 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15880 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15881 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15882 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15883 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15884 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15885 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15886 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15887 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15888 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15889 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15890 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15891 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15892 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15893 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15894 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15895 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15896 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15897 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15898 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15899 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15900 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V5_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15901 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15902 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15903 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15904 { 7259 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15905 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15906 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15907 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15908 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15909 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15910 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15911 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15912 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15913 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15914 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15915 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15916 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15917 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15918 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15919 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15920 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15921 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15922 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15923 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15924 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15925 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15926 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15927 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15928 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15929 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15930 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15931 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15932 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15933 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15934 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15935 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15936 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15937 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15938 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15939 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15940 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15941 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15942 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15943 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15944 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15945 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15946 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15947 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15948 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15949 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15950 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15951 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15952 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15953 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15954 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15955 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15956 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15957 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15958 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15959 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15960 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15961 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15962 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15963 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15964 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15965 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15966 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15967 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15968 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15969 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15970 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15971 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15972 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15973 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15974 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15975 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V5_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15976 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15977 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15978 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15979 { 7276 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15980 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15981 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15982 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15983 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15984 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15985 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15986 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15987 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15988 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15989 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15990 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15991 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15992 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15993 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15994 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
15995 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15996 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15997 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15998 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
15999 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16000 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16001 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16002 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16003 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16004 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16005 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16006 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16007 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16008 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16009 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16010 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16011 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16012 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16013 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16014 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16015 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16016 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16017 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16018 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16019 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16020 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16021 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16022 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16023 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16024 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16025 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16026 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16027 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16028 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16029 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16030 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16031 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16032 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16033 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16034 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16035 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16036 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16037 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16038 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16039 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16040 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V5_V12_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16041 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V12_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16042 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V12_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16043 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V12_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16044 { 7296 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V12_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16045 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16046 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16047 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16048 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16049 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16050 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16051 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16052 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16053 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16054 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16055 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16056 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16057 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16058 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16059 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16060 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16061 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16062 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16063 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16064 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16065 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16066 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16067 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16068 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16069 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16070 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16071 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16072 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16073 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16074 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16075 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16076 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16077 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16078 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16079 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16080 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16081 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16082 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16083 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16084 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16085 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16086 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16087 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16088 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16089 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16090 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16091 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16092 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16093 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16094 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16095 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16096 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16097 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16098 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16099 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16100 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16101 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16102 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16103 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16104 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16105 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V5_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16106 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16107 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16108 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16109 { 7318 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16110 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16111 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16112 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16113 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16114 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16115 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16116 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16117 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16118 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16119 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16120 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16121 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16122 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16123 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16124 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16125 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16126 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16127 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16128 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16129 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16130 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16131 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16132 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16133 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16134 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16135 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16136 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16137 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16138 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16139 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16140 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16141 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16142 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16143 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16144 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16145 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16146 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16147 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16148 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16149 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16150 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16151 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16152 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16153 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16154 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16155 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16156 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16157 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16158 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16159 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16160 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16161 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16162 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16163 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16164 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16165 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16166 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16167 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16168 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16169 { 7337 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16170 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16171 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16172 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16173 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16174 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16175 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16176 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16177 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16178 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16179 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16180 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16181 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16182 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16183 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16184 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16185 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16186 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16187 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16188 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16189 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16190 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16191 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16192 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16193 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16194 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16195 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16196 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16197 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16198 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16199 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16200 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16201 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16202 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16203 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16204 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16205 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16206 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16207 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16208 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16209 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16210 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16211 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16212 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16213 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16214 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16215 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16216 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16217 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16218 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16219 { 7354 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16220 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16221 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16222 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16223 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16224 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16225 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16226 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16227 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16228 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16229 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16230 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16231 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16232 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16233 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16234 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16235 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16236 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16237 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16238 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16239 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16240 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16241 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16242 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16243 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16244 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16245 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16246 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16247 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16248 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16249 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16250 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16251 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16252 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16253 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16254 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16255 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16256 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16257 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16258 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16259 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16260 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16261 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16262 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16263 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16264 { 7373 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16265 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16266 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16267 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16268 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16269 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16270 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16271 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16272 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16273 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16274 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16275 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16276 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16277 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16278 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16279 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16280 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16281 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16282 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16283 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16284 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16285 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16286 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16287 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16288 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16289 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16290 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16291 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16292 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16293 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16294 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16295 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16296 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16297 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16298 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16299 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16300 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16301 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16302 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16303 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16304 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16305 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16306 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16307 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16308 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16309 { 7391 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16310 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16311 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16312 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16313 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16314 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16315 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16316 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16317 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16318 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16319 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16320 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16321 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16322 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16323 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16324 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16325 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16326 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16327 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16328 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16329 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16330 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16331 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16332 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16333 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16334 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16335 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16336 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16337 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16338 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16339 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16340 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16341 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16342 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16343 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16344 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16345 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16346 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16347 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16348 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16349 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16350 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16351 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16352 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16353 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16354 { 7411 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16355 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16356 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16357 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16358 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16359 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16360 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16361 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16362 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16363 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16364 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16365 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16366 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16367 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16368 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16369 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16370 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16371 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16372 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16373 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16374 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16375 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16376 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16377 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16378 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16379 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16380 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16381 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16382 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16383 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16384 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16385 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16386 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16387 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16388 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16389 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16390 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16391 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16392 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16393 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16394 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16395 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16396 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16397 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16398 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16399 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16400 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16401 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16402 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16403 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16404 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16405 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16406 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16407 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16408 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16409 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16410 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16411 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16412 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16413 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16414 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16415 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16416 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16417 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16418 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16419 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16420 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16421 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16422 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16423 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16424 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16425 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16426 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16427 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16428 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16429 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16430 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16431 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16432 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16433 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16434 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16435 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V5_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16436 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16437 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16438 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16439 { 7428 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16440 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16441 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16442 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16443 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16444 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16445 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16446 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16447 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16448 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16449 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16450 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16451 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16452 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16453 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16454 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16455 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16456 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16457 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16458 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16459 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16460 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16461 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16462 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16463 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16464 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16465 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16466 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16467 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16468 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16469 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16470 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16471 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16472 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16473 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16474 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16475 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16476 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16477 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16478 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16479 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16480 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16481 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16482 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16483 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16484 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16485 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16486 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16487 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16488 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16489 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16490 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16491 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16492 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16493 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16494 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16495 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16496 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16497 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16498 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16499 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16500 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16501 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16502 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16503 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16504 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16505 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16506 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16507 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16508 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16509 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16510 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16511 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16512 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16513 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16514 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16515 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16516 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16517 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16518 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16519 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16520 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V5_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16521 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16522 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16523 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16524 { 7444 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16525 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16526 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16527 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16528 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16529 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16530 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16531 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16532 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16533 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16534 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16535 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16536 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16537 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16538 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16539 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16540 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16541 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16542 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16543 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16544 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16545 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16546 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16547 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16548 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16549 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16550 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16551 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16552 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16553 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16554 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16555 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16556 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16557 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16558 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16559 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16560 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16561 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16562 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16563 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16564 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16565 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16566 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16567 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16568 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16569 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16570 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16571 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16572 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16573 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16574 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16575 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16576 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16577 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16578 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16579 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16580 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16581 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16582 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16583 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16584 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16585 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16586 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16587 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16588 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16589 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16590 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16591 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16592 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16593 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16594 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16595 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V5_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16596 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16597 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16598 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16599 { 7463 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16600 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16601 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16602 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16603 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16604 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16605 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16606 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16607 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16608 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16609 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16610 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16611 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16612 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16613 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16614 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16615 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16616 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16617 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16618 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16619 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16620 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16621 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16622 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16623 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16624 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16625 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16626 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16627 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16628 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16629 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16630 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16631 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16632 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16633 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16634 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16635 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16636 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16637 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16638 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16639 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16640 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16641 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16642 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16643 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16644 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16645 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16646 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16647 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16648 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16649 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16650 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16651 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16652 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16653 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16654 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16655 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16656 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16657 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16658 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16659 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16660 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16661 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16662 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16663 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16664 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16665 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16666 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16667 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16668 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16669 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16670 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V5_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16671 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16672 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16673 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16674 { 7484 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16675 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16676 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16677 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16678 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16679 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16680 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16681 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16682 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16683 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16684 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16685 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16686 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16687 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16688 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16689 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16690 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16691 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16692 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16693 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16694 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16695 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16696 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16697 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16698 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16699 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16700 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16701 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16702 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16703 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16704 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16705 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16706 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16707 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16708 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16709 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16710 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16711 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16712 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16713 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16714 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16715 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16716 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16717 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16718 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16719 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16720 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16721 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16722 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16723 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16724 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16725 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16726 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16727 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16728 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16729 { 7502 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16730 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16731 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16732 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16733 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16734 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16735 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16736 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16737 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16738 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16739 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16740 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16741 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16742 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16743 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16744 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16745 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16746 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16747 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16748 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16749 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16750 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16751 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16752 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16753 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16754 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16755 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16756 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16757 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16758 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16759 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16760 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16761 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16762 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16763 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16764 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16765 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16766 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16767 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16768 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16769 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16770 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16771 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16772 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16773 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16774 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16775 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16776 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16777 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16778 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16779 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16780 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16781 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16782 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16783 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16784 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16785 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16786 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16787 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16788 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16789 { 7518 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16790 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16791 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16792 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16793 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16794 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16795 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16796 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16797 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16798 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16799 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16800 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16801 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16802 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16803 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16804 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16805 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16806 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16807 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16808 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16809 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16810 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16811 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16812 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16813 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16814 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16815 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16816 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16817 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16818 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16819 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16820 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16821 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16822 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16823 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16824 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16825 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16826 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16827 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16828 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16829 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16830 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16831 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16832 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16833 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16834 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16835 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16836 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16837 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16838 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16839 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16840 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16841 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16842 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16843 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16844 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16845 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16846 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16847 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16848 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16849 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16850 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16851 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16852 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16853 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16854 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16855 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16856 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16857 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16858 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16859 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16860 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16861 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16862 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16863 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16864 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16865 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16866 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16867 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16868 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16869 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16870 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V5_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16871 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16872 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16873 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16874 { 7536 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16875 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16876 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16877 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16878 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16879 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16880 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16881 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16882 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16883 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16884 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16885 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16886 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16887 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16888 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16889 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16890 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16891 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16892 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16893 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16894 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16895 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16896 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16897 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16898 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16899 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16900 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16901 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16902 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16903 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16904 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16905 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16906 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16907 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16908 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16909 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16910 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16911 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16912 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16913 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16914 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16915 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16916 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16917 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16918 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16919 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16920 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16921 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16922 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16923 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16924 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16925 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16926 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16927 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16928 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16929 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16930 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16931 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16932 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16933 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16934 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16935 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16936 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16937 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16938 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16939 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16940 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16941 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16942 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16943 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16944 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16945 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16946 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16947 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16948 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16949 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16950 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16951 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16952 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16953 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16954 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16955 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V5_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16956 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16957 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16958 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16959 { 7551 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16960 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16961 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16962 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16963 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16964 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16965 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16966 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16967 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16968 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16969 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16970 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16971 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16972 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16973 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16974 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16975 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16976 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16977 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16978 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16979 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
16980 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16981 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16982 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16983 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16984 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16985 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16986 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16987 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16988 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16989 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16990 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16991 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16992 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16993 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16994 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16995 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16996 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16997 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16998 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
16999 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17000 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17001 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17002 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17003 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17004 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17005 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17006 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17007 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17008 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17009 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17010 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17011 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17012 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17013 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17014 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17015 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17016 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17017 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17018 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17019 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17020 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17021 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17022 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17023 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17024 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17025 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17026 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17027 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17028 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17029 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V9_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17030 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V5_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17031 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17032 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17033 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17034 { 7569 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V11_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17035 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17036 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17037 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17038 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17039 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17040 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17041 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17042 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17043 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17044 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17045 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17046 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17047 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17048 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17049 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17050 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17051 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V16, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17052 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17053 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17054 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17055 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17056 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17057 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17058 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17059 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17060 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17061 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17062 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17063 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17064 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17065 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17066 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17067 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17068 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17069 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17070 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17071 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V16_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17072 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17073 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17074 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17075 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17076 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17077 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17078 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17079 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17080 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17081 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17082 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17083 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17084 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17085 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17086 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17087 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17088 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17089 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17090 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17091 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17092 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17093 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17094 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V6_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17095 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17096 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17097 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17098 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17099 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V7_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17100 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17101 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17102 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17103 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17104 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V8_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17105 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V5_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17106 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17107 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17108 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17109 { 7589 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V10_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17110 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17111 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17112 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17113 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17114 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17115 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17116 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17117 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17118 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17119 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17120 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17121 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17122 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17123 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17124 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17125 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17126 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17127 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17128 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17129 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17130 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17131 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17132 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17133 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17134 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17135 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17136 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17137 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17138 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17139 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17140 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17141 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17142 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17143 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17144 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17145 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17146 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17147 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17148 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17149 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17150 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17151 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17152 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17153 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17154 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17155 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17156 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17157 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17158 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17159 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17160 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17161 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17162 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17163 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17164 { 7606 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17165 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17166 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17167 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17168 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17169 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17170 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17171 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17172 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17173 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17174 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17175 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17176 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17177 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17178 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17179 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17180 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17181 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V8, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17182 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17183 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17184 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17185 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17186 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17187 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17188 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17189 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17190 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17191 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17192 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17193 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17194 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17195 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17196 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17197 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17198 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17199 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17200 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17201 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V8_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17202 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17203 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17204 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17205 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17206 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17207 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17208 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17209 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17210 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17211 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17212 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17213 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17214 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17215 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17216 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17217 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17218 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17219 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17220 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V5_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17221 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17222 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17223 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17224 { 7621 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V5_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17225 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17226 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17227 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17228 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V5_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17229 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17230 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17231 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17232 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17233 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17234 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17235 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17236 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17237 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17238 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17239 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17240 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17241 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17242 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17243 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17244 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17245 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17246 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17247 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17248 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V5_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17249 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17250 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17251 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17252 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17253 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17254 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17255 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17256 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17257 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17258 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17259 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17260 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17261 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17262 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17263 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17264 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17265 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17266 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17267 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17268 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17269 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17270 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17271 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17272 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17273 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17274 { 7638 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17275 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17276 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17277 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17278 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17279 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17280 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17281 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17282 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17283 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17284 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17285 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17286 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17287 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17288 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17289 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17290 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17291 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17292 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17293 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17294 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17295 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17296 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17297 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17298 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17299 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17300 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17301 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17302 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17303 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17304 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17305 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17306 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17307 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17308 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17309 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17310 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17311 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17312 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17313 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17314 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17315 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17316 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17317 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17318 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17319 { 7654 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17320 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V5_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17321 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V5_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17322 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V5_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17323 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17324 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17325 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17326 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17327 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17328 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17329 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17330 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17331 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17332 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17333 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17334 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17335 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V5_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17336 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V5_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17337 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V5_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17338 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17339 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17340 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17341 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17342 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17343 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17344 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17345 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17346 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17347 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17348 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17349 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17350 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V5_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17351 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17352 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17353 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17354 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17355 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V5_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17356 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17357 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17358 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17359 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17360 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V5_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_160, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17361 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17362 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17363 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17364 { 7672 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17365 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17366 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17367 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17368 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17369 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17370 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17371 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17372 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17373 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17374 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17375 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17376 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17377 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17378 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17379 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17380 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17381 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17382 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17383 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17384 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17385 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17386 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17387 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17388 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17389 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17390 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17391 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17392 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17393 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17394 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17395 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17396 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17397 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17398 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17399 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17400 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17401 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17402 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17403 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17404 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17405 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17406 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17407 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17408 { 7687 /* image_store */, AMDGPU::IMAGE_STORE_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17409 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17410 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17411 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17412 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17413 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17414 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17415 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17416 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17417 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17418 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17419 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17420 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17421 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17422 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17423 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17424 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
17425 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17426 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17427 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17428 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17429 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17430 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17431 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17432 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17433 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17434 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17435 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17436 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17437 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17438 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17439 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17440 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17441 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17442 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17443 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17444 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17445 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17446 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17447 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17448 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17449 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17450 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17451 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17452 { 7699 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmD16 }, },
17453 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17454 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17455 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17456 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17457 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17458 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17459 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17460 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17461 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17462 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17463 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17464 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17465 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17466 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17467 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17468 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17469 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17470 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17471 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17472 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17473 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17474 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17475 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17476 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17477 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17478 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17479 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17480 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17481 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17482 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17483 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17484 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17485 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17486 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17487 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17488 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17489 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17490 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17491 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17492 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17493 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17494 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17495 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17496 { 7715 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17497 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17498 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17499 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17500 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17501 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17502 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17503 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17504 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17505 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17506 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17507 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17508 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17509 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V4, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17510 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V3, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17511 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V2, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17512 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V1, ConvertCustom_cvtMIMG, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
17513 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17514 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17515 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17516 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17517 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17518 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17519 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17520 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17521 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17522 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17523 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17524 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17525 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V4_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17526 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V3_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17527 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V2_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17528 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V1_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17529 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17530 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17531 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17532 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V2_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17533 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17534 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17535 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17536 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V3_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17537 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_128, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17538 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_96, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17539 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
17540 { 7735 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V4_nsa_gfx10, ConvertCustom_cvtMIMG, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK__93_, MCK_SReg_256, MCK_ImmDMask, MCK_ImmDim, MCK_ImmUNorm, MCK_ImmDLC, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE }, },
18075 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18076 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18077 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18078 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18079 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18080 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18081 { 9380 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, },
18082 { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_512, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18083 { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_512, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18084 { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_512, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18085 { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_512, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18086 { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_512, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18087 { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_512, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18088 { 9400 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_512, MCK_SReg_128, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, },
18089 { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18090 { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18091 { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18092 { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18093 { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18094 { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18095 { 9423 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, },
18096 { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18097 { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18098 { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18099 { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18100 { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18101 { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18102 { 9445 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, },
18103 { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_256, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18104 { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_256, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18105 { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_256, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18106 { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_256, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18107 { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_256, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18108 { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_256, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18109 { 9467 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_256, MCK_SReg_128, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, },
18110 { 9489 /* s_buffer_store_dword */, AMDGPU::S_BUFFER_STORE_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18111 { 9489 /* s_buffer_store_dword */, AMDGPU::S_BUFFER_STORE_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18112 { 9489 /* s_buffer_store_dword */, AMDGPU::S_BUFFER_STORE_DWORD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18113 { 9489 /* s_buffer_store_dword */, AMDGPU::S_BUFFER_STORE_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18114 { 9510 /* s_buffer_store_dwordx2 */, AMDGPU::S_BUFFER_STORE_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18115 { 9510 /* s_buffer_store_dwordx2 */, AMDGPU::S_BUFFER_STORE_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18116 { 9510 /* s_buffer_store_dwordx2 */, AMDGPU::S_BUFFER_STORE_DWORDX2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18117 { 9510 /* s_buffer_store_dwordx2 */, AMDGPU::S_BUFFER_STORE_DWORDX2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18118 { 9533 /* s_buffer_store_dwordx4 */, AMDGPU::S_BUFFER_STORE_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18119 { 9533 /* s_buffer_store_dwordx4 */, AMDGPU::S_BUFFER_STORE_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18120 { 9533 /* s_buffer_store_dwordx4 */, AMDGPU::S_BUFFER_STORE_DWORDX4_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18121 { 9533 /* s_buffer_store_dwordx4 */, AMDGPU::S_BUFFER_STORE_DWORDX4_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18273 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18274 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18275 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18276 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18277 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18278 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18279 { 10626 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, },
18280 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_512, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18281 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_512, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18282 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_512, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18283 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_512, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18284 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_512, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18285 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_512, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18286 { 10639 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_512, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, },
18287 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18288 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18289 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18290 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18291 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18292 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18293 { 10655 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, },
18294 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18295 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18296 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18297 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18298 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18299 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18300 { 10670 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, },
18301 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_256, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18302 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_256, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18303 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_256, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18304 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX6GFX7, { MCK_SReg_256, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC, MCK_ImmDLC }, },
18305 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX10Plus, { MCK_SReg_256, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18306 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX8GFX9, { MCK_SReg_256, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18307 { 10685 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_isGFX7Only, { MCK_SReg_256, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC, MCK_ImmDLC }, },
18449 { 11480 /* s_scratch_load_dword */, AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18450 { 11480 /* s_scratch_load_dword */, AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18451 { 11480 /* s_scratch_load_dword */, AMDGPU::S_SCRATCH_LOAD_DWORD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18452 { 11480 /* s_scratch_load_dword */, AMDGPU::S_SCRATCH_LOAD_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18453 { 11501 /* s_scratch_load_dwordx2 */, AMDGPU::S_SCRATCH_LOAD_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18454 { 11501 /* s_scratch_load_dwordx2 */, AMDGPU::S_SCRATCH_LOAD_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18455 { 11501 /* s_scratch_load_dwordx2 */, AMDGPU::S_SCRATCH_LOAD_DWORDX2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18456 { 11501 /* s_scratch_load_dwordx2 */, AMDGPU::S_SCRATCH_LOAD_DWORDX2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18457 { 11524 /* s_scratch_load_dwordx4 */, AMDGPU::S_SCRATCH_LOAD_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18458 { 11524 /* s_scratch_load_dwordx4 */, AMDGPU::S_SCRATCH_LOAD_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18459 { 11524 /* s_scratch_load_dwordx4 */, AMDGPU::S_SCRATCH_LOAD_DWORDX4_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18460 { 11524 /* s_scratch_load_dwordx4 */, AMDGPU::S_SCRATCH_LOAD_DWORDX4_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18461 { 11547 /* s_scratch_store_dword */, AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18462 { 11547 /* s_scratch_store_dword */, AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18463 { 11547 /* s_scratch_store_dword */, AMDGPU::S_SCRATCH_STORE_DWORD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18464 { 11547 /* s_scratch_store_dword */, AMDGPU::S_SCRATCH_STORE_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18465 { 11569 /* s_scratch_store_dwordx2 */, AMDGPU::S_SCRATCH_STORE_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18466 { 11569 /* s_scratch_store_dwordx2 */, AMDGPU::S_SCRATCH_STORE_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18467 { 11569 /* s_scratch_store_dwordx2 */, AMDGPU::S_SCRATCH_STORE_DWORDX2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18468 { 11569 /* s_scratch_store_dwordx2 */, AMDGPU::S_SCRATCH_STORE_DWORDX2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18469 { 11593 /* s_scratch_store_dwordx4 */, AMDGPU::S_SCRATCH_STORE_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18470 { 11593 /* s_scratch_store_dwordx4 */, AMDGPU::S_SCRATCH_STORE_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18471 { 11593 /* s_scratch_store_dwordx4 */, AMDGPU::S_SCRATCH_STORE_DWORDX4_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18472 { 11593 /* s_scratch_store_dwordx4 */, AMDGPU::S_SCRATCH_STORE_DWORDX4_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18499 { 11835 /* s_store_dword */, AMDGPU::S_STORE_DWORD_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18500 { 11835 /* s_store_dword */, AMDGPU::S_STORE_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18501 { 11835 /* s_store_dword */, AMDGPU::S_STORE_DWORD_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18502 { 11835 /* s_store_dword */, AMDGPU::S_STORE_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18503 { 11849 /* s_store_dwordx2 */, AMDGPU::S_STORE_DWORDX2_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18504 { 11849 /* s_store_dwordx2 */, AMDGPU::S_STORE_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18505 { 11849 /* s_store_dwordx2 */, AMDGPU::S_STORE_DWORDX2_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18506 { 11849 /* s_store_dwordx2 */, AMDGPU::S_STORE_DWORDX2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18507 { 11865 /* s_store_dwordx4 */, AMDGPU::S_STORE_DWORDX4_SGPR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18508 { 11865 /* s_store_dwordx4 */, AMDGPU::S_STORE_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC, MCK_ImmDLC }, },
18509 { 11865 /* s_store_dwordx4 */, AMDGPU::S_STORE_DWORDX4_IMM_gfx10, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX10Plus, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18510 { 11865 /* s_store_dwordx4 */, AMDGPU::S_STORE_DWORDX4_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3__ImmDLC1_4, AMFBS_HasScalarStores_isGFX8GFX9, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC, MCK_ImmDLC }, },
18563 { 12271 /* scratch_load_dword */, AMDGPU::SCRATCH_LOAD_DWORD_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18564 { 12271 /* scratch_load_dword */, AMDGPU::SCRATCH_LOAD_DWORD_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18565 { 12271 /* scratch_load_dword */, AMDGPU::SCRATCH_LOAD_DWORD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18566 { 12271 /* scratch_load_dword */, AMDGPU::SCRATCH_LOAD_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18567 { 12290 /* scratch_load_dwordx2 */, AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18568 { 12290 /* scratch_load_dwordx2 */, AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18569 { 12290 /* scratch_load_dwordx2 */, AMDGPU::SCRATCH_LOAD_DWORDX2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18570 { 12290 /* scratch_load_dwordx2 */, AMDGPU::SCRATCH_LOAD_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18571 { 12311 /* scratch_load_dwordx3 */, AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18572 { 12311 /* scratch_load_dwordx3 */, AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18573 { 12311 /* scratch_load_dwordx3 */, AMDGPU::SCRATCH_LOAD_DWORDX3_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18574 { 12311 /* scratch_load_dwordx3 */, AMDGPU::SCRATCH_LOAD_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18575 { 12332 /* scratch_load_dwordx4 */, AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18576 { 12332 /* scratch_load_dwordx4 */, AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18577 { 12332 /* scratch_load_dwordx4 */, AMDGPU::SCRATCH_LOAD_DWORDX4_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18578 { 12332 /* scratch_load_dwordx4 */, AMDGPU::SCRATCH_LOAD_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18579 { 12353 /* scratch_load_sbyte */, AMDGPU::SCRATCH_LOAD_SBYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18580 { 12353 /* scratch_load_sbyte */, AMDGPU::SCRATCH_LOAD_SBYTE_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18581 { 12353 /* scratch_load_sbyte */, AMDGPU::SCRATCH_LOAD_SBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18582 { 12353 /* scratch_load_sbyte */, AMDGPU::SCRATCH_LOAD_SBYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18583 { 12372 /* scratch_load_sbyte_d16 */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18584 { 12372 /* scratch_load_sbyte_d16 */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18585 { 12372 /* scratch_load_sbyte_d16 */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18586 { 12372 /* scratch_load_sbyte_d16 */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18587 { 12395 /* scratch_load_sbyte_d16_hi */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18588 { 12395 /* scratch_load_sbyte_d16_hi */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18589 { 12395 /* scratch_load_sbyte_d16_hi */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18590 { 12395 /* scratch_load_sbyte_d16_hi */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18591 { 12421 /* scratch_load_short_d16 */, AMDGPU::SCRATCH_LOAD_SHORT_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18592 { 12421 /* scratch_load_short_d16 */, AMDGPU::SCRATCH_LOAD_SHORT_D16_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18593 { 12421 /* scratch_load_short_d16 */, AMDGPU::SCRATCH_LOAD_SHORT_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18594 { 12421 /* scratch_load_short_d16 */, AMDGPU::SCRATCH_LOAD_SHORT_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18595 { 12444 /* scratch_load_short_d16_hi */, AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18596 { 12444 /* scratch_load_short_d16_hi */, AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18597 { 12444 /* scratch_load_short_d16_hi */, AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18598 { 12444 /* scratch_load_short_d16_hi */, AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18599 { 12470 /* scratch_load_sshort */, AMDGPU::SCRATCH_LOAD_SSHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18600 { 12470 /* scratch_load_sshort */, AMDGPU::SCRATCH_LOAD_SSHORT_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18601 { 12470 /* scratch_load_sshort */, AMDGPU::SCRATCH_LOAD_SSHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18602 { 12470 /* scratch_load_sshort */, AMDGPU::SCRATCH_LOAD_SSHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18603 { 12490 /* scratch_load_ubyte */, AMDGPU::SCRATCH_LOAD_UBYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18604 { 12490 /* scratch_load_ubyte */, AMDGPU::SCRATCH_LOAD_UBYTE_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18605 { 12490 /* scratch_load_ubyte */, AMDGPU::SCRATCH_LOAD_UBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18606 { 12490 /* scratch_load_ubyte */, AMDGPU::SCRATCH_LOAD_UBYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18607 { 12509 /* scratch_load_ubyte_d16 */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18608 { 12509 /* scratch_load_ubyte_d16 */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18609 { 12509 /* scratch_load_ubyte_d16 */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18610 { 12509 /* scratch_load_ubyte_d16 */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18611 { 12532 /* scratch_load_ubyte_d16_hi */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18612 { 12532 /* scratch_load_ubyte_d16_hi */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18613 { 12532 /* scratch_load_ubyte_d16_hi */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18614 { 12532 /* scratch_load_ubyte_d16_hi */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18615 { 12558 /* scratch_load_ushort */, AMDGPU::SCRATCH_LOAD_USHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18616 { 12558 /* scratch_load_ushort */, AMDGPU::SCRATCH_LOAD_USHORT_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18617 { 12558 /* scratch_load_ushort */, AMDGPU::SCRATCH_LOAD_USHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18618 { 12558 /* scratch_load_ushort */, AMDGPU::SCRATCH_LOAD_USHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18619 { 12578 /* scratch_store_byte */, AMDGPU::SCRATCH_STORE_BYTE_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18620 { 12578 /* scratch_store_byte */, AMDGPU::SCRATCH_STORE_BYTE_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18621 { 12578 /* scratch_store_byte */, AMDGPU::SCRATCH_STORE_BYTE_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18622 { 12578 /* scratch_store_byte */, AMDGPU::SCRATCH_STORE_BYTE_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18623 { 12597 /* scratch_store_byte_d16_hi */, AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18624 { 12597 /* scratch_store_byte_d16_hi */, AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18625 { 12597 /* scratch_store_byte_d16_hi */, AMDGPU::SCRATCH_STORE_BYTE_D16_HI_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18626 { 12597 /* scratch_store_byte_d16_hi */, AMDGPU::SCRATCH_STORE_BYTE_D16_HI_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18627 { 12623 /* scratch_store_dword */, AMDGPU::SCRATCH_STORE_DWORD_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18628 { 12623 /* scratch_store_dword */, AMDGPU::SCRATCH_STORE_DWORD_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18629 { 12623 /* scratch_store_dword */, AMDGPU::SCRATCH_STORE_DWORD_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18630 { 12623 /* scratch_store_dword */, AMDGPU::SCRATCH_STORE_DWORD_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18631 { 12643 /* scratch_store_dwordx2 */, AMDGPU::SCRATCH_STORE_DWORDX2_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VReg_64, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18632 { 12643 /* scratch_store_dwordx2 */, AMDGPU::SCRATCH_STORE_DWORDX2_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VReg_64, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18633 { 12643 /* scratch_store_dwordx2 */, AMDGPU::SCRATCH_STORE_DWORDX2_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18634 { 12643 /* scratch_store_dwordx2 */, AMDGPU::SCRATCH_STORE_DWORDX2_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18635 { 12665 /* scratch_store_dwordx3 */, AMDGPU::SCRATCH_STORE_DWORDX3_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VReg_96, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18636 { 12665 /* scratch_store_dwordx3 */, AMDGPU::SCRATCH_STORE_DWORDX3_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VReg_96, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18637 { 12665 /* scratch_store_dwordx3 */, AMDGPU::SCRATCH_STORE_DWORDX3_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18638 { 12665 /* scratch_store_dwordx3 */, AMDGPU::SCRATCH_STORE_DWORDX3_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18639 { 12687 /* scratch_store_dwordx4 */, AMDGPU::SCRATCH_STORE_DWORDX4_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VReg_128, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18640 { 12687 /* scratch_store_dwordx4 */, AMDGPU::SCRATCH_STORE_DWORDX4_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VReg_128, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18641 { 12687 /* scratch_store_dwordx4 */, AMDGPU::SCRATCH_STORE_DWORDX4_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18642 { 12687 /* scratch_store_dwordx4 */, AMDGPU::SCRATCH_STORE_DWORDX4_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18643 { 12709 /* scratch_store_short */, AMDGPU::SCRATCH_STORE_SHORT_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18644 { 12709 /* scratch_store_short */, AMDGPU::SCRATCH_STORE_SHORT_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18645 { 12709 /* scratch_store_short */, AMDGPU::SCRATCH_STORE_SHORT_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18646 { 12709 /* scratch_store_short */, AMDGPU::SCRATCH_STORE_SHORT_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18647 { 12729 /* scratch_store_short_d16_hi */, AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18648 { 12729 /* scratch_store_short_d16_hi */, AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18649 { 12729 /* scratch_store_short_d16_hi */, AMDGPU::SCRATCH_STORE_SHORT_D16_HI_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18650 { 12729 /* scratch_store_short_d16_hi */, AMDGPU::SCRATCH_STORE_SHORT_D16_HI_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18651 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18652 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18653 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18654 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18655 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18656 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18657 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18658 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18659 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18660 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18661 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18662 { 12756 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18663 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18664 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18665 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18666 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18667 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18668 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18669 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18670 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18671 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18672 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18673 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18674 { 12782 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18675 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18676 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18677 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18678 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18679 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18680 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18681 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18682 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18683 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18684 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18685 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18686 { 12809 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18687 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18688 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18689 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18690 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18691 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18692 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18693 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18694 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18695 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18696 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18697 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18698 { 12837 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18699 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18700 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18701 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18702 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18703 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18704 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18705 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18706 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18707 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18708 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18709 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18710 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18711 { 12866 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18712 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18713 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18714 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18715 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18716 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18717 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18718 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18719 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18720 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18721 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18722 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18723 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18724 { 12888 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18725 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18726 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18727 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18728 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18729 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18730 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18731 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18732 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18733 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18734 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18735 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18736 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18737 { 12911 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18738 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18739 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18740 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18741 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18742 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18743 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18744 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18745 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18746 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18747 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18748 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18749 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18750 { 12935 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18751 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18752 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18753 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18754 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18755 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18756 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18757 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18758 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18759 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18760 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18761 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18762 { 12960 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18763 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18764 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18765 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18766 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18767 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18768 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18769 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18770 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18771 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18772 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18773 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18774 { 12987 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18775 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18776 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18777 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18778 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18779 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18780 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18781 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18782 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18783 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18784 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18785 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18786 { 13015 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18787 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18788 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18789 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18790 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18791 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18792 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18793 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18794 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18795 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18796 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18797 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18798 { 13044 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_HasPackedD16VMem_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18799 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18800 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18801 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18802 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18803 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18804 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18805 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18806 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18807 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18808 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18809 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18810 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18811 { 13074 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18812 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18813 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18814 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18815 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18816 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18817 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18818 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18819 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18820 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18821 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18822 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18823 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18824 { 13097 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18825 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18826 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18827 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18828 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18829 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18830 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18831 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18832 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18833 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18834 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18835 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18836 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18837 { 13121 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18838 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18839 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18840 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18841 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_ADDR64_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18842 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18843 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18844 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18845 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18846 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18847 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18848 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx10, ConvertCustom_cvtMtbuf, AMFBS_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18849 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_gfx6_gfx7, ConvertCustom_cvtMtbuf, AMFBS_isGFX6GFX7, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
18850 { 13146 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, AMFBS_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE, MCK_ImmDLC, MCK_ImmSWZ }, },
25743 { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25748 { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25753 { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25758 { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25764 { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25770 { 731 /* buffer_load_dword */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25776 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25781 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25787 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25792 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25797 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25802 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25808 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25814 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25820 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25825 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25830 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25835 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25841 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25847 { 731 /* buffer_load_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25853 { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25858 { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25863 { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25868 { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25874 { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25880 { 731 /* buffer_load_dword */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25886 { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
25891 { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25897 { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25903 { 749 /* buffer_load_dwordx2 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25909 { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25915 { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
25920 { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25926 { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25932 { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25938 { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
25943 { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25949 { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25955 { 749 /* buffer_load_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25961 { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
25966 { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25972 { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
25978 { 749 /* buffer_load_dwordx2 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
25984 { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
25989 { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
25995 { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26001 { 769 /* buffer_load_dwordx3 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26007 { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26013 { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26018 { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26024 { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26030 { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26036 { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26041 { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26047 { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26053 { 769 /* buffer_load_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26059 { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26064 { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26070 { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26076 { 769 /* buffer_load_dwordx3 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26082 { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26087 { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26093 { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26099 { 789 /* buffer_load_dwordx4 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26105 { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26111 { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26116 { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26122 { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26128 { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26134 { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26139 { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26145 { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26151 { 789 /* buffer_load_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26157 { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
26162 { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26168 { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26174 { 789 /* buffer_load_dwordx4 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26180 { 809 /* buffer_load_format_d16_hi_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
26186 { 809 /* buffer_load_format_d16_hi_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
26192 { 809 /* buffer_load_format_d16_hi_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
26198 { 809 /* buffer_load_format_d16_hi_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
26204 { 837 /* buffer_load_format_d16_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26210 { 837 /* buffer_load_format_d16_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26216 { 837 /* buffer_load_format_d16_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26222 { 837 /* buffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26228 { 837 /* buffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26234 { 837 /* buffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26240 { 837 /* buffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26246 { 837 /* buffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26252 { 837 /* buffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26258 { 837 /* buffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26264 { 837 /* buffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26270 { 837 /* buffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26276 { 862 /* buffer_load_format_d16_xy */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26282 { 862 /* buffer_load_format_d16_xy */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26288 { 862 /* buffer_load_format_d16_xy */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26294 { 862 /* buffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26300 { 862 /* buffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26306 { 862 /* buffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26312 { 862 /* buffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26318 { 862 /* buffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26324 { 862 /* buffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26330 { 862 /* buffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26336 { 862 /* buffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26342 { 862 /* buffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26348 { 888 /* buffer_load_format_d16_xyz */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26354 { 888 /* buffer_load_format_d16_xyz */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26360 { 888 /* buffer_load_format_d16_xyz */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26366 { 888 /* buffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26372 { 888 /* buffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26378 { 888 /* buffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26384 { 888 /* buffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26390 { 888 /* buffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26396 { 888 /* buffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26402 { 888 /* buffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26408 { 888 /* buffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26414 { 888 /* buffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26420 { 915 /* buffer_load_format_d16_xyzw */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26426 { 915 /* buffer_load_format_d16_xyzw */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26432 { 915 /* buffer_load_format_d16_xyzw */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26438 { 915 /* buffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26444 { 915 /* buffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26450 { 915 /* buffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26456 { 915 /* buffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26462 { 915 /* buffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26468 { 915 /* buffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26474 { 915 /* buffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
26480 { 915 /* buffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
26486 { 915 /* buffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
26492 { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26497 { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26502 { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26507 { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26513 { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26519 { 943 /* buffer_load_format_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26525 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26530 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26536 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26541 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26546 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26551 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26557 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26563 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26569 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26574 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26579 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26584 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26590 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26596 { 943 /* buffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26602 { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26607 { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26612 { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26617 { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26623 { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26629 { 943 /* buffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26635 { 964 /* buffer_load_format_xy */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26641 { 964 /* buffer_load_format_xy */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26647 { 964 /* buffer_load_format_xy */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26653 { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26659 { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26665 { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26671 { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26677 { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26683 { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26689 { 964 /* buffer_load_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26695 { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26701 { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26707 { 964 /* buffer_load_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26713 { 986 /* buffer_load_format_xyz */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26719 { 986 /* buffer_load_format_xyz */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26725 { 986 /* buffer_load_format_xyz */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26731 { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26737 { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26743 { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26749 { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26755 { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26761 { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26767 { 986 /* buffer_load_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26773 { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26779 { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26785 { 986 /* buffer_load_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26791 { 1009 /* buffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26797 { 1009 /* buffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26803 { 1009 /* buffer_load_format_xyzw */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26809 { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26815 { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26821 { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26827 { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26833 { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26839 { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26845 { 1009 /* buffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26851 { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26857 { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26863 { 1009 /* buffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26869 { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26874 { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26879 { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26884 { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26890 { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26896 { 1033 /* buffer_load_sbyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26902 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26907 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26913 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26918 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26923 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26928 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26934 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26940 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26946 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26951 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26956 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26961 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26967 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26973 { 1033 /* buffer_load_sbyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26979 { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
26984 { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
26989 { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
26994 { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27000 { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27006 { 1033 /* buffer_load_sbyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27012 { 1051 /* buffer_load_sbyte_d16 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27018 { 1051 /* buffer_load_sbyte_d16 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27024 { 1051 /* buffer_load_sbyte_d16 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27030 { 1051 /* buffer_load_sbyte_d16 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27036 { 1051 /* buffer_load_sbyte_d16 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27042 { 1051 /* buffer_load_sbyte_d16 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27048 { 1051 /* buffer_load_sbyte_d16 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27054 { 1051 /* buffer_load_sbyte_d16 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27060 { 1073 /* buffer_load_sbyte_d16_hi */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27066 { 1073 /* buffer_load_sbyte_d16_hi */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27072 { 1073 /* buffer_load_sbyte_d16_hi */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27078 { 1073 /* buffer_load_sbyte_d16_hi */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27084 { 1073 /* buffer_load_sbyte_d16_hi */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27090 { 1073 /* buffer_load_sbyte_d16_hi */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27096 { 1073 /* buffer_load_sbyte_d16_hi */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27102 { 1073 /* buffer_load_sbyte_d16_hi */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27108 { 1098 /* buffer_load_short_d16 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27114 { 1098 /* buffer_load_short_d16 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27120 { 1098 /* buffer_load_short_d16 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27126 { 1098 /* buffer_load_short_d16 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27132 { 1098 /* buffer_load_short_d16 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27138 { 1098 /* buffer_load_short_d16 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27144 { 1098 /* buffer_load_short_d16 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27150 { 1098 /* buffer_load_short_d16 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27156 { 1120 /* buffer_load_short_d16_hi */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27162 { 1120 /* buffer_load_short_d16_hi */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27168 { 1120 /* buffer_load_short_d16_hi */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27174 { 1120 /* buffer_load_short_d16_hi */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27180 { 1120 /* buffer_load_short_d16_hi */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27186 { 1120 /* buffer_load_short_d16_hi */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27192 { 1120 /* buffer_load_short_d16_hi */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27198 { 1120 /* buffer_load_short_d16_hi */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27204 { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27209 { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27214 { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27219 { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27225 { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27231 { 1145 /* buffer_load_sshort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27237 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27242 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27248 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27253 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27258 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27263 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27269 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27275 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27281 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27286 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27291 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27296 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27302 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27308 { 1145 /* buffer_load_sshort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27314 { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27319 { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27324 { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27329 { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27335 { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27341 { 1145 /* buffer_load_sshort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27347 { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27352 { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27357 { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27362 { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27368 { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27374 { 1164 /* buffer_load_ubyte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27380 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27385 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27391 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27396 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27401 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27406 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27412 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27418 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27424 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27429 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27434 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27439 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27445 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27451 { 1164 /* buffer_load_ubyte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27457 { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27462 { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27467 { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27472 { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27478 { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27484 { 1164 /* buffer_load_ubyte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27490 { 1182 /* buffer_load_ubyte_d16 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27496 { 1182 /* buffer_load_ubyte_d16 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27502 { 1182 /* buffer_load_ubyte_d16 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27508 { 1182 /* buffer_load_ubyte_d16 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27514 { 1182 /* buffer_load_ubyte_d16 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27520 { 1182 /* buffer_load_ubyte_d16 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27526 { 1182 /* buffer_load_ubyte_d16 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27532 { 1182 /* buffer_load_ubyte_d16 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27538 { 1204 /* buffer_load_ubyte_d16_hi */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27544 { 1204 /* buffer_load_ubyte_d16_hi */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27550 { 1204 /* buffer_load_ubyte_d16_hi */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27556 { 1204 /* buffer_load_ubyte_d16_hi */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27562 { 1204 /* buffer_load_ubyte_d16_hi */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27568 { 1204 /* buffer_load_ubyte_d16_hi */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27574 { 1204 /* buffer_load_ubyte_d16_hi */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27580 { 1204 /* buffer_load_ubyte_d16_hi */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27586 { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27591 { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27596 { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27601 { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27607 { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27613 { 1229 /* buffer_load_ushort */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27619 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27624 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27630 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27635 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27640 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27645 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27651 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27657 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27663 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27668 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27673 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27678 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27684 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27690 { 1229 /* buffer_load_ushort */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27696 { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27701 { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27706 { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27711 { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27717 { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27723 { 1229 /* buffer_load_ushort */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27729 { 1248 /* buffer_store_byte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27735 { 1248 /* buffer_store_byte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27741 { 1248 /* buffer_store_byte */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27747 { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27753 { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27759 { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27765 { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27771 { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27777 { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27783 { 1248 /* buffer_store_byte */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27789 { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27795 { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27801 { 1248 /* buffer_store_byte */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27807 { 1266 /* buffer_store_byte_d16_hi */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27813 { 1266 /* buffer_store_byte_d16_hi */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27819 { 1266 /* buffer_store_byte_d16_hi */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27825 { 1266 /* buffer_store_byte_d16_hi */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27831 { 1266 /* buffer_store_byte_d16_hi */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27837 { 1266 /* buffer_store_byte_d16_hi */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27843 { 1266 /* buffer_store_byte_d16_hi */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
27849 { 1266 /* buffer_store_byte_d16_hi */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
27855 { 1291 /* buffer_store_dword */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27861 { 1291 /* buffer_store_dword */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27867 { 1291 /* buffer_store_dword */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27873 { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27879 { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27885 { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27891 { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27897 { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27903 { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27909 { 1291 /* buffer_store_dword */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27915 { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27921 { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27927 { 1291 /* buffer_store_dword */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27933 { 1310 /* buffer_store_dwordx2 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27939 { 1310 /* buffer_store_dwordx2 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27945 { 1310 /* buffer_store_dwordx2 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27951 { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27957 { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27963 { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27969 { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27975 { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27981 { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
27987 { 1310 /* buffer_store_dwordx2 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
27993 { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
27999 { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28005 { 1310 /* buffer_store_dwordx2 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28011 { 1331 /* buffer_store_dwordx3 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28017 { 1331 /* buffer_store_dwordx3 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28023 { 1331 /* buffer_store_dwordx3 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28029 { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28035 { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28041 { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28047 { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28053 { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28059 { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28065 { 1331 /* buffer_store_dwordx3 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28071 { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28077 { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28083 { 1331 /* buffer_store_dwordx3 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28089 { 1352 /* buffer_store_dwordx4 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28095 { 1352 /* buffer_store_dwordx4 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28101 { 1352 /* buffer_store_dwordx4 */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28107 { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28113 { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28119 { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28125 { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28131 { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28137 { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28143 { 1352 /* buffer_store_dwordx4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28149 { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28155 { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28161 { 1352 /* buffer_store_dwordx4 */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28167 { 1373 /* buffer_store_format_d16_hi_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28173 { 1373 /* buffer_store_format_d16_hi_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28179 { 1373 /* buffer_store_format_d16_hi_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28185 { 1373 /* buffer_store_format_d16_hi_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28191 { 1402 /* buffer_store_format_d16_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28197 { 1402 /* buffer_store_format_d16_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28203 { 1402 /* buffer_store_format_d16_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28209 { 1402 /* buffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28215 { 1402 /* buffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28221 { 1402 /* buffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28227 { 1402 /* buffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28233 { 1402 /* buffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28239 { 1402 /* buffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28245 { 1402 /* buffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28251 { 1402 /* buffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28257 { 1402 /* buffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28263 { 1428 /* buffer_store_format_d16_xy */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28269 { 1428 /* buffer_store_format_d16_xy */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28275 { 1428 /* buffer_store_format_d16_xy */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28281 { 1428 /* buffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28287 { 1428 /* buffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28293 { 1428 /* buffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28299 { 1428 /* buffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28305 { 1428 /* buffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28311 { 1428 /* buffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28317 { 1428 /* buffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28323 { 1428 /* buffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28329 { 1428 /* buffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28335 { 1455 /* buffer_store_format_d16_xyz */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28341 { 1455 /* buffer_store_format_d16_xyz */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28347 { 1455 /* buffer_store_format_d16_xyz */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28353 { 1455 /* buffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28359 { 1455 /* buffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28365 { 1455 /* buffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28371 { 1455 /* buffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28377 { 1455 /* buffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28383 { 1455 /* buffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28389 { 1455 /* buffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28395 { 1455 /* buffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28401 { 1455 /* buffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28407 { 1483 /* buffer_store_format_d16_xyzw */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28413 { 1483 /* buffer_store_format_d16_xyzw */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28419 { 1483 /* buffer_store_format_d16_xyzw */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28425 { 1483 /* buffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28431 { 1483 /* buffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28437 { 1483 /* buffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28443 { 1483 /* buffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28449 { 1483 /* buffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28455 { 1483 /* buffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28461 { 1483 /* buffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
28467 { 1483 /* buffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
28473 { 1483 /* buffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
28479 { 1512 /* buffer_store_format_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28485 { 1512 /* buffer_store_format_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28491 { 1512 /* buffer_store_format_x */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28497 { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28503 { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28509 { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28515 { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28521 { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28527 { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28533 { 1512 /* buffer_store_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28539 { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28545 { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28551 { 1512 /* buffer_store_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28557 { 1534 /* buffer_store_format_xy */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28563 { 1534 /* buffer_store_format_xy */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28569 { 1534 /* buffer_store_format_xy */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28575 { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28581 { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28587 { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28593 { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28599 { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28605 { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28611 { 1534 /* buffer_store_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28617 { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28623 { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28629 { 1534 /* buffer_store_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28635 { 1557 /* buffer_store_format_xyz */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28641 { 1557 /* buffer_store_format_xyz */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28647 { 1557 /* buffer_store_format_xyz */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28653 { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28659 { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28665 { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28671 { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28677 { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28683 { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28689 { 1557 /* buffer_store_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28695 { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28701 { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28707 { 1557 /* buffer_store_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28713 { 1581 /* buffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28719 { 1581 /* buffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28725 { 1581 /* buffer_store_format_xyzw */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28731 { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28737 { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28743 { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28749 { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28755 { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28761 { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28767 { 1581 /* buffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28773 { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28779 { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28785 { 1581 /* buffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28790 { 1606 /* buffer_store_lds_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_isGFX8GFX9_isGFX8GFX9 },
28795 { 1629 /* buffer_store_short */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28801 { 1629 /* buffer_store_short */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28807 { 1629 /* buffer_store_short */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28813 { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28819 { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28825 { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28831 { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28837 { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28843 { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28849 { 1629 /* buffer_store_short */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28855 { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
28861 { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
28867 { 1629 /* buffer_store_short */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
28873 { 1648 /* buffer_store_short_d16_hi */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
28879 { 1648 /* buffer_store_short_d16_hi */, 32 /* 5 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28885 { 1648 /* buffer_store_short_d16_hi */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
28891 { 1648 /* buffer_store_short_d16_hi */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28897 { 1648 /* buffer_store_short_d16_hi */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
28903 { 1648 /* buffer_store_short_d16_hi */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
28909 { 1648 /* buffer_store_short_d16_hi */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
28915 { 1648 /* buffer_store_short_d16_hi */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30204 { 4573 /* flat_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30208 { 4573 /* flat_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30212 { 4573 /* flat_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30216 { 4589 /* flat_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30220 { 4589 /* flat_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30224 { 4589 /* flat_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30228 { 4607 /* flat_load_dwordx3 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30232 { 4607 /* flat_load_dwordx3 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30236 { 4607 /* flat_load_dwordx3 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30240 { 4625 /* flat_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30244 { 4625 /* flat_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30248 { 4625 /* flat_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30252 { 4643 /* flat_load_sbyte */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30256 { 4643 /* flat_load_sbyte */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30260 { 4643 /* flat_load_sbyte */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30264 { 4659 /* flat_load_sbyte_d16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
30268 { 4659 /* flat_load_sbyte_d16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30272 { 4679 /* flat_load_sbyte_d16_hi */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
30276 { 4679 /* flat_load_sbyte_d16_hi */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30280 { 4702 /* flat_load_short_d16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
30284 { 4702 /* flat_load_short_d16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30288 { 4722 /* flat_load_short_d16_hi */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
30292 { 4722 /* flat_load_short_d16_hi */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30296 { 4745 /* flat_load_sshort */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30300 { 4745 /* flat_load_sshort */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30304 { 4745 /* flat_load_sshort */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30308 { 4762 /* flat_load_ubyte */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30312 { 4762 /* flat_load_ubyte */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30316 { 4762 /* flat_load_ubyte */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30320 { 4778 /* flat_load_ubyte_d16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
30324 { 4778 /* flat_load_ubyte_d16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30328 { 4798 /* flat_load_ubyte_d16_hi */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
30332 { 4798 /* flat_load_ubyte_d16_hi */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30336 { 4821 /* flat_load_ushort */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30340 { 4821 /* flat_load_ushort */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30344 { 4821 /* flat_load_ushort */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30348 { 4838 /* flat_store_byte */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30352 { 4838 /* flat_store_byte */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30356 { 4838 /* flat_store_byte */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30360 { 4854 /* flat_store_byte_d16_hi */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
30364 { 4854 /* flat_store_byte_d16_hi */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30368 { 4877 /* flat_store_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30372 { 4877 /* flat_store_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30376 { 4877 /* flat_store_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30380 { 4894 /* flat_store_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30384 { 4894 /* flat_store_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30388 { 4894 /* flat_store_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30392 { 4913 /* flat_store_dwordx3 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30396 { 4913 /* flat_store_dwordx3 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30400 { 4913 /* flat_store_dwordx3 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30404 { 4932 /* flat_store_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30408 { 4932 /* flat_store_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30412 { 4932 /* flat_store_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30416 { 4951 /* flat_store_short */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30420 { 4951 /* flat_store_short */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30424 { 4951 /* flat_store_short */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30428 { 4968 /* flat_store_short_d16_hi */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX10Plus },
30432 { 4968 /* flat_store_short_d16_hi */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30908 { 5693 /* global_load_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30912 { 5693 /* global_load_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30916 { 5693 /* global_load_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30920 { 5693 /* global_load_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30924 { 5711 /* global_load_dwordx2 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30928 { 5711 /* global_load_dwordx2 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30932 { 5711 /* global_load_dwordx2 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30936 { 5711 /* global_load_dwordx2 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30940 { 5731 /* global_load_dwordx3 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30944 { 5731 /* global_load_dwordx3 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30948 { 5731 /* global_load_dwordx3 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30952 { 5731 /* global_load_dwordx3 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30956 { 5751 /* global_load_dwordx4 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30960 { 5751 /* global_load_dwordx4 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30964 { 5751 /* global_load_dwordx4 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30968 { 5751 /* global_load_dwordx4 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30972 { 5771 /* global_load_sbyte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30976 { 5771 /* global_load_sbyte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30980 { 5771 /* global_load_sbyte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30984 { 5771 /* global_load_sbyte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30988 { 5789 /* global_load_sbyte_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30992 { 5789 /* global_load_sbyte_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30996 { 5789 /* global_load_sbyte_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31000 { 5789 /* global_load_sbyte_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31004 { 5811 /* global_load_sbyte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31008 { 5811 /* global_load_sbyte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31012 { 5811 /* global_load_sbyte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31016 { 5811 /* global_load_sbyte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31020 { 5836 /* global_load_short_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31024 { 5836 /* global_load_short_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31028 { 5836 /* global_load_short_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31032 { 5836 /* global_load_short_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31036 { 5858 /* global_load_short_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31040 { 5858 /* global_load_short_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31044 { 5858 /* global_load_short_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31048 { 5858 /* global_load_short_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31052 { 5883 /* global_load_sshort */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31056 { 5883 /* global_load_sshort */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31060 { 5883 /* global_load_sshort */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31064 { 5883 /* global_load_sshort */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31068 { 5902 /* global_load_ubyte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31072 { 5902 /* global_load_ubyte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31076 { 5902 /* global_load_ubyte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31080 { 5902 /* global_load_ubyte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31084 { 5920 /* global_load_ubyte_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31088 { 5920 /* global_load_ubyte_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31092 { 5920 /* global_load_ubyte_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31096 { 5920 /* global_load_ubyte_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31100 { 5942 /* global_load_ubyte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31104 { 5942 /* global_load_ubyte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31108 { 5942 /* global_load_ubyte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31112 { 5942 /* global_load_ubyte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31116 { 5967 /* global_load_ushort */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31120 { 5967 /* global_load_ushort */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31124 { 5967 /* global_load_ushort */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31128 { 5967 /* global_load_ushort */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31132 { 5986 /* global_store_byte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31136 { 5986 /* global_store_byte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31140 { 5986 /* global_store_byte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31144 { 5986 /* global_store_byte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31148 { 6004 /* global_store_byte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31152 { 6004 /* global_store_byte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31156 { 6004 /* global_store_byte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31160 { 6004 /* global_store_byte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31164 { 6029 /* global_store_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31168 { 6029 /* global_store_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31172 { 6029 /* global_store_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31176 { 6029 /* global_store_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31180 { 6048 /* global_store_dwordx2 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31184 { 6048 /* global_store_dwordx2 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31188 { 6048 /* global_store_dwordx2 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31192 { 6048 /* global_store_dwordx2 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31196 { 6069 /* global_store_dwordx3 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31200 { 6069 /* global_store_dwordx3 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31204 { 6069 /* global_store_dwordx3 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31208 { 6069 /* global_store_dwordx3 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31212 { 6090 /* global_store_dwordx4 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31216 { 6090 /* global_store_dwordx4 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31220 { 6090 /* global_store_dwordx4 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31224 { 6090 /* global_store_dwordx4 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31228 { 6111 /* global_store_short */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31232 { 6111 /* global_store_short */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31236 { 6111 /* global_store_short */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31240 { 6111 /* global_store_short */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31244 { 6130 /* global_store_short_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31248 { 6130 /* global_store_short_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31252 { 6130 /* global_store_short_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31256 { 6130 /* global_store_short_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31258 { 6156 /* image_atomic_add */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31266 { 6156 /* image_atomic_add */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31274 { 6156 /* image_atomic_add */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31282 { 6156 /* image_atomic_add */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31290 { 6156 /* image_atomic_add */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31298 { 6156 /* image_atomic_add */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31306 { 6156 /* image_atomic_add */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31314 { 6156 /* image_atomic_add */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31322 { 6156 /* image_atomic_add */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31330 { 6156 /* image_atomic_add */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31338 { 6156 /* image_atomic_add */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31346 { 6156 /* image_atomic_add */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31354 { 6156 /* image_atomic_add */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31362 { 6156 /* image_atomic_add */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31370 { 6156 /* image_atomic_add */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31378 { 6156 /* image_atomic_add */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31387 { 6156 /* image_atomic_add */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31396 { 6156 /* image_atomic_add */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31405 { 6156 /* image_atomic_add */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31414 { 6156 /* image_atomic_add */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31423 { 6156 /* image_atomic_add */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31432 { 6156 /* image_atomic_add */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31441 { 6156 /* image_atomic_add */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31450 { 6156 /* image_atomic_add */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31459 { 6156 /* image_atomic_add */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31468 { 6156 /* image_atomic_add */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31477 { 6156 /* image_atomic_add */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31486 { 6156 /* image_atomic_add */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31495 { 6156 /* image_atomic_add */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31504 { 6156 /* image_atomic_add */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31512 { 6173 /* image_atomic_and */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31520 { 6173 /* image_atomic_and */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31528 { 6173 /* image_atomic_and */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31536 { 6173 /* image_atomic_and */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31544 { 6173 /* image_atomic_and */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31552 { 6173 /* image_atomic_and */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31560 { 6173 /* image_atomic_and */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31568 { 6173 /* image_atomic_and */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31576 { 6173 /* image_atomic_and */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31584 { 6173 /* image_atomic_and */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31592 { 6173 /* image_atomic_and */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31600 { 6173 /* image_atomic_and */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31608 { 6173 /* image_atomic_and */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31616 { 6173 /* image_atomic_and */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31624 { 6173 /* image_atomic_and */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31632 { 6173 /* image_atomic_and */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31641 { 6173 /* image_atomic_and */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31650 { 6173 /* image_atomic_and */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31659 { 6173 /* image_atomic_and */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31668 { 6173 /* image_atomic_and */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31677 { 6173 /* image_atomic_and */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31686 { 6173 /* image_atomic_and */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31695 { 6173 /* image_atomic_and */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31704 { 6173 /* image_atomic_and */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31713 { 6173 /* image_atomic_and */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31722 { 6173 /* image_atomic_and */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31731 { 6173 /* image_atomic_and */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31740 { 6173 /* image_atomic_and */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31749 { 6173 /* image_atomic_and */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31758 { 6173 /* image_atomic_and */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31766 { 6190 /* image_atomic_cmpswap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31774 { 6190 /* image_atomic_cmpswap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31782 { 6190 /* image_atomic_cmpswap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31790 { 6190 /* image_atomic_cmpswap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31798 { 6190 /* image_atomic_cmpswap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31806 { 6190 /* image_atomic_cmpswap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31814 { 6190 /* image_atomic_cmpswap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31822 { 6190 /* image_atomic_cmpswap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31830 { 6190 /* image_atomic_cmpswap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31838 { 6190 /* image_atomic_cmpswap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31846 { 6190 /* image_atomic_cmpswap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31854 { 6190 /* image_atomic_cmpswap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31862 { 6190 /* image_atomic_cmpswap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31870 { 6190 /* image_atomic_cmpswap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31878 { 6190 /* image_atomic_cmpswap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
31886 { 6190 /* image_atomic_cmpswap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
31895 { 6190 /* image_atomic_cmpswap */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31904 { 6190 /* image_atomic_cmpswap */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31913 { 6190 /* image_atomic_cmpswap */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31922 { 6190 /* image_atomic_cmpswap */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31931 { 6190 /* image_atomic_cmpswap */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31940 { 6190 /* image_atomic_cmpswap */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31949 { 6190 /* image_atomic_cmpswap */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31958 { 6190 /* image_atomic_cmpswap */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31967 { 6190 /* image_atomic_cmpswap */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31976 { 6190 /* image_atomic_cmpswap */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31985 { 6190 /* image_atomic_cmpswap */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
31994 { 6190 /* image_atomic_cmpswap */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32003 { 6190 /* image_atomic_cmpswap */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32012 { 6190 /* image_atomic_cmpswap */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32020 { 6211 /* image_atomic_dec */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32028 { 6211 /* image_atomic_dec */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32036 { 6211 /* image_atomic_dec */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32044 { 6211 /* image_atomic_dec */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32052 { 6211 /* image_atomic_dec */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32060 { 6211 /* image_atomic_dec */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32068 { 6211 /* image_atomic_dec */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32076 { 6211 /* image_atomic_dec */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32084 { 6211 /* image_atomic_dec */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32092 { 6211 /* image_atomic_dec */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32100 { 6211 /* image_atomic_dec */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32108 { 6211 /* image_atomic_dec */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32116 { 6211 /* image_atomic_dec */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32124 { 6211 /* image_atomic_dec */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32132 { 6211 /* image_atomic_dec */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32140 { 6211 /* image_atomic_dec */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32149 { 6211 /* image_atomic_dec */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32158 { 6211 /* image_atomic_dec */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32167 { 6211 /* image_atomic_dec */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32176 { 6211 /* image_atomic_dec */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32185 { 6211 /* image_atomic_dec */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32194 { 6211 /* image_atomic_dec */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32203 { 6211 /* image_atomic_dec */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32212 { 6211 /* image_atomic_dec */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32221 { 6211 /* image_atomic_dec */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32230 { 6211 /* image_atomic_dec */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32239 { 6211 /* image_atomic_dec */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32248 { 6211 /* image_atomic_dec */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32257 { 6211 /* image_atomic_dec */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32266 { 6211 /* image_atomic_dec */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32274 { 6228 /* image_atomic_inc */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32282 { 6228 /* image_atomic_inc */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32290 { 6228 /* image_atomic_inc */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32298 { 6228 /* image_atomic_inc */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32306 { 6228 /* image_atomic_inc */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32314 { 6228 /* image_atomic_inc */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32322 { 6228 /* image_atomic_inc */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32330 { 6228 /* image_atomic_inc */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32338 { 6228 /* image_atomic_inc */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32346 { 6228 /* image_atomic_inc */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32354 { 6228 /* image_atomic_inc */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32362 { 6228 /* image_atomic_inc */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32370 { 6228 /* image_atomic_inc */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32378 { 6228 /* image_atomic_inc */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32386 { 6228 /* image_atomic_inc */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32394 { 6228 /* image_atomic_inc */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32403 { 6228 /* image_atomic_inc */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32412 { 6228 /* image_atomic_inc */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32421 { 6228 /* image_atomic_inc */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32430 { 6228 /* image_atomic_inc */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32439 { 6228 /* image_atomic_inc */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32448 { 6228 /* image_atomic_inc */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32457 { 6228 /* image_atomic_inc */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32466 { 6228 /* image_atomic_inc */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32475 { 6228 /* image_atomic_inc */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32484 { 6228 /* image_atomic_inc */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32493 { 6228 /* image_atomic_inc */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32502 { 6228 /* image_atomic_inc */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32511 { 6228 /* image_atomic_inc */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32520 { 6228 /* image_atomic_inc */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32528 { 6245 /* image_atomic_or */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32536 { 6245 /* image_atomic_or */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32544 { 6245 /* image_atomic_or */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32552 { 6245 /* image_atomic_or */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32560 { 6245 /* image_atomic_or */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32568 { 6245 /* image_atomic_or */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32576 { 6245 /* image_atomic_or */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32584 { 6245 /* image_atomic_or */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32592 { 6245 /* image_atomic_or */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32600 { 6245 /* image_atomic_or */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32608 { 6245 /* image_atomic_or */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32616 { 6245 /* image_atomic_or */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32624 { 6245 /* image_atomic_or */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32632 { 6245 /* image_atomic_or */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32640 { 6245 /* image_atomic_or */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32648 { 6245 /* image_atomic_or */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32657 { 6245 /* image_atomic_or */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32666 { 6245 /* image_atomic_or */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32675 { 6245 /* image_atomic_or */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32684 { 6245 /* image_atomic_or */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32693 { 6245 /* image_atomic_or */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32702 { 6245 /* image_atomic_or */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32711 { 6245 /* image_atomic_or */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32720 { 6245 /* image_atomic_or */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32729 { 6245 /* image_atomic_or */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32738 { 6245 /* image_atomic_or */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32747 { 6245 /* image_atomic_or */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32756 { 6245 /* image_atomic_or */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32765 { 6245 /* image_atomic_or */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32774 { 6245 /* image_atomic_or */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32782 { 6261 /* image_atomic_smax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32790 { 6261 /* image_atomic_smax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32798 { 6261 /* image_atomic_smax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32806 { 6261 /* image_atomic_smax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32814 { 6261 /* image_atomic_smax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32822 { 6261 /* image_atomic_smax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32830 { 6261 /* image_atomic_smax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32838 { 6261 /* image_atomic_smax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32846 { 6261 /* image_atomic_smax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32854 { 6261 /* image_atomic_smax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32862 { 6261 /* image_atomic_smax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32870 { 6261 /* image_atomic_smax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32878 { 6261 /* image_atomic_smax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32886 { 6261 /* image_atomic_smax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32894 { 6261 /* image_atomic_smax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
32902 { 6261 /* image_atomic_smax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
32911 { 6261 /* image_atomic_smax */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32920 { 6261 /* image_atomic_smax */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32929 { 6261 /* image_atomic_smax */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32938 { 6261 /* image_atomic_smax */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32947 { 6261 /* image_atomic_smax */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32956 { 6261 /* image_atomic_smax */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32965 { 6261 /* image_atomic_smax */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32974 { 6261 /* image_atomic_smax */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32983 { 6261 /* image_atomic_smax */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
32992 { 6261 /* image_atomic_smax */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33001 { 6261 /* image_atomic_smax */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33010 { 6261 /* image_atomic_smax */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33019 { 6261 /* image_atomic_smax */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33028 { 6261 /* image_atomic_smax */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33036 { 6279 /* image_atomic_smin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33044 { 6279 /* image_atomic_smin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33052 { 6279 /* image_atomic_smin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33060 { 6279 /* image_atomic_smin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33068 { 6279 /* image_atomic_smin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33076 { 6279 /* image_atomic_smin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33084 { 6279 /* image_atomic_smin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33092 { 6279 /* image_atomic_smin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33100 { 6279 /* image_atomic_smin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33108 { 6279 /* image_atomic_smin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33116 { 6279 /* image_atomic_smin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33124 { 6279 /* image_atomic_smin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33132 { 6279 /* image_atomic_smin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33140 { 6279 /* image_atomic_smin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33148 { 6279 /* image_atomic_smin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33156 { 6279 /* image_atomic_smin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33165 { 6279 /* image_atomic_smin */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33174 { 6279 /* image_atomic_smin */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33183 { 6279 /* image_atomic_smin */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33192 { 6279 /* image_atomic_smin */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33201 { 6279 /* image_atomic_smin */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33210 { 6279 /* image_atomic_smin */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33219 { 6279 /* image_atomic_smin */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33228 { 6279 /* image_atomic_smin */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33237 { 6279 /* image_atomic_smin */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33246 { 6279 /* image_atomic_smin */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33255 { 6279 /* image_atomic_smin */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33264 { 6279 /* image_atomic_smin */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33273 { 6279 /* image_atomic_smin */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33282 { 6279 /* image_atomic_smin */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33290 { 6297 /* image_atomic_sub */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33298 { 6297 /* image_atomic_sub */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33306 { 6297 /* image_atomic_sub */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33314 { 6297 /* image_atomic_sub */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33322 { 6297 /* image_atomic_sub */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33330 { 6297 /* image_atomic_sub */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33338 { 6297 /* image_atomic_sub */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33346 { 6297 /* image_atomic_sub */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33354 { 6297 /* image_atomic_sub */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33362 { 6297 /* image_atomic_sub */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33370 { 6297 /* image_atomic_sub */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33378 { 6297 /* image_atomic_sub */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33386 { 6297 /* image_atomic_sub */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33394 { 6297 /* image_atomic_sub */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33402 { 6297 /* image_atomic_sub */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33410 { 6297 /* image_atomic_sub */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33419 { 6297 /* image_atomic_sub */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33428 { 6297 /* image_atomic_sub */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33437 { 6297 /* image_atomic_sub */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33446 { 6297 /* image_atomic_sub */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33455 { 6297 /* image_atomic_sub */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33464 { 6297 /* image_atomic_sub */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33473 { 6297 /* image_atomic_sub */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33482 { 6297 /* image_atomic_sub */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33491 { 6297 /* image_atomic_sub */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33500 { 6297 /* image_atomic_sub */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33509 { 6297 /* image_atomic_sub */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33518 { 6297 /* image_atomic_sub */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33527 { 6297 /* image_atomic_sub */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33536 { 6297 /* image_atomic_sub */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33544 { 6314 /* image_atomic_swap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33552 { 6314 /* image_atomic_swap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33560 { 6314 /* image_atomic_swap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33568 { 6314 /* image_atomic_swap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33576 { 6314 /* image_atomic_swap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33584 { 6314 /* image_atomic_swap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33592 { 6314 /* image_atomic_swap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33600 { 6314 /* image_atomic_swap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33608 { 6314 /* image_atomic_swap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33616 { 6314 /* image_atomic_swap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33624 { 6314 /* image_atomic_swap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33632 { 6314 /* image_atomic_swap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33640 { 6314 /* image_atomic_swap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33648 { 6314 /* image_atomic_swap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33656 { 6314 /* image_atomic_swap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33664 { 6314 /* image_atomic_swap */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33673 { 6314 /* image_atomic_swap */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33682 { 6314 /* image_atomic_swap */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33691 { 6314 /* image_atomic_swap */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33700 { 6314 /* image_atomic_swap */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33709 { 6314 /* image_atomic_swap */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33718 { 6314 /* image_atomic_swap */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33727 { 6314 /* image_atomic_swap */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33736 { 6314 /* image_atomic_swap */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33745 { 6314 /* image_atomic_swap */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33754 { 6314 /* image_atomic_swap */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33763 { 6314 /* image_atomic_swap */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33772 { 6314 /* image_atomic_swap */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33781 { 6314 /* image_atomic_swap */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33790 { 6314 /* image_atomic_swap */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33798 { 6332 /* image_atomic_umax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33806 { 6332 /* image_atomic_umax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33814 { 6332 /* image_atomic_umax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33822 { 6332 /* image_atomic_umax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33830 { 6332 /* image_atomic_umax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33838 { 6332 /* image_atomic_umax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33846 { 6332 /* image_atomic_umax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33854 { 6332 /* image_atomic_umax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33862 { 6332 /* image_atomic_umax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33870 { 6332 /* image_atomic_umax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33878 { 6332 /* image_atomic_umax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33886 { 6332 /* image_atomic_umax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33894 { 6332 /* image_atomic_umax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33902 { 6332 /* image_atomic_umax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33910 { 6332 /* image_atomic_umax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
33918 { 6332 /* image_atomic_umax */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
33927 { 6332 /* image_atomic_umax */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33936 { 6332 /* image_atomic_umax */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33945 { 6332 /* image_atomic_umax */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33954 { 6332 /* image_atomic_umax */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33963 { 6332 /* image_atomic_umax */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33972 { 6332 /* image_atomic_umax */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33981 { 6332 /* image_atomic_umax */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33990 { 6332 /* image_atomic_umax */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
33999 { 6332 /* image_atomic_umax */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34008 { 6332 /* image_atomic_umax */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34017 { 6332 /* image_atomic_umax */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34026 { 6332 /* image_atomic_umax */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34035 { 6332 /* image_atomic_umax */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34044 { 6332 /* image_atomic_umax */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34052 { 6350 /* image_atomic_umin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34060 { 6350 /* image_atomic_umin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34068 { 6350 /* image_atomic_umin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34076 { 6350 /* image_atomic_umin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34084 { 6350 /* image_atomic_umin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34092 { 6350 /* image_atomic_umin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34100 { 6350 /* image_atomic_umin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34108 { 6350 /* image_atomic_umin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34116 { 6350 /* image_atomic_umin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34124 { 6350 /* image_atomic_umin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34132 { 6350 /* image_atomic_umin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34140 { 6350 /* image_atomic_umin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34148 { 6350 /* image_atomic_umin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34156 { 6350 /* image_atomic_umin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34164 { 6350 /* image_atomic_umin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34172 { 6350 /* image_atomic_umin */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34181 { 6350 /* image_atomic_umin */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34190 { 6350 /* image_atomic_umin */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34199 { 6350 /* image_atomic_umin */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34208 { 6350 /* image_atomic_umin */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34217 { 6350 /* image_atomic_umin */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34226 { 6350 /* image_atomic_umin */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34235 { 6350 /* image_atomic_umin */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34244 { 6350 /* image_atomic_umin */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34253 { 6350 /* image_atomic_umin */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34262 { 6350 /* image_atomic_umin */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34271 { 6350 /* image_atomic_umin */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34280 { 6350 /* image_atomic_umin */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34289 { 6350 /* image_atomic_umin */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34298 { 6350 /* image_atomic_umin */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34306 { 6368 /* image_atomic_xor */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34314 { 6368 /* image_atomic_xor */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34322 { 6368 /* image_atomic_xor */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34330 { 6368 /* image_atomic_xor */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34338 { 6368 /* image_atomic_xor */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34346 { 6368 /* image_atomic_xor */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34354 { 6368 /* image_atomic_xor */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34362 { 6368 /* image_atomic_xor */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34370 { 6368 /* image_atomic_xor */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34378 { 6368 /* image_atomic_xor */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34386 { 6368 /* image_atomic_xor */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34394 { 6368 /* image_atomic_xor */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34402 { 6368 /* image_atomic_xor */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34410 { 6368 /* image_atomic_xor */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34418 { 6368 /* image_atomic_xor */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7 },
34426 { 6368 /* image_atomic_xor */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX8GFX9 },
34435 { 6368 /* image_atomic_xor */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34444 { 6368 /* image_atomic_xor */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34453 { 6368 /* image_atomic_xor */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34462 { 6368 /* image_atomic_xor */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34471 { 6368 /* image_atomic_xor */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34480 { 6368 /* image_atomic_xor */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34489 { 6368 /* image_atomic_xor */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34498 { 6368 /* image_atomic_xor */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34507 { 6368 /* image_atomic_xor */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34516 { 6368 /* image_atomic_xor */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34525 { 6368 /* image_atomic_xor */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34534 { 6368 /* image_atomic_xor */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34543 { 6368 /* image_atomic_xor */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34552 { 6368 /* image_atomic_xor */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34560 { 6385 /* image_gather4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34569 { 6385 /* image_gather4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34578 { 6385 /* image_gather4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34587 { 6385 /* image_gather4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34596 { 6385 /* image_gather4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34605 { 6385 /* image_gather4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34614 { 6385 /* image_gather4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34623 { 6385 /* image_gather4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34632 { 6385 /* image_gather4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34641 { 6385 /* image_gather4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34650 { 6385 /* image_gather4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34659 { 6385 /* image_gather4 */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34669 { 6385 /* image_gather4 */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34679 { 6385 /* image_gather4 */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34689 { 6385 /* image_gather4 */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34699 { 6385 /* image_gather4 */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34709 { 6385 /* image_gather4 */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34719 { 6385 /* image_gather4 */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34729 { 6385 /* image_gather4 */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34739 { 6385 /* image_gather4 */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34749 { 6385 /* image_gather4 */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34759 { 6385 /* image_gather4 */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34769 { 6385 /* image_gather4 */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34779 { 6385 /* image_gather4 */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34789 { 6385 /* image_gather4 */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34799 { 6385 /* image_gather4 */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34809 { 6385 /* image_gather4 */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34819 { 6385 /* image_gather4 */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34829 { 6385 /* image_gather4 */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34839 { 6385 /* image_gather4 */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34848 { 6399 /* image_gather4_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34857 { 6399 /* image_gather4_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34866 { 6399 /* image_gather4_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34875 { 6399 /* image_gather4_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34884 { 6399 /* image_gather4_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34893 { 6399 /* image_gather4_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34902 { 6399 /* image_gather4_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34911 { 6399 /* image_gather4_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34920 { 6399 /* image_gather4_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
34930 { 6399 /* image_gather4_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34940 { 6399 /* image_gather4_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34950 { 6399 /* image_gather4_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34960 { 6399 /* image_gather4_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34970 { 6399 /* image_gather4_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34980 { 6399 /* image_gather4_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
34990 { 6399 /* image_gather4_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35000 { 6399 /* image_gather4_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35010 { 6399 /* image_gather4_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35020 { 6399 /* image_gather4_b */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35030 { 6399 /* image_gather4_b */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35040 { 6399 /* image_gather4_b */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35050 { 6399 /* image_gather4_b */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35060 { 6399 /* image_gather4_b */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35070 { 6399 /* image_gather4_b */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35080 { 6399 /* image_gather4_b */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35090 { 6399 /* image_gather4_b */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35100 { 6399 /* image_gather4_b */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35109 { 6415 /* image_gather4_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35118 { 6415 /* image_gather4_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35127 { 6415 /* image_gather4_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35136 { 6415 /* image_gather4_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35145 { 6415 /* image_gather4_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35154 { 6415 /* image_gather4_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35163 { 6415 /* image_gather4_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35172 { 6415 /* image_gather4_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35181 { 6415 /* image_gather4_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35190 { 6415 /* image_gather4_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35199 { 6415 /* image_gather4_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35208 { 6415 /* image_gather4_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35218 { 6415 /* image_gather4_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35228 { 6415 /* image_gather4_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35238 { 6415 /* image_gather4_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35248 { 6415 /* image_gather4_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35258 { 6415 /* image_gather4_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35268 { 6415 /* image_gather4_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35278 { 6415 /* image_gather4_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35288 { 6415 /* image_gather4_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35298 { 6415 /* image_gather4_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35308 { 6415 /* image_gather4_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35318 { 6415 /* image_gather4_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35328 { 6415 /* image_gather4_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35338 { 6415 /* image_gather4_b_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35348 { 6415 /* image_gather4_b_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35358 { 6415 /* image_gather4_b_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35368 { 6415 /* image_gather4_b_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35378 { 6415 /* image_gather4_b_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35388 { 6415 /* image_gather4_b_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35398 { 6415 /* image_gather4_b_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35408 { 6415 /* image_gather4_b_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35418 { 6415 /* image_gather4_b_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35428 { 6415 /* image_gather4_b_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35438 { 6415 /* image_gather4_b_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35448 { 6415 /* image_gather4_b_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35457 { 6434 /* image_gather4_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35466 { 6434 /* image_gather4_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35475 { 6434 /* image_gather4_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35484 { 6434 /* image_gather4_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35493 { 6434 /* image_gather4_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35502 { 6434 /* image_gather4_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35511 { 6434 /* image_gather4_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35520 { 6434 /* image_gather4_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35529 { 6434 /* image_gather4_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35539 { 6434 /* image_gather4_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35549 { 6434 /* image_gather4_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35559 { 6434 /* image_gather4_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35569 { 6434 /* image_gather4_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35579 { 6434 /* image_gather4_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35589 { 6434 /* image_gather4_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35599 { 6434 /* image_gather4_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35609 { 6434 /* image_gather4_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35619 { 6434 /* image_gather4_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35629 { 6434 /* image_gather4_b_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35639 { 6434 /* image_gather4_b_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35649 { 6434 /* image_gather4_b_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35659 { 6434 /* image_gather4_b_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35669 { 6434 /* image_gather4_b_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35679 { 6434 /* image_gather4_b_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35689 { 6434 /* image_gather4_b_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35699 { 6434 /* image_gather4_b_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35709 { 6434 /* image_gather4_b_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35719 { 6434 /* image_gather4_b_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35729 { 6434 /* image_gather4_b_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35739 { 6434 /* image_gather4_b_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35748 { 6455 /* image_gather4_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35757 { 6455 /* image_gather4_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35766 { 6455 /* image_gather4_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35775 { 6455 /* image_gather4_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35784 { 6455 /* image_gather4_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35793 { 6455 /* image_gather4_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35802 { 6455 /* image_gather4_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35811 { 6455 /* image_gather4_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35820 { 6455 /* image_gather4_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
35830 { 6455 /* image_gather4_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35840 { 6455 /* image_gather4_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35850 { 6455 /* image_gather4_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35860 { 6455 /* image_gather4_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35870 { 6455 /* image_gather4_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35880 { 6455 /* image_gather4_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35890 { 6455 /* image_gather4_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35900 { 6455 /* image_gather4_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35910 { 6455 /* image_gather4_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35920 { 6455 /* image_gather4_b_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35930 { 6455 /* image_gather4_b_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35940 { 6455 /* image_gather4_b_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35950 { 6455 /* image_gather4_b_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35960 { 6455 /* image_gather4_b_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35970 { 6455 /* image_gather4_b_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35980 { 6455 /* image_gather4_b_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
35990 { 6455 /* image_gather4_b_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36000 { 6455 /* image_gather4_b_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36009 { 6473 /* image_gather4_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36018 { 6473 /* image_gather4_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36027 { 6473 /* image_gather4_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36036 { 6473 /* image_gather4_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36045 { 6473 /* image_gather4_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36054 { 6473 /* image_gather4_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36063 { 6473 /* image_gather4_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36072 { 6473 /* image_gather4_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36081 { 6473 /* image_gather4_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36091 { 6473 /* image_gather4_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36101 { 6473 /* image_gather4_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36111 { 6473 /* image_gather4_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36121 { 6473 /* image_gather4_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36131 { 6473 /* image_gather4_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36141 { 6473 /* image_gather4_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36151 { 6473 /* image_gather4_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36161 { 6473 /* image_gather4_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36171 { 6473 /* image_gather4_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36181 { 6473 /* image_gather4_c */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36191 { 6473 /* image_gather4_c */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36201 { 6473 /* image_gather4_c */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36211 { 6473 /* image_gather4_c */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36221 { 6473 /* image_gather4_c */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36231 { 6473 /* image_gather4_c */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36241 { 6473 /* image_gather4_c */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36251 { 6473 /* image_gather4_c */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36261 { 6473 /* image_gather4_c */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36270 { 6489 /* image_gather4_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36279 { 6489 /* image_gather4_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36288 { 6489 /* image_gather4_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36297 { 6489 /* image_gather4_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36306 { 6489 /* image_gather4_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36315 { 6489 /* image_gather4_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36324 { 6489 /* image_gather4_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36333 { 6489 /* image_gather4_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36342 { 6489 /* image_gather4_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36352 { 6489 /* image_gather4_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36362 { 6489 /* image_gather4_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36372 { 6489 /* image_gather4_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36382 { 6489 /* image_gather4_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36392 { 6489 /* image_gather4_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36402 { 6489 /* image_gather4_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36412 { 6489 /* image_gather4_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36422 { 6489 /* image_gather4_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36432 { 6489 /* image_gather4_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36442 { 6489 /* image_gather4_c_b */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36452 { 6489 /* image_gather4_c_b */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36462 { 6489 /* image_gather4_c_b */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36472 { 6489 /* image_gather4_c_b */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36482 { 6489 /* image_gather4_c_b */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36492 { 6489 /* image_gather4_c_b */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36502 { 6489 /* image_gather4_c_b */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36512 { 6489 /* image_gather4_c_b */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36522 { 6489 /* image_gather4_c_b */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36531 { 6507 /* image_gather4_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36540 { 6507 /* image_gather4_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36549 { 6507 /* image_gather4_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36558 { 6507 /* image_gather4_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36567 { 6507 /* image_gather4_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36576 { 6507 /* image_gather4_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36585 { 6507 /* image_gather4_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36594 { 6507 /* image_gather4_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36603 { 6507 /* image_gather4_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36613 { 6507 /* image_gather4_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36623 { 6507 /* image_gather4_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36633 { 6507 /* image_gather4_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36643 { 6507 /* image_gather4_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36653 { 6507 /* image_gather4_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36663 { 6507 /* image_gather4_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36673 { 6507 /* image_gather4_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36683 { 6507 /* image_gather4_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36693 { 6507 /* image_gather4_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36703 { 6507 /* image_gather4_c_b_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36713 { 6507 /* image_gather4_c_b_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36723 { 6507 /* image_gather4_c_b_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36733 { 6507 /* image_gather4_c_b_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36743 { 6507 /* image_gather4_c_b_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36753 { 6507 /* image_gather4_c_b_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36763 { 6507 /* image_gather4_c_b_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36773 { 6507 /* image_gather4_c_b_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36783 { 6507 /* image_gather4_c_b_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36793 { 6507 /* image_gather4_c_b_cl */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36803 { 6507 /* image_gather4_c_b_cl */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36813 { 6507 /* image_gather4_c_b_cl */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36822 { 6528 /* image_gather4_c_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36831 { 6528 /* image_gather4_c_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36840 { 6528 /* image_gather4_c_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36849 { 6528 /* image_gather4_c_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36858 { 6528 /* image_gather4_c_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36867 { 6528 /* image_gather4_c_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
36877 { 6528 /* image_gather4_c_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36887 { 6528 /* image_gather4_c_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36897 { 6528 /* image_gather4_c_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36907 { 6528 /* image_gather4_c_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36917 { 6528 /* image_gather4_c_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36927 { 6528 /* image_gather4_c_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36937 { 6528 /* image_gather4_c_b_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36947 { 6528 /* image_gather4_c_b_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36957 { 6528 /* image_gather4_c_b_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36967 { 6528 /* image_gather4_c_b_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36977 { 6528 /* image_gather4_c_b_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36987 { 6528 /* image_gather4_c_b_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
36997 { 6528 /* image_gather4_c_b_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37007 { 6528 /* image_gather4_c_b_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37017 { 6528 /* image_gather4_c_b_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37027 { 6528 /* image_gather4_c_b_cl_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37037 { 6528 /* image_gather4_c_b_cl_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37047 { 6528 /* image_gather4_c_b_cl_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37056 { 6551 /* image_gather4_c_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37065 { 6551 /* image_gather4_c_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37074 { 6551 /* image_gather4_c_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37083 { 6551 /* image_gather4_c_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37092 { 6551 /* image_gather4_c_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37101 { 6551 /* image_gather4_c_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37111 { 6551 /* image_gather4_c_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37121 { 6551 /* image_gather4_c_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37131 { 6551 /* image_gather4_c_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37141 { 6551 /* image_gather4_c_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37151 { 6551 /* image_gather4_c_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37161 { 6551 /* image_gather4_c_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37171 { 6551 /* image_gather4_c_b_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37181 { 6551 /* image_gather4_c_b_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37191 { 6551 /* image_gather4_c_b_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37201 { 6551 /* image_gather4_c_b_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37211 { 6551 /* image_gather4_c_b_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37221 { 6551 /* image_gather4_c_b_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37231 { 6551 /* image_gather4_c_b_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37241 { 6551 /* image_gather4_c_b_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37251 { 6551 /* image_gather4_c_b_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37260 { 6571 /* image_gather4_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37269 { 6571 /* image_gather4_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37278 { 6571 /* image_gather4_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37287 { 6571 /* image_gather4_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37296 { 6571 /* image_gather4_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37305 { 6571 /* image_gather4_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37314 { 6571 /* image_gather4_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37323 { 6571 /* image_gather4_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37332 { 6571 /* image_gather4_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37341 { 6571 /* image_gather4_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37350 { 6571 /* image_gather4_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37359 { 6571 /* image_gather4_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37369 { 6571 /* image_gather4_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37379 { 6571 /* image_gather4_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37389 { 6571 /* image_gather4_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37399 { 6571 /* image_gather4_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37409 { 6571 /* image_gather4_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37419 { 6571 /* image_gather4_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37429 { 6571 /* image_gather4_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37439 { 6571 /* image_gather4_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37449 { 6571 /* image_gather4_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37459 { 6571 /* image_gather4_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37469 { 6571 /* image_gather4_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37479 { 6571 /* image_gather4_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37489 { 6571 /* image_gather4_c_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37499 { 6571 /* image_gather4_c_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37509 { 6571 /* image_gather4_c_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37519 { 6571 /* image_gather4_c_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37529 { 6571 /* image_gather4_c_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37539 { 6571 /* image_gather4_c_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37549 { 6571 /* image_gather4_c_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37559 { 6571 /* image_gather4_c_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37569 { 6571 /* image_gather4_c_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37579 { 6571 /* image_gather4_c_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37589 { 6571 /* image_gather4_c_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37599 { 6571 /* image_gather4_c_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37608 { 6590 /* image_gather4_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37617 { 6590 /* image_gather4_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37626 { 6590 /* image_gather4_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37635 { 6590 /* image_gather4_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37644 { 6590 /* image_gather4_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37653 { 6590 /* image_gather4_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37662 { 6590 /* image_gather4_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37671 { 6590 /* image_gather4_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37680 { 6590 /* image_gather4_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37690 { 6590 /* image_gather4_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37700 { 6590 /* image_gather4_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37710 { 6590 /* image_gather4_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37720 { 6590 /* image_gather4_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37730 { 6590 /* image_gather4_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37740 { 6590 /* image_gather4_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37750 { 6590 /* image_gather4_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37760 { 6590 /* image_gather4_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37770 { 6590 /* image_gather4_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37780 { 6590 /* image_gather4_c_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37790 { 6590 /* image_gather4_c_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37800 { 6590 /* image_gather4_c_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37810 { 6590 /* image_gather4_c_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37820 { 6590 /* image_gather4_c_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37830 { 6590 /* image_gather4_c_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37840 { 6590 /* image_gather4_c_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37850 { 6590 /* image_gather4_c_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37860 { 6590 /* image_gather4_c_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37870 { 6590 /* image_gather4_c_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37880 { 6590 /* image_gather4_c_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37890 { 6590 /* image_gather4_c_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
37899 { 6611 /* image_gather4_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37908 { 6611 /* image_gather4_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37917 { 6611 /* image_gather4_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37926 { 6611 /* image_gather4_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37935 { 6611 /* image_gather4_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37944 { 6611 /* image_gather4_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37953 { 6611 /* image_gather4_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37962 { 6611 /* image_gather4_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37971 { 6611 /* image_gather4_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37980 { 6611 /* image_gather4_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37989 { 6611 /* image_gather4_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
37998 { 6611 /* image_gather4_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38008 { 6611 /* image_gather4_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38018 { 6611 /* image_gather4_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38028 { 6611 /* image_gather4_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38038 { 6611 /* image_gather4_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38048 { 6611 /* image_gather4_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38058 { 6611 /* image_gather4_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38068 { 6611 /* image_gather4_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38078 { 6611 /* image_gather4_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38088 { 6611 /* image_gather4_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38098 { 6611 /* image_gather4_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38108 { 6611 /* image_gather4_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38118 { 6611 /* image_gather4_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38128 { 6611 /* image_gather4_c_l */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38138 { 6611 /* image_gather4_c_l */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38148 { 6611 /* image_gather4_c_l */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38158 { 6611 /* image_gather4_c_l */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38168 { 6611 /* image_gather4_c_l */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38178 { 6611 /* image_gather4_c_l */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38188 { 6611 /* image_gather4_c_l */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38198 { 6611 /* image_gather4_c_l */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38208 { 6611 /* image_gather4_c_l */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38218 { 6611 /* image_gather4_c_l */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38228 { 6611 /* image_gather4_c_l */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38238 { 6611 /* image_gather4_c_l */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38247 { 6629 /* image_gather4_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38256 { 6629 /* image_gather4_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38265 { 6629 /* image_gather4_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38274 { 6629 /* image_gather4_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38283 { 6629 /* image_gather4_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38292 { 6629 /* image_gather4_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38301 { 6629 /* image_gather4_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38310 { 6629 /* image_gather4_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38319 { 6629 /* image_gather4_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38329 { 6629 /* image_gather4_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38339 { 6629 /* image_gather4_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38349 { 6629 /* image_gather4_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38359 { 6629 /* image_gather4_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38369 { 6629 /* image_gather4_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38379 { 6629 /* image_gather4_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38389 { 6629 /* image_gather4_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38399 { 6629 /* image_gather4_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38409 { 6629 /* image_gather4_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38419 { 6629 /* image_gather4_c_l_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38429 { 6629 /* image_gather4_c_l_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38439 { 6629 /* image_gather4_c_l_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38449 { 6629 /* image_gather4_c_l_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38459 { 6629 /* image_gather4_c_l_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38469 { 6629 /* image_gather4_c_l_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38479 { 6629 /* image_gather4_c_l_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38489 { 6629 /* image_gather4_c_l_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38499 { 6629 /* image_gather4_c_l_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38509 { 6629 /* image_gather4_c_l_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38519 { 6629 /* image_gather4_c_l_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38529 { 6629 /* image_gather4_c_l_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38538 { 6649 /* image_gather4_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38547 { 6649 /* image_gather4_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38556 { 6649 /* image_gather4_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38565 { 6649 /* image_gather4_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38574 { 6649 /* image_gather4_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38583 { 6649 /* image_gather4_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38592 { 6649 /* image_gather4_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38601 { 6649 /* image_gather4_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38610 { 6649 /* image_gather4_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38620 { 6649 /* image_gather4_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38630 { 6649 /* image_gather4_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38640 { 6649 /* image_gather4_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38650 { 6649 /* image_gather4_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38660 { 6649 /* image_gather4_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38670 { 6649 /* image_gather4_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38680 { 6649 /* image_gather4_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38690 { 6649 /* image_gather4_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38700 { 6649 /* image_gather4_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38710 { 6649 /* image_gather4_c_lz */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38720 { 6649 /* image_gather4_c_lz */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38730 { 6649 /* image_gather4_c_lz */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38740 { 6649 /* image_gather4_c_lz */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38750 { 6649 /* image_gather4_c_lz */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38760 { 6649 /* image_gather4_c_lz */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38770 { 6649 /* image_gather4_c_lz */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38780 { 6649 /* image_gather4_c_lz */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38790 { 6649 /* image_gather4_c_lz */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38799 { 6668 /* image_gather4_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38808 { 6668 /* image_gather4_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38817 { 6668 /* image_gather4_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38826 { 6668 /* image_gather4_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38835 { 6668 /* image_gather4_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38844 { 6668 /* image_gather4_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38853 { 6668 /* image_gather4_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38862 { 6668 /* image_gather4_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38871 { 6668 /* image_gather4_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
38881 { 6668 /* image_gather4_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38891 { 6668 /* image_gather4_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38901 { 6668 /* image_gather4_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38911 { 6668 /* image_gather4_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38921 { 6668 /* image_gather4_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38931 { 6668 /* image_gather4_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38941 { 6668 /* image_gather4_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38951 { 6668 /* image_gather4_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38961 { 6668 /* image_gather4_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38971 { 6668 /* image_gather4_c_lz_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38981 { 6668 /* image_gather4_c_lz_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
38991 { 6668 /* image_gather4_c_lz_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39001 { 6668 /* image_gather4_c_lz_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39011 { 6668 /* image_gather4_c_lz_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39021 { 6668 /* image_gather4_c_lz_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39031 { 6668 /* image_gather4_c_lz_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39041 { 6668 /* image_gather4_c_lz_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39051 { 6668 /* image_gather4_c_lz_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39060 { 6689 /* image_gather4_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39069 { 6689 /* image_gather4_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39078 { 6689 /* image_gather4_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39087 { 6689 /* image_gather4_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39096 { 6689 /* image_gather4_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39105 { 6689 /* image_gather4_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39114 { 6689 /* image_gather4_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39123 { 6689 /* image_gather4_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39132 { 6689 /* image_gather4_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39142 { 6689 /* image_gather4_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39152 { 6689 /* image_gather4_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39162 { 6689 /* image_gather4_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39172 { 6689 /* image_gather4_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39182 { 6689 /* image_gather4_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39192 { 6689 /* image_gather4_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39202 { 6689 /* image_gather4_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39212 { 6689 /* image_gather4_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39222 { 6689 /* image_gather4_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39232 { 6689 /* image_gather4_c_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39242 { 6689 /* image_gather4_c_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39252 { 6689 /* image_gather4_c_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39262 { 6689 /* image_gather4_c_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39272 { 6689 /* image_gather4_c_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39282 { 6689 /* image_gather4_c_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39292 { 6689 /* image_gather4_c_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39302 { 6689 /* image_gather4_c_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39312 { 6689 /* image_gather4_c_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39321 { 6707 /* image_gather4_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39330 { 6707 /* image_gather4_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39339 { 6707 /* image_gather4_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39348 { 6707 /* image_gather4_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39357 { 6707 /* image_gather4_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39366 { 6707 /* image_gather4_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39375 { 6707 /* image_gather4_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39384 { 6707 /* image_gather4_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39393 { 6707 /* image_gather4_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39402 { 6707 /* image_gather4_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39411 { 6707 /* image_gather4_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39420 { 6707 /* image_gather4_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39430 { 6707 /* image_gather4_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39440 { 6707 /* image_gather4_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39450 { 6707 /* image_gather4_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39460 { 6707 /* image_gather4_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39470 { 6707 /* image_gather4_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39480 { 6707 /* image_gather4_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39490 { 6707 /* image_gather4_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39500 { 6707 /* image_gather4_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39510 { 6707 /* image_gather4_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39520 { 6707 /* image_gather4_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39530 { 6707 /* image_gather4_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39540 { 6707 /* image_gather4_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39550 { 6707 /* image_gather4_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39560 { 6707 /* image_gather4_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39570 { 6707 /* image_gather4_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39580 { 6707 /* image_gather4_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39590 { 6707 /* image_gather4_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39600 { 6707 /* image_gather4_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39610 { 6707 /* image_gather4_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39620 { 6707 /* image_gather4_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39630 { 6707 /* image_gather4_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39639 { 6724 /* image_gather4_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39648 { 6724 /* image_gather4_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39657 { 6724 /* image_gather4_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39666 { 6724 /* image_gather4_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39675 { 6724 /* image_gather4_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39684 { 6724 /* image_gather4_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39693 { 6724 /* image_gather4_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39702 { 6724 /* image_gather4_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39711 { 6724 /* image_gather4_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39720 { 6724 /* image_gather4_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39729 { 6724 /* image_gather4_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39738 { 6724 /* image_gather4_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39748 { 6724 /* image_gather4_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39758 { 6724 /* image_gather4_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39768 { 6724 /* image_gather4_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39778 { 6724 /* image_gather4_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39788 { 6724 /* image_gather4_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39798 { 6724 /* image_gather4_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39808 { 6724 /* image_gather4_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39818 { 6724 /* image_gather4_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39828 { 6724 /* image_gather4_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39838 { 6724 /* image_gather4_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39848 { 6724 /* image_gather4_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39858 { 6724 /* image_gather4_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39868 { 6724 /* image_gather4_cl_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39878 { 6724 /* image_gather4_cl_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39888 { 6724 /* image_gather4_cl_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39898 { 6724 /* image_gather4_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39908 { 6724 /* image_gather4_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39918 { 6724 /* image_gather4_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39928 { 6724 /* image_gather4_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39938 { 6724 /* image_gather4_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39948 { 6724 /* image_gather4_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39958 { 6724 /* image_gather4_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39968 { 6724 /* image_gather4_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39978 { 6724 /* image_gather4_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
39987 { 6743 /* image_gather4_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
39996 { 6743 /* image_gather4_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40005 { 6743 /* image_gather4_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40014 { 6743 /* image_gather4_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40023 { 6743 /* image_gather4_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40032 { 6743 /* image_gather4_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40041 { 6743 /* image_gather4_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40050 { 6743 /* image_gather4_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40059 { 6743 /* image_gather4_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40068 { 6743 /* image_gather4_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40077 { 6743 /* image_gather4_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40086 { 6743 /* image_gather4_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40096 { 6743 /* image_gather4_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40106 { 6743 /* image_gather4_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40116 { 6743 /* image_gather4_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40126 { 6743 /* image_gather4_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40136 { 6743 /* image_gather4_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40146 { 6743 /* image_gather4_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40156 { 6743 /* image_gather4_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40166 { 6743 /* image_gather4_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40176 { 6743 /* image_gather4_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40186 { 6743 /* image_gather4_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40196 { 6743 /* image_gather4_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40206 { 6743 /* image_gather4_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40216 { 6743 /* image_gather4_l */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40226 { 6743 /* image_gather4_l */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40236 { 6743 /* image_gather4_l */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40246 { 6743 /* image_gather4_l */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40256 { 6743 /* image_gather4_l */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40266 { 6743 /* image_gather4_l */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40276 { 6743 /* image_gather4_l */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40286 { 6743 /* image_gather4_l */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40296 { 6743 /* image_gather4_l */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40305 { 6759 /* image_gather4_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40314 { 6759 /* image_gather4_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40323 { 6759 /* image_gather4_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40332 { 6759 /* image_gather4_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40341 { 6759 /* image_gather4_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40350 { 6759 /* image_gather4_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40359 { 6759 /* image_gather4_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40368 { 6759 /* image_gather4_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40377 { 6759 /* image_gather4_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40386 { 6759 /* image_gather4_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40395 { 6759 /* image_gather4_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40404 { 6759 /* image_gather4_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40414 { 6759 /* image_gather4_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40424 { 6759 /* image_gather4_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40434 { 6759 /* image_gather4_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40444 { 6759 /* image_gather4_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40454 { 6759 /* image_gather4_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40464 { 6759 /* image_gather4_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40474 { 6759 /* image_gather4_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40484 { 6759 /* image_gather4_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40494 { 6759 /* image_gather4_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40504 { 6759 /* image_gather4_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40514 { 6759 /* image_gather4_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40524 { 6759 /* image_gather4_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40534 { 6759 /* image_gather4_l_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40544 { 6759 /* image_gather4_l_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40554 { 6759 /* image_gather4_l_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40564 { 6759 /* image_gather4_l_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40574 { 6759 /* image_gather4_l_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40584 { 6759 /* image_gather4_l_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40594 { 6759 /* image_gather4_l_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40604 { 6759 /* image_gather4_l_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40614 { 6759 /* image_gather4_l_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40624 { 6759 /* image_gather4_l_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40634 { 6759 /* image_gather4_l_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40644 { 6759 /* image_gather4_l_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40653 { 6777 /* image_gather4_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40662 { 6777 /* image_gather4_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40671 { 6777 /* image_gather4_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40680 { 6777 /* image_gather4_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40689 { 6777 /* image_gather4_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40698 { 6777 /* image_gather4_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40707 { 6777 /* image_gather4_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40716 { 6777 /* image_gather4_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40725 { 6777 /* image_gather4_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40734 { 6777 /* image_gather4_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40743 { 6777 /* image_gather4_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40752 { 6777 /* image_gather4_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40762 { 6777 /* image_gather4_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40772 { 6777 /* image_gather4_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40782 { 6777 /* image_gather4_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40792 { 6777 /* image_gather4_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40802 { 6777 /* image_gather4_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40812 { 6777 /* image_gather4_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40822 { 6777 /* image_gather4_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40832 { 6777 /* image_gather4_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40842 { 6777 /* image_gather4_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40852 { 6777 /* image_gather4_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40862 { 6777 /* image_gather4_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40872 { 6777 /* image_gather4_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40882 { 6777 /* image_gather4_lz */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40892 { 6777 /* image_gather4_lz */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40902 { 6777 /* image_gather4_lz */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40912 { 6777 /* image_gather4_lz */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40922 { 6777 /* image_gather4_lz */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40932 { 6777 /* image_gather4_lz */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
40941 { 6794 /* image_gather4_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40950 { 6794 /* image_gather4_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40959 { 6794 /* image_gather4_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40968 { 6794 /* image_gather4_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40977 { 6794 /* image_gather4_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40986 { 6794 /* image_gather4_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
40995 { 6794 /* image_gather4_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41004 { 6794 /* image_gather4_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41013 { 6794 /* image_gather4_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41023 { 6794 /* image_gather4_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41033 { 6794 /* image_gather4_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41043 { 6794 /* image_gather4_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41053 { 6794 /* image_gather4_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41063 { 6794 /* image_gather4_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41073 { 6794 /* image_gather4_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41083 { 6794 /* image_gather4_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41093 { 6794 /* image_gather4_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41103 { 6794 /* image_gather4_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41113 { 6794 /* image_gather4_lz_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41123 { 6794 /* image_gather4_lz_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41133 { 6794 /* image_gather4_lz_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41143 { 6794 /* image_gather4_lz_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41153 { 6794 /* image_gather4_lz_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41163 { 6794 /* image_gather4_lz_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41173 { 6794 /* image_gather4_lz_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41183 { 6794 /* image_gather4_lz_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41193 { 6794 /* image_gather4_lz_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41202 { 6813 /* image_gather4_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41211 { 6813 /* image_gather4_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41220 { 6813 /* image_gather4_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41229 { 6813 /* image_gather4_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41238 { 6813 /* image_gather4_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41247 { 6813 /* image_gather4_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41256 { 6813 /* image_gather4_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41265 { 6813 /* image_gather4_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41274 { 6813 /* image_gather4_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41284 { 6813 /* image_gather4_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41294 { 6813 /* image_gather4_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41304 { 6813 /* image_gather4_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41314 { 6813 /* image_gather4_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41324 { 6813 /* image_gather4_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41334 { 6813 /* image_gather4_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41344 { 6813 /* image_gather4_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41354 { 6813 /* image_gather4_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41364 { 6813 /* image_gather4_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41374 { 6813 /* image_gather4_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41384 { 6813 /* image_gather4_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41394 { 6813 /* image_gather4_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41404 { 6813 /* image_gather4_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41414 { 6813 /* image_gather4_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41424 { 6813 /* image_gather4_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41434 { 6813 /* image_gather4_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41444 { 6813 /* image_gather4_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41454 { 6813 /* image_gather4_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41463 { 6829 /* image_get_lod */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41471 { 6829 /* image_get_lod */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41479 { 6829 /* image_get_lod */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41487 { 6829 /* image_get_lod */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41495 { 6829 /* image_get_lod */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41503 { 6829 /* image_get_lod */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41511 { 6829 /* image_get_lod */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41519 { 6829 /* image_get_lod */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41527 { 6829 /* image_get_lod */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41535 { 6829 /* image_get_lod */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41543 { 6829 /* image_get_lod */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41551 { 6829 /* image_get_lod */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41559 { 6829 /* image_get_lod */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41567 { 6829 /* image_get_lod */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41575 { 6829 /* image_get_lod */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41583 { 6829 /* image_get_lod */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41591 { 6829 /* image_get_lod */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41599 { 6829 /* image_get_lod */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41607 { 6829 /* image_get_lod */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41615 { 6829 /* image_get_lod */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41624 { 6829 /* image_get_lod */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41633 { 6829 /* image_get_lod */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41642 { 6829 /* image_get_lod */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41651 { 6829 /* image_get_lod */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41660 { 6829 /* image_get_lod */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41669 { 6829 /* image_get_lod */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41678 { 6829 /* image_get_lod */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41687 { 6829 /* image_get_lod */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41696 { 6829 /* image_get_lod */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41705 { 6829 /* image_get_lod */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41714 { 6829 /* image_get_lod */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41723 { 6829 /* image_get_lod */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41732 { 6829 /* image_get_lod */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41741 { 6829 /* image_get_lod */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41750 { 6829 /* image_get_lod */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41759 { 6829 /* image_get_lod */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41768 { 6829 /* image_get_lod */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41777 { 6829 /* image_get_lod */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41786 { 6829 /* image_get_lod */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41795 { 6829 /* image_get_lod */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41804 { 6829 /* image_get_lod */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41813 { 6829 /* image_get_lod */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41822 { 6829 /* image_get_lod */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41831 { 6829 /* image_get_lod */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41840 { 6829 /* image_get_lod */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41849 { 6829 /* image_get_lod */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41858 { 6829 /* image_get_lod */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41867 { 6829 /* image_get_lod */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41876 { 6829 /* image_get_lod */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41885 { 6829 /* image_get_lod */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
41893 { 6843 /* image_get_resinfo */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41901 { 6843 /* image_get_resinfo */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41909 { 6843 /* image_get_resinfo */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41917 { 6843 /* image_get_resinfo */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41925 { 6843 /* image_get_resinfo */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41933 { 6843 /* image_get_resinfo */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41941 { 6843 /* image_get_resinfo */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41949 { 6843 /* image_get_resinfo */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41957 { 6843 /* image_get_resinfo */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41965 { 6843 /* image_get_resinfo */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41973 { 6843 /* image_get_resinfo */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41981 { 6843 /* image_get_resinfo */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41989 { 6843 /* image_get_resinfo */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
41997 { 6843 /* image_get_resinfo */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42005 { 6843 /* image_get_resinfo */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42013 { 6843 /* image_get_resinfo */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42021 { 6843 /* image_get_resinfo */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42029 { 6843 /* image_get_resinfo */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42037 { 6843 /* image_get_resinfo */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42045 { 6843 /* image_get_resinfo */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42054 { 6843 /* image_get_resinfo */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42063 { 6843 /* image_get_resinfo */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42072 { 6843 /* image_get_resinfo */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42081 { 6843 /* image_get_resinfo */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42090 { 6843 /* image_get_resinfo */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42099 { 6843 /* image_get_resinfo */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42108 { 6843 /* image_get_resinfo */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42117 { 6843 /* image_get_resinfo */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42126 { 6843 /* image_get_resinfo */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42135 { 6843 /* image_get_resinfo */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42144 { 6843 /* image_get_resinfo */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42153 { 6843 /* image_get_resinfo */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42162 { 6843 /* image_get_resinfo */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42171 { 6843 /* image_get_resinfo */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42180 { 6843 /* image_get_resinfo */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42189 { 6843 /* image_get_resinfo */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42198 { 6843 /* image_get_resinfo */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42207 { 6843 /* image_get_resinfo */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42216 { 6843 /* image_get_resinfo */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42225 { 6843 /* image_get_resinfo */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42234 { 6843 /* image_get_resinfo */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42243 { 6843 /* image_get_resinfo */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42252 { 6843 /* image_get_resinfo */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42261 { 6843 /* image_get_resinfo */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42270 { 6843 /* image_get_resinfo */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42279 { 6843 /* image_get_resinfo */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42288 { 6843 /* image_get_resinfo */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42297 { 6843 /* image_get_resinfo */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42306 { 6843 /* image_get_resinfo */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42315 { 6843 /* image_get_resinfo */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42324 { 6843 /* image_get_resinfo */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42333 { 6843 /* image_get_resinfo */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42342 { 6843 /* image_get_resinfo */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42351 { 6843 /* image_get_resinfo */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42360 { 6843 /* image_get_resinfo */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42368 { 6861 /* image_load */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42377 { 6861 /* image_load */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42386 { 6861 /* image_load */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42395 { 6861 /* image_load */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42404 { 6861 /* image_load */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42413 { 6861 /* image_load */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42422 { 6861 /* image_load */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42431 { 6861 /* image_load */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42440 { 6861 /* image_load */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42449 { 6861 /* image_load */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42458 { 6861 /* image_load */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42467 { 6861 /* image_load */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42476 { 6861 /* image_load */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42485 { 6861 /* image_load */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42494 { 6861 /* image_load */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42503 { 6861 /* image_load */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42512 { 6861 /* image_load */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42521 { 6861 /* image_load */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42530 { 6861 /* image_load */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42539 { 6861 /* image_load */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42549 { 6861 /* image_load */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42559 { 6861 /* image_load */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42569 { 6861 /* image_load */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42579 { 6861 /* image_load */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42589 { 6861 /* image_load */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42599 { 6861 /* image_load */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42609 { 6861 /* image_load */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42619 { 6861 /* image_load */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42629 { 6861 /* image_load */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42639 { 6861 /* image_load */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42649 { 6861 /* image_load */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42659 { 6861 /* image_load */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42669 { 6861 /* image_load */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42679 { 6861 /* image_load */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42689 { 6861 /* image_load */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42699 { 6861 /* image_load */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42709 { 6861 /* image_load */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42719 { 6861 /* image_load */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42729 { 6861 /* image_load */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42739 { 6861 /* image_load */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42749 { 6861 /* image_load */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42759 { 6861 /* image_load */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42769 { 6861 /* image_load */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42779 { 6861 /* image_load */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42789 { 6861 /* image_load */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42799 { 6861 /* image_load */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42809 { 6861 /* image_load */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42819 { 6861 /* image_load */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42829 { 6861 /* image_load */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42839 { 6861 /* image_load */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42849 { 6861 /* image_load */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42859 { 6861 /* image_load */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42869 { 6861 /* image_load */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42879 { 6861 /* image_load */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42889 { 6861 /* image_load */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
42898 { 6872 /* image_load_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42907 { 6872 /* image_load_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42916 { 6872 /* image_load_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42925 { 6872 /* image_load_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42934 { 6872 /* image_load_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42943 { 6872 /* image_load_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42952 { 6872 /* image_load_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42961 { 6872 /* image_load_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42970 { 6872 /* image_load_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42979 { 6872 /* image_load_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42988 { 6872 /* image_load_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
42997 { 6872 /* image_load_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43006 { 6872 /* image_load_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43015 { 6872 /* image_load_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43024 { 6872 /* image_load_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43033 { 6872 /* image_load_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43042 { 6872 /* image_load_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43051 { 6872 /* image_load_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43060 { 6872 /* image_load_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43069 { 6872 /* image_load_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43079 { 6872 /* image_load_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43089 { 6872 /* image_load_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43099 { 6872 /* image_load_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43109 { 6872 /* image_load_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43119 { 6872 /* image_load_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43129 { 6872 /* image_load_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43139 { 6872 /* image_load_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43149 { 6872 /* image_load_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43159 { 6872 /* image_load_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43169 { 6872 /* image_load_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43179 { 6872 /* image_load_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43189 { 6872 /* image_load_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43199 { 6872 /* image_load_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43209 { 6872 /* image_load_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43219 { 6872 /* image_load_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43229 { 6872 /* image_load_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43239 { 6872 /* image_load_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43249 { 6872 /* image_load_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43259 { 6872 /* image_load_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43269 { 6872 /* image_load_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43279 { 6872 /* image_load_mip */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43289 { 6872 /* image_load_mip */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43299 { 6872 /* image_load_mip */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43309 { 6872 /* image_load_mip */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43319 { 6872 /* image_load_mip */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43329 { 6872 /* image_load_mip */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43339 { 6872 /* image_load_mip */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43349 { 6872 /* image_load_mip */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43359 { 6872 /* image_load_mip */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43369 { 6872 /* image_load_mip */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43379 { 6872 /* image_load_mip */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43389 { 6872 /* image_load_mip */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43399 { 6872 /* image_load_mip */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43409 { 6872 /* image_load_mip */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43419 { 6872 /* image_load_mip */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43428 { 6887 /* image_load_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43436 { 6887 /* image_load_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43444 { 6887 /* image_load_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43452 { 6887 /* image_load_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43460 { 6887 /* image_load_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43468 { 6887 /* image_load_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43476 { 6887 /* image_load_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43484 { 6887 /* image_load_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43492 { 6887 /* image_load_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43500 { 6887 /* image_load_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43508 { 6887 /* image_load_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43516 { 6887 /* image_load_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43524 { 6887 /* image_load_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43532 { 6887 /* image_load_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43540 { 6887 /* image_load_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43548 { 6887 /* image_load_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43556 { 6887 /* image_load_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43564 { 6887 /* image_load_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43572 { 6887 /* image_load_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43580 { 6887 /* image_load_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43589 { 6887 /* image_load_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43598 { 6887 /* image_load_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43607 { 6887 /* image_load_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43616 { 6887 /* image_load_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43625 { 6887 /* image_load_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43634 { 6887 /* image_load_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43643 { 6887 /* image_load_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43652 { 6887 /* image_load_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43661 { 6887 /* image_load_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43670 { 6887 /* image_load_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43679 { 6887 /* image_load_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43688 { 6887 /* image_load_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43697 { 6887 /* image_load_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43706 { 6887 /* image_load_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43715 { 6887 /* image_load_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43724 { 6887 /* image_load_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43733 { 6887 /* image_load_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43742 { 6887 /* image_load_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43751 { 6887 /* image_load_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43760 { 6887 /* image_load_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43769 { 6887 /* image_load_mip_pck */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43778 { 6887 /* image_load_mip_pck */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43787 { 6887 /* image_load_mip_pck */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43796 { 6887 /* image_load_mip_pck */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43805 { 6887 /* image_load_mip_pck */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43814 { 6887 /* image_load_mip_pck */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43823 { 6887 /* image_load_mip_pck */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43832 { 6887 /* image_load_mip_pck */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43841 { 6887 /* image_load_mip_pck */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43850 { 6887 /* image_load_mip_pck */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43859 { 6887 /* image_load_mip_pck */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43868 { 6887 /* image_load_mip_pck */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43877 { 6887 /* image_load_mip_pck */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43886 { 6887 /* image_load_mip_pck */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43895 { 6887 /* image_load_mip_pck */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
43903 { 6906 /* image_load_mip_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43911 { 6906 /* image_load_mip_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43919 { 6906 /* image_load_mip_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43927 { 6906 /* image_load_mip_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43935 { 6906 /* image_load_mip_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43943 { 6906 /* image_load_mip_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43951 { 6906 /* image_load_mip_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43959 { 6906 /* image_load_mip_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43967 { 6906 /* image_load_mip_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43975 { 6906 /* image_load_mip_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43983 { 6906 /* image_load_mip_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43991 { 6906 /* image_load_mip_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
43999 { 6906 /* image_load_mip_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44007 { 6906 /* image_load_mip_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44015 { 6906 /* image_load_mip_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44023 { 6906 /* image_load_mip_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44031 { 6906 /* image_load_mip_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44039 { 6906 /* image_load_mip_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44047 { 6906 /* image_load_mip_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44055 { 6906 /* image_load_mip_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44064 { 6906 /* image_load_mip_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44073 { 6906 /* image_load_mip_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44082 { 6906 /* image_load_mip_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44091 { 6906 /* image_load_mip_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44100 { 6906 /* image_load_mip_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44109 { 6906 /* image_load_mip_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44118 { 6906 /* image_load_mip_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44127 { 6906 /* image_load_mip_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44136 { 6906 /* image_load_mip_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44145 { 6906 /* image_load_mip_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44154 { 6906 /* image_load_mip_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44163 { 6906 /* image_load_mip_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44172 { 6906 /* image_load_mip_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44181 { 6906 /* image_load_mip_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44190 { 6906 /* image_load_mip_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44199 { 6906 /* image_load_mip_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44208 { 6906 /* image_load_mip_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44217 { 6906 /* image_load_mip_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44226 { 6906 /* image_load_mip_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44235 { 6906 /* image_load_mip_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44244 { 6906 /* image_load_mip_pck_sgn */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44253 { 6906 /* image_load_mip_pck_sgn */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44262 { 6906 /* image_load_mip_pck_sgn */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44271 { 6906 /* image_load_mip_pck_sgn */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44280 { 6906 /* image_load_mip_pck_sgn */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44289 { 6906 /* image_load_mip_pck_sgn */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44298 { 6906 /* image_load_mip_pck_sgn */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44307 { 6906 /* image_load_mip_pck_sgn */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44316 { 6906 /* image_load_mip_pck_sgn */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44325 { 6906 /* image_load_mip_pck_sgn */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44334 { 6906 /* image_load_mip_pck_sgn */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44343 { 6906 /* image_load_mip_pck_sgn */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44352 { 6906 /* image_load_mip_pck_sgn */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44361 { 6906 /* image_load_mip_pck_sgn */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44370 { 6906 /* image_load_mip_pck_sgn */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44378 { 6929 /* image_load_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44386 { 6929 /* image_load_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44394 { 6929 /* image_load_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44402 { 6929 /* image_load_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44410 { 6929 /* image_load_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44418 { 6929 /* image_load_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44426 { 6929 /* image_load_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44434 { 6929 /* image_load_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44442 { 6929 /* image_load_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44450 { 6929 /* image_load_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44458 { 6929 /* image_load_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44466 { 6929 /* image_load_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44474 { 6929 /* image_load_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44482 { 6929 /* image_load_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44490 { 6929 /* image_load_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44498 { 6929 /* image_load_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44506 { 6929 /* image_load_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44514 { 6929 /* image_load_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44522 { 6929 /* image_load_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44530 { 6929 /* image_load_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44539 { 6929 /* image_load_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44548 { 6929 /* image_load_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44557 { 6929 /* image_load_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44566 { 6929 /* image_load_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44575 { 6929 /* image_load_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44584 { 6929 /* image_load_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44593 { 6929 /* image_load_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44602 { 6929 /* image_load_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44611 { 6929 /* image_load_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44620 { 6929 /* image_load_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44629 { 6929 /* image_load_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44638 { 6929 /* image_load_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44647 { 6929 /* image_load_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44656 { 6929 /* image_load_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44665 { 6929 /* image_load_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44674 { 6929 /* image_load_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44683 { 6929 /* image_load_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44692 { 6929 /* image_load_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44701 { 6929 /* image_load_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44710 { 6929 /* image_load_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44719 { 6929 /* image_load_pck */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44728 { 6929 /* image_load_pck */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44737 { 6929 /* image_load_pck */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44746 { 6929 /* image_load_pck */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44755 { 6929 /* image_load_pck */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44764 { 6929 /* image_load_pck */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44773 { 6929 /* image_load_pck */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44782 { 6929 /* image_load_pck */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44791 { 6929 /* image_load_pck */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44800 { 6929 /* image_load_pck */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44809 { 6929 /* image_load_pck */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44818 { 6929 /* image_load_pck */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44827 { 6929 /* image_load_pck */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44836 { 6929 /* image_load_pck */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44845 { 6929 /* image_load_pck */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
44853 { 6944 /* image_load_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44861 { 6944 /* image_load_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44869 { 6944 /* image_load_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44877 { 6944 /* image_load_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44885 { 6944 /* image_load_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44893 { 6944 /* image_load_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44901 { 6944 /* image_load_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44909 { 6944 /* image_load_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44917 { 6944 /* image_load_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44925 { 6944 /* image_load_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44933 { 6944 /* image_load_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44941 { 6944 /* image_load_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44949 { 6944 /* image_load_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44957 { 6944 /* image_load_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44965 { 6944 /* image_load_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44973 { 6944 /* image_load_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44981 { 6944 /* image_load_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44989 { 6944 /* image_load_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
44997 { 6944 /* image_load_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45005 { 6944 /* image_load_pck_sgn */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45014 { 6944 /* image_load_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45023 { 6944 /* image_load_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45032 { 6944 /* image_load_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45041 { 6944 /* image_load_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45050 { 6944 /* image_load_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45059 { 6944 /* image_load_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45068 { 6944 /* image_load_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45077 { 6944 /* image_load_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45086 { 6944 /* image_load_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45095 { 6944 /* image_load_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45104 { 6944 /* image_load_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45113 { 6944 /* image_load_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45122 { 6944 /* image_load_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45131 { 6944 /* image_load_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45140 { 6944 /* image_load_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45149 { 6944 /* image_load_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45158 { 6944 /* image_load_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45167 { 6944 /* image_load_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45176 { 6944 /* image_load_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45185 { 6944 /* image_load_pck_sgn */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45194 { 6944 /* image_load_pck_sgn */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45203 { 6944 /* image_load_pck_sgn */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45212 { 6944 /* image_load_pck_sgn */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45221 { 6944 /* image_load_pck_sgn */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45230 { 6944 /* image_load_pck_sgn */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45239 { 6944 /* image_load_pck_sgn */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45248 { 6944 /* image_load_pck_sgn */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45257 { 6944 /* image_load_pck_sgn */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45266 { 6944 /* image_load_pck_sgn */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45275 { 6944 /* image_load_pck_sgn */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45284 { 6944 /* image_load_pck_sgn */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45293 { 6944 /* image_load_pck_sgn */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45302 { 6944 /* image_load_pck_sgn */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45311 { 6944 /* image_load_pck_sgn */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45320 { 6944 /* image_load_pck_sgn */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45328 { 6963 /* image_sample */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45337 { 6963 /* image_sample */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45346 { 6963 /* image_sample */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45355 { 6963 /* image_sample */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45364 { 6963 /* image_sample */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45373 { 6963 /* image_sample */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45382 { 6963 /* image_sample */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45391 { 6963 /* image_sample */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45400 { 6963 /* image_sample */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45409 { 6963 /* image_sample */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45418 { 6963 /* image_sample */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45427 { 6963 /* image_sample */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45436 { 6963 /* image_sample */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45445 { 6963 /* image_sample */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45454 { 6963 /* image_sample */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45463 { 6963 /* image_sample */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45472 { 6963 /* image_sample */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45481 { 6963 /* image_sample */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45490 { 6963 /* image_sample */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45499 { 6963 /* image_sample */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45509 { 6963 /* image_sample */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45519 { 6963 /* image_sample */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45529 { 6963 /* image_sample */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45539 { 6963 /* image_sample */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45549 { 6963 /* image_sample */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45559 { 6963 /* image_sample */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45569 { 6963 /* image_sample */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45579 { 6963 /* image_sample */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45589 { 6963 /* image_sample */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45599 { 6963 /* image_sample */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45609 { 6963 /* image_sample */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45619 { 6963 /* image_sample */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45629 { 6963 /* image_sample */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45639 { 6963 /* image_sample */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45649 { 6963 /* image_sample */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45659 { 6963 /* image_sample */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45669 { 6963 /* image_sample */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45679 { 6963 /* image_sample */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45689 { 6963 /* image_sample */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45699 { 6963 /* image_sample */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45709 { 6963 /* image_sample */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45719 { 6963 /* image_sample */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45729 { 6963 /* image_sample */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45739 { 6963 /* image_sample */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45749 { 6963 /* image_sample */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45759 { 6963 /* image_sample */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45769 { 6963 /* image_sample */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45779 { 6963 /* image_sample */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45789 { 6963 /* image_sample */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45799 { 6963 /* image_sample */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45808 { 6976 /* image_sample_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45817 { 6976 /* image_sample_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45826 { 6976 /* image_sample_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45835 { 6976 /* image_sample_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45844 { 6976 /* image_sample_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45853 { 6976 /* image_sample_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45862 { 6976 /* image_sample_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45871 { 6976 /* image_sample_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45880 { 6976 /* image_sample_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45889 { 6976 /* image_sample_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45898 { 6976 /* image_sample_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45907 { 6976 /* image_sample_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45916 { 6976 /* image_sample_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45925 { 6976 /* image_sample_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45934 { 6976 /* image_sample_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
45944 { 6976 /* image_sample_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45954 { 6976 /* image_sample_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45964 { 6976 /* image_sample_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45974 { 6976 /* image_sample_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45984 { 6976 /* image_sample_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
45994 { 6976 /* image_sample_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46004 { 6976 /* image_sample_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46014 { 6976 /* image_sample_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46024 { 6976 /* image_sample_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46034 { 6976 /* image_sample_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46044 { 6976 /* image_sample_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46054 { 6976 /* image_sample_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46064 { 6976 /* image_sample_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46074 { 6976 /* image_sample_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46084 { 6976 /* image_sample_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46094 { 6976 /* image_sample_b */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46104 { 6976 /* image_sample_b */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46114 { 6976 /* image_sample_b */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46124 { 6976 /* image_sample_b */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46134 { 6976 /* image_sample_b */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46144 { 6976 /* image_sample_b */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46154 { 6976 /* image_sample_b */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46164 { 6976 /* image_sample_b */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46174 { 6976 /* image_sample_b */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46184 { 6976 /* image_sample_b */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46194 { 6976 /* image_sample_b */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46204 { 6976 /* image_sample_b */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46214 { 6976 /* image_sample_b */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46224 { 6976 /* image_sample_b */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46234 { 6976 /* image_sample_b */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46243 { 6991 /* image_sample_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46252 { 6991 /* image_sample_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46261 { 6991 /* image_sample_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46270 { 6991 /* image_sample_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46279 { 6991 /* image_sample_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46288 { 6991 /* image_sample_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46297 { 6991 /* image_sample_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46306 { 6991 /* image_sample_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46315 { 6991 /* image_sample_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46324 { 6991 /* image_sample_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46333 { 6991 /* image_sample_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46342 { 6991 /* image_sample_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46351 { 6991 /* image_sample_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46360 { 6991 /* image_sample_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46369 { 6991 /* image_sample_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46378 { 6991 /* image_sample_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46387 { 6991 /* image_sample_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46396 { 6991 /* image_sample_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46405 { 6991 /* image_sample_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46414 { 6991 /* image_sample_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46424 { 6991 /* image_sample_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46434 { 6991 /* image_sample_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46444 { 6991 /* image_sample_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46454 { 6991 /* image_sample_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46464 { 6991 /* image_sample_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46474 { 6991 /* image_sample_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46484 { 6991 /* image_sample_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46494 { 6991 /* image_sample_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46504 { 6991 /* image_sample_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46514 { 6991 /* image_sample_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46524 { 6991 /* image_sample_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46534 { 6991 /* image_sample_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46544 { 6991 /* image_sample_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46554 { 6991 /* image_sample_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46564 { 6991 /* image_sample_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46574 { 6991 /* image_sample_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46584 { 6991 /* image_sample_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46594 { 6991 /* image_sample_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46604 { 6991 /* image_sample_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46614 { 6991 /* image_sample_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46624 { 6991 /* image_sample_b_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46634 { 6991 /* image_sample_b_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46644 { 6991 /* image_sample_b_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46654 { 6991 /* image_sample_b_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46664 { 6991 /* image_sample_b_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46674 { 6991 /* image_sample_b_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46684 { 6991 /* image_sample_b_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46694 { 6991 /* image_sample_b_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46704 { 6991 /* image_sample_b_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46714 { 6991 /* image_sample_b_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46724 { 6991 /* image_sample_b_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46734 { 6991 /* image_sample_b_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46744 { 6991 /* image_sample_b_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46754 { 6991 /* image_sample_b_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46764 { 6991 /* image_sample_b_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46774 { 6991 /* image_sample_b_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46784 { 6991 /* image_sample_b_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46794 { 6991 /* image_sample_b_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46804 { 6991 /* image_sample_b_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46814 { 6991 /* image_sample_b_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46823 { 7009 /* image_sample_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46832 { 7009 /* image_sample_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46841 { 7009 /* image_sample_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46850 { 7009 /* image_sample_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46859 { 7009 /* image_sample_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46868 { 7009 /* image_sample_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46877 { 7009 /* image_sample_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46886 { 7009 /* image_sample_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46895 { 7009 /* image_sample_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46904 { 7009 /* image_sample_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46913 { 7009 /* image_sample_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46922 { 7009 /* image_sample_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46931 { 7009 /* image_sample_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46940 { 7009 /* image_sample_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46949 { 7009 /* image_sample_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
46959 { 7009 /* image_sample_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46969 { 7009 /* image_sample_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46979 { 7009 /* image_sample_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46989 { 7009 /* image_sample_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
46999 { 7009 /* image_sample_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47009 { 7009 /* image_sample_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47019 { 7009 /* image_sample_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47029 { 7009 /* image_sample_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47039 { 7009 /* image_sample_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47049 { 7009 /* image_sample_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47059 { 7009 /* image_sample_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47069 { 7009 /* image_sample_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47079 { 7009 /* image_sample_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47089 { 7009 /* image_sample_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47099 { 7009 /* image_sample_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47109 { 7009 /* image_sample_b_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47119 { 7009 /* image_sample_b_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47129 { 7009 /* image_sample_b_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47139 { 7009 /* image_sample_b_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47149 { 7009 /* image_sample_b_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47159 { 7009 /* image_sample_b_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47169 { 7009 /* image_sample_b_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47179 { 7009 /* image_sample_b_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47189 { 7009 /* image_sample_b_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47199 { 7009 /* image_sample_b_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47209 { 7009 /* image_sample_b_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47219 { 7009 /* image_sample_b_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47229 { 7009 /* image_sample_b_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47239 { 7009 /* image_sample_b_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47249 { 7009 /* image_sample_b_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47259 { 7009 /* image_sample_b_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47269 { 7009 /* image_sample_b_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47279 { 7009 /* image_sample_b_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47289 { 7009 /* image_sample_b_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47299 { 7009 /* image_sample_b_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47308 { 7029 /* image_sample_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47317 { 7029 /* image_sample_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47326 { 7029 /* image_sample_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47335 { 7029 /* image_sample_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47344 { 7029 /* image_sample_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47353 { 7029 /* image_sample_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47362 { 7029 /* image_sample_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47371 { 7029 /* image_sample_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47380 { 7029 /* image_sample_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47389 { 7029 /* image_sample_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47398 { 7029 /* image_sample_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47407 { 7029 /* image_sample_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47416 { 7029 /* image_sample_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47425 { 7029 /* image_sample_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47434 { 7029 /* image_sample_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47444 { 7029 /* image_sample_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47454 { 7029 /* image_sample_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47464 { 7029 /* image_sample_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47474 { 7029 /* image_sample_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47484 { 7029 /* image_sample_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47494 { 7029 /* image_sample_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47504 { 7029 /* image_sample_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47514 { 7029 /* image_sample_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47524 { 7029 /* image_sample_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47534 { 7029 /* image_sample_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47544 { 7029 /* image_sample_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47554 { 7029 /* image_sample_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47564 { 7029 /* image_sample_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47574 { 7029 /* image_sample_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47584 { 7029 /* image_sample_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47594 { 7029 /* image_sample_b_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47604 { 7029 /* image_sample_b_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47614 { 7029 /* image_sample_b_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47624 { 7029 /* image_sample_b_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47634 { 7029 /* image_sample_b_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47644 { 7029 /* image_sample_b_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47654 { 7029 /* image_sample_b_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47664 { 7029 /* image_sample_b_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47674 { 7029 /* image_sample_b_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47684 { 7029 /* image_sample_b_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47694 { 7029 /* image_sample_b_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47704 { 7029 /* image_sample_b_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47714 { 7029 /* image_sample_b_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47724 { 7029 /* image_sample_b_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47734 { 7029 /* image_sample_b_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47743 { 7046 /* image_sample_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47752 { 7046 /* image_sample_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47761 { 7046 /* image_sample_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47770 { 7046 /* image_sample_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47779 { 7046 /* image_sample_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47788 { 7046 /* image_sample_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47797 { 7046 /* image_sample_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47806 { 7046 /* image_sample_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47815 { 7046 /* image_sample_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47824 { 7046 /* image_sample_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47833 { 7046 /* image_sample_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47842 { 7046 /* image_sample_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47851 { 7046 /* image_sample_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47860 { 7046 /* image_sample_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47869 { 7046 /* image_sample_c */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
47879 { 7046 /* image_sample_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47889 { 7046 /* image_sample_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47899 { 7046 /* image_sample_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47909 { 7046 /* image_sample_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47919 { 7046 /* image_sample_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47929 { 7046 /* image_sample_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47939 { 7046 /* image_sample_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47949 { 7046 /* image_sample_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47959 { 7046 /* image_sample_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47969 { 7046 /* image_sample_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47979 { 7046 /* image_sample_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47989 { 7046 /* image_sample_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
47999 { 7046 /* image_sample_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48009 { 7046 /* image_sample_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48019 { 7046 /* image_sample_c */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48029 { 7046 /* image_sample_c */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48039 { 7046 /* image_sample_c */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48049 { 7046 /* image_sample_c */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48059 { 7046 /* image_sample_c */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48069 { 7046 /* image_sample_c */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48079 { 7046 /* image_sample_c */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48089 { 7046 /* image_sample_c */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48099 { 7046 /* image_sample_c */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48109 { 7046 /* image_sample_c */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48119 { 7046 /* image_sample_c */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48129 { 7046 /* image_sample_c */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48139 { 7046 /* image_sample_c */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48149 { 7046 /* image_sample_c */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48159 { 7046 /* image_sample_c */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48169 { 7046 /* image_sample_c */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48178 { 7061 /* image_sample_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48187 { 7061 /* image_sample_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48196 { 7061 /* image_sample_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48205 { 7061 /* image_sample_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48214 { 7061 /* image_sample_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48223 { 7061 /* image_sample_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48232 { 7061 /* image_sample_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48241 { 7061 /* image_sample_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48250 { 7061 /* image_sample_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48259 { 7061 /* image_sample_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48268 { 7061 /* image_sample_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48277 { 7061 /* image_sample_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48286 { 7061 /* image_sample_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48295 { 7061 /* image_sample_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48304 { 7061 /* image_sample_c_b */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48314 { 7061 /* image_sample_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48324 { 7061 /* image_sample_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48334 { 7061 /* image_sample_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48344 { 7061 /* image_sample_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48354 { 7061 /* image_sample_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48364 { 7061 /* image_sample_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48374 { 7061 /* image_sample_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48384 { 7061 /* image_sample_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48394 { 7061 /* image_sample_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48404 { 7061 /* image_sample_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48414 { 7061 /* image_sample_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48424 { 7061 /* image_sample_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48434 { 7061 /* image_sample_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48444 { 7061 /* image_sample_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48454 { 7061 /* image_sample_c_b */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48464 { 7061 /* image_sample_c_b */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48474 { 7061 /* image_sample_c_b */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48484 { 7061 /* image_sample_c_b */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48494 { 7061 /* image_sample_c_b */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48504 { 7061 /* image_sample_c_b */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48514 { 7061 /* image_sample_c_b */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48524 { 7061 /* image_sample_c_b */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48534 { 7061 /* image_sample_c_b */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48544 { 7061 /* image_sample_c_b */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48554 { 7061 /* image_sample_c_b */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48564 { 7061 /* image_sample_c_b */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48574 { 7061 /* image_sample_c_b */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48584 { 7061 /* image_sample_c_b */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48594 { 7061 /* image_sample_c_b */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48604 { 7061 /* image_sample_c_b */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48613 { 7078 /* image_sample_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48622 { 7078 /* image_sample_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48631 { 7078 /* image_sample_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48640 { 7078 /* image_sample_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48649 { 7078 /* image_sample_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48658 { 7078 /* image_sample_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48667 { 7078 /* image_sample_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48676 { 7078 /* image_sample_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48685 { 7078 /* image_sample_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48694 { 7078 /* image_sample_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48703 { 7078 /* image_sample_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48712 { 7078 /* image_sample_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48721 { 7078 /* image_sample_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48730 { 7078 /* image_sample_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48739 { 7078 /* image_sample_c_b_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
48749 { 7078 /* image_sample_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48759 { 7078 /* image_sample_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48769 { 7078 /* image_sample_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48779 { 7078 /* image_sample_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48789 { 7078 /* image_sample_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48799 { 7078 /* image_sample_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48809 { 7078 /* image_sample_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48819 { 7078 /* image_sample_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48829 { 7078 /* image_sample_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48839 { 7078 /* image_sample_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48849 { 7078 /* image_sample_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48859 { 7078 /* image_sample_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48869 { 7078 /* image_sample_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48879 { 7078 /* image_sample_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48889 { 7078 /* image_sample_c_b_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48899 { 7078 /* image_sample_c_b_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48909 { 7078 /* image_sample_c_b_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48919 { 7078 /* image_sample_c_b_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48929 { 7078 /* image_sample_c_b_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48939 { 7078 /* image_sample_c_b_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48949 { 7078 /* image_sample_c_b_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48959 { 7078 /* image_sample_c_b_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48969 { 7078 /* image_sample_c_b_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48979 { 7078 /* image_sample_c_b_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48989 { 7078 /* image_sample_c_b_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
48999 { 7078 /* image_sample_c_b_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49009 { 7078 /* image_sample_c_b_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49019 { 7078 /* image_sample_c_b_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49029 { 7078 /* image_sample_c_b_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49039 { 7078 /* image_sample_c_b_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49049 { 7078 /* image_sample_c_b_cl */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49059 { 7078 /* image_sample_c_b_cl */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49069 { 7078 /* image_sample_c_b_cl */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49079 { 7078 /* image_sample_c_b_cl */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49089 { 7078 /* image_sample_c_b_cl */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49098 { 7098 /* image_sample_c_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49107 { 7098 /* image_sample_c_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49116 { 7098 /* image_sample_c_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49125 { 7098 /* image_sample_c_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49134 { 7098 /* image_sample_c_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49143 { 7098 /* image_sample_c_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49152 { 7098 /* image_sample_c_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49161 { 7098 /* image_sample_c_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49170 { 7098 /* image_sample_c_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49179 { 7098 /* image_sample_c_b_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49189 { 7098 /* image_sample_c_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49199 { 7098 /* image_sample_c_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49209 { 7098 /* image_sample_c_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49219 { 7098 /* image_sample_c_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49229 { 7098 /* image_sample_c_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49239 { 7098 /* image_sample_c_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49249 { 7098 /* image_sample_c_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49259 { 7098 /* image_sample_c_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49269 { 7098 /* image_sample_c_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49279 { 7098 /* image_sample_c_b_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49289 { 7098 /* image_sample_c_b_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49299 { 7098 /* image_sample_c_b_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49309 { 7098 /* image_sample_c_b_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49319 { 7098 /* image_sample_c_b_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49329 { 7098 /* image_sample_c_b_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49339 { 7098 /* image_sample_c_b_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49349 { 7098 /* image_sample_c_b_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49359 { 7098 /* image_sample_c_b_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49369 { 7098 /* image_sample_c_b_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49379 { 7098 /* image_sample_c_b_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49389 { 7098 /* image_sample_c_b_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49399 { 7098 /* image_sample_c_b_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49409 { 7098 /* image_sample_c_b_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49419 { 7098 /* image_sample_c_b_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49429 { 7098 /* image_sample_c_b_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49439 { 7098 /* image_sample_c_b_cl_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49449 { 7098 /* image_sample_c_b_cl_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49459 { 7098 /* image_sample_c_b_cl_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49469 { 7098 /* image_sample_c_b_cl_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49479 { 7098 /* image_sample_c_b_cl_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49488 { 7120 /* image_sample_c_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49497 { 7120 /* image_sample_c_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49506 { 7120 /* image_sample_c_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49515 { 7120 /* image_sample_c_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49524 { 7120 /* image_sample_c_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49533 { 7120 /* image_sample_c_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49542 { 7120 /* image_sample_c_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49551 { 7120 /* image_sample_c_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49560 { 7120 /* image_sample_c_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49569 { 7120 /* image_sample_c_b_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49579 { 7120 /* image_sample_c_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49589 { 7120 /* image_sample_c_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49599 { 7120 /* image_sample_c_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49609 { 7120 /* image_sample_c_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49619 { 7120 /* image_sample_c_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49629 { 7120 /* image_sample_c_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49639 { 7120 /* image_sample_c_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49649 { 7120 /* image_sample_c_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49659 { 7120 /* image_sample_c_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49669 { 7120 /* image_sample_c_b_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49679 { 7120 /* image_sample_c_b_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49689 { 7120 /* image_sample_c_b_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49699 { 7120 /* image_sample_c_b_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49709 { 7120 /* image_sample_c_b_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49719 { 7120 /* image_sample_c_b_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49729 { 7120 /* image_sample_c_b_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49739 { 7120 /* image_sample_c_b_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49749 { 7120 /* image_sample_c_b_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49759 { 7120 /* image_sample_c_b_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49769 { 7120 /* image_sample_c_b_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49779 { 7120 /* image_sample_c_b_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49789 { 7120 /* image_sample_c_b_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49799 { 7120 /* image_sample_c_b_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49809 { 7120 /* image_sample_c_b_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49819 { 7120 /* image_sample_c_b_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
49828 { 7139 /* image_sample_c_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49837 { 7139 /* image_sample_c_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49846 { 7139 /* image_sample_c_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49855 { 7139 /* image_sample_c_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49864 { 7139 /* image_sample_c_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49873 { 7139 /* image_sample_c_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49882 { 7139 /* image_sample_c_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49891 { 7139 /* image_sample_c_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49900 { 7139 /* image_sample_c_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49909 { 7139 /* image_sample_c_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49918 { 7139 /* image_sample_c_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49927 { 7139 /* image_sample_c_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49936 { 7139 /* image_sample_c_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49945 { 7139 /* image_sample_c_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49954 { 7139 /* image_sample_c_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49963 { 7139 /* image_sample_c_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49972 { 7139 /* image_sample_c_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49981 { 7139 /* image_sample_c_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49990 { 7139 /* image_sample_c_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
49999 { 7139 /* image_sample_c_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50009 { 7139 /* image_sample_c_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50019 { 7139 /* image_sample_c_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50029 { 7139 /* image_sample_c_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50039 { 7139 /* image_sample_c_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50049 { 7139 /* image_sample_c_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50059 { 7139 /* image_sample_c_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50069 { 7139 /* image_sample_c_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50079 { 7139 /* image_sample_c_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50089 { 7139 /* image_sample_c_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50099 { 7139 /* image_sample_c_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50109 { 7139 /* image_sample_c_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50119 { 7139 /* image_sample_c_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50129 { 7139 /* image_sample_c_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50139 { 7139 /* image_sample_c_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50149 { 7139 /* image_sample_c_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50159 { 7139 /* image_sample_c_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50169 { 7139 /* image_sample_c_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50179 { 7139 /* image_sample_c_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50189 { 7139 /* image_sample_c_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50199 { 7139 /* image_sample_c_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50209 { 7139 /* image_sample_c_cd */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50219 { 7139 /* image_sample_c_cd */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50229 { 7139 /* image_sample_c_cd */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50239 { 7139 /* image_sample_c_cd */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50249 { 7139 /* image_sample_c_cd */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50259 { 7139 /* image_sample_c_cd */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50269 { 7139 /* image_sample_c_cd */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50279 { 7139 /* image_sample_c_cd */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50289 { 7139 /* image_sample_c_cd */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50299 { 7139 /* image_sample_c_cd */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50309 { 7139 /* image_sample_c_cd */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50319 { 7139 /* image_sample_c_cd */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50329 { 7139 /* image_sample_c_cd */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50339 { 7139 /* image_sample_c_cd */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50349 { 7139 /* image_sample_c_cd */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50359 { 7139 /* image_sample_c_cd */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50369 { 7139 /* image_sample_c_cd */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50379 { 7139 /* image_sample_c_cd */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50389 { 7139 /* image_sample_c_cd */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50399 { 7139 /* image_sample_c_cd */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50409 { 7139 /* image_sample_c_cd */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50419 { 7139 /* image_sample_c_cd */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50429 { 7139 /* image_sample_c_cd */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50439 { 7139 /* image_sample_c_cd */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50449 { 7139 /* image_sample_c_cd */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50459 { 7139 /* image_sample_c_cd */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50469 { 7139 /* image_sample_c_cd */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50479 { 7139 /* image_sample_c_cd */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50489 { 7139 /* image_sample_c_cd */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50499 { 7139 /* image_sample_c_cd */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50509 { 7139 /* image_sample_c_cd */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50519 { 7139 /* image_sample_c_cd */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50529 { 7139 /* image_sample_c_cd */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50539 { 7139 /* image_sample_c_cd */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50549 { 7139 /* image_sample_c_cd */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50558 { 7157 /* image_sample_c_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50567 { 7157 /* image_sample_c_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50576 { 7157 /* image_sample_c_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50585 { 7157 /* image_sample_c_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50594 { 7157 /* image_sample_c_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50603 { 7157 /* image_sample_c_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50612 { 7157 /* image_sample_c_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50621 { 7157 /* image_sample_c_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50630 { 7157 /* image_sample_c_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50639 { 7157 /* image_sample_c_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50648 { 7157 /* image_sample_c_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50657 { 7157 /* image_sample_c_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50666 { 7157 /* image_sample_c_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50675 { 7157 /* image_sample_c_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50684 { 7157 /* image_sample_c_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50693 { 7157 /* image_sample_c_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50702 { 7157 /* image_sample_c_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50711 { 7157 /* image_sample_c_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50720 { 7157 /* image_sample_c_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50729 { 7157 /* image_sample_c_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
50739 { 7157 /* image_sample_c_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50749 { 7157 /* image_sample_c_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50759 { 7157 /* image_sample_c_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50769 { 7157 /* image_sample_c_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50779 { 7157 /* image_sample_c_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50789 { 7157 /* image_sample_c_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50799 { 7157 /* image_sample_c_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50809 { 7157 /* image_sample_c_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50819 { 7157 /* image_sample_c_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50829 { 7157 /* image_sample_c_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50839 { 7157 /* image_sample_c_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50849 { 7157 /* image_sample_c_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50859 { 7157 /* image_sample_c_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50869 { 7157 /* image_sample_c_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50879 { 7157 /* image_sample_c_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50889 { 7157 /* image_sample_c_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50899 { 7157 /* image_sample_c_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50909 { 7157 /* image_sample_c_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50919 { 7157 /* image_sample_c_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50929 { 7157 /* image_sample_c_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50939 { 7157 /* image_sample_c_cd_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50949 { 7157 /* image_sample_c_cd_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50959 { 7157 /* image_sample_c_cd_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50969 { 7157 /* image_sample_c_cd_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50979 { 7157 /* image_sample_c_cd_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50989 { 7157 /* image_sample_c_cd_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
50999 { 7157 /* image_sample_c_cd_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51009 { 7157 /* image_sample_c_cd_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51019 { 7157 /* image_sample_c_cd_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51029 { 7157 /* image_sample_c_cd_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51039 { 7157 /* image_sample_c_cd_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51049 { 7157 /* image_sample_c_cd_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51059 { 7157 /* image_sample_c_cd_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51069 { 7157 /* image_sample_c_cd_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51079 { 7157 /* image_sample_c_cd_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51089 { 7157 /* image_sample_c_cd_cl */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51099 { 7157 /* image_sample_c_cd_cl */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51109 { 7157 /* image_sample_c_cd_cl */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51119 { 7157 /* image_sample_c_cd_cl */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51129 { 7157 /* image_sample_c_cd_cl */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51139 { 7157 /* image_sample_c_cd_cl */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51149 { 7157 /* image_sample_c_cd_cl */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51159 { 7157 /* image_sample_c_cd_cl */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51169 { 7157 /* image_sample_c_cd_cl */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51179 { 7157 /* image_sample_c_cd_cl */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51189 { 7157 /* image_sample_c_cd_cl */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51199 { 7157 /* image_sample_c_cd_cl */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51209 { 7157 /* image_sample_c_cd_cl */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51219 { 7157 /* image_sample_c_cd_cl */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51229 { 7157 /* image_sample_c_cd_cl */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51239 { 7157 /* image_sample_c_cd_cl */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51249 { 7157 /* image_sample_c_cd_cl */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51259 { 7157 /* image_sample_c_cd_cl */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51269 { 7157 /* image_sample_c_cd_cl */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51279 { 7157 /* image_sample_c_cd_cl */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51288 { 7178 /* image_sample_c_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51297 { 7178 /* image_sample_c_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51306 { 7178 /* image_sample_c_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51315 { 7178 /* image_sample_c_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51324 { 7178 /* image_sample_c_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51333 { 7178 /* image_sample_c_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51342 { 7178 /* image_sample_c_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51351 { 7178 /* image_sample_c_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51360 { 7178 /* image_sample_c_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51369 { 7178 /* image_sample_c_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51378 { 7178 /* image_sample_c_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51387 { 7178 /* image_sample_c_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51396 { 7178 /* image_sample_c_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51405 { 7178 /* image_sample_c_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51414 { 7178 /* image_sample_c_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51424 { 7178 /* image_sample_c_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51434 { 7178 /* image_sample_c_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51444 { 7178 /* image_sample_c_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51454 { 7178 /* image_sample_c_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51464 { 7178 /* image_sample_c_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51474 { 7178 /* image_sample_c_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51484 { 7178 /* image_sample_c_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51494 { 7178 /* image_sample_c_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51504 { 7178 /* image_sample_c_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51514 { 7178 /* image_sample_c_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51524 { 7178 /* image_sample_c_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51534 { 7178 /* image_sample_c_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51544 { 7178 /* image_sample_c_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51554 { 7178 /* image_sample_c_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51564 { 7178 /* image_sample_c_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51574 { 7178 /* image_sample_c_cd_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51584 { 7178 /* image_sample_c_cd_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51594 { 7178 /* image_sample_c_cd_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51604 { 7178 /* image_sample_c_cd_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51614 { 7178 /* image_sample_c_cd_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51624 { 7178 /* image_sample_c_cd_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51634 { 7178 /* image_sample_c_cd_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51644 { 7178 /* image_sample_c_cd_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51654 { 7178 /* image_sample_c_cd_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51664 { 7178 /* image_sample_c_cd_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51674 { 7178 /* image_sample_c_cd_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51684 { 7178 /* image_sample_c_cd_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51694 { 7178 /* image_sample_c_cd_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51704 { 7178 /* image_sample_c_cd_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51714 { 7178 /* image_sample_c_cd_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51724 { 7178 /* image_sample_c_cd_cl_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51734 { 7178 /* image_sample_c_cd_cl_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51744 { 7178 /* image_sample_c_cd_cl_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51754 { 7178 /* image_sample_c_cd_cl_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51764 { 7178 /* image_sample_c_cd_cl_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51774 { 7178 /* image_sample_c_cd_cl_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51784 { 7178 /* image_sample_c_cd_cl_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51794 { 7178 /* image_sample_c_cd_cl_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51804 { 7178 /* image_sample_c_cd_cl_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51814 { 7178 /* image_sample_c_cd_cl_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51824 { 7178 /* image_sample_c_cd_cl_o */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51834 { 7178 /* image_sample_c_cd_cl_o */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51844 { 7178 /* image_sample_c_cd_cl_o */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51854 { 7178 /* image_sample_c_cd_cl_o */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51864 { 7178 /* image_sample_c_cd_cl_o */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51874 { 7178 /* image_sample_c_cd_cl_o */, 2097152 /* 21 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51884 { 7178 /* image_sample_c_cd_cl_o */, 2097152 /* 21 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51894 { 7178 /* image_sample_c_cd_cl_o */, 2097152 /* 21 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51904 { 7178 /* image_sample_c_cd_cl_o */, 2097152 /* 21 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51914 { 7178 /* image_sample_c_cd_cl_o */, 2097152 /* 21 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
51923 { 7201 /* image_sample_c_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51932 { 7201 /* image_sample_c_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51941 { 7201 /* image_sample_c_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51950 { 7201 /* image_sample_c_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51959 { 7201 /* image_sample_c_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51968 { 7201 /* image_sample_c_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51977 { 7201 /* image_sample_c_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51986 { 7201 /* image_sample_c_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
51995 { 7201 /* image_sample_c_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52004 { 7201 /* image_sample_c_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52013 { 7201 /* image_sample_c_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52022 { 7201 /* image_sample_c_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52031 { 7201 /* image_sample_c_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52040 { 7201 /* image_sample_c_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52049 { 7201 /* image_sample_c_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52059 { 7201 /* image_sample_c_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52069 { 7201 /* image_sample_c_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52079 { 7201 /* image_sample_c_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52089 { 7201 /* image_sample_c_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52099 { 7201 /* image_sample_c_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52109 { 7201 /* image_sample_c_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52119 { 7201 /* image_sample_c_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52129 { 7201 /* image_sample_c_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52139 { 7201 /* image_sample_c_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52149 { 7201 /* image_sample_c_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52159 { 7201 /* image_sample_c_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52169 { 7201 /* image_sample_c_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52179 { 7201 /* image_sample_c_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52189 { 7201 /* image_sample_c_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52199 { 7201 /* image_sample_c_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52209 { 7201 /* image_sample_c_cd_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52219 { 7201 /* image_sample_c_cd_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52229 { 7201 /* image_sample_c_cd_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52239 { 7201 /* image_sample_c_cd_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52249 { 7201 /* image_sample_c_cd_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52259 { 7201 /* image_sample_c_cd_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52269 { 7201 /* image_sample_c_cd_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52279 { 7201 /* image_sample_c_cd_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52289 { 7201 /* image_sample_c_cd_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52299 { 7201 /* image_sample_c_cd_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52309 { 7201 /* image_sample_c_cd_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52319 { 7201 /* image_sample_c_cd_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52329 { 7201 /* image_sample_c_cd_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52339 { 7201 /* image_sample_c_cd_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52349 { 7201 /* image_sample_c_cd_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52359 { 7201 /* image_sample_c_cd_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52369 { 7201 /* image_sample_c_cd_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52379 { 7201 /* image_sample_c_cd_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52389 { 7201 /* image_sample_c_cd_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52399 { 7201 /* image_sample_c_cd_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52409 { 7201 /* image_sample_c_cd_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52419 { 7201 /* image_sample_c_cd_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52429 { 7201 /* image_sample_c_cd_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52439 { 7201 /* image_sample_c_cd_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52449 { 7201 /* image_sample_c_cd_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52459 { 7201 /* image_sample_c_cd_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52469 { 7201 /* image_sample_c_cd_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52479 { 7201 /* image_sample_c_cd_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52489 { 7201 /* image_sample_c_cd_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52499 { 7201 /* image_sample_c_cd_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52509 { 7201 /* image_sample_c_cd_o */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52519 { 7201 /* image_sample_c_cd_o */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52529 { 7201 /* image_sample_c_cd_o */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52539 { 7201 /* image_sample_c_cd_o */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52549 { 7201 /* image_sample_c_cd_o */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52558 { 7221 /* image_sample_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52567 { 7221 /* image_sample_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52576 { 7221 /* image_sample_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52585 { 7221 /* image_sample_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52594 { 7221 /* image_sample_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52603 { 7221 /* image_sample_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52612 { 7221 /* image_sample_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52621 { 7221 /* image_sample_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52630 { 7221 /* image_sample_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52639 { 7221 /* image_sample_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52648 { 7221 /* image_sample_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52657 { 7221 /* image_sample_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52666 { 7221 /* image_sample_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52675 { 7221 /* image_sample_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52684 { 7221 /* image_sample_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52693 { 7221 /* image_sample_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52702 { 7221 /* image_sample_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52711 { 7221 /* image_sample_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52720 { 7221 /* image_sample_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52729 { 7221 /* image_sample_c_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
52739 { 7221 /* image_sample_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52749 { 7221 /* image_sample_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52759 { 7221 /* image_sample_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52769 { 7221 /* image_sample_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52779 { 7221 /* image_sample_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52789 { 7221 /* image_sample_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52799 { 7221 /* image_sample_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52809 { 7221 /* image_sample_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52819 { 7221 /* image_sample_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52829 { 7221 /* image_sample_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52839 { 7221 /* image_sample_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52849 { 7221 /* image_sample_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52859 { 7221 /* image_sample_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52869 { 7221 /* image_sample_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52879 { 7221 /* image_sample_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52889 { 7221 /* image_sample_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52899 { 7221 /* image_sample_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52909 { 7221 /* image_sample_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52919 { 7221 /* image_sample_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52929 { 7221 /* image_sample_c_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52939 { 7221 /* image_sample_c_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52949 { 7221 /* image_sample_c_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52959 { 7221 /* image_sample_c_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52969 { 7221 /* image_sample_c_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52979 { 7221 /* image_sample_c_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52989 { 7221 /* image_sample_c_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
52999 { 7221 /* image_sample_c_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53009 { 7221 /* image_sample_c_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53019 { 7221 /* image_sample_c_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53029 { 7221 /* image_sample_c_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53039 { 7221 /* image_sample_c_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53049 { 7221 /* image_sample_c_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53059 { 7221 /* image_sample_c_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53069 { 7221 /* image_sample_c_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53079 { 7221 /* image_sample_c_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53089 { 7221 /* image_sample_c_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53099 { 7221 /* image_sample_c_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53109 { 7221 /* image_sample_c_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53119 { 7221 /* image_sample_c_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53129 { 7221 /* image_sample_c_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53138 { 7239 /* image_sample_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53147 { 7239 /* image_sample_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53156 { 7239 /* image_sample_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53165 { 7239 /* image_sample_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53174 { 7239 /* image_sample_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53183 { 7239 /* image_sample_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53192 { 7239 /* image_sample_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53201 { 7239 /* image_sample_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53210 { 7239 /* image_sample_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53219 { 7239 /* image_sample_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53228 { 7239 /* image_sample_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53237 { 7239 /* image_sample_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53246 { 7239 /* image_sample_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53255 { 7239 /* image_sample_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53264 { 7239 /* image_sample_c_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53274 { 7239 /* image_sample_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53284 { 7239 /* image_sample_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53294 { 7239 /* image_sample_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53304 { 7239 /* image_sample_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53314 { 7239 /* image_sample_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53324 { 7239 /* image_sample_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53334 { 7239 /* image_sample_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53344 { 7239 /* image_sample_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53354 { 7239 /* image_sample_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53364 { 7239 /* image_sample_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53374 { 7239 /* image_sample_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53384 { 7239 /* image_sample_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53394 { 7239 /* image_sample_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53404 { 7239 /* image_sample_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53414 { 7239 /* image_sample_c_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53424 { 7239 /* image_sample_c_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53434 { 7239 /* image_sample_c_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53444 { 7239 /* image_sample_c_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53454 { 7239 /* image_sample_c_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53464 { 7239 /* image_sample_c_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53474 { 7239 /* image_sample_c_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53484 { 7239 /* image_sample_c_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53494 { 7239 /* image_sample_c_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53504 { 7239 /* image_sample_c_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53514 { 7239 /* image_sample_c_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53524 { 7239 /* image_sample_c_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53534 { 7239 /* image_sample_c_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53544 { 7239 /* image_sample_c_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53554 { 7239 /* image_sample_c_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53564 { 7239 /* image_sample_c_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53574 { 7239 /* image_sample_c_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53584 { 7239 /* image_sample_c_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53594 { 7239 /* image_sample_c_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53604 { 7239 /* image_sample_c_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53614 { 7239 /* image_sample_c_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53623 { 7259 /* image_sample_c_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53632 { 7259 /* image_sample_c_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53641 { 7259 /* image_sample_c_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53650 { 7259 /* image_sample_c_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53659 { 7259 /* image_sample_c_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53668 { 7259 /* image_sample_c_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53677 { 7259 /* image_sample_c_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53686 { 7259 /* image_sample_c_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53695 { 7259 /* image_sample_c_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53704 { 7259 /* image_sample_c_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53713 { 7259 /* image_sample_c_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53722 { 7259 /* image_sample_c_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53731 { 7259 /* image_sample_c_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53740 { 7259 /* image_sample_c_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53749 { 7259 /* image_sample_c_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53758 { 7259 /* image_sample_c_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53767 { 7259 /* image_sample_c_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53776 { 7259 /* image_sample_c_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53785 { 7259 /* image_sample_c_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53794 { 7259 /* image_sample_c_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
53804 { 7259 /* image_sample_c_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53814 { 7259 /* image_sample_c_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53824 { 7259 /* image_sample_c_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53834 { 7259 /* image_sample_c_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53844 { 7259 /* image_sample_c_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53854 { 7259 /* image_sample_c_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53864 { 7259 /* image_sample_c_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53874 { 7259 /* image_sample_c_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53884 { 7259 /* image_sample_c_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53894 { 7259 /* image_sample_c_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53904 { 7259 /* image_sample_c_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53914 { 7259 /* image_sample_c_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53924 { 7259 /* image_sample_c_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53934 { 7259 /* image_sample_c_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53944 { 7259 /* image_sample_c_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53954 { 7259 /* image_sample_c_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53964 { 7259 /* image_sample_c_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53974 { 7259 /* image_sample_c_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53984 { 7259 /* image_sample_c_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
53994 { 7259 /* image_sample_c_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54004 { 7259 /* image_sample_c_d */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54014 { 7259 /* image_sample_c_d */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54024 { 7259 /* image_sample_c_d */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54034 { 7259 /* image_sample_c_d */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54044 { 7259 /* image_sample_c_d */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54054 { 7259 /* image_sample_c_d */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54064 { 7259 /* image_sample_c_d */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54074 { 7259 /* image_sample_c_d */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54084 { 7259 /* image_sample_c_d */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54094 { 7259 /* image_sample_c_d */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54104 { 7259 /* image_sample_c_d */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54114 { 7259 /* image_sample_c_d */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54124 { 7259 /* image_sample_c_d */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54134 { 7259 /* image_sample_c_d */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54144 { 7259 /* image_sample_c_d */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54154 { 7259 /* image_sample_c_d */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54164 { 7259 /* image_sample_c_d */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54174 { 7259 /* image_sample_c_d */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54184 { 7259 /* image_sample_c_d */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54194 { 7259 /* image_sample_c_d */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54204 { 7259 /* image_sample_c_d */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54214 { 7259 /* image_sample_c_d */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54224 { 7259 /* image_sample_c_d */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54234 { 7259 /* image_sample_c_d */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54244 { 7259 /* image_sample_c_d */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54254 { 7259 /* image_sample_c_d */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54264 { 7259 /* image_sample_c_d */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54274 { 7259 /* image_sample_c_d */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54284 { 7259 /* image_sample_c_d */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54294 { 7259 /* image_sample_c_d */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54304 { 7259 /* image_sample_c_d */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54314 { 7259 /* image_sample_c_d */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54324 { 7259 /* image_sample_c_d */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54334 { 7259 /* image_sample_c_d */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54344 { 7259 /* image_sample_c_d */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54353 { 7276 /* image_sample_c_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54362 { 7276 /* image_sample_c_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54371 { 7276 /* image_sample_c_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54380 { 7276 /* image_sample_c_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54389 { 7276 /* image_sample_c_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54398 { 7276 /* image_sample_c_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54407 { 7276 /* image_sample_c_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54416 { 7276 /* image_sample_c_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54425 { 7276 /* image_sample_c_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54434 { 7276 /* image_sample_c_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54443 { 7276 /* image_sample_c_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54452 { 7276 /* image_sample_c_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54461 { 7276 /* image_sample_c_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54470 { 7276 /* image_sample_c_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54479 { 7276 /* image_sample_c_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54488 { 7276 /* image_sample_c_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54497 { 7276 /* image_sample_c_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54506 { 7276 /* image_sample_c_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54515 { 7276 /* image_sample_c_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54524 { 7276 /* image_sample_c_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
54534 { 7276 /* image_sample_c_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54544 { 7276 /* image_sample_c_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54554 { 7276 /* image_sample_c_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54564 { 7276 /* image_sample_c_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54574 { 7276 /* image_sample_c_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54584 { 7276 /* image_sample_c_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54594 { 7276 /* image_sample_c_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54604 { 7276 /* image_sample_c_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54614 { 7276 /* image_sample_c_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54624 { 7276 /* image_sample_c_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54634 { 7276 /* image_sample_c_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54644 { 7276 /* image_sample_c_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54654 { 7276 /* image_sample_c_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54664 { 7276 /* image_sample_c_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54674 { 7276 /* image_sample_c_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54684 { 7276 /* image_sample_c_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54694 { 7276 /* image_sample_c_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54704 { 7276 /* image_sample_c_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54714 { 7276 /* image_sample_c_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54724 { 7276 /* image_sample_c_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54734 { 7276 /* image_sample_c_d_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54744 { 7276 /* image_sample_c_d_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54754 { 7276 /* image_sample_c_d_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54764 { 7276 /* image_sample_c_d_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54774 { 7276 /* image_sample_c_d_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54784 { 7276 /* image_sample_c_d_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54794 { 7276 /* image_sample_c_d_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54804 { 7276 /* image_sample_c_d_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54814 { 7276 /* image_sample_c_d_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54824 { 7276 /* image_sample_c_d_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54834 { 7276 /* image_sample_c_d_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54844 { 7276 /* image_sample_c_d_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54854 { 7276 /* image_sample_c_d_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54864 { 7276 /* image_sample_c_d_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54874 { 7276 /* image_sample_c_d_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54884 { 7276 /* image_sample_c_d_cl */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54894 { 7276 /* image_sample_c_d_cl */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54904 { 7276 /* image_sample_c_d_cl */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54914 { 7276 /* image_sample_c_d_cl */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54924 { 7276 /* image_sample_c_d_cl */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54934 { 7276 /* image_sample_c_d_cl */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54944 { 7276 /* image_sample_c_d_cl */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54954 { 7276 /* image_sample_c_d_cl */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54964 { 7276 /* image_sample_c_d_cl */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54974 { 7276 /* image_sample_c_d_cl */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54984 { 7276 /* image_sample_c_d_cl */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
54994 { 7276 /* image_sample_c_d_cl */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55004 { 7276 /* image_sample_c_d_cl */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55014 { 7276 /* image_sample_c_d_cl */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55024 { 7276 /* image_sample_c_d_cl */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55034 { 7276 /* image_sample_c_d_cl */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55044 { 7276 /* image_sample_c_d_cl */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55054 { 7276 /* image_sample_c_d_cl */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55064 { 7276 /* image_sample_c_d_cl */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55074 { 7276 /* image_sample_c_d_cl */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55083 { 7296 /* image_sample_c_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55092 { 7296 /* image_sample_c_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55101 { 7296 /* image_sample_c_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55110 { 7296 /* image_sample_c_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55119 { 7296 /* image_sample_c_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55128 { 7296 /* image_sample_c_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55137 { 7296 /* image_sample_c_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55146 { 7296 /* image_sample_c_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55155 { 7296 /* image_sample_c_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55164 { 7296 /* image_sample_c_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55173 { 7296 /* image_sample_c_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55182 { 7296 /* image_sample_c_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55191 { 7296 /* image_sample_c_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55200 { 7296 /* image_sample_c_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55209 { 7296 /* image_sample_c_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55219 { 7296 /* image_sample_c_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55229 { 7296 /* image_sample_c_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55239 { 7296 /* image_sample_c_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55249 { 7296 /* image_sample_c_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55259 { 7296 /* image_sample_c_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55269 { 7296 /* image_sample_c_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55279 { 7296 /* image_sample_c_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55289 { 7296 /* image_sample_c_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55299 { 7296 /* image_sample_c_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55309 { 7296 /* image_sample_c_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55319 { 7296 /* image_sample_c_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55329 { 7296 /* image_sample_c_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55339 { 7296 /* image_sample_c_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55349 { 7296 /* image_sample_c_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55359 { 7296 /* image_sample_c_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55369 { 7296 /* image_sample_c_d_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55379 { 7296 /* image_sample_c_d_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55389 { 7296 /* image_sample_c_d_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55399 { 7296 /* image_sample_c_d_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55409 { 7296 /* image_sample_c_d_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55419 { 7296 /* image_sample_c_d_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55429 { 7296 /* image_sample_c_d_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55439 { 7296 /* image_sample_c_d_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55449 { 7296 /* image_sample_c_d_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55459 { 7296 /* image_sample_c_d_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55469 { 7296 /* image_sample_c_d_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55479 { 7296 /* image_sample_c_d_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55489 { 7296 /* image_sample_c_d_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55499 { 7296 /* image_sample_c_d_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55509 { 7296 /* image_sample_c_d_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55519 { 7296 /* image_sample_c_d_cl_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55529 { 7296 /* image_sample_c_d_cl_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55539 { 7296 /* image_sample_c_d_cl_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55549 { 7296 /* image_sample_c_d_cl_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55559 { 7296 /* image_sample_c_d_cl_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55569 { 7296 /* image_sample_c_d_cl_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55579 { 7296 /* image_sample_c_d_cl_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55589 { 7296 /* image_sample_c_d_cl_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55599 { 7296 /* image_sample_c_d_cl_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55609 { 7296 /* image_sample_c_d_cl_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55619 { 7296 /* image_sample_c_d_cl_o */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55629 { 7296 /* image_sample_c_d_cl_o */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55639 { 7296 /* image_sample_c_d_cl_o */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55649 { 7296 /* image_sample_c_d_cl_o */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55659 { 7296 /* image_sample_c_d_cl_o */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55669 { 7296 /* image_sample_c_d_cl_o */, 2097152 /* 21 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55679 { 7296 /* image_sample_c_d_cl_o */, 2097152 /* 21 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55689 { 7296 /* image_sample_c_d_cl_o */, 2097152 /* 21 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55699 { 7296 /* image_sample_c_d_cl_o */, 2097152 /* 21 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55709 { 7296 /* image_sample_c_d_cl_o */, 2097152 /* 21 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55718 { 7318 /* image_sample_c_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55727 { 7318 /* image_sample_c_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55736 { 7318 /* image_sample_c_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55745 { 7318 /* image_sample_c_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55754 { 7318 /* image_sample_c_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55763 { 7318 /* image_sample_c_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55772 { 7318 /* image_sample_c_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55781 { 7318 /* image_sample_c_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55790 { 7318 /* image_sample_c_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55799 { 7318 /* image_sample_c_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55808 { 7318 /* image_sample_c_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55817 { 7318 /* image_sample_c_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55826 { 7318 /* image_sample_c_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55835 { 7318 /* image_sample_c_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55844 { 7318 /* image_sample_c_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
55854 { 7318 /* image_sample_c_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55864 { 7318 /* image_sample_c_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55874 { 7318 /* image_sample_c_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55884 { 7318 /* image_sample_c_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55894 { 7318 /* image_sample_c_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55904 { 7318 /* image_sample_c_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55914 { 7318 /* image_sample_c_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55924 { 7318 /* image_sample_c_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55934 { 7318 /* image_sample_c_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55944 { 7318 /* image_sample_c_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55954 { 7318 /* image_sample_c_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55964 { 7318 /* image_sample_c_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55974 { 7318 /* image_sample_c_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55984 { 7318 /* image_sample_c_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
55994 { 7318 /* image_sample_c_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56004 { 7318 /* image_sample_c_d_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56014 { 7318 /* image_sample_c_d_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56024 { 7318 /* image_sample_c_d_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56034 { 7318 /* image_sample_c_d_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56044 { 7318 /* image_sample_c_d_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56054 { 7318 /* image_sample_c_d_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56064 { 7318 /* image_sample_c_d_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56074 { 7318 /* image_sample_c_d_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56084 { 7318 /* image_sample_c_d_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56094 { 7318 /* image_sample_c_d_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56104 { 7318 /* image_sample_c_d_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56114 { 7318 /* image_sample_c_d_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56124 { 7318 /* image_sample_c_d_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56134 { 7318 /* image_sample_c_d_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56144 { 7318 /* image_sample_c_d_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56154 { 7318 /* image_sample_c_d_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56164 { 7318 /* image_sample_c_d_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56174 { 7318 /* image_sample_c_d_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56184 { 7318 /* image_sample_c_d_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56194 { 7318 /* image_sample_c_d_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56204 { 7318 /* image_sample_c_d_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56214 { 7318 /* image_sample_c_d_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56224 { 7318 /* image_sample_c_d_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56234 { 7318 /* image_sample_c_d_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56244 { 7318 /* image_sample_c_d_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56254 { 7318 /* image_sample_c_d_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56264 { 7318 /* image_sample_c_d_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56274 { 7318 /* image_sample_c_d_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56284 { 7318 /* image_sample_c_d_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56294 { 7318 /* image_sample_c_d_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56304 { 7318 /* image_sample_c_d_o */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56314 { 7318 /* image_sample_c_d_o */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56324 { 7318 /* image_sample_c_d_o */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56334 { 7318 /* image_sample_c_d_o */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56344 { 7318 /* image_sample_c_d_o */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56353 { 7337 /* image_sample_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56362 { 7337 /* image_sample_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56371 { 7337 /* image_sample_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56380 { 7337 /* image_sample_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56389 { 7337 /* image_sample_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56398 { 7337 /* image_sample_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56407 { 7337 /* image_sample_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56416 { 7337 /* image_sample_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56425 { 7337 /* image_sample_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56434 { 7337 /* image_sample_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56443 { 7337 /* image_sample_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56452 { 7337 /* image_sample_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56461 { 7337 /* image_sample_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56470 { 7337 /* image_sample_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56479 { 7337 /* image_sample_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56488 { 7337 /* image_sample_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56497 { 7337 /* image_sample_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56506 { 7337 /* image_sample_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56515 { 7337 /* image_sample_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56524 { 7337 /* image_sample_c_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56534 { 7337 /* image_sample_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56544 { 7337 /* image_sample_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56554 { 7337 /* image_sample_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56564 { 7337 /* image_sample_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56574 { 7337 /* image_sample_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56584 { 7337 /* image_sample_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56594 { 7337 /* image_sample_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56604 { 7337 /* image_sample_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56614 { 7337 /* image_sample_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56624 { 7337 /* image_sample_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56634 { 7337 /* image_sample_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56644 { 7337 /* image_sample_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56654 { 7337 /* image_sample_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56664 { 7337 /* image_sample_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56674 { 7337 /* image_sample_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56684 { 7337 /* image_sample_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56694 { 7337 /* image_sample_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56704 { 7337 /* image_sample_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56714 { 7337 /* image_sample_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56724 { 7337 /* image_sample_c_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56734 { 7337 /* image_sample_c_l */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56744 { 7337 /* image_sample_c_l */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56754 { 7337 /* image_sample_c_l */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56764 { 7337 /* image_sample_c_l */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56774 { 7337 /* image_sample_c_l */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56784 { 7337 /* image_sample_c_l */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56794 { 7337 /* image_sample_c_l */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56804 { 7337 /* image_sample_c_l */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56814 { 7337 /* image_sample_c_l */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56824 { 7337 /* image_sample_c_l */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56834 { 7337 /* image_sample_c_l */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56844 { 7337 /* image_sample_c_l */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56854 { 7337 /* image_sample_c_l */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56864 { 7337 /* image_sample_c_l */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56874 { 7337 /* image_sample_c_l */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56884 { 7337 /* image_sample_c_l */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56894 { 7337 /* image_sample_c_l */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56904 { 7337 /* image_sample_c_l */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56914 { 7337 /* image_sample_c_l */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56924 { 7337 /* image_sample_c_l */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
56933 { 7354 /* image_sample_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56942 { 7354 /* image_sample_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56951 { 7354 /* image_sample_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56960 { 7354 /* image_sample_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56969 { 7354 /* image_sample_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56978 { 7354 /* image_sample_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56987 { 7354 /* image_sample_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
56996 { 7354 /* image_sample_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57005 { 7354 /* image_sample_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57014 { 7354 /* image_sample_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57023 { 7354 /* image_sample_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57032 { 7354 /* image_sample_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57041 { 7354 /* image_sample_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57050 { 7354 /* image_sample_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57059 { 7354 /* image_sample_c_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57069 { 7354 /* image_sample_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57079 { 7354 /* image_sample_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57089 { 7354 /* image_sample_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57099 { 7354 /* image_sample_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57109 { 7354 /* image_sample_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57119 { 7354 /* image_sample_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57129 { 7354 /* image_sample_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57139 { 7354 /* image_sample_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57149 { 7354 /* image_sample_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57159 { 7354 /* image_sample_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57169 { 7354 /* image_sample_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57179 { 7354 /* image_sample_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57189 { 7354 /* image_sample_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57199 { 7354 /* image_sample_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57209 { 7354 /* image_sample_c_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57219 { 7354 /* image_sample_c_l_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57229 { 7354 /* image_sample_c_l_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57239 { 7354 /* image_sample_c_l_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57249 { 7354 /* image_sample_c_l_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57259 { 7354 /* image_sample_c_l_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57269 { 7354 /* image_sample_c_l_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57279 { 7354 /* image_sample_c_l_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57289 { 7354 /* image_sample_c_l_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57299 { 7354 /* image_sample_c_l_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57309 { 7354 /* image_sample_c_l_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57319 { 7354 /* image_sample_c_l_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57329 { 7354 /* image_sample_c_l_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57339 { 7354 /* image_sample_c_l_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57349 { 7354 /* image_sample_c_l_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57359 { 7354 /* image_sample_c_l_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57369 { 7354 /* image_sample_c_l_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57379 { 7354 /* image_sample_c_l_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57389 { 7354 /* image_sample_c_l_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57399 { 7354 /* image_sample_c_l_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57409 { 7354 /* image_sample_c_l_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57418 { 7373 /* image_sample_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57427 { 7373 /* image_sample_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57436 { 7373 /* image_sample_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57445 { 7373 /* image_sample_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57454 { 7373 /* image_sample_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57463 { 7373 /* image_sample_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57472 { 7373 /* image_sample_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57481 { 7373 /* image_sample_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57490 { 7373 /* image_sample_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57499 { 7373 /* image_sample_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57508 { 7373 /* image_sample_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57517 { 7373 /* image_sample_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57526 { 7373 /* image_sample_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57535 { 7373 /* image_sample_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57544 { 7373 /* image_sample_c_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57554 { 7373 /* image_sample_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57564 { 7373 /* image_sample_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57574 { 7373 /* image_sample_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57584 { 7373 /* image_sample_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57594 { 7373 /* image_sample_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57604 { 7373 /* image_sample_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57614 { 7373 /* image_sample_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57624 { 7373 /* image_sample_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57634 { 7373 /* image_sample_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57644 { 7373 /* image_sample_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57654 { 7373 /* image_sample_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57664 { 7373 /* image_sample_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57674 { 7373 /* image_sample_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57684 { 7373 /* image_sample_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57694 { 7373 /* image_sample_c_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57704 { 7373 /* image_sample_c_lz */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57714 { 7373 /* image_sample_c_lz */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57724 { 7373 /* image_sample_c_lz */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57734 { 7373 /* image_sample_c_lz */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57744 { 7373 /* image_sample_c_lz */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57754 { 7373 /* image_sample_c_lz */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57764 { 7373 /* image_sample_c_lz */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57774 { 7373 /* image_sample_c_lz */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57784 { 7373 /* image_sample_c_lz */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57794 { 7373 /* image_sample_c_lz */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57804 { 7373 /* image_sample_c_lz */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57814 { 7373 /* image_sample_c_lz */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57824 { 7373 /* image_sample_c_lz */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57834 { 7373 /* image_sample_c_lz */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57844 { 7373 /* image_sample_c_lz */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57853 { 7391 /* image_sample_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57862 { 7391 /* image_sample_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57871 { 7391 /* image_sample_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57880 { 7391 /* image_sample_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57889 { 7391 /* image_sample_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57898 { 7391 /* image_sample_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57907 { 7391 /* image_sample_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57916 { 7391 /* image_sample_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57925 { 7391 /* image_sample_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57934 { 7391 /* image_sample_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57943 { 7391 /* image_sample_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57952 { 7391 /* image_sample_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57961 { 7391 /* image_sample_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57970 { 7391 /* image_sample_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57979 { 7391 /* image_sample_c_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
57989 { 7391 /* image_sample_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
57999 { 7391 /* image_sample_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58009 { 7391 /* image_sample_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58019 { 7391 /* image_sample_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58029 { 7391 /* image_sample_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58039 { 7391 /* image_sample_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58049 { 7391 /* image_sample_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58059 { 7391 /* image_sample_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58069 { 7391 /* image_sample_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58079 { 7391 /* image_sample_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58089 { 7391 /* image_sample_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58099 { 7391 /* image_sample_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58109 { 7391 /* image_sample_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58119 { 7391 /* image_sample_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58129 { 7391 /* image_sample_c_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58139 { 7391 /* image_sample_c_lz_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58149 { 7391 /* image_sample_c_lz_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58159 { 7391 /* image_sample_c_lz_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58169 { 7391 /* image_sample_c_lz_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58179 { 7391 /* image_sample_c_lz_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58189 { 7391 /* image_sample_c_lz_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58199 { 7391 /* image_sample_c_lz_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58209 { 7391 /* image_sample_c_lz_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58219 { 7391 /* image_sample_c_lz_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58229 { 7391 /* image_sample_c_lz_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58239 { 7391 /* image_sample_c_lz_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58249 { 7391 /* image_sample_c_lz_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58259 { 7391 /* image_sample_c_lz_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58269 { 7391 /* image_sample_c_lz_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58279 { 7391 /* image_sample_c_lz_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58288 { 7411 /* image_sample_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58297 { 7411 /* image_sample_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58306 { 7411 /* image_sample_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58315 { 7411 /* image_sample_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58324 { 7411 /* image_sample_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58333 { 7411 /* image_sample_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58342 { 7411 /* image_sample_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58351 { 7411 /* image_sample_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58360 { 7411 /* image_sample_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58369 { 7411 /* image_sample_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58378 { 7411 /* image_sample_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58387 { 7411 /* image_sample_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58396 { 7411 /* image_sample_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58405 { 7411 /* image_sample_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58414 { 7411 /* image_sample_c_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58424 { 7411 /* image_sample_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58434 { 7411 /* image_sample_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58444 { 7411 /* image_sample_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58454 { 7411 /* image_sample_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58464 { 7411 /* image_sample_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58474 { 7411 /* image_sample_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58484 { 7411 /* image_sample_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58494 { 7411 /* image_sample_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58504 { 7411 /* image_sample_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58514 { 7411 /* image_sample_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58524 { 7411 /* image_sample_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58534 { 7411 /* image_sample_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58544 { 7411 /* image_sample_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58554 { 7411 /* image_sample_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58564 { 7411 /* image_sample_c_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58574 { 7411 /* image_sample_c_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58584 { 7411 /* image_sample_c_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58594 { 7411 /* image_sample_c_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58604 { 7411 /* image_sample_c_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58614 { 7411 /* image_sample_c_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58624 { 7411 /* image_sample_c_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58634 { 7411 /* image_sample_c_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58644 { 7411 /* image_sample_c_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58654 { 7411 /* image_sample_c_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58664 { 7411 /* image_sample_c_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58674 { 7411 /* image_sample_c_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58684 { 7411 /* image_sample_c_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58694 { 7411 /* image_sample_c_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58704 { 7411 /* image_sample_c_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58714 { 7411 /* image_sample_c_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58723 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58732 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58741 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58750 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58759 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58768 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58777 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58786 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58795 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58804 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58813 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58822 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58831 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58840 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58849 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58858 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58867 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58876 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58885 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58894 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58903 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58912 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58921 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58930 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58939 { 7428 /* image_sample_cd */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
58949 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58959 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58969 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58979 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58989 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
58999 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59009 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59019 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59029 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59039 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59049 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59059 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59069 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59079 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59089 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59099 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59109 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59119 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59129 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59139 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59149 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59159 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59169 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59179 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59189 { 7428 /* image_sample_cd */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59199 { 7428 /* image_sample_cd */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59209 { 7428 /* image_sample_cd */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59219 { 7428 /* image_sample_cd */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59229 { 7428 /* image_sample_cd */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59239 { 7428 /* image_sample_cd */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59249 { 7428 /* image_sample_cd */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59259 { 7428 /* image_sample_cd */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59269 { 7428 /* image_sample_cd */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59279 { 7428 /* image_sample_cd */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59289 { 7428 /* image_sample_cd */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59299 { 7428 /* image_sample_cd */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59309 { 7428 /* image_sample_cd */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59319 { 7428 /* image_sample_cd */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59329 { 7428 /* image_sample_cd */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59339 { 7428 /* image_sample_cd */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59349 { 7428 /* image_sample_cd */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59359 { 7428 /* image_sample_cd */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59369 { 7428 /* image_sample_cd */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59379 { 7428 /* image_sample_cd */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59389 { 7428 /* image_sample_cd */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59399 { 7428 /* image_sample_cd */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59409 { 7428 /* image_sample_cd */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59419 { 7428 /* image_sample_cd */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59429 { 7428 /* image_sample_cd */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59439 { 7428 /* image_sample_cd */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59449 { 7428 /* image_sample_cd */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59459 { 7428 /* image_sample_cd */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59469 { 7428 /* image_sample_cd */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59479 { 7428 /* image_sample_cd */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59489 { 7428 /* image_sample_cd */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59499 { 7428 /* image_sample_cd */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59509 { 7428 /* image_sample_cd */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59519 { 7428 /* image_sample_cd */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59529 { 7428 /* image_sample_cd */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59539 { 7428 /* image_sample_cd */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59548 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59557 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59566 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59575 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59584 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59593 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59602 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59611 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59620 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59629 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59638 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59647 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59656 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59665 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59674 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59683 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59692 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59701 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59710 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59719 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59728 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59737 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59746 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59755 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59764 { 7444 /* image_sample_cd_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
59774 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59784 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59794 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59804 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59814 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59824 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59834 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59844 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59854 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59864 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59874 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59884 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59894 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59904 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59914 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59924 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59934 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59944 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59954 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59964 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59974 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59984 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
59994 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60004 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60014 { 7444 /* image_sample_cd_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60024 { 7444 /* image_sample_cd_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60034 { 7444 /* image_sample_cd_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60044 { 7444 /* image_sample_cd_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60054 { 7444 /* image_sample_cd_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60064 { 7444 /* image_sample_cd_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60074 { 7444 /* image_sample_cd_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60084 { 7444 /* image_sample_cd_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60094 { 7444 /* image_sample_cd_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60104 { 7444 /* image_sample_cd_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60114 { 7444 /* image_sample_cd_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60124 { 7444 /* image_sample_cd_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60134 { 7444 /* image_sample_cd_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60144 { 7444 /* image_sample_cd_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60154 { 7444 /* image_sample_cd_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60164 { 7444 /* image_sample_cd_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60174 { 7444 /* image_sample_cd_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60184 { 7444 /* image_sample_cd_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60194 { 7444 /* image_sample_cd_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60204 { 7444 /* image_sample_cd_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60214 { 7444 /* image_sample_cd_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60224 { 7444 /* image_sample_cd_cl */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60234 { 7444 /* image_sample_cd_cl */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60244 { 7444 /* image_sample_cd_cl */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60254 { 7444 /* image_sample_cd_cl */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60264 { 7444 /* image_sample_cd_cl */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60274 { 7444 /* image_sample_cd_cl */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60284 { 7444 /* image_sample_cd_cl */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60294 { 7444 /* image_sample_cd_cl */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60304 { 7444 /* image_sample_cd_cl */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60314 { 7444 /* image_sample_cd_cl */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60324 { 7444 /* image_sample_cd_cl */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60334 { 7444 /* image_sample_cd_cl */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60344 { 7444 /* image_sample_cd_cl */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60354 { 7444 /* image_sample_cd_cl */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60364 { 7444 /* image_sample_cd_cl */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60373 { 7463 /* image_sample_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60382 { 7463 /* image_sample_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60391 { 7463 /* image_sample_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60400 { 7463 /* image_sample_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60409 { 7463 /* image_sample_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60418 { 7463 /* image_sample_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60427 { 7463 /* image_sample_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60436 { 7463 /* image_sample_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60445 { 7463 /* image_sample_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60454 { 7463 /* image_sample_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60463 { 7463 /* image_sample_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60472 { 7463 /* image_sample_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60481 { 7463 /* image_sample_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60490 { 7463 /* image_sample_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60499 { 7463 /* image_sample_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60508 { 7463 /* image_sample_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60517 { 7463 /* image_sample_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60526 { 7463 /* image_sample_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60535 { 7463 /* image_sample_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60544 { 7463 /* image_sample_cd_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
60554 { 7463 /* image_sample_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60564 { 7463 /* image_sample_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60574 { 7463 /* image_sample_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60584 { 7463 /* image_sample_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60594 { 7463 /* image_sample_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60604 { 7463 /* image_sample_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60614 { 7463 /* image_sample_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60624 { 7463 /* image_sample_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60634 { 7463 /* image_sample_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60644 { 7463 /* image_sample_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60654 { 7463 /* image_sample_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60664 { 7463 /* image_sample_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60674 { 7463 /* image_sample_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60684 { 7463 /* image_sample_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60694 { 7463 /* image_sample_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60704 { 7463 /* image_sample_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60714 { 7463 /* image_sample_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60724 { 7463 /* image_sample_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60734 { 7463 /* image_sample_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60744 { 7463 /* image_sample_cd_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60754 { 7463 /* image_sample_cd_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60764 { 7463 /* image_sample_cd_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60774 { 7463 /* image_sample_cd_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60784 { 7463 /* image_sample_cd_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60794 { 7463 /* image_sample_cd_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60804 { 7463 /* image_sample_cd_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60814 { 7463 /* image_sample_cd_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60824 { 7463 /* image_sample_cd_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60834 { 7463 /* image_sample_cd_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60844 { 7463 /* image_sample_cd_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60854 { 7463 /* image_sample_cd_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60864 { 7463 /* image_sample_cd_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60874 { 7463 /* image_sample_cd_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60884 { 7463 /* image_sample_cd_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60894 { 7463 /* image_sample_cd_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60904 { 7463 /* image_sample_cd_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60914 { 7463 /* image_sample_cd_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60924 { 7463 /* image_sample_cd_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60934 { 7463 /* image_sample_cd_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60944 { 7463 /* image_sample_cd_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60954 { 7463 /* image_sample_cd_cl_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60964 { 7463 /* image_sample_cd_cl_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60974 { 7463 /* image_sample_cd_cl_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60984 { 7463 /* image_sample_cd_cl_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
60994 { 7463 /* image_sample_cd_cl_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61004 { 7463 /* image_sample_cd_cl_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61014 { 7463 /* image_sample_cd_cl_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61024 { 7463 /* image_sample_cd_cl_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61034 { 7463 /* image_sample_cd_cl_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61044 { 7463 /* image_sample_cd_cl_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61054 { 7463 /* image_sample_cd_cl_o */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61064 { 7463 /* image_sample_cd_cl_o */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61074 { 7463 /* image_sample_cd_cl_o */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61084 { 7463 /* image_sample_cd_cl_o */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61094 { 7463 /* image_sample_cd_cl_o */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61103 { 7484 /* image_sample_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61112 { 7484 /* image_sample_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61121 { 7484 /* image_sample_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61130 { 7484 /* image_sample_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61139 { 7484 /* image_sample_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61148 { 7484 /* image_sample_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61157 { 7484 /* image_sample_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61166 { 7484 /* image_sample_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61175 { 7484 /* image_sample_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61184 { 7484 /* image_sample_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61193 { 7484 /* image_sample_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61202 { 7484 /* image_sample_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61211 { 7484 /* image_sample_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61220 { 7484 /* image_sample_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61229 { 7484 /* image_sample_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61238 { 7484 /* image_sample_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61247 { 7484 /* image_sample_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61256 { 7484 /* image_sample_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61265 { 7484 /* image_sample_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61274 { 7484 /* image_sample_cd_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61284 { 7484 /* image_sample_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61294 { 7484 /* image_sample_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61304 { 7484 /* image_sample_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61314 { 7484 /* image_sample_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61324 { 7484 /* image_sample_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61334 { 7484 /* image_sample_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61344 { 7484 /* image_sample_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61354 { 7484 /* image_sample_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61364 { 7484 /* image_sample_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61374 { 7484 /* image_sample_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61384 { 7484 /* image_sample_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61394 { 7484 /* image_sample_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61404 { 7484 /* image_sample_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61414 { 7484 /* image_sample_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61424 { 7484 /* image_sample_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61434 { 7484 /* image_sample_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61444 { 7484 /* image_sample_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61454 { 7484 /* image_sample_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61464 { 7484 /* image_sample_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61474 { 7484 /* image_sample_cd_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61484 { 7484 /* image_sample_cd_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61494 { 7484 /* image_sample_cd_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61504 { 7484 /* image_sample_cd_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61514 { 7484 /* image_sample_cd_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61524 { 7484 /* image_sample_cd_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61534 { 7484 /* image_sample_cd_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61544 { 7484 /* image_sample_cd_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61554 { 7484 /* image_sample_cd_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61564 { 7484 /* image_sample_cd_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61574 { 7484 /* image_sample_cd_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61584 { 7484 /* image_sample_cd_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61594 { 7484 /* image_sample_cd_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61604 { 7484 /* image_sample_cd_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61614 { 7484 /* image_sample_cd_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61624 { 7484 /* image_sample_cd_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61634 { 7484 /* image_sample_cd_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61644 { 7484 /* image_sample_cd_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61654 { 7484 /* image_sample_cd_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61664 { 7484 /* image_sample_cd_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61674 { 7484 /* image_sample_cd_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61684 { 7484 /* image_sample_cd_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61694 { 7484 /* image_sample_cd_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61704 { 7484 /* image_sample_cd_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61714 { 7484 /* image_sample_cd_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61724 { 7484 /* image_sample_cd_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61734 { 7484 /* image_sample_cd_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61744 { 7484 /* image_sample_cd_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61754 { 7484 /* image_sample_cd_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61764 { 7484 /* image_sample_cd_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61774 { 7484 /* image_sample_cd_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61784 { 7484 /* image_sample_cd_o */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61794 { 7484 /* image_sample_cd_o */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61804 { 7484 /* image_sample_cd_o */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61814 { 7484 /* image_sample_cd_o */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61824 { 7484 /* image_sample_cd_o */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
61833 { 7502 /* image_sample_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61842 { 7502 /* image_sample_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61851 { 7502 /* image_sample_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61860 { 7502 /* image_sample_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61869 { 7502 /* image_sample_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61878 { 7502 /* image_sample_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61887 { 7502 /* image_sample_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61896 { 7502 /* image_sample_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61905 { 7502 /* image_sample_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61914 { 7502 /* image_sample_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61923 { 7502 /* image_sample_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61932 { 7502 /* image_sample_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61941 { 7502 /* image_sample_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61950 { 7502 /* image_sample_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61959 { 7502 /* image_sample_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61968 { 7502 /* image_sample_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61977 { 7502 /* image_sample_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61986 { 7502 /* image_sample_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
61995 { 7502 /* image_sample_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62004 { 7502 /* image_sample_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62014 { 7502 /* image_sample_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62024 { 7502 /* image_sample_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62034 { 7502 /* image_sample_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62044 { 7502 /* image_sample_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62054 { 7502 /* image_sample_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62064 { 7502 /* image_sample_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62074 { 7502 /* image_sample_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62084 { 7502 /* image_sample_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62094 { 7502 /* image_sample_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62104 { 7502 /* image_sample_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62114 { 7502 /* image_sample_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62124 { 7502 /* image_sample_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62134 { 7502 /* image_sample_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62144 { 7502 /* image_sample_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62154 { 7502 /* image_sample_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62164 { 7502 /* image_sample_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62174 { 7502 /* image_sample_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62184 { 7502 /* image_sample_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62194 { 7502 /* image_sample_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62204 { 7502 /* image_sample_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62214 { 7502 /* image_sample_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62224 { 7502 /* image_sample_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62234 { 7502 /* image_sample_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62244 { 7502 /* image_sample_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62254 { 7502 /* image_sample_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62264 { 7502 /* image_sample_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62274 { 7502 /* image_sample_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62284 { 7502 /* image_sample_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62294 { 7502 /* image_sample_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62304 { 7502 /* image_sample_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62314 { 7502 /* image_sample_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62324 { 7502 /* image_sample_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62334 { 7502 /* image_sample_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62344 { 7502 /* image_sample_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62354 { 7502 /* image_sample_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62363 { 7518 /* image_sample_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62372 { 7518 /* image_sample_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62381 { 7518 /* image_sample_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62390 { 7518 /* image_sample_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62399 { 7518 /* image_sample_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62408 { 7518 /* image_sample_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62417 { 7518 /* image_sample_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62426 { 7518 /* image_sample_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62435 { 7518 /* image_sample_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62444 { 7518 /* image_sample_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62453 { 7518 /* image_sample_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62462 { 7518 /* image_sample_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62471 { 7518 /* image_sample_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62480 { 7518 /* image_sample_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62489 { 7518 /* image_sample_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62498 { 7518 /* image_sample_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62507 { 7518 /* image_sample_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62516 { 7518 /* image_sample_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62525 { 7518 /* image_sample_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62534 { 7518 /* image_sample_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62544 { 7518 /* image_sample_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62554 { 7518 /* image_sample_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62564 { 7518 /* image_sample_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62574 { 7518 /* image_sample_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62584 { 7518 /* image_sample_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62594 { 7518 /* image_sample_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62604 { 7518 /* image_sample_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62614 { 7518 /* image_sample_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62624 { 7518 /* image_sample_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62634 { 7518 /* image_sample_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62644 { 7518 /* image_sample_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62654 { 7518 /* image_sample_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62664 { 7518 /* image_sample_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62674 { 7518 /* image_sample_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62684 { 7518 /* image_sample_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62694 { 7518 /* image_sample_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62704 { 7518 /* image_sample_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62714 { 7518 /* image_sample_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62724 { 7518 /* image_sample_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62734 { 7518 /* image_sample_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62744 { 7518 /* image_sample_cl_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62754 { 7518 /* image_sample_cl_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62764 { 7518 /* image_sample_cl_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62774 { 7518 /* image_sample_cl_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62784 { 7518 /* image_sample_cl_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62794 { 7518 /* image_sample_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62804 { 7518 /* image_sample_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62814 { 7518 /* image_sample_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62824 { 7518 /* image_sample_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62834 { 7518 /* image_sample_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62844 { 7518 /* image_sample_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62854 { 7518 /* image_sample_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62864 { 7518 /* image_sample_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62874 { 7518 /* image_sample_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62884 { 7518 /* image_sample_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62894 { 7518 /* image_sample_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62904 { 7518 /* image_sample_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62914 { 7518 /* image_sample_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62924 { 7518 /* image_sample_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62934 { 7518 /* image_sample_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
62943 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62952 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62961 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62970 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62979 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62988 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
62997 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63006 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63015 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63024 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63033 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63042 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63051 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63060 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63069 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63078 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63087 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63096 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63105 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63114 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63123 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63132 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63141 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63150 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63159 { 7536 /* image_sample_d */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63169 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63179 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63189 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63199 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63209 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63219 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63229 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63239 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63249 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63259 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63269 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63279 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63289 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63299 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63309 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63319 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63329 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63339 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63349 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63359 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63369 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63379 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63389 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63399 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63409 { 7536 /* image_sample_d */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63419 { 7536 /* image_sample_d */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63429 { 7536 /* image_sample_d */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63439 { 7536 /* image_sample_d */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63449 { 7536 /* image_sample_d */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63459 { 7536 /* image_sample_d */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63469 { 7536 /* image_sample_d */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63479 { 7536 /* image_sample_d */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63489 { 7536 /* image_sample_d */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63499 { 7536 /* image_sample_d */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63509 { 7536 /* image_sample_d */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63519 { 7536 /* image_sample_d */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63529 { 7536 /* image_sample_d */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63539 { 7536 /* image_sample_d */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63549 { 7536 /* image_sample_d */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63559 { 7536 /* image_sample_d */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63569 { 7536 /* image_sample_d */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63579 { 7536 /* image_sample_d */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63589 { 7536 /* image_sample_d */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63599 { 7536 /* image_sample_d */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63609 { 7536 /* image_sample_d */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63619 { 7536 /* image_sample_d */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63629 { 7536 /* image_sample_d */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63639 { 7536 /* image_sample_d */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63649 { 7536 /* image_sample_d */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63659 { 7536 /* image_sample_d */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63669 { 7536 /* image_sample_d */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63679 { 7536 /* image_sample_d */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63689 { 7536 /* image_sample_d */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63699 { 7536 /* image_sample_d */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63709 { 7536 /* image_sample_d */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63719 { 7536 /* image_sample_d */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63729 { 7536 /* image_sample_d */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63739 { 7536 /* image_sample_d */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63749 { 7536 /* image_sample_d */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63759 { 7536 /* image_sample_d */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
63768 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63777 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63786 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63795 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63804 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63813 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63822 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63831 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63840 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63849 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63858 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63867 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63876 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63885 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63894 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63903 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63912 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63921 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63930 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63939 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63948 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63957 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63966 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63975 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63984 { 7551 /* image_sample_d_cl */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
63994 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64004 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64014 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64024 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64034 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64044 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64054 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64064 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64074 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64084 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64094 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64104 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64114 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64124 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64134 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64144 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64154 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64164 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64174 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64184 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64194 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64204 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64214 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64224 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64234 { 7551 /* image_sample_d_cl */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64244 { 7551 /* image_sample_d_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64254 { 7551 /* image_sample_d_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64264 { 7551 /* image_sample_d_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64274 { 7551 /* image_sample_d_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64284 { 7551 /* image_sample_d_cl */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64294 { 7551 /* image_sample_d_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64304 { 7551 /* image_sample_d_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64314 { 7551 /* image_sample_d_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64324 { 7551 /* image_sample_d_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64334 { 7551 /* image_sample_d_cl */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64344 { 7551 /* image_sample_d_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64354 { 7551 /* image_sample_d_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64364 { 7551 /* image_sample_d_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64374 { 7551 /* image_sample_d_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64384 { 7551 /* image_sample_d_cl */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64394 { 7551 /* image_sample_d_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64404 { 7551 /* image_sample_d_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64414 { 7551 /* image_sample_d_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64424 { 7551 /* image_sample_d_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64434 { 7551 /* image_sample_d_cl */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64444 { 7551 /* image_sample_d_cl */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64454 { 7551 /* image_sample_d_cl */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64464 { 7551 /* image_sample_d_cl */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64474 { 7551 /* image_sample_d_cl */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64484 { 7551 /* image_sample_d_cl */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64494 { 7551 /* image_sample_d_cl */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64504 { 7551 /* image_sample_d_cl */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64514 { 7551 /* image_sample_d_cl */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64524 { 7551 /* image_sample_d_cl */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64534 { 7551 /* image_sample_d_cl */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64544 { 7551 /* image_sample_d_cl */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64554 { 7551 /* image_sample_d_cl */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64564 { 7551 /* image_sample_d_cl */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64574 { 7551 /* image_sample_d_cl */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64584 { 7551 /* image_sample_d_cl */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64593 { 7569 /* image_sample_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64602 { 7569 /* image_sample_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64611 { 7569 /* image_sample_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64620 { 7569 /* image_sample_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64629 { 7569 /* image_sample_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64638 { 7569 /* image_sample_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64647 { 7569 /* image_sample_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64656 { 7569 /* image_sample_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64665 { 7569 /* image_sample_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64674 { 7569 /* image_sample_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64683 { 7569 /* image_sample_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64692 { 7569 /* image_sample_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64701 { 7569 /* image_sample_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64710 { 7569 /* image_sample_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64719 { 7569 /* image_sample_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64728 { 7569 /* image_sample_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64737 { 7569 /* image_sample_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64746 { 7569 /* image_sample_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64755 { 7569 /* image_sample_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64764 { 7569 /* image_sample_d_cl_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
64774 { 7569 /* image_sample_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64784 { 7569 /* image_sample_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64794 { 7569 /* image_sample_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64804 { 7569 /* image_sample_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64814 { 7569 /* image_sample_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64824 { 7569 /* image_sample_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64834 { 7569 /* image_sample_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64844 { 7569 /* image_sample_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64854 { 7569 /* image_sample_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64864 { 7569 /* image_sample_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64874 { 7569 /* image_sample_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64884 { 7569 /* image_sample_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64894 { 7569 /* image_sample_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64904 { 7569 /* image_sample_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64914 { 7569 /* image_sample_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64924 { 7569 /* image_sample_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64934 { 7569 /* image_sample_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64944 { 7569 /* image_sample_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64954 { 7569 /* image_sample_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64964 { 7569 /* image_sample_d_cl_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64974 { 7569 /* image_sample_d_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64984 { 7569 /* image_sample_d_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
64994 { 7569 /* image_sample_d_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65004 { 7569 /* image_sample_d_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65014 { 7569 /* image_sample_d_cl_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65024 { 7569 /* image_sample_d_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65034 { 7569 /* image_sample_d_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65044 { 7569 /* image_sample_d_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65054 { 7569 /* image_sample_d_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65064 { 7569 /* image_sample_d_cl_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65074 { 7569 /* image_sample_d_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65084 { 7569 /* image_sample_d_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65094 { 7569 /* image_sample_d_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65104 { 7569 /* image_sample_d_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65114 { 7569 /* image_sample_d_cl_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65124 { 7569 /* image_sample_d_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65134 { 7569 /* image_sample_d_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65144 { 7569 /* image_sample_d_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65154 { 7569 /* image_sample_d_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65164 { 7569 /* image_sample_d_cl_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65174 { 7569 /* image_sample_d_cl_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65184 { 7569 /* image_sample_d_cl_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65194 { 7569 /* image_sample_d_cl_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65204 { 7569 /* image_sample_d_cl_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65214 { 7569 /* image_sample_d_cl_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65224 { 7569 /* image_sample_d_cl_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65234 { 7569 /* image_sample_d_cl_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65244 { 7569 /* image_sample_d_cl_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65254 { 7569 /* image_sample_d_cl_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65264 { 7569 /* image_sample_d_cl_o */, 262144 /* 18 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65274 { 7569 /* image_sample_d_cl_o */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65284 { 7569 /* image_sample_d_cl_o */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65294 { 7569 /* image_sample_d_cl_o */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65304 { 7569 /* image_sample_d_cl_o */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65314 { 7569 /* image_sample_d_cl_o */, 1048576 /* 20 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65323 { 7589 /* image_sample_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65332 { 7589 /* image_sample_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65341 { 7589 /* image_sample_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65350 { 7589 /* image_sample_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65359 { 7589 /* image_sample_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65368 { 7589 /* image_sample_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65377 { 7589 /* image_sample_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65386 { 7589 /* image_sample_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65395 { 7589 /* image_sample_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65404 { 7589 /* image_sample_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65413 { 7589 /* image_sample_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65422 { 7589 /* image_sample_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65431 { 7589 /* image_sample_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65440 { 7589 /* image_sample_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65449 { 7589 /* image_sample_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65458 { 7589 /* image_sample_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65467 { 7589 /* image_sample_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65476 { 7589 /* image_sample_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65485 { 7589 /* image_sample_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65494 { 7589 /* image_sample_d_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
65504 { 7589 /* image_sample_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65514 { 7589 /* image_sample_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65524 { 7589 /* image_sample_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65534 { 7589 /* image_sample_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65544 { 7589 /* image_sample_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65554 { 7589 /* image_sample_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65564 { 7589 /* image_sample_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65574 { 7589 /* image_sample_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65584 { 7589 /* image_sample_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65594 { 7589 /* image_sample_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65604 { 7589 /* image_sample_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65614 { 7589 /* image_sample_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65624 { 7589 /* image_sample_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65634 { 7589 /* image_sample_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65644 { 7589 /* image_sample_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65654 { 7589 /* image_sample_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65664 { 7589 /* image_sample_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65674 { 7589 /* image_sample_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65684 { 7589 /* image_sample_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65694 { 7589 /* image_sample_d_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65704 { 7589 /* image_sample_d_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65714 { 7589 /* image_sample_d_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65724 { 7589 /* image_sample_d_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65734 { 7589 /* image_sample_d_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65744 { 7589 /* image_sample_d_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65754 { 7589 /* image_sample_d_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65764 { 7589 /* image_sample_d_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65774 { 7589 /* image_sample_d_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65784 { 7589 /* image_sample_d_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65794 { 7589 /* image_sample_d_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65804 { 7589 /* image_sample_d_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65814 { 7589 /* image_sample_d_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65824 { 7589 /* image_sample_d_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65834 { 7589 /* image_sample_d_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65844 { 7589 /* image_sample_d_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65854 { 7589 /* image_sample_d_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65864 { 7589 /* image_sample_d_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65874 { 7589 /* image_sample_d_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65884 { 7589 /* image_sample_d_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65894 { 7589 /* image_sample_d_o */, 32768 /* 15 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65904 { 7589 /* image_sample_d_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65914 { 7589 /* image_sample_d_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65924 { 7589 /* image_sample_d_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65934 { 7589 /* image_sample_d_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65944 { 7589 /* image_sample_d_o */, 65536 /* 16 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65954 { 7589 /* image_sample_d_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65964 { 7589 /* image_sample_d_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65974 { 7589 /* image_sample_d_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65984 { 7589 /* image_sample_d_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
65994 { 7589 /* image_sample_d_o */, 131072 /* 17 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66004 { 7589 /* image_sample_d_o */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66014 { 7589 /* image_sample_d_o */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66024 { 7589 /* image_sample_d_o */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66034 { 7589 /* image_sample_d_o */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66044 { 7589 /* image_sample_d_o */, 524288 /* 19 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66053 { 7606 /* image_sample_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66062 { 7606 /* image_sample_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66071 { 7606 /* image_sample_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66080 { 7606 /* image_sample_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66089 { 7606 /* image_sample_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66098 { 7606 /* image_sample_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66107 { 7606 /* image_sample_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66116 { 7606 /* image_sample_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66125 { 7606 /* image_sample_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66134 { 7606 /* image_sample_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66143 { 7606 /* image_sample_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66152 { 7606 /* image_sample_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66161 { 7606 /* image_sample_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66170 { 7606 /* image_sample_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66179 { 7606 /* image_sample_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66188 { 7606 /* image_sample_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66197 { 7606 /* image_sample_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66206 { 7606 /* image_sample_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66215 { 7606 /* image_sample_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66224 { 7606 /* image_sample_l */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66234 { 7606 /* image_sample_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66244 { 7606 /* image_sample_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66254 { 7606 /* image_sample_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66264 { 7606 /* image_sample_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66274 { 7606 /* image_sample_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66284 { 7606 /* image_sample_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66294 { 7606 /* image_sample_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66304 { 7606 /* image_sample_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66314 { 7606 /* image_sample_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66324 { 7606 /* image_sample_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66334 { 7606 /* image_sample_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66344 { 7606 /* image_sample_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66354 { 7606 /* image_sample_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66364 { 7606 /* image_sample_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66374 { 7606 /* image_sample_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66384 { 7606 /* image_sample_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66394 { 7606 /* image_sample_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66404 { 7606 /* image_sample_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66414 { 7606 /* image_sample_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66424 { 7606 /* image_sample_l */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66434 { 7606 /* image_sample_l */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66444 { 7606 /* image_sample_l */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66454 { 7606 /* image_sample_l */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66464 { 7606 /* image_sample_l */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66474 { 7606 /* image_sample_l */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66484 { 7606 /* image_sample_l */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66494 { 7606 /* image_sample_l */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66504 { 7606 /* image_sample_l */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66514 { 7606 /* image_sample_l */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66524 { 7606 /* image_sample_l */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66534 { 7606 /* image_sample_l */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66544 { 7606 /* image_sample_l */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66554 { 7606 /* image_sample_l */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66564 { 7606 /* image_sample_l */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66574 { 7606 /* image_sample_l */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66583 { 7621 /* image_sample_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66592 { 7621 /* image_sample_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66601 { 7621 /* image_sample_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66610 { 7621 /* image_sample_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66619 { 7621 /* image_sample_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66628 { 7621 /* image_sample_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66637 { 7621 /* image_sample_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66646 { 7621 /* image_sample_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66655 { 7621 /* image_sample_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66664 { 7621 /* image_sample_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66673 { 7621 /* image_sample_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66682 { 7621 /* image_sample_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66691 { 7621 /* image_sample_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66700 { 7621 /* image_sample_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66709 { 7621 /* image_sample_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66718 { 7621 /* image_sample_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66727 { 7621 /* image_sample_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66736 { 7621 /* image_sample_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66745 { 7621 /* image_sample_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66754 { 7621 /* image_sample_l_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
66764 { 7621 /* image_sample_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66774 { 7621 /* image_sample_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66784 { 7621 /* image_sample_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66794 { 7621 /* image_sample_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66804 { 7621 /* image_sample_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66814 { 7621 /* image_sample_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66824 { 7621 /* image_sample_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66834 { 7621 /* image_sample_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66844 { 7621 /* image_sample_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66854 { 7621 /* image_sample_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66864 { 7621 /* image_sample_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66874 { 7621 /* image_sample_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66884 { 7621 /* image_sample_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66894 { 7621 /* image_sample_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66904 { 7621 /* image_sample_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66914 { 7621 /* image_sample_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66924 { 7621 /* image_sample_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66934 { 7621 /* image_sample_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66944 { 7621 /* image_sample_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66954 { 7621 /* image_sample_l_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66964 { 7621 /* image_sample_l_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66974 { 7621 /* image_sample_l_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66984 { 7621 /* image_sample_l_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
66994 { 7621 /* image_sample_l_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67004 { 7621 /* image_sample_l_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67014 { 7621 /* image_sample_l_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67024 { 7621 /* image_sample_l_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67034 { 7621 /* image_sample_l_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67044 { 7621 /* image_sample_l_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67054 { 7621 /* image_sample_l_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67064 { 7621 /* image_sample_l_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67074 { 7621 /* image_sample_l_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67084 { 7621 /* image_sample_l_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67094 { 7621 /* image_sample_l_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67104 { 7621 /* image_sample_l_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67114 { 7621 /* image_sample_l_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67124 { 7621 /* image_sample_l_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67134 { 7621 /* image_sample_l_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67144 { 7621 /* image_sample_l_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67154 { 7621 /* image_sample_l_o */, 16384 /* 14 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67163 { 7638 /* image_sample_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67172 { 7638 /* image_sample_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67181 { 7638 /* image_sample_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67190 { 7638 /* image_sample_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67199 { 7638 /* image_sample_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67208 { 7638 /* image_sample_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67217 { 7638 /* image_sample_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67226 { 7638 /* image_sample_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67235 { 7638 /* image_sample_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67244 { 7638 /* image_sample_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67253 { 7638 /* image_sample_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67262 { 7638 /* image_sample_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67271 { 7638 /* image_sample_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67280 { 7638 /* image_sample_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67289 { 7638 /* image_sample_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67298 { 7638 /* image_sample_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67307 { 7638 /* image_sample_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67316 { 7638 /* image_sample_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67325 { 7638 /* image_sample_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67334 { 7638 /* image_sample_lz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67344 { 7638 /* image_sample_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67354 { 7638 /* image_sample_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67364 { 7638 /* image_sample_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67374 { 7638 /* image_sample_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67384 { 7638 /* image_sample_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67394 { 7638 /* image_sample_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67404 { 7638 /* image_sample_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67414 { 7638 /* image_sample_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67424 { 7638 /* image_sample_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67434 { 7638 /* image_sample_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67444 { 7638 /* image_sample_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67454 { 7638 /* image_sample_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67464 { 7638 /* image_sample_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67474 { 7638 /* image_sample_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67484 { 7638 /* image_sample_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67494 { 7638 /* image_sample_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67504 { 7638 /* image_sample_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67514 { 7638 /* image_sample_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67524 { 7638 /* image_sample_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67534 { 7638 /* image_sample_lz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67544 { 7638 /* image_sample_lz */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67554 { 7638 /* image_sample_lz */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67564 { 7638 /* image_sample_lz */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67574 { 7638 /* image_sample_lz */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67584 { 7638 /* image_sample_lz */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67594 { 7638 /* image_sample_lz */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67604 { 7638 /* image_sample_lz */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67614 { 7638 /* image_sample_lz */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67624 { 7638 /* image_sample_lz */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67634 { 7638 /* image_sample_lz */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67643 { 7654 /* image_sample_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67652 { 7654 /* image_sample_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67661 { 7654 /* image_sample_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67670 { 7654 /* image_sample_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67679 { 7654 /* image_sample_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67688 { 7654 /* image_sample_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67697 { 7654 /* image_sample_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67706 { 7654 /* image_sample_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67715 { 7654 /* image_sample_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67724 { 7654 /* image_sample_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67733 { 7654 /* image_sample_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67742 { 7654 /* image_sample_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67751 { 7654 /* image_sample_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67760 { 7654 /* image_sample_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67769 { 7654 /* image_sample_lz_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
67779 { 7654 /* image_sample_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67789 { 7654 /* image_sample_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67799 { 7654 /* image_sample_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67809 { 7654 /* image_sample_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67819 { 7654 /* image_sample_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67829 { 7654 /* image_sample_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67839 { 7654 /* image_sample_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67849 { 7654 /* image_sample_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67859 { 7654 /* image_sample_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67869 { 7654 /* image_sample_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67879 { 7654 /* image_sample_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67889 { 7654 /* image_sample_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67899 { 7654 /* image_sample_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67909 { 7654 /* image_sample_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67919 { 7654 /* image_sample_lz_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67929 { 7654 /* image_sample_lz_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67939 { 7654 /* image_sample_lz_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67949 { 7654 /* image_sample_lz_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67959 { 7654 /* image_sample_lz_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67969 { 7654 /* image_sample_lz_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67979 { 7654 /* image_sample_lz_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67989 { 7654 /* image_sample_lz_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
67999 { 7654 /* image_sample_lz_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68009 { 7654 /* image_sample_lz_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68019 { 7654 /* image_sample_lz_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68029 { 7654 /* image_sample_lz_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68039 { 7654 /* image_sample_lz_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68049 { 7654 /* image_sample_lz_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68059 { 7654 /* image_sample_lz_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68069 { 7654 /* image_sample_lz_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68078 { 7672 /* image_sample_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68087 { 7672 /* image_sample_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68096 { 7672 /* image_sample_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68105 { 7672 /* image_sample_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68114 { 7672 /* image_sample_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68123 { 7672 /* image_sample_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68132 { 7672 /* image_sample_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68141 { 7672 /* image_sample_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68150 { 7672 /* image_sample_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68159 { 7672 /* image_sample_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68168 { 7672 /* image_sample_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68177 { 7672 /* image_sample_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68186 { 7672 /* image_sample_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68195 { 7672 /* image_sample_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68204 { 7672 /* image_sample_o */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68214 { 7672 /* image_sample_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68224 { 7672 /* image_sample_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68234 { 7672 /* image_sample_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68244 { 7672 /* image_sample_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68254 { 7672 /* image_sample_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68264 { 7672 /* image_sample_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68274 { 7672 /* image_sample_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68284 { 7672 /* image_sample_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68294 { 7672 /* image_sample_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68304 { 7672 /* image_sample_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68314 { 7672 /* image_sample_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68324 { 7672 /* image_sample_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68334 { 7672 /* image_sample_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68344 { 7672 /* image_sample_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68354 { 7672 /* image_sample_o */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68364 { 7672 /* image_sample_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68374 { 7672 /* image_sample_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68384 { 7672 /* image_sample_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68394 { 7672 /* image_sample_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68404 { 7672 /* image_sample_o */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68414 { 7672 /* image_sample_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68424 { 7672 /* image_sample_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68434 { 7672 /* image_sample_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68444 { 7672 /* image_sample_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68454 { 7672 /* image_sample_o */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68464 { 7672 /* image_sample_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68474 { 7672 /* image_sample_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68484 { 7672 /* image_sample_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68494 { 7672 /* image_sample_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68504 { 7672 /* image_sample_o */, 8192 /* 13 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68513 { 7687 /* image_store */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68522 { 7687 /* image_store */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68531 { 7687 /* image_store */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68540 { 7687 /* image_store */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68549 { 7687 /* image_store */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68558 { 7687 /* image_store */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68567 { 7687 /* image_store */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68576 { 7687 /* image_store */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68585 { 7687 /* image_store */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68594 { 7687 /* image_store */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68603 { 7687 /* image_store */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68612 { 7687 /* image_store */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68621 { 7687 /* image_store */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68630 { 7687 /* image_store */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68639 { 7687 /* image_store */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68648 { 7687 /* image_store */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68658 { 7687 /* image_store */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68668 { 7687 /* image_store */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68678 { 7687 /* image_store */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68688 { 7687 /* image_store */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68698 { 7687 /* image_store */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68708 { 7687 /* image_store */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68718 { 7687 /* image_store */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68728 { 7687 /* image_store */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68738 { 7687 /* image_store */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68748 { 7687 /* image_store */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68758 { 7687 /* image_store */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68768 { 7687 /* image_store */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68778 { 7687 /* image_store */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68788 { 7687 /* image_store */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68798 { 7687 /* image_store */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68808 { 7687 /* image_store */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68818 { 7687 /* image_store */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68828 { 7687 /* image_store */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68838 { 7687 /* image_store */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68848 { 7687 /* image_store */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68858 { 7687 /* image_store */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68868 { 7687 /* image_store */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68878 { 7687 /* image_store */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68888 { 7687 /* image_store */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68898 { 7687 /* image_store */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68908 { 7687 /* image_store */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68918 { 7687 /* image_store */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68928 { 7687 /* image_store */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
68937 { 7699 /* image_store_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68946 { 7699 /* image_store_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68955 { 7699 /* image_store_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68964 { 7699 /* image_store_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68973 { 7699 /* image_store_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68982 { 7699 /* image_store_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
68991 { 7699 /* image_store_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69000 { 7699 /* image_store_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69009 { 7699 /* image_store_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69018 { 7699 /* image_store_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69027 { 7699 /* image_store_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69036 { 7699 /* image_store_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69045 { 7699 /* image_store_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69054 { 7699 /* image_store_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69063 { 7699 /* image_store_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69072 { 7699 /* image_store_mip */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69082 { 7699 /* image_store_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69092 { 7699 /* image_store_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69102 { 7699 /* image_store_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69112 { 7699 /* image_store_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69122 { 7699 /* image_store_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69132 { 7699 /* image_store_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69142 { 7699 /* image_store_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69152 { 7699 /* image_store_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69162 { 7699 /* image_store_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69172 { 7699 /* image_store_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69182 { 7699 /* image_store_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69192 { 7699 /* image_store_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69202 { 7699 /* image_store_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69212 { 7699 /* image_store_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69222 { 7699 /* image_store_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69232 { 7699 /* image_store_mip */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69242 { 7699 /* image_store_mip */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69252 { 7699 /* image_store_mip */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69262 { 7699 /* image_store_mip */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69272 { 7699 /* image_store_mip */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69282 { 7699 /* image_store_mip */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69292 { 7699 /* image_store_mip */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69302 { 7699 /* image_store_mip */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69312 { 7699 /* image_store_mip */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69322 { 7699 /* image_store_mip */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69332 { 7699 /* image_store_mip */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69342 { 7699 /* image_store_mip */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69352 { 7699 /* image_store_mip */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69361 { 7715 /* image_store_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69369 { 7715 /* image_store_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69377 { 7715 /* image_store_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69385 { 7715 /* image_store_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69393 { 7715 /* image_store_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69401 { 7715 /* image_store_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69409 { 7715 /* image_store_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69417 { 7715 /* image_store_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69425 { 7715 /* image_store_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69433 { 7715 /* image_store_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69441 { 7715 /* image_store_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69449 { 7715 /* image_store_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69457 { 7715 /* image_store_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69465 { 7715 /* image_store_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69473 { 7715 /* image_store_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69481 { 7715 /* image_store_mip_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69490 { 7715 /* image_store_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69499 { 7715 /* image_store_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69508 { 7715 /* image_store_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69517 { 7715 /* image_store_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69526 { 7715 /* image_store_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69535 { 7715 /* image_store_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69544 { 7715 /* image_store_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69553 { 7715 /* image_store_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69562 { 7715 /* image_store_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69571 { 7715 /* image_store_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69580 { 7715 /* image_store_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69589 { 7715 /* image_store_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69598 { 7715 /* image_store_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69607 { 7715 /* image_store_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69616 { 7715 /* image_store_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69625 { 7715 /* image_store_mip_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69634 { 7715 /* image_store_mip_pck */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69643 { 7715 /* image_store_mip_pck */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69652 { 7715 /* image_store_mip_pck */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69661 { 7715 /* image_store_mip_pck */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69670 { 7715 /* image_store_mip_pck */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69679 { 7715 /* image_store_mip_pck */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69688 { 7715 /* image_store_mip_pck */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69697 { 7715 /* image_store_mip_pck */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69706 { 7715 /* image_store_mip_pck */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69715 { 7715 /* image_store_mip_pck */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69724 { 7715 /* image_store_mip_pck */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69733 { 7715 /* image_store_mip_pck */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69741 { 7735 /* image_store_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69749 { 7735 /* image_store_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69757 { 7735 /* image_store_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69765 { 7735 /* image_store_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69773 { 7735 /* image_store_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69781 { 7735 /* image_store_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69789 { 7735 /* image_store_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69797 { 7735 /* image_store_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69805 { 7735 /* image_store_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69813 { 7735 /* image_store_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69821 { 7735 /* image_store_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69829 { 7735 /* image_store_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69837 { 7735 /* image_store_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69845 { 7735 /* image_store_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69853 { 7735 /* image_store_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69861 { 7735 /* image_store_pck */, 32 /* 5 */, MCK_ImmGLC, AMFBS_isGFX6GFX7GFX8GFX9_isGFX6GFX7GFX8GFX9 },
69870 { 7735 /* image_store_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69879 { 7735 /* image_store_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69888 { 7735 /* image_store_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69897 { 7735 /* image_store_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69906 { 7735 /* image_store_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69915 { 7735 /* image_store_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69924 { 7735 /* image_store_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69933 { 7735 /* image_store_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69942 { 7735 /* image_store_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69951 { 7735 /* image_store_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69960 { 7735 /* image_store_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69969 { 7735 /* image_store_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69978 { 7735 /* image_store_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69987 { 7735 /* image_store_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
69996 { 7735 /* image_store_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
70005 { 7735 /* image_store_pck */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
70014 { 7735 /* image_store_pck */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
70023 { 7735 /* image_store_pck */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
70032 { 7735 /* image_store_pck */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
70041 { 7735 /* image_store_pck */, 1024 /* 10 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
70050 { 7735 /* image_store_pck */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
70059 { 7735 /* image_store_pck */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
70068 { 7735 /* image_store_pck */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
70077 { 7735 /* image_store_pck */, 2048 /* 11 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
70086 { 7735 /* image_store_pck */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
70095 { 7735 /* image_store_pck */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
70104 { 7735 /* image_store_pck */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
70113 { 7735 /* image_store_pck */, 4096 /* 12 */, MCK_ImmGLC, AMFBS_isGFX10Plus_isGFX10Plus },
70752 { 9380 /* s_buffer_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70754 { 9380 /* s_buffer_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70756 { 9380 /* s_buffer_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70759 { 9380 /* s_buffer_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70762 { 9380 /* s_buffer_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70765 { 9380 /* s_buffer_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70768 { 9380 /* s_buffer_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX7Only },
70770 { 9400 /* s_buffer_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70772 { 9400 /* s_buffer_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70774 { 9400 /* s_buffer_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70777 { 9400 /* s_buffer_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70780 { 9400 /* s_buffer_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70783 { 9400 /* s_buffer_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70786 { 9400 /* s_buffer_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX7Only },
70788 { 9423 /* s_buffer_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70790 { 9423 /* s_buffer_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70792 { 9423 /* s_buffer_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70795 { 9423 /* s_buffer_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70798 { 9423 /* s_buffer_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70801 { 9423 /* s_buffer_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70804 { 9423 /* s_buffer_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX7Only },
70806 { 9445 /* s_buffer_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70808 { 9445 /* s_buffer_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70810 { 9445 /* s_buffer_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70813 { 9445 /* s_buffer_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70816 { 9445 /* s_buffer_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70819 { 9445 /* s_buffer_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70822 { 9445 /* s_buffer_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX7Only },
70824 { 9467 /* s_buffer_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70826 { 9467 /* s_buffer_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70828 { 9467 /* s_buffer_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70831 { 9467 /* s_buffer_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70834 { 9467 /* s_buffer_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70837 { 9467 /* s_buffer_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70840 { 9467 /* s_buffer_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX7Only },
70842 { 9489 /* s_buffer_store_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX10Plus },
70844 { 9489 /* s_buffer_store_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX8GFX9 },
70847 { 9489 /* s_buffer_store_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX10Plus },
70850 { 9489 /* s_buffer_store_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX8GFX9 },
70852 { 9510 /* s_buffer_store_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX10Plus },
70854 { 9510 /* s_buffer_store_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX8GFX9 },
70857 { 9510 /* s_buffer_store_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX10Plus },
70860 { 9510 /* s_buffer_store_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX8GFX9 },
70862 { 9533 /* s_buffer_store_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX10Plus },
70864 { 9533 /* s_buffer_store_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX8GFX9 },
70867 { 9533 /* s_buffer_store_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX10Plus },
70870 { 9533 /* s_buffer_store_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX8GFX9 },
70904 { 10626 /* s_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70906 { 10626 /* s_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70908 { 10626 /* s_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70911 { 10626 /* s_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70914 { 10626 /* s_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70917 { 10626 /* s_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70920 { 10626 /* s_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX7Only },
70922 { 10639 /* s_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70924 { 10639 /* s_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70926 { 10639 /* s_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70929 { 10639 /* s_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70932 { 10639 /* s_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70935 { 10639 /* s_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70938 { 10639 /* s_load_dwordx16 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX7Only },
70940 { 10655 /* s_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70942 { 10655 /* s_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70944 { 10655 /* s_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70947 { 10655 /* s_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70950 { 10655 /* s_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70953 { 10655 /* s_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70956 { 10655 /* s_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX7Only },
70958 { 10670 /* s_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70960 { 10670 /* s_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70962 { 10670 /* s_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70965 { 10670 /* s_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70968 { 10670 /* s_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70971 { 10670 /* s_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70974 { 10670 /* s_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX7Only },
70976 { 10685 /* s_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70978 { 10685 /* s_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70980 { 10685 /* s_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70983 { 10685 /* s_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
70986 { 10685 /* s_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
70989 { 10685 /* s_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
70992 { 10685 /* s_load_dwordx8 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_isGFX7Only },
70994 { 11480 /* s_scratch_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus },
70996 { 11480 /* s_scratch_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9 },
70999 { 11480 /* s_scratch_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus },
71002 { 11480 /* s_scratch_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9 },
71004 { 11501 /* s_scratch_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus },
71006 { 11501 /* s_scratch_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9 },
71009 { 11501 /* s_scratch_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus },
71012 { 11501 /* s_scratch_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9 },
71014 { 11524 /* s_scratch_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus },
71016 { 11524 /* s_scratch_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9 },
71019 { 11524 /* s_scratch_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX10Plus },
71022 { 11524 /* s_scratch_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9 },
71024 { 11547 /* s_scratch_store_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts },
71026 { 11547 /* s_scratch_store_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9 },
71029 { 11547 /* s_scratch_store_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts },
71032 { 11547 /* s_scratch_store_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9 },
71034 { 11569 /* s_scratch_store_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts },
71036 { 11569 /* s_scratch_store_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9 },
71039 { 11569 /* s_scratch_store_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts },
71042 { 11569 /* s_scratch_store_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9 },
71044 { 11593 /* s_scratch_store_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts },
71046 { 11593 /* s_scratch_store_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9 },
71049 { 11593 /* s_scratch_store_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX10Plus_HasScalarFlatScratchInsts },
71052 { 11593 /* s_scratch_store_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarFlatScratchInsts_isGFX8GFX9 },
71064 { 11835 /* s_store_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX10Plus },
71066 { 11835 /* s_store_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX8GFX9 },
71069 { 11835 /* s_store_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX10Plus },
71072 { 11835 /* s_store_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX8GFX9 },
71074 { 11849 /* s_store_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX10Plus },
71076 { 11849 /* s_store_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX8GFX9 },
71079 { 11849 /* s_store_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX10Plus },
71082 { 11849 /* s_store_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX8GFX9 },
71084 { 11865 /* s_store_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX10Plus },
71086 { 11865 /* s_store_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX8GFX9 },
71089 { 11865 /* s_store_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX10Plus },
71092 { 11865 /* s_store_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasScalarStores_isGFX8GFX9 },
71098 { 12271 /* scratch_load_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71102 { 12271 /* scratch_load_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71106 { 12271 /* scratch_load_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71110 { 12271 /* scratch_load_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71114 { 12290 /* scratch_load_dwordx2 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71118 { 12290 /* scratch_load_dwordx2 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71122 { 12290 /* scratch_load_dwordx2 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71126 { 12290 /* scratch_load_dwordx2 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71130 { 12311 /* scratch_load_dwordx3 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71134 { 12311 /* scratch_load_dwordx3 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71138 { 12311 /* scratch_load_dwordx3 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71142 { 12311 /* scratch_load_dwordx3 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71146 { 12332 /* scratch_load_dwordx4 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71150 { 12332 /* scratch_load_dwordx4 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71154 { 12332 /* scratch_load_dwordx4 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71158 { 12332 /* scratch_load_dwordx4 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71162 { 12353 /* scratch_load_sbyte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71166 { 12353 /* scratch_load_sbyte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71170 { 12353 /* scratch_load_sbyte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71174 { 12353 /* scratch_load_sbyte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71178 { 12372 /* scratch_load_sbyte_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71182 { 12372 /* scratch_load_sbyte_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71186 { 12372 /* scratch_load_sbyte_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71190 { 12372 /* scratch_load_sbyte_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71194 { 12395 /* scratch_load_sbyte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71198 { 12395 /* scratch_load_sbyte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71202 { 12395 /* scratch_load_sbyte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71206 { 12395 /* scratch_load_sbyte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71210 { 12421 /* scratch_load_short_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71214 { 12421 /* scratch_load_short_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71218 { 12421 /* scratch_load_short_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71222 { 12421 /* scratch_load_short_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71226 { 12444 /* scratch_load_short_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71230 { 12444 /* scratch_load_short_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71234 { 12444 /* scratch_load_short_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71238 { 12444 /* scratch_load_short_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71242 { 12470 /* scratch_load_sshort */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71246 { 12470 /* scratch_load_sshort */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71250 { 12470 /* scratch_load_sshort */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71254 { 12470 /* scratch_load_sshort */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71258 { 12490 /* scratch_load_ubyte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71262 { 12490 /* scratch_load_ubyte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71266 { 12490 /* scratch_load_ubyte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71270 { 12490 /* scratch_load_ubyte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71274 { 12509 /* scratch_load_ubyte_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71278 { 12509 /* scratch_load_ubyte_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71282 { 12509 /* scratch_load_ubyte_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71286 { 12509 /* scratch_load_ubyte_d16 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71290 { 12532 /* scratch_load_ubyte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71294 { 12532 /* scratch_load_ubyte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71298 { 12532 /* scratch_load_ubyte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71302 { 12532 /* scratch_load_ubyte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71306 { 12558 /* scratch_load_ushort */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71310 { 12558 /* scratch_load_ushort */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71314 { 12558 /* scratch_load_ushort */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71318 { 12558 /* scratch_load_ushort */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71322 { 12578 /* scratch_store_byte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71326 { 12578 /* scratch_store_byte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71330 { 12578 /* scratch_store_byte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71334 { 12578 /* scratch_store_byte */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71338 { 12597 /* scratch_store_byte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71342 { 12597 /* scratch_store_byte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71346 { 12597 /* scratch_store_byte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71350 { 12597 /* scratch_store_byte_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71354 { 12623 /* scratch_store_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71358 { 12623 /* scratch_store_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71362 { 12623 /* scratch_store_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71366 { 12623 /* scratch_store_dword */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71370 { 12643 /* scratch_store_dwordx2 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71374 { 12643 /* scratch_store_dwordx2 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71378 { 12643 /* scratch_store_dwordx2 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71382 { 12643 /* scratch_store_dwordx2 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71386 { 12665 /* scratch_store_dwordx3 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71390 { 12665 /* scratch_store_dwordx3 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71394 { 12665 /* scratch_store_dwordx3 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71398 { 12665 /* scratch_store_dwordx3 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71402 { 12687 /* scratch_store_dwordx4 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71406 { 12687 /* scratch_store_dwordx4 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71410 { 12687 /* scratch_store_dwordx4 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71414 { 12687 /* scratch_store_dwordx4 */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71418 { 12709 /* scratch_store_short */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71422 { 12709 /* scratch_store_short */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71426 { 12709 /* scratch_store_short */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71430 { 12709 /* scratch_store_short */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71434 { 12729 /* scratch_store_short_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71438 { 12729 /* scratch_store_short_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71442 { 12729 /* scratch_store_short_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71446 { 12729 /* scratch_store_short_d16_hi */, 16 /* 4 */, MCK_ImmGLC, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71450 { 12756 /* tbuffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71457 { 12756 /* tbuffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71464 { 12756 /* tbuffer_load_format_d16_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71471 { 12756 /* tbuffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71478 { 12756 /* tbuffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71485 { 12756 /* tbuffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71492 { 12756 /* tbuffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71499 { 12756 /* tbuffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71506 { 12756 /* tbuffer_load_format_d16_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71513 { 12756 /* tbuffer_load_format_d16_x */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71520 { 12756 /* tbuffer_load_format_d16_x */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71527 { 12756 /* tbuffer_load_format_d16_x */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71534 { 12782 /* tbuffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71541 { 12782 /* tbuffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71548 { 12782 /* tbuffer_load_format_d16_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71555 { 12782 /* tbuffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71562 { 12782 /* tbuffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71569 { 12782 /* tbuffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71576 { 12782 /* tbuffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71583 { 12782 /* tbuffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71590 { 12782 /* tbuffer_load_format_d16_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71597 { 12782 /* tbuffer_load_format_d16_xy */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71604 { 12782 /* tbuffer_load_format_d16_xy */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71611 { 12782 /* tbuffer_load_format_d16_xy */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71618 { 12809 /* tbuffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71625 { 12809 /* tbuffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71632 { 12809 /* tbuffer_load_format_d16_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71639 { 12809 /* tbuffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71646 { 12809 /* tbuffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71653 { 12809 /* tbuffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71660 { 12809 /* tbuffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71667 { 12809 /* tbuffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71674 { 12809 /* tbuffer_load_format_d16_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71681 { 12809 /* tbuffer_load_format_d16_xyz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71688 { 12809 /* tbuffer_load_format_d16_xyz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71695 { 12809 /* tbuffer_load_format_d16_xyz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71702 { 12837 /* tbuffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71709 { 12837 /* tbuffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71716 { 12837 /* tbuffer_load_format_d16_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71723 { 12837 /* tbuffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71730 { 12837 /* tbuffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71737 { 12837 /* tbuffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71744 { 12837 /* tbuffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71751 { 12837 /* tbuffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71758 { 12837 /* tbuffer_load_format_d16_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71765 { 12837 /* tbuffer_load_format_d16_xyzw */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
71772 { 12837 /* tbuffer_load_format_d16_xyzw */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
71779 { 12837 /* tbuffer_load_format_d16_xyzw */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
71786 { 12866 /* tbuffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
71793 { 12866 /* tbuffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71800 { 12866 /* tbuffer_load_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
71807 { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71814 { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
71821 { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71828 { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
71835 { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
71842 { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71849 { 12866 /* tbuffer_load_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
71856 { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
71863 { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71870 { 12866 /* tbuffer_load_format_x */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
71877 { 12888 /* tbuffer_load_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
71884 { 12888 /* tbuffer_load_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71891 { 12888 /* tbuffer_load_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
71898 { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71905 { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
71912 { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71919 { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
71926 { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
71933 { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71940 { 12888 /* tbuffer_load_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
71947 { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
71954 { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71961 { 12888 /* tbuffer_load_format_xy */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
71968 { 12911 /* tbuffer_load_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
71975 { 12911 /* tbuffer_load_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71982 { 12911 /* tbuffer_load_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
71989 { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
71996 { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72003 { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72010 { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72017 { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72024 { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72031 { 12911 /* tbuffer_load_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72038 { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72045 { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72052 { 12911 /* tbuffer_load_format_xyz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72059 { 12935 /* tbuffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72066 { 12935 /* tbuffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72073 { 12935 /* tbuffer_load_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72080 { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72087 { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72094 { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72101 { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72108 { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72115 { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72122 { 12935 /* tbuffer_load_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72129 { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72136 { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72143 { 12935 /* tbuffer_load_format_xyzw */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72150 { 12960 /* tbuffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72157 { 12960 /* tbuffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72164 { 12960 /* tbuffer_store_format_d16_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72171 { 12960 /* tbuffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72178 { 12960 /* tbuffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72185 { 12960 /* tbuffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72192 { 12960 /* tbuffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72199 { 12960 /* tbuffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72206 { 12960 /* tbuffer_store_format_d16_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72213 { 12960 /* tbuffer_store_format_d16_x */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72220 { 12960 /* tbuffer_store_format_d16_x */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72227 { 12960 /* tbuffer_store_format_d16_x */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72234 { 12987 /* tbuffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72241 { 12987 /* tbuffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72248 { 12987 /* tbuffer_store_format_d16_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72255 { 12987 /* tbuffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72262 { 12987 /* tbuffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72269 { 12987 /* tbuffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72276 { 12987 /* tbuffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72283 { 12987 /* tbuffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72290 { 12987 /* tbuffer_store_format_d16_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72297 { 12987 /* tbuffer_store_format_d16_xy */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72304 { 12987 /* tbuffer_store_format_d16_xy */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72311 { 12987 /* tbuffer_store_format_d16_xy */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72318 { 13015 /* tbuffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72325 { 13015 /* tbuffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72332 { 13015 /* tbuffer_store_format_d16_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72339 { 13015 /* tbuffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72346 { 13015 /* tbuffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72353 { 13015 /* tbuffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72360 { 13015 /* tbuffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72367 { 13015 /* tbuffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72374 { 13015 /* tbuffer_store_format_d16_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72381 { 13015 /* tbuffer_store_format_d16_xyz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72388 { 13015 /* tbuffer_store_format_d16_xyz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72395 { 13015 /* tbuffer_store_format_d16_xyz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72402 { 13044 /* tbuffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72409 { 13044 /* tbuffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72416 { 13044 /* tbuffer_store_format_d16_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72423 { 13044 /* tbuffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72430 { 13044 /* tbuffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72437 { 13044 /* tbuffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72444 { 13044 /* tbuffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72451 { 13044 /* tbuffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72458 { 13044 /* tbuffer_store_format_d16_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72465 { 13044 /* tbuffer_store_format_d16_xyzw */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasUnpackedD16VMem_HasUnpackedD16VMem },
72472 { 13044 /* tbuffer_store_format_d16_xyzw */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX10Plus },
72479 { 13044 /* tbuffer_store_format_d16_xyzw */, 256 /* 8 */, MCK_ImmGLC, AMFBS_HasPackedD16VMem_isGFX8GFX9 },
72486 { 13074 /* tbuffer_store_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72493 { 13074 /* tbuffer_store_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72500 { 13074 /* tbuffer_store_format_x */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72507 { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72514 { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72521 { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72528 { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72535 { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72542 { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72549 { 13074 /* tbuffer_store_format_x */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72556 { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72563 { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72570 { 13074 /* tbuffer_store_format_x */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72577 { 13097 /* tbuffer_store_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72584 { 13097 /* tbuffer_store_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72591 { 13097 /* tbuffer_store_format_xy */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72598 { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72605 { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72612 { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72619 { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72626 { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72633 { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72640 { 13097 /* tbuffer_store_format_xy */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72647 { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72654 { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72661 { 13097 /* tbuffer_store_format_xy */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72668 { 13121 /* tbuffer_store_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72675 { 13121 /* tbuffer_store_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72682 { 13121 /* tbuffer_store_format_xyz */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72689 { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72696 { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72703 { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72710 { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72717 { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72724 { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72731 { 13121 /* tbuffer_store_format_xyz */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72738 { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72745 { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72752 { 13121 /* tbuffer_store_format_xyz */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72759 { 13146 /* tbuffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72766 { 13146 /* tbuffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72773 { 13146 /* tbuffer_store_format_xyzw */, 64 /* 6 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72780 { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72787 { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72794 { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72801 { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72808 { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72815 { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72822 { 13146 /* tbuffer_store_format_xyzw */, 128 /* 7 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
72829 { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX10Plus },
72836 { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX6GFX7 },
72843 { 13146 /* tbuffer_store_format_xyzw */, 256 /* 8 */, MCK_ImmGLC, AMFBS_isGFX8GFX9 },
80333 case MCK_ImmGLC: