reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

 5189   case MCK_ImmFlatOffset:
 6001   case MCK_ImmFlatOffset: {
10142   case MCK_ImmFlatOffset: return "MCK_ImmFlatOffset";
12874   { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12875   { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12876   { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12877   { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12878   { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12879   { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12880   { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12881   { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12882   { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12883   { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12884   { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12885   { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12886   { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12887   { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12888   { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12889   { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12890   { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12891   { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12892   { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12893   { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12894   { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12895   { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12896   { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12897   { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12898   { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12899   { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12900   { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12901   { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12902   { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12903   { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12904   { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12905   { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12906   { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12907   { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12908   { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12909   { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12910   { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12911   { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12912   { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12913   { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12914   { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12915   { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12916   { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12917   { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12918   { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12919   { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12920   { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12921   { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12922   { 4131 /* flat_atomic_fcmpswap */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12923   { 4131 /* flat_atomic_fcmpswap */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12924   { 4131 /* flat_atomic_fcmpswap */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12925   { 4131 /* flat_atomic_fcmpswap */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12926   { 4152 /* flat_atomic_fcmpswap_x2 */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12927   { 4152 /* flat_atomic_fcmpswap_x2 */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12928   { 4152 /* flat_atomic_fcmpswap_x2 */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12929   { 4152 /* flat_atomic_fcmpswap_x2 */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12930   { 4176 /* flat_atomic_fmax */, AMDGPU::FLAT_ATOMIC_FMAX_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12931   { 4176 /* flat_atomic_fmax */, AMDGPU::FLAT_ATOMIC_FMAX_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12932   { 4176 /* flat_atomic_fmax */, AMDGPU::FLAT_ATOMIC_FMAX_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12933   { 4176 /* flat_atomic_fmax */, AMDGPU::FLAT_ATOMIC_FMAX_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12934   { 4193 /* flat_atomic_fmax_x2 */, AMDGPU::FLAT_ATOMIC_FMAX_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12935   { 4193 /* flat_atomic_fmax_x2 */, AMDGPU::FLAT_ATOMIC_FMAX_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12936   { 4193 /* flat_atomic_fmax_x2 */, AMDGPU::FLAT_ATOMIC_FMAX_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12937   { 4193 /* flat_atomic_fmax_x2 */, AMDGPU::FLAT_ATOMIC_FMAX_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12938   { 4213 /* flat_atomic_fmin */, AMDGPU::FLAT_ATOMIC_FMIN_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12939   { 4213 /* flat_atomic_fmin */, AMDGPU::FLAT_ATOMIC_FMIN_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12940   { 4213 /* flat_atomic_fmin */, AMDGPU::FLAT_ATOMIC_FMIN_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12941   { 4213 /* flat_atomic_fmin */, AMDGPU::FLAT_ATOMIC_FMIN_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12942   { 4230 /* flat_atomic_fmin_x2 */, AMDGPU::FLAT_ATOMIC_FMIN_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12943   { 4230 /* flat_atomic_fmin_x2 */, AMDGPU::FLAT_ATOMIC_FMIN_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12944   { 4230 /* flat_atomic_fmin_x2 */, AMDGPU::FLAT_ATOMIC_FMIN_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12945   { 4230 /* flat_atomic_fmin_x2 */, AMDGPU::FLAT_ATOMIC_FMIN_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_isGFX7GFX10_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12946   { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12947   { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12948   { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12949   { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12950   { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12951   { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12952   { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12953   { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12954   { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12955   { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12956   { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12957   { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12958   { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12959   { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12960   { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12961   { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12962   { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12963   { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12964   { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12965   { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12966   { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12967   { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12968   { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12969   { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12970   { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12971   { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12972   { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12973   { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12974   { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12975   { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12976   { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12977   { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12978   { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12979   { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12980   { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12981   { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12982   { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12983   { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12984   { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12985   { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12986   { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12987   { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12988   { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12989   { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12990   { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12991   { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12992   { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12993   { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12994   { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12995   { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12996   { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12997   { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12998   { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12999   { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13000   { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13001   { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13002   { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13003   { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13004   { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13005   { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13006   { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13007   { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13008   { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13009   { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13010   { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13011   { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13012   { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13013   { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13014   { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13015   { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13016   { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13017   { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13018   { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13019   { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13020   { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13021   { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13022   { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13023   { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13024   { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13025   { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13026   { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13027   { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13028   { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13029   { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13030   { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13031   { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13032   { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13033   { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13034   { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13035   { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13036   { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13037   { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13038   { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13039   { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13040   { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13041   { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13042   { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13043   { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13044   { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13045   { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13046   { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13047   { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13048   { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13049   { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13050   { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13051   { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13052   { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13053   { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13054   { 4573 /* flat_load_dword */, AMDGPU::FLAT_LOAD_DWORD_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13055   { 4573 /* flat_load_dword */, AMDGPU::FLAT_LOAD_DWORD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13056   { 4573 /* flat_load_dword */, AMDGPU::FLAT_LOAD_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13057   { 4589 /* flat_load_dwordx2 */, AMDGPU::FLAT_LOAD_DWORDX2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13058   { 4589 /* flat_load_dwordx2 */, AMDGPU::FLAT_LOAD_DWORDX2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13059   { 4589 /* flat_load_dwordx2 */, AMDGPU::FLAT_LOAD_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13060   { 4607 /* flat_load_dwordx3 */, AMDGPU::FLAT_LOAD_DWORDX3_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_96, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13061   { 4607 /* flat_load_dwordx3 */, AMDGPU::FLAT_LOAD_DWORDX3_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13062   { 4607 /* flat_load_dwordx3 */, AMDGPU::FLAT_LOAD_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13063   { 4625 /* flat_load_dwordx4 */, AMDGPU::FLAT_LOAD_DWORDX4_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_128, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13064   { 4625 /* flat_load_dwordx4 */, AMDGPU::FLAT_LOAD_DWORDX4_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13065   { 4625 /* flat_load_dwordx4 */, AMDGPU::FLAT_LOAD_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13066   { 4643 /* flat_load_sbyte */, AMDGPU::FLAT_LOAD_SBYTE_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13067   { 4643 /* flat_load_sbyte */, AMDGPU::FLAT_LOAD_SBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13068   { 4643 /* flat_load_sbyte */, AMDGPU::FLAT_LOAD_SBYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13069   { 4659 /* flat_load_sbyte_d16 */, AMDGPU::FLAT_LOAD_SBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13070   { 4659 /* flat_load_sbyte_d16 */, AMDGPU::FLAT_LOAD_SBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13071   { 4679 /* flat_load_sbyte_d16_hi */, AMDGPU::FLAT_LOAD_SBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13072   { 4679 /* flat_load_sbyte_d16_hi */, AMDGPU::FLAT_LOAD_SBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13073   { 4702 /* flat_load_short_d16 */, AMDGPU::FLAT_LOAD_SHORT_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13074   { 4702 /* flat_load_short_d16 */, AMDGPU::FLAT_LOAD_SHORT_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13075   { 4722 /* flat_load_short_d16_hi */, AMDGPU::FLAT_LOAD_SHORT_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13076   { 4722 /* flat_load_short_d16_hi */, AMDGPU::FLAT_LOAD_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13077   { 4745 /* flat_load_sshort */, AMDGPU::FLAT_LOAD_SSHORT_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13078   { 4745 /* flat_load_sshort */, AMDGPU::FLAT_LOAD_SSHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13079   { 4745 /* flat_load_sshort */, AMDGPU::FLAT_LOAD_SSHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13080   { 4762 /* flat_load_ubyte */, AMDGPU::FLAT_LOAD_UBYTE_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13081   { 4762 /* flat_load_ubyte */, AMDGPU::FLAT_LOAD_UBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13082   { 4762 /* flat_load_ubyte */, AMDGPU::FLAT_LOAD_UBYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13083   { 4778 /* flat_load_ubyte_d16 */, AMDGPU::FLAT_LOAD_UBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13084   { 4778 /* flat_load_ubyte_d16 */, AMDGPU::FLAT_LOAD_UBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13085   { 4798 /* flat_load_ubyte_d16_hi */, AMDGPU::FLAT_LOAD_UBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13086   { 4798 /* flat_load_ubyte_d16_hi */, AMDGPU::FLAT_LOAD_UBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5__imm_95_0, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13087   { 4821 /* flat_load_ushort */, AMDGPU::FLAT_LOAD_USHORT_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13088   { 4821 /* flat_load_ushort */, AMDGPU::FLAT_LOAD_USHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13089   { 4821 /* flat_load_ushort */, AMDGPU::FLAT_LOAD_USHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13090   { 4838 /* flat_store_byte */, AMDGPU::FLAT_STORE_BYTE_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13091   { 4838 /* flat_store_byte */, AMDGPU::FLAT_STORE_BYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13092   { 4838 /* flat_store_byte */, AMDGPU::FLAT_STORE_BYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13093   { 4854 /* flat_store_byte_d16_hi */, AMDGPU::FLAT_STORE_BYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13094   { 4854 /* flat_store_byte_d16_hi */, AMDGPU::FLAT_STORE_BYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13095   { 4877 /* flat_store_dword */, AMDGPU::FLAT_STORE_DWORD_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13096   { 4877 /* flat_store_dword */, AMDGPU::FLAT_STORE_DWORD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13097   { 4877 /* flat_store_dword */, AMDGPU::FLAT_STORE_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13098   { 4894 /* flat_store_dwordx2 */, AMDGPU::FLAT_STORE_DWORDX2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13099   { 4894 /* flat_store_dwordx2 */, AMDGPU::FLAT_STORE_DWORDX2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13100   { 4894 /* flat_store_dwordx2 */, AMDGPU::FLAT_STORE_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13101   { 4913 /* flat_store_dwordx3 */, AMDGPU::FLAT_STORE_DWORDX3_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_96, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13102   { 4913 /* flat_store_dwordx3 */, AMDGPU::FLAT_STORE_DWORDX3_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13103   { 4913 /* flat_store_dwordx3 */, AMDGPU::FLAT_STORE_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13104   { 4932 /* flat_store_dwordx4 */, AMDGPU::FLAT_STORE_DWORDX4_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13105   { 4932 /* flat_store_dwordx4 */, AMDGPU::FLAT_STORE_DWORDX4_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13106   { 4932 /* flat_store_dwordx4 */, AMDGPU::FLAT_STORE_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13107   { 4951 /* flat_store_short */, AMDGPU::FLAT_STORE_SHORT_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13108   { 4951 /* flat_store_short */, AMDGPU::FLAT_STORE_SHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13109   { 4951 /* flat_store_short */, AMDGPU::FLAT_STORE_SHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13110   { 4968 /* flat_store_short_d16_hi */, AMDGPU::FLAT_STORE_SHORT_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasD16LoadStore_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13111   { 4968 /* flat_store_short_d16_hi */, AMDGPU::FLAT_STORE_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasD16LoadStore_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13112   { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13113   { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13114   { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13115   { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13116   { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13117   { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13118   { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13119   { 4992 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13120   { 5010 /* global_atomic_add_f32 */, AMDGPU::GLOBAL_ATOMIC_ADD_F32_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13121   { 5010 /* global_atomic_add_f32 */, AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13122   { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13123   { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13124   { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13125   { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13126   { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13127   { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13128   { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13129   { 5032 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13130   { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13131   { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13132   { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13133   { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13134   { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13135   { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13136   { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13137   { 5053 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13138   { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13139   { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13140   { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13141   { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13142   { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13143   { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13144   { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13145   { 5071 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13146   { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13147   { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13148   { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13149   { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13150   { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13151   { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13152   { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13153   { 5092 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13154   { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13155   { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13156   { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13157   { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13158   { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13159   { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13160   { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13161   { 5114 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13162   { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13163   { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13164   { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13165   { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13166   { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13167   { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13168   { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13169   { 5139 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13170   { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13171   { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13172   { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13173   { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13174   { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13175   { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13176   { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13177   { 5157 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13178   { 5178 /* global_atomic_fcmpswap */, AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13179   { 5178 /* global_atomic_fcmpswap */, AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13180   { 5178 /* global_atomic_fcmpswap */, AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13181   { 5178 /* global_atomic_fcmpswap */, AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13182   { 5201 /* global_atomic_fcmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13183   { 5201 /* global_atomic_fcmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13184   { 5201 /* global_atomic_fcmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13185   { 5201 /* global_atomic_fcmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13186   { 5227 /* global_atomic_fmax */, AMDGPU::GLOBAL_ATOMIC_FMAX_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13187   { 5227 /* global_atomic_fmax */, AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13188   { 5227 /* global_atomic_fmax */, AMDGPU::GLOBAL_ATOMIC_FMAX_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13189   { 5227 /* global_atomic_fmax */, AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13190   { 5246 /* global_atomic_fmax_x2 */, AMDGPU::GLOBAL_ATOMIC_FMAX_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13191   { 5246 /* global_atomic_fmax_x2 */, AMDGPU::GLOBAL_ATOMIC_FMAX_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13192   { 5246 /* global_atomic_fmax_x2 */, AMDGPU::GLOBAL_ATOMIC_FMAX_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13193   { 5246 /* global_atomic_fmax_x2 */, AMDGPU::GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13194   { 5268 /* global_atomic_fmin */, AMDGPU::GLOBAL_ATOMIC_FMIN_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13195   { 5268 /* global_atomic_fmin */, AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13196   { 5268 /* global_atomic_fmin */, AMDGPU::GLOBAL_ATOMIC_FMIN_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13197   { 5268 /* global_atomic_fmin */, AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13198   { 5287 /* global_atomic_fmin_x2 */, AMDGPU::GLOBAL_ATOMIC_FMIN_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13199   { 5287 /* global_atomic_fmin_x2 */, AMDGPU::GLOBAL_ATOMIC_FMIN_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13200   { 5287 /* global_atomic_fmin_x2 */, AMDGPU::GLOBAL_ATOMIC_FMIN_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13201   { 5287 /* global_atomic_fmin_x2 */, AMDGPU::GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13202   { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13203   { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13204   { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13205   { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13206   { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13207   { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13208   { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13209   { 5309 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13210   { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13211   { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13212   { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13213   { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13214   { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13215   { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13216   { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13217   { 5327 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13218   { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13219   { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13220   { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13221   { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13222   { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13223   { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13224   { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13225   { 5348 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13226   { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13227   { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13228   { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13229   { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13230   { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13231   { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13232   { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13233   { 5365 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13234   { 5385 /* global_atomic_pk_add_f16 */, AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13235   { 5385 /* global_atomic_pk_add_f16 */, AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13236   { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13237   { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13238   { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13239   { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13240   { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13241   { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13242   { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13243   { 5410 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13244   { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13245   { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13246   { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13247   { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13248   { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13249   { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13250   { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13251   { 5429 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13252   { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13253   { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13254   { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13255   { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13256   { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13257   { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13258   { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13259   { 5451 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13260   { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13261   { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13262   { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13263   { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13264   { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13265   { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13266   { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13267   { 5470 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13268   { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13269   { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13270   { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13271   { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13272   { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13273   { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13274   { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13275   { 5492 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13276   { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13277   { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13278   { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13279   { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13280   { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13281   { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13282   { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13283   { 5510 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13284   { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13285   { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13286   { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13287   { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13288   { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13289   { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13290   { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13291   { 5531 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13292   { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13293   { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13294   { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13295   { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13296   { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13297   { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13298   { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13299   { 5550 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13300   { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13301   { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13302   { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13303   { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13304   { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13305   { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13306   { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13307   { 5572 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13308   { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13309   { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13310   { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13311   { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13312   { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13313   { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13314   { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13315   { 5591 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13316   { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13317   { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13318   { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13319   { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13320   { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13321   { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13322   { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13323   { 5613 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13324   { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13325   { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13326   { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13327   { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13328   { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13329   { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13330   { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13331   { 5632 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13332   { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13333   { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13334   { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13335   { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13336   { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13337   { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13338   { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13339   { 5654 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13340   { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13341   { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13342   { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13343   { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13344   { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13345   { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13346   { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13347   { 5672 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmFlatOffset1_4__ImmSLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13348   { 5693 /* global_load_dword */, AMDGPU::GLOBAL_LOAD_DWORD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13349   { 5693 /* global_load_dword */, AMDGPU::GLOBAL_LOAD_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13350   { 5693 /* global_load_dword */, AMDGPU::GLOBAL_LOAD_DWORD_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13351   { 5693 /* global_load_dword */, AMDGPU::GLOBAL_LOAD_DWORD_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13352   { 5711 /* global_load_dwordx2 */, AMDGPU::GLOBAL_LOAD_DWORDX2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13353   { 5711 /* global_load_dwordx2 */, AMDGPU::GLOBAL_LOAD_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13354   { 5711 /* global_load_dwordx2 */, AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13355   { 5711 /* global_load_dwordx2 */, AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13356   { 5731 /* global_load_dwordx3 */, AMDGPU::GLOBAL_LOAD_DWORDX3_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13357   { 5731 /* global_load_dwordx3 */, AMDGPU::GLOBAL_LOAD_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13358   { 5731 /* global_load_dwordx3 */, AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13359   { 5731 /* global_load_dwordx3 */, AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13360   { 5751 /* global_load_dwordx4 */, AMDGPU::GLOBAL_LOAD_DWORDX4_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13361   { 5751 /* global_load_dwordx4 */, AMDGPU::GLOBAL_LOAD_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13362   { 5751 /* global_load_dwordx4 */, AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13363   { 5751 /* global_load_dwordx4 */, AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13364   { 5771 /* global_load_sbyte */, AMDGPU::GLOBAL_LOAD_SBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13365   { 5771 /* global_load_sbyte */, AMDGPU::GLOBAL_LOAD_SBYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13366   { 5771 /* global_load_sbyte */, AMDGPU::GLOBAL_LOAD_SBYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13367   { 5771 /* global_load_sbyte */, AMDGPU::GLOBAL_LOAD_SBYTE_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13368   { 5789 /* global_load_sbyte_d16 */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13369   { 5789 /* global_load_sbyte_d16 */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13370   { 5789 /* global_load_sbyte_d16 */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13371   { 5789 /* global_load_sbyte_d16 */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13372   { 5811 /* global_load_sbyte_d16_hi */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13373   { 5811 /* global_load_sbyte_d16_hi */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13374   { 5811 /* global_load_sbyte_d16_hi */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13375   { 5811 /* global_load_sbyte_d16_hi */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13376   { 5836 /* global_load_short_d16 */, AMDGPU::GLOBAL_LOAD_SHORT_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13377   { 5836 /* global_load_short_d16 */, AMDGPU::GLOBAL_LOAD_SHORT_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13378   { 5836 /* global_load_short_d16 */, AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13379   { 5836 /* global_load_short_d16 */, AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13380   { 5858 /* global_load_short_d16_hi */, AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13381   { 5858 /* global_load_short_d16_hi */, AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13382   { 5858 /* global_load_short_d16_hi */, AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13383   { 5858 /* global_load_short_d16_hi */, AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13384   { 5883 /* global_load_sshort */, AMDGPU::GLOBAL_LOAD_SSHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13385   { 5883 /* global_load_sshort */, AMDGPU::GLOBAL_LOAD_SSHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13386   { 5883 /* global_load_sshort */, AMDGPU::GLOBAL_LOAD_SSHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13387   { 5883 /* global_load_sshort */, AMDGPU::GLOBAL_LOAD_SSHORT_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13388   { 5902 /* global_load_ubyte */, AMDGPU::GLOBAL_LOAD_UBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13389   { 5902 /* global_load_ubyte */, AMDGPU::GLOBAL_LOAD_UBYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13390   { 5902 /* global_load_ubyte */, AMDGPU::GLOBAL_LOAD_UBYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13391   { 5902 /* global_load_ubyte */, AMDGPU::GLOBAL_LOAD_UBYTE_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13392   { 5920 /* global_load_ubyte_d16 */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13393   { 5920 /* global_load_ubyte_d16 */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13394   { 5920 /* global_load_ubyte_d16 */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13395   { 5920 /* global_load_ubyte_d16 */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13396   { 5942 /* global_load_ubyte_d16_hi */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13397   { 5942 /* global_load_ubyte_d16_hi */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13398   { 5942 /* global_load_ubyte_d16_hi */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13399   { 5942 /* global_load_ubyte_d16_hi */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6__imm_95_0, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13400   { 5967 /* global_load_ushort */, AMDGPU::GLOBAL_LOAD_USHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13401   { 5967 /* global_load_ushort */, AMDGPU::GLOBAL_LOAD_USHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13402   { 5967 /* global_load_ushort */, AMDGPU::GLOBAL_LOAD_USHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13403   { 5967 /* global_load_ushort */, AMDGPU::GLOBAL_LOAD_USHORT_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13404   { 5986 /* global_store_byte */, AMDGPU::GLOBAL_STORE_BYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13405   { 5986 /* global_store_byte */, AMDGPU::GLOBAL_STORE_BYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13406   { 5986 /* global_store_byte */, AMDGPU::GLOBAL_STORE_BYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13407   { 5986 /* global_store_byte */, AMDGPU::GLOBAL_STORE_BYTE_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13408   { 6004 /* global_store_byte_d16_hi */, AMDGPU::GLOBAL_STORE_BYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13409   { 6004 /* global_store_byte_d16_hi */, AMDGPU::GLOBAL_STORE_BYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13410   { 6004 /* global_store_byte_d16_hi */, AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13411   { 6004 /* global_store_byte_d16_hi */, AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13412   { 6029 /* global_store_dword */, AMDGPU::GLOBAL_STORE_DWORD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13413   { 6029 /* global_store_dword */, AMDGPU::GLOBAL_STORE_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13414   { 6029 /* global_store_dword */, AMDGPU::GLOBAL_STORE_DWORD_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13415   { 6029 /* global_store_dword */, AMDGPU::GLOBAL_STORE_DWORD_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13416   { 6048 /* global_store_dwordx2 */, AMDGPU::GLOBAL_STORE_DWORDX2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13417   { 6048 /* global_store_dwordx2 */, AMDGPU::GLOBAL_STORE_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13418   { 6048 /* global_store_dwordx2 */, AMDGPU::GLOBAL_STORE_DWORDX2_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13419   { 6048 /* global_store_dwordx2 */, AMDGPU::GLOBAL_STORE_DWORDX2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13420   { 6069 /* global_store_dwordx3 */, AMDGPU::GLOBAL_STORE_DWORDX3_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13421   { 6069 /* global_store_dwordx3 */, AMDGPU::GLOBAL_STORE_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13422   { 6069 /* global_store_dwordx3 */, AMDGPU::GLOBAL_STORE_DWORDX3_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13423   { 6069 /* global_store_dwordx3 */, AMDGPU::GLOBAL_STORE_DWORDX3_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13424   { 6090 /* global_store_dwordx4 */, AMDGPU::GLOBAL_STORE_DWORDX4_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13425   { 6090 /* global_store_dwordx4 */, AMDGPU::GLOBAL_STORE_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13426   { 6090 /* global_store_dwordx4 */, AMDGPU::GLOBAL_STORE_DWORDX4_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13427   { 6090 /* global_store_dwordx4 */, AMDGPU::GLOBAL_STORE_DWORDX4_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13428   { 6111 /* global_store_short */, AMDGPU::GLOBAL_STORE_SHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13429   { 6111 /* global_store_short */, AMDGPU::GLOBAL_STORE_SHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13430   { 6111 /* global_store_short */, AMDGPU::GLOBAL_STORE_SHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13431   { 6111 /* global_store_short */, AMDGPU::GLOBAL_STORE_SHORT_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13432   { 6130 /* global_store_short_d16_hi */, AMDGPU::GLOBAL_STORE_SHORT_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13433   { 6130 /* global_store_short_d16_hi */, AMDGPU::GLOBAL_STORE_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13434   { 6130 /* global_store_short_d16_hi */, AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13435   { 6130 /* global_store_short_d16_hi */, AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatGlobalInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18563   { 12271 /* scratch_load_dword */, AMDGPU::SCRATCH_LOAD_DWORD_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18564   { 12271 /* scratch_load_dword */, AMDGPU::SCRATCH_LOAD_DWORD_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18565   { 12271 /* scratch_load_dword */, AMDGPU::SCRATCH_LOAD_DWORD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18566   { 12271 /* scratch_load_dword */, AMDGPU::SCRATCH_LOAD_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18567   { 12290 /* scratch_load_dwordx2 */, AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VReg_64, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18568   { 12290 /* scratch_load_dwordx2 */, AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VReg_64, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18569   { 12290 /* scratch_load_dwordx2 */, AMDGPU::SCRATCH_LOAD_DWORDX2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18570   { 12290 /* scratch_load_dwordx2 */, AMDGPU::SCRATCH_LOAD_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18571   { 12311 /* scratch_load_dwordx3 */, AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VReg_96, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18572   { 12311 /* scratch_load_dwordx3 */, AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VReg_96, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18573   { 12311 /* scratch_load_dwordx3 */, AMDGPU::SCRATCH_LOAD_DWORDX3_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VReg_96, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18574   { 12311 /* scratch_load_dwordx3 */, AMDGPU::SCRATCH_LOAD_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VReg_96, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18575   { 12332 /* scratch_load_dwordx4 */, AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VReg_128, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18576   { 12332 /* scratch_load_dwordx4 */, AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VReg_128, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18577   { 12332 /* scratch_load_dwordx4 */, AMDGPU::SCRATCH_LOAD_DWORDX4_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VReg_128, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18578   { 12332 /* scratch_load_dwordx4 */, AMDGPU::SCRATCH_LOAD_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VReg_128, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18579   { 12353 /* scratch_load_sbyte */, AMDGPU::SCRATCH_LOAD_SBYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18580   { 12353 /* scratch_load_sbyte */, AMDGPU::SCRATCH_LOAD_SBYTE_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18581   { 12353 /* scratch_load_sbyte */, AMDGPU::SCRATCH_LOAD_SBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18582   { 12353 /* scratch_load_sbyte */, AMDGPU::SCRATCH_LOAD_SBYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18583   { 12372 /* scratch_load_sbyte_d16 */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18584   { 12372 /* scratch_load_sbyte_d16 */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18585   { 12372 /* scratch_load_sbyte_d16 */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18586   { 12372 /* scratch_load_sbyte_d16 */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18587   { 12395 /* scratch_load_sbyte_d16_hi */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18588   { 12395 /* scratch_load_sbyte_d16_hi */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18589   { 12395 /* scratch_load_sbyte_d16_hi */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18590   { 12395 /* scratch_load_sbyte_d16_hi */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18591   { 12421 /* scratch_load_short_d16 */, AMDGPU::SCRATCH_LOAD_SHORT_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18592   { 12421 /* scratch_load_short_d16 */, AMDGPU::SCRATCH_LOAD_SHORT_D16_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18593   { 12421 /* scratch_load_short_d16 */, AMDGPU::SCRATCH_LOAD_SHORT_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18594   { 12421 /* scratch_load_short_d16 */, AMDGPU::SCRATCH_LOAD_SHORT_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18595   { 12444 /* scratch_load_short_d16_hi */, AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18596   { 12444 /* scratch_load_short_d16_hi */, AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18597   { 12444 /* scratch_load_short_d16_hi */, AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18598   { 12444 /* scratch_load_short_d16_hi */, AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18599   { 12470 /* scratch_load_sshort */, AMDGPU::SCRATCH_LOAD_SSHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18600   { 12470 /* scratch_load_sshort */, AMDGPU::SCRATCH_LOAD_SSHORT_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18601   { 12470 /* scratch_load_sshort */, AMDGPU::SCRATCH_LOAD_SSHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18602   { 12470 /* scratch_load_sshort */, AMDGPU::SCRATCH_LOAD_SSHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18603   { 12490 /* scratch_load_ubyte */, AMDGPU::SCRATCH_LOAD_UBYTE_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18604   { 12490 /* scratch_load_ubyte */, AMDGPU::SCRATCH_LOAD_UBYTE_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18605   { 12490 /* scratch_load_ubyte */, AMDGPU::SCRATCH_LOAD_UBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18606   { 12490 /* scratch_load_ubyte */, AMDGPU::SCRATCH_LOAD_UBYTE_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18607   { 12509 /* scratch_load_ubyte_d16 */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18608   { 12509 /* scratch_load_ubyte_d16 */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18609   { 12509 /* scratch_load_ubyte_d16 */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18610   { 12509 /* scratch_load_ubyte_d16 */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18611   { 12532 /* scratch_load_ubyte_d16_hi */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18612   { 12532 /* scratch_load_ubyte_d16_hi */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18613   { 12532 /* scratch_load_ubyte_d16_hi */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18614   { 12532 /* scratch_load_ubyte_d16_hi */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18615   { 12558 /* scratch_load_ushort */, AMDGPU::SCRATCH_LOAD_USHORT_SADDR_gfx10, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18616   { 12558 /* scratch_load_ushort */, AMDGPU::SCRATCH_LOAD_USHORT_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18617   { 12558 /* scratch_load_ushort */, AMDGPU::SCRATCH_LOAD_USHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18618   { 12558 /* scratch_load_ushort */, AMDGPU::SCRATCH_LOAD_USHORT_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18619   { 12578 /* scratch_store_byte */, AMDGPU::SCRATCH_STORE_BYTE_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18620   { 12578 /* scratch_store_byte */, AMDGPU::SCRATCH_STORE_BYTE_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18621   { 12578 /* scratch_store_byte */, AMDGPU::SCRATCH_STORE_BYTE_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18622   { 12578 /* scratch_store_byte */, AMDGPU::SCRATCH_STORE_BYTE_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18623   { 12597 /* scratch_store_byte_d16_hi */, AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18624   { 12597 /* scratch_store_byte_d16_hi */, AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18625   { 12597 /* scratch_store_byte_d16_hi */, AMDGPU::SCRATCH_STORE_BYTE_D16_HI_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18626   { 12597 /* scratch_store_byte_d16_hi */, AMDGPU::SCRATCH_STORE_BYTE_D16_HI_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18627   { 12623 /* scratch_store_dword */, AMDGPU::SCRATCH_STORE_DWORD_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18628   { 12623 /* scratch_store_dword */, AMDGPU::SCRATCH_STORE_DWORD_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18629   { 12623 /* scratch_store_dword */, AMDGPU::SCRATCH_STORE_DWORD_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18630   { 12623 /* scratch_store_dword */, AMDGPU::SCRATCH_STORE_DWORD_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18631   { 12643 /* scratch_store_dwordx2 */, AMDGPU::SCRATCH_STORE_DWORDX2_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VReg_64, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18632   { 12643 /* scratch_store_dwordx2 */, AMDGPU::SCRATCH_STORE_DWORDX2_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VReg_64, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18633   { 12643 /* scratch_store_dwordx2 */, AMDGPU::SCRATCH_STORE_DWORDX2_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18634   { 12643 /* scratch_store_dwordx2 */, AMDGPU::SCRATCH_STORE_DWORDX2_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18635   { 12665 /* scratch_store_dwordx3 */, AMDGPU::SCRATCH_STORE_DWORDX3_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VReg_96, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18636   { 12665 /* scratch_store_dwordx3 */, AMDGPU::SCRATCH_STORE_DWORDX3_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VReg_96, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18637   { 12665 /* scratch_store_dwordx3 */, AMDGPU::SCRATCH_STORE_DWORDX3_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_96, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18638   { 12665 /* scratch_store_dwordx3 */, AMDGPU::SCRATCH_STORE_DWORDX3_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_96, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18639   { 12687 /* scratch_store_dwordx4 */, AMDGPU::SCRATCH_STORE_DWORDX4_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VReg_128, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18640   { 12687 /* scratch_store_dwordx4 */, AMDGPU::SCRATCH_STORE_DWORDX4_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VReg_128, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18641   { 12687 /* scratch_store_dwordx4 */, AMDGPU::SCRATCH_STORE_DWORDX4_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18642   { 12687 /* scratch_store_dwordx4 */, AMDGPU::SCRATCH_STORE_DWORDX4_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_128, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18643   { 12709 /* scratch_store_short */, AMDGPU::SCRATCH_STORE_SHORT_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18644   { 12709 /* scratch_store_short */, AMDGPU::SCRATCH_STORE_SHORT_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18645   { 12709 /* scratch_store_short */, AMDGPU::SCRATCH_STORE_SHORT_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18646   { 12709 /* scratch_store_short */, AMDGPU::SCRATCH_STORE_SHORT_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18647   { 12729 /* scratch_store_short_d16_hi */, AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR_gfx10, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18648   { 12729 /* scratch_store_short_d16_hi */, AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18649   { 12729 /* scratch_store_short_d16_hi */, AMDGPU::SCRATCH_STORE_SHORT_D16_HI_gfx10, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
18650   { 12729 /* scratch_store_short_d16_hi */, AMDGPU::SCRATCH_STORE_SHORT_D16_HI_vi, Convert__Reg1_1__Reg1_0__ImmFlatOffset1_3__ImmGLC1_4__ImmSLC1_5__ImmDLC1_6, AMFBS_HasFlatScratchInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
29842   { 3983 /* flat_atomic_add */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29844   { 3983 /* flat_atomic_add */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29846   { 3983 /* flat_atomic_add */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29848   { 3983 /* flat_atomic_add */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29850   { 3983 /* flat_atomic_add */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29852   { 3983 /* flat_atomic_add */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29854   { 3999 /* flat_atomic_add_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29856   { 3999 /* flat_atomic_add_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29858   { 3999 /* flat_atomic_add_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29860   { 3999 /* flat_atomic_add_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29862   { 3999 /* flat_atomic_add_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29864   { 3999 /* flat_atomic_add_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29866   { 4018 /* flat_atomic_and */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29868   { 4018 /* flat_atomic_and */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29870   { 4018 /* flat_atomic_and */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29872   { 4018 /* flat_atomic_and */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29874   { 4018 /* flat_atomic_and */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29876   { 4018 /* flat_atomic_and */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29878   { 4034 /* flat_atomic_and_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29880   { 4034 /* flat_atomic_and_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29882   { 4034 /* flat_atomic_and_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29884   { 4034 /* flat_atomic_and_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29886   { 4034 /* flat_atomic_and_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29888   { 4034 /* flat_atomic_and_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29890   { 4053 /* flat_atomic_cmpswap */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29892   { 4053 /* flat_atomic_cmpswap */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29894   { 4053 /* flat_atomic_cmpswap */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29896   { 4053 /* flat_atomic_cmpswap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29898   { 4053 /* flat_atomic_cmpswap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29900   { 4053 /* flat_atomic_cmpswap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29902   { 4073 /* flat_atomic_cmpswap_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29904   { 4073 /* flat_atomic_cmpswap_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29906   { 4073 /* flat_atomic_cmpswap_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29908   { 4073 /* flat_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29910   { 4073 /* flat_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29912   { 4073 /* flat_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29914   { 4096 /* flat_atomic_dec */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29916   { 4096 /* flat_atomic_dec */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29918   { 4096 /* flat_atomic_dec */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29920   { 4096 /* flat_atomic_dec */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29922   { 4096 /* flat_atomic_dec */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29924   { 4096 /* flat_atomic_dec */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29926   { 4112 /* flat_atomic_dec_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29928   { 4112 /* flat_atomic_dec_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29930   { 4112 /* flat_atomic_dec_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29932   { 4112 /* flat_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29934   { 4112 /* flat_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29936   { 4112 /* flat_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29938   { 4131 /* flat_atomic_fcmpswap */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only },
29940   { 4131 /* flat_atomic_fcmpswap */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus },
29942   { 4131 /* flat_atomic_fcmpswap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only },
29944   { 4131 /* flat_atomic_fcmpswap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus },
29946   { 4152 /* flat_atomic_fcmpswap_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only },
29948   { 4152 /* flat_atomic_fcmpswap_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus },
29950   { 4152 /* flat_atomic_fcmpswap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only },
29952   { 4152 /* flat_atomic_fcmpswap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus },
29954   { 4176 /* flat_atomic_fmax */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only },
29956   { 4176 /* flat_atomic_fmax */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus },
29958   { 4176 /* flat_atomic_fmax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only },
29960   { 4176 /* flat_atomic_fmax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus },
29962   { 4193 /* flat_atomic_fmax_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only },
29964   { 4193 /* flat_atomic_fmax_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus },
29966   { 4193 /* flat_atomic_fmax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only },
29968   { 4193 /* flat_atomic_fmax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus },
29970   { 4213 /* flat_atomic_fmin */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only },
29972   { 4213 /* flat_atomic_fmin */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus },
29974   { 4213 /* flat_atomic_fmin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only },
29976   { 4213 /* flat_atomic_fmin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus },
29978   { 4230 /* flat_atomic_fmin_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only },
29980   { 4230 /* flat_atomic_fmin_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus },
29982   { 4230 /* flat_atomic_fmin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX7Only },
29984   { 4230 /* flat_atomic_fmin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX7GFX10_isGFX10Plus },
29986   { 4250 /* flat_atomic_inc */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29988   { 4250 /* flat_atomic_inc */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29990   { 4250 /* flat_atomic_inc */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29992   { 4250 /* flat_atomic_inc */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29994   { 4250 /* flat_atomic_inc */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29996   { 4250 /* flat_atomic_inc */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
29998   { 4266 /* flat_atomic_inc_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30000   { 4266 /* flat_atomic_inc_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30002   { 4266 /* flat_atomic_inc_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30004   { 4266 /* flat_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30006   { 4266 /* flat_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30008   { 4266 /* flat_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30010   { 4285 /* flat_atomic_or */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30012   { 4285 /* flat_atomic_or */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30014   { 4285 /* flat_atomic_or */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30016   { 4285 /* flat_atomic_or */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30018   { 4285 /* flat_atomic_or */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30020   { 4285 /* flat_atomic_or */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30022   { 4300 /* flat_atomic_or_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30024   { 4300 /* flat_atomic_or_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30026   { 4300 /* flat_atomic_or_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30028   { 4300 /* flat_atomic_or_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30030   { 4300 /* flat_atomic_or_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30032   { 4300 /* flat_atomic_or_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30034   { 4318 /* flat_atomic_smax */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30036   { 4318 /* flat_atomic_smax */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30038   { 4318 /* flat_atomic_smax */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30040   { 4318 /* flat_atomic_smax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30042   { 4318 /* flat_atomic_smax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30044   { 4318 /* flat_atomic_smax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30046   { 4335 /* flat_atomic_smax_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30048   { 4335 /* flat_atomic_smax_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30050   { 4335 /* flat_atomic_smax_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30052   { 4335 /* flat_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30054   { 4335 /* flat_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30056   { 4335 /* flat_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30058   { 4355 /* flat_atomic_smin */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30060   { 4355 /* flat_atomic_smin */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30062   { 4355 /* flat_atomic_smin */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30064   { 4355 /* flat_atomic_smin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30066   { 4355 /* flat_atomic_smin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30068   { 4355 /* flat_atomic_smin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30070   { 4372 /* flat_atomic_smin_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30072   { 4372 /* flat_atomic_smin_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30074   { 4372 /* flat_atomic_smin_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30076   { 4372 /* flat_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30078   { 4372 /* flat_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30080   { 4372 /* flat_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30082   { 4392 /* flat_atomic_sub */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30084   { 4392 /* flat_atomic_sub */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30086   { 4392 /* flat_atomic_sub */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30088   { 4392 /* flat_atomic_sub */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30090   { 4392 /* flat_atomic_sub */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30092   { 4392 /* flat_atomic_sub */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30094   { 4408 /* flat_atomic_sub_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30096   { 4408 /* flat_atomic_sub_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30098   { 4408 /* flat_atomic_sub_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30100   { 4408 /* flat_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30102   { 4408 /* flat_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30104   { 4408 /* flat_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30106   { 4427 /* flat_atomic_swap */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30108   { 4427 /* flat_atomic_swap */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30110   { 4427 /* flat_atomic_swap */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30112   { 4427 /* flat_atomic_swap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30114   { 4427 /* flat_atomic_swap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30116   { 4427 /* flat_atomic_swap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30118   { 4444 /* flat_atomic_swap_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30120   { 4444 /* flat_atomic_swap_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30122   { 4444 /* flat_atomic_swap_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30124   { 4444 /* flat_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30126   { 4444 /* flat_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30128   { 4444 /* flat_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30130   { 4464 /* flat_atomic_umax */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30132   { 4464 /* flat_atomic_umax */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30134   { 4464 /* flat_atomic_umax */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30136   { 4464 /* flat_atomic_umax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30138   { 4464 /* flat_atomic_umax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30140   { 4464 /* flat_atomic_umax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30142   { 4481 /* flat_atomic_umax_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30144   { 4481 /* flat_atomic_umax_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30146   { 4481 /* flat_atomic_umax_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30148   { 4481 /* flat_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30150   { 4481 /* flat_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30152   { 4481 /* flat_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30154   { 4501 /* flat_atomic_umin */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30156   { 4501 /* flat_atomic_umin */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30158   { 4501 /* flat_atomic_umin */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30160   { 4501 /* flat_atomic_umin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30162   { 4501 /* flat_atomic_umin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30164   { 4501 /* flat_atomic_umin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30166   { 4518 /* flat_atomic_umin_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30168   { 4518 /* flat_atomic_umin_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30170   { 4518 /* flat_atomic_umin_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30172   { 4518 /* flat_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30174   { 4518 /* flat_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30176   { 4518 /* flat_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30178   { 4538 /* flat_atomic_xor */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30180   { 4538 /* flat_atomic_xor */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30182   { 4538 /* flat_atomic_xor */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30184   { 4538 /* flat_atomic_xor */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30186   { 4538 /* flat_atomic_xor */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30188   { 4538 /* flat_atomic_xor */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30190   { 4554 /* flat_atomic_xor_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30192   { 4554 /* flat_atomic_xor_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30194   { 4554 /* flat_atomic_xor_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30196   { 4554 /* flat_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30198   { 4554 /* flat_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30200   { 4554 /* flat_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30202   { 4573 /* flat_load_dword */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30206   { 4573 /* flat_load_dword */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30210   { 4573 /* flat_load_dword */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30214   { 4589 /* flat_load_dwordx2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30218   { 4589 /* flat_load_dwordx2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30222   { 4589 /* flat_load_dwordx2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30226   { 4607 /* flat_load_dwordx3 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30230   { 4607 /* flat_load_dwordx3 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30234   { 4607 /* flat_load_dwordx3 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30238   { 4625 /* flat_load_dwordx4 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30242   { 4625 /* flat_load_dwordx4 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30246   { 4625 /* flat_load_dwordx4 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30250   { 4643 /* flat_load_sbyte */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30254   { 4643 /* flat_load_sbyte */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30258   { 4643 /* flat_load_sbyte */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30262   { 4659 /* flat_load_sbyte_d16 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
30266   { 4659 /* flat_load_sbyte_d16 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30270   { 4679 /* flat_load_sbyte_d16_hi */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
30274   { 4679 /* flat_load_sbyte_d16_hi */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30278   { 4702 /* flat_load_short_d16 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
30282   { 4702 /* flat_load_short_d16 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30286   { 4722 /* flat_load_short_d16_hi */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
30290   { 4722 /* flat_load_short_d16_hi */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30294   { 4745 /* flat_load_sshort */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30298   { 4745 /* flat_load_sshort */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30302   { 4745 /* flat_load_sshort */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30306   { 4762 /* flat_load_ubyte */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30310   { 4762 /* flat_load_ubyte */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30314   { 4762 /* flat_load_ubyte */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30318   { 4778 /* flat_load_ubyte_d16 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
30322   { 4778 /* flat_load_ubyte_d16 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30326   { 4798 /* flat_load_ubyte_d16_hi */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
30330   { 4798 /* flat_load_ubyte_d16_hi */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30334   { 4821 /* flat_load_ushort */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30338   { 4821 /* flat_load_ushort */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30342   { 4821 /* flat_load_ushort */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30346   { 4838 /* flat_store_byte */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30350   { 4838 /* flat_store_byte */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30354   { 4838 /* flat_store_byte */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30358   { 4854 /* flat_store_byte_d16_hi */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
30362   { 4854 /* flat_store_byte_d16_hi */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30366   { 4877 /* flat_store_dword */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30370   { 4877 /* flat_store_dword */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30374   { 4877 /* flat_store_dword */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30378   { 4894 /* flat_store_dwordx2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30382   { 4894 /* flat_store_dwordx2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30386   { 4894 /* flat_store_dwordx2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30390   { 4913 /* flat_store_dwordx3 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30394   { 4913 /* flat_store_dwordx3 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30398   { 4913 /* flat_store_dwordx3 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30402   { 4932 /* flat_store_dwordx4 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30406   { 4932 /* flat_store_dwordx4 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30410   { 4932 /* flat_store_dwordx4 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30414   { 4951 /* flat_store_short */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30418   { 4951 /* flat_store_short */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30422   { 4951 /* flat_store_short */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX8GFX9 },
30426   { 4968 /* flat_store_short_d16_hi */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasD16LoadStore_isGFX10Plus },
30430   { 4968 /* flat_store_short_d16_hi */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasD16LoadStore_isGFX8GFX9 },
30434   { 4992 /* global_atomic_add */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30436   { 4992 /* global_atomic_add */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30438   { 4992 /* global_atomic_add */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30440   { 4992 /* global_atomic_add */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30442   { 4992 /* global_atomic_add */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30444   { 4992 /* global_atomic_add */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30446   { 4992 /* global_atomic_add */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30448   { 4992 /* global_atomic_add */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30450   { 5010 /* global_atomic_add_f32 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
30452   { 5010 /* global_atomic_add_f32 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
30454   { 5032 /* global_atomic_add_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30456   { 5032 /* global_atomic_add_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30458   { 5032 /* global_atomic_add_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30460   { 5032 /* global_atomic_add_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30462   { 5032 /* global_atomic_add_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30464   { 5032 /* global_atomic_add_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30466   { 5032 /* global_atomic_add_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30468   { 5032 /* global_atomic_add_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30470   { 5053 /* global_atomic_and */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30472   { 5053 /* global_atomic_and */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30474   { 5053 /* global_atomic_and */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30476   { 5053 /* global_atomic_and */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30478   { 5053 /* global_atomic_and */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30480   { 5053 /* global_atomic_and */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30482   { 5053 /* global_atomic_and */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30484   { 5053 /* global_atomic_and */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30486   { 5071 /* global_atomic_and_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30488   { 5071 /* global_atomic_and_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30490   { 5071 /* global_atomic_and_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30492   { 5071 /* global_atomic_and_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30494   { 5071 /* global_atomic_and_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30496   { 5071 /* global_atomic_and_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30498   { 5071 /* global_atomic_and_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30500   { 5071 /* global_atomic_and_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30502   { 5092 /* global_atomic_cmpswap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30504   { 5092 /* global_atomic_cmpswap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30506   { 5092 /* global_atomic_cmpswap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30508   { 5092 /* global_atomic_cmpswap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30510   { 5092 /* global_atomic_cmpswap */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30512   { 5092 /* global_atomic_cmpswap */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30514   { 5092 /* global_atomic_cmpswap */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30516   { 5092 /* global_atomic_cmpswap */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30518   { 5114 /* global_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30520   { 5114 /* global_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30522   { 5114 /* global_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30524   { 5114 /* global_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30526   { 5114 /* global_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30528   { 5114 /* global_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30530   { 5114 /* global_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30532   { 5114 /* global_atomic_cmpswap_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30534   { 5139 /* global_atomic_dec */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30536   { 5139 /* global_atomic_dec */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30538   { 5139 /* global_atomic_dec */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30540   { 5139 /* global_atomic_dec */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30542   { 5139 /* global_atomic_dec */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30544   { 5139 /* global_atomic_dec */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30546   { 5139 /* global_atomic_dec */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30548   { 5139 /* global_atomic_dec */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30550   { 5157 /* global_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30552   { 5157 /* global_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30554   { 5157 /* global_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30556   { 5157 /* global_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30558   { 5157 /* global_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30560   { 5157 /* global_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30562   { 5157 /* global_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30564   { 5157 /* global_atomic_dec_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30566   { 5178 /* global_atomic_fcmpswap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30568   { 5178 /* global_atomic_fcmpswap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30570   { 5178 /* global_atomic_fcmpswap */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30572   { 5178 /* global_atomic_fcmpswap */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30574   { 5201 /* global_atomic_fcmpswap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30576   { 5201 /* global_atomic_fcmpswap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30578   { 5201 /* global_atomic_fcmpswap_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30580   { 5201 /* global_atomic_fcmpswap_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30582   { 5227 /* global_atomic_fmax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30584   { 5227 /* global_atomic_fmax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30586   { 5227 /* global_atomic_fmax */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30588   { 5227 /* global_atomic_fmax */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30590   { 5246 /* global_atomic_fmax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30592   { 5246 /* global_atomic_fmax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30594   { 5246 /* global_atomic_fmax_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30596   { 5246 /* global_atomic_fmax_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30598   { 5268 /* global_atomic_fmin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30600   { 5268 /* global_atomic_fmin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30602   { 5268 /* global_atomic_fmin */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30604   { 5268 /* global_atomic_fmin */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30606   { 5287 /* global_atomic_fmin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30608   { 5287 /* global_atomic_fmin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30610   { 5287 /* global_atomic_fmin_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30612   { 5287 /* global_atomic_fmin_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_isGFX10Plus_isGFX10Plus },
30614   { 5309 /* global_atomic_inc */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30616   { 5309 /* global_atomic_inc */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30618   { 5309 /* global_atomic_inc */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30620   { 5309 /* global_atomic_inc */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30622   { 5309 /* global_atomic_inc */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30624   { 5309 /* global_atomic_inc */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30626   { 5309 /* global_atomic_inc */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30628   { 5309 /* global_atomic_inc */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30630   { 5327 /* global_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30632   { 5327 /* global_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30634   { 5327 /* global_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30636   { 5327 /* global_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30638   { 5327 /* global_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30640   { 5327 /* global_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30642   { 5327 /* global_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30644   { 5327 /* global_atomic_inc_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30646   { 5348 /* global_atomic_or */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30648   { 5348 /* global_atomic_or */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30650   { 5348 /* global_atomic_or */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30652   { 5348 /* global_atomic_or */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30654   { 5348 /* global_atomic_or */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30656   { 5348 /* global_atomic_or */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30658   { 5348 /* global_atomic_or */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30660   { 5348 /* global_atomic_or */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30662   { 5365 /* global_atomic_or_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30664   { 5365 /* global_atomic_or_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30666   { 5365 /* global_atomic_or_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30668   { 5365 /* global_atomic_or_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30670   { 5365 /* global_atomic_or_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30672   { 5365 /* global_atomic_or_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30674   { 5365 /* global_atomic_or_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30676   { 5365 /* global_atomic_or_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30678   { 5385 /* global_atomic_pk_add_f16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
30680   { 5385 /* global_atomic_pk_add_f16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },
30682   { 5410 /* global_atomic_smax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30684   { 5410 /* global_atomic_smax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30686   { 5410 /* global_atomic_smax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30688   { 5410 /* global_atomic_smax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30690   { 5410 /* global_atomic_smax */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30692   { 5410 /* global_atomic_smax */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30694   { 5410 /* global_atomic_smax */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30696   { 5410 /* global_atomic_smax */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30698   { 5429 /* global_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30700   { 5429 /* global_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30702   { 5429 /* global_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30704   { 5429 /* global_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30706   { 5429 /* global_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30708   { 5429 /* global_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30710   { 5429 /* global_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30712   { 5429 /* global_atomic_smax_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30714   { 5451 /* global_atomic_smin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30716   { 5451 /* global_atomic_smin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30718   { 5451 /* global_atomic_smin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30720   { 5451 /* global_atomic_smin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30722   { 5451 /* global_atomic_smin */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30724   { 5451 /* global_atomic_smin */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30726   { 5451 /* global_atomic_smin */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30728   { 5451 /* global_atomic_smin */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30730   { 5470 /* global_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30732   { 5470 /* global_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30734   { 5470 /* global_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30736   { 5470 /* global_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30738   { 5470 /* global_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30740   { 5470 /* global_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30742   { 5470 /* global_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30744   { 5470 /* global_atomic_smin_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30746   { 5492 /* global_atomic_sub */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30748   { 5492 /* global_atomic_sub */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30750   { 5492 /* global_atomic_sub */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30752   { 5492 /* global_atomic_sub */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30754   { 5492 /* global_atomic_sub */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30756   { 5492 /* global_atomic_sub */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30758   { 5492 /* global_atomic_sub */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30760   { 5492 /* global_atomic_sub */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30762   { 5510 /* global_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30764   { 5510 /* global_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30766   { 5510 /* global_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30768   { 5510 /* global_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30770   { 5510 /* global_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30772   { 5510 /* global_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30774   { 5510 /* global_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30776   { 5510 /* global_atomic_sub_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30778   { 5531 /* global_atomic_swap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30780   { 5531 /* global_atomic_swap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30782   { 5531 /* global_atomic_swap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30784   { 5531 /* global_atomic_swap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30786   { 5531 /* global_atomic_swap */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30788   { 5531 /* global_atomic_swap */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30790   { 5531 /* global_atomic_swap */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30792   { 5531 /* global_atomic_swap */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30794   { 5550 /* global_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30796   { 5550 /* global_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30798   { 5550 /* global_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30800   { 5550 /* global_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30802   { 5550 /* global_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30804   { 5550 /* global_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30806   { 5550 /* global_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30808   { 5550 /* global_atomic_swap_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30810   { 5572 /* global_atomic_umax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30812   { 5572 /* global_atomic_umax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30814   { 5572 /* global_atomic_umax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30816   { 5572 /* global_atomic_umax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30818   { 5572 /* global_atomic_umax */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30820   { 5572 /* global_atomic_umax */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30822   { 5572 /* global_atomic_umax */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30824   { 5572 /* global_atomic_umax */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30826   { 5591 /* global_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30828   { 5591 /* global_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30830   { 5591 /* global_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30832   { 5591 /* global_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30834   { 5591 /* global_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30836   { 5591 /* global_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30838   { 5591 /* global_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30840   { 5591 /* global_atomic_umax_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30842   { 5613 /* global_atomic_umin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30844   { 5613 /* global_atomic_umin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30846   { 5613 /* global_atomic_umin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30848   { 5613 /* global_atomic_umin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30850   { 5613 /* global_atomic_umin */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30852   { 5613 /* global_atomic_umin */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30854   { 5613 /* global_atomic_umin */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30856   { 5613 /* global_atomic_umin */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30858   { 5632 /* global_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30860   { 5632 /* global_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30862   { 5632 /* global_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30864   { 5632 /* global_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30866   { 5632 /* global_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30868   { 5632 /* global_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30870   { 5632 /* global_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30872   { 5632 /* global_atomic_umin_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30874   { 5654 /* global_atomic_xor */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30876   { 5654 /* global_atomic_xor */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30878   { 5654 /* global_atomic_xor */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30880   { 5654 /* global_atomic_xor */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30882   { 5654 /* global_atomic_xor */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30884   { 5654 /* global_atomic_xor */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30886   { 5654 /* global_atomic_xor */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30888   { 5654 /* global_atomic_xor */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30890   { 5672 /* global_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30892   { 5672 /* global_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30894   { 5672 /* global_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30896   { 5672 /* global_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30898   { 5672 /* global_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30900   { 5672 /* global_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30902   { 5672 /* global_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30904   { 5672 /* global_atomic_xor_x2 */, 16 /* 4 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30906   { 5693 /* global_load_dword */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30910   { 5693 /* global_load_dword */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30914   { 5693 /* global_load_dword */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30918   { 5693 /* global_load_dword */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30922   { 5711 /* global_load_dwordx2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30926   { 5711 /* global_load_dwordx2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30930   { 5711 /* global_load_dwordx2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30934   { 5711 /* global_load_dwordx2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30938   { 5731 /* global_load_dwordx3 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30942   { 5731 /* global_load_dwordx3 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30946   { 5731 /* global_load_dwordx3 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30950   { 5731 /* global_load_dwordx3 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30954   { 5751 /* global_load_dwordx4 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30958   { 5751 /* global_load_dwordx4 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30962   { 5751 /* global_load_dwordx4 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30966   { 5751 /* global_load_dwordx4 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30970   { 5771 /* global_load_sbyte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30974   { 5771 /* global_load_sbyte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30978   { 5771 /* global_load_sbyte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30982   { 5771 /* global_load_sbyte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30986   { 5789 /* global_load_sbyte_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30990   { 5789 /* global_load_sbyte_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
30994   { 5789 /* global_load_sbyte_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
30998   { 5789 /* global_load_sbyte_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31002   { 5811 /* global_load_sbyte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31006   { 5811 /* global_load_sbyte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31010   { 5811 /* global_load_sbyte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31014   { 5811 /* global_load_sbyte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31018   { 5836 /* global_load_short_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31022   { 5836 /* global_load_short_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31026   { 5836 /* global_load_short_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31030   { 5836 /* global_load_short_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31034   { 5858 /* global_load_short_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31038   { 5858 /* global_load_short_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31042   { 5858 /* global_load_short_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31046   { 5858 /* global_load_short_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31050   { 5883 /* global_load_sshort */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31054   { 5883 /* global_load_sshort */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31058   { 5883 /* global_load_sshort */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31062   { 5883 /* global_load_sshort */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31066   { 5902 /* global_load_ubyte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31070   { 5902 /* global_load_ubyte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31074   { 5902 /* global_load_ubyte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31078   { 5902 /* global_load_ubyte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31082   { 5920 /* global_load_ubyte_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31086   { 5920 /* global_load_ubyte_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31090   { 5920 /* global_load_ubyte_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31094   { 5920 /* global_load_ubyte_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31098   { 5942 /* global_load_ubyte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31102   { 5942 /* global_load_ubyte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31106   { 5942 /* global_load_ubyte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31110   { 5942 /* global_load_ubyte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31114   { 5967 /* global_load_ushort */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31118   { 5967 /* global_load_ushort */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31122   { 5967 /* global_load_ushort */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31126   { 5967 /* global_load_ushort */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31130   { 5986 /* global_store_byte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31134   { 5986 /* global_store_byte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31138   { 5986 /* global_store_byte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31142   { 5986 /* global_store_byte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31146   { 6004 /* global_store_byte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31150   { 6004 /* global_store_byte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31154   { 6004 /* global_store_byte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31158   { 6004 /* global_store_byte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31162   { 6029 /* global_store_dword */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31166   { 6029 /* global_store_dword */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31170   { 6029 /* global_store_dword */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31174   { 6029 /* global_store_dword */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31178   { 6048 /* global_store_dwordx2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31182   { 6048 /* global_store_dwordx2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31186   { 6048 /* global_store_dwordx2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31190   { 6048 /* global_store_dwordx2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31194   { 6069 /* global_store_dwordx3 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31198   { 6069 /* global_store_dwordx3 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31202   { 6069 /* global_store_dwordx3 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31206   { 6069 /* global_store_dwordx3 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31210   { 6090 /* global_store_dwordx4 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31214   { 6090 /* global_store_dwordx4 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31218   { 6090 /* global_store_dwordx4 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31222   { 6090 /* global_store_dwordx4 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31226   { 6111 /* global_store_short */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31230   { 6111 /* global_store_short */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31234   { 6111 /* global_store_short */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31238   { 6111 /* global_store_short */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31242   { 6130 /* global_store_short_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31246   { 6130 /* global_store_short_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
31250   { 6130 /* global_store_short_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX10Plus },
31254   { 6130 /* global_store_short_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatGlobalInsts_isGFX8GFX9 },
71096   { 12271 /* scratch_load_dword */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71100   { 12271 /* scratch_load_dword */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71104   { 12271 /* scratch_load_dword */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71108   { 12271 /* scratch_load_dword */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71112   { 12290 /* scratch_load_dwordx2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71116   { 12290 /* scratch_load_dwordx2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71120   { 12290 /* scratch_load_dwordx2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71124   { 12290 /* scratch_load_dwordx2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71128   { 12311 /* scratch_load_dwordx3 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71132   { 12311 /* scratch_load_dwordx3 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71136   { 12311 /* scratch_load_dwordx3 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71140   { 12311 /* scratch_load_dwordx3 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71144   { 12332 /* scratch_load_dwordx4 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71148   { 12332 /* scratch_load_dwordx4 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71152   { 12332 /* scratch_load_dwordx4 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71156   { 12332 /* scratch_load_dwordx4 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71160   { 12353 /* scratch_load_sbyte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71164   { 12353 /* scratch_load_sbyte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71168   { 12353 /* scratch_load_sbyte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71172   { 12353 /* scratch_load_sbyte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71176   { 12372 /* scratch_load_sbyte_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71180   { 12372 /* scratch_load_sbyte_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71184   { 12372 /* scratch_load_sbyte_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71188   { 12372 /* scratch_load_sbyte_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71192   { 12395 /* scratch_load_sbyte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71196   { 12395 /* scratch_load_sbyte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71200   { 12395 /* scratch_load_sbyte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71204   { 12395 /* scratch_load_sbyte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71208   { 12421 /* scratch_load_short_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71212   { 12421 /* scratch_load_short_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71216   { 12421 /* scratch_load_short_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71220   { 12421 /* scratch_load_short_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71224   { 12444 /* scratch_load_short_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71228   { 12444 /* scratch_load_short_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71232   { 12444 /* scratch_load_short_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71236   { 12444 /* scratch_load_short_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71240   { 12470 /* scratch_load_sshort */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71244   { 12470 /* scratch_load_sshort */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71248   { 12470 /* scratch_load_sshort */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71252   { 12470 /* scratch_load_sshort */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71256   { 12490 /* scratch_load_ubyte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71260   { 12490 /* scratch_load_ubyte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71264   { 12490 /* scratch_load_ubyte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71268   { 12490 /* scratch_load_ubyte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71272   { 12509 /* scratch_load_ubyte_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71276   { 12509 /* scratch_load_ubyte_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71280   { 12509 /* scratch_load_ubyte_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71284   { 12509 /* scratch_load_ubyte_d16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71288   { 12532 /* scratch_load_ubyte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71292   { 12532 /* scratch_load_ubyte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71296   { 12532 /* scratch_load_ubyte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71300   { 12532 /* scratch_load_ubyte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71304   { 12558 /* scratch_load_ushort */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71308   { 12558 /* scratch_load_ushort */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71312   { 12558 /* scratch_load_ushort */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71316   { 12558 /* scratch_load_ushort */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71320   { 12578 /* scratch_store_byte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71324   { 12578 /* scratch_store_byte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71328   { 12578 /* scratch_store_byte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71332   { 12578 /* scratch_store_byte */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71336   { 12597 /* scratch_store_byte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71340   { 12597 /* scratch_store_byte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71344   { 12597 /* scratch_store_byte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71348   { 12597 /* scratch_store_byte_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71352   { 12623 /* scratch_store_dword */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71356   { 12623 /* scratch_store_dword */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71360   { 12623 /* scratch_store_dword */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71364   { 12623 /* scratch_store_dword */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71368   { 12643 /* scratch_store_dwordx2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71372   { 12643 /* scratch_store_dwordx2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71376   { 12643 /* scratch_store_dwordx2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71380   { 12643 /* scratch_store_dwordx2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71384   { 12665 /* scratch_store_dwordx3 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71388   { 12665 /* scratch_store_dwordx3 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71392   { 12665 /* scratch_store_dwordx3 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71396   { 12665 /* scratch_store_dwordx3 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71400   { 12687 /* scratch_store_dwordx4 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71404   { 12687 /* scratch_store_dwordx4 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71408   { 12687 /* scratch_store_dwordx4 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71412   { 12687 /* scratch_store_dwordx4 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71416   { 12709 /* scratch_store_short */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71420   { 12709 /* scratch_store_short */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71424   { 12709 /* scratch_store_short */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71428   { 12709 /* scratch_store_short */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71432   { 12729 /* scratch_store_short_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71436   { 12729 /* scratch_store_short_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
71440   { 12729 /* scratch_store_short_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX10Plus },
71444   { 12729 /* scratch_store_short_d16_hi */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatScratchInsts_isGFX8GFX9 },
80315   case MCK_ImmFlatOffset: