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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 5264 case MCK_ImmFI:
6197 case MCK_ImmFI: {
10170 case MCK_ImmFI: return "MCK_ImmFI";
23559 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23560 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_dpp8_w64_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPP8, MCK_ImmFI }, },
23561 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_dpp8_w32_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPP8, MCK_ImmFI }, },
23562 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23563 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_dpp_w64_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23564 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_dpp_w32_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23568 { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23570 { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23571 { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23573 { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23574 { 13355 /* v_add_nc_u32 */, AMDGPU::V_ADD_NC_U32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23575 { 13355 /* v_add_nc_u32 */, AMDGPU::V_ADD_NC_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23583 { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23585 { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23587 { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23589 { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23590 { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23592 { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23593 { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23595 { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23596 { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23598 { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23605 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23606 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp8_w64_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPP8, MCK_ImmFI }, },
23607 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp8_w32_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPP8, MCK_ImmFI }, },
23609 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23610 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp_w64_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23611 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp_w32_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23612 { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23614 { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23615 { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23617 { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23618 { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23620 { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23621 { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23623 { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23624 { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23626 { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23627 { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23629 { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23630 { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23632 { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23633 { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23635 { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23636 { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23638 { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23639 { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23641 { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23642 { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23644 { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23645 { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23647 { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23648 { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23650 { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23651 { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23653 { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23654 { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23656 { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23657 { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23659 { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23660 { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23662 { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23663 { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23665 { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23666 { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23668 { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23669 { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23671 { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23672 { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23674 { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23675 { 22781 /* v_dot2c_f32_f16 */, AMDGPU::V_DOT2C_F32_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDot5Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23677 { 22781 /* v_dot2c_f32_f16 */, AMDGPU::V_DOT2C_F32_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDot5Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23679 { 22841 /* v_dot4c_i32_i8 */, AMDGPU::V_DOT4C_I32_I8_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDot6Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23681 { 22841 /* v_dot4c_i32_i8 */, AMDGPU::V_DOT4C_I32_I8_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDot6Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithIntInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23683 { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23685 { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23686 { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23688 { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23690 { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23692 { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23693 { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23695 { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23696 { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23698 { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23699 { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23701 { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23702 { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23704 { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23705 { 23122 /* v_fmac_f16 */, AMDGPU::V_FMAC_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23706 { 23122 /* v_fmac_f16 */, AMDGPU::V_FMAC_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23707 { 23133 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23709 { 23133 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23710 { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23712 { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23713 { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23715 { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23716 { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23718 { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23719 { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23721 { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23722 { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23724 { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23725 { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23727 { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23728 { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23730 { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23731 { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23733 { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23734 { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23736 { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23739 { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23741 { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23743 { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23745 { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23747 { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23749 { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23750 { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23751 { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23752 { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23754 { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23755 { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23757 { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23759 { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23761 { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23763 { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23765 { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23766 { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23768 { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23769 { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23771 { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23773 { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23775 { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23777 { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23779 { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23780 { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23782 { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23783 { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23785 { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23786 { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23788 { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23789 { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23791 { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23792 { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23794 { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23795 { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23797 { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23798 { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23800 { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23801 { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23803 { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23805 { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23807 { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23808 { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23810 { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23811 { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23813 { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23814 { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23816 { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23817 { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23819 { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23820 { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23822 { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23823 { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23825 { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23826 { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23828 { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23829 { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23831 { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23832 { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23834 { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23835 { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23837 { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23839 { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23841 { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23842 { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23844 { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23845 { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23847 { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23848 { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23850 { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23853 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23854 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_dpp8_w64_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPP8, MCK_ImmFI }, },
23855 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_dpp8_w32_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPP8, MCK_ImmFI }, },
23856 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23857 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_dpp_w64_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23858 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_dpp_w32_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23862 { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23864 { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23865 { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23867 { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23868 { 26067 /* v_sub_nc_u32 */, AMDGPU::V_SUB_NC_U32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23869 { 26067 /* v_sub_nc_u32 */, AMDGPU::V_SUB_NC_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23883 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23884 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_dpp8_w64_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPP8, MCK_ImmFI }, },
23885 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_dpp8_w32_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPP8, MCK_ImmFI }, },
23886 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23887 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_dpp_w64_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23888 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_dpp_w32_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23892 { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23894 { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23895 { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23897 { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23898 { 26230 /* v_subrev_nc_u32 */, AMDGPU::V_SUBREV_NC_U32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23899 { 26230 /* v_subrev_nc_u32 */, AMDGPU::V_SUBREV_NC_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23903 { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23905 { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23906 { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23908 { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23909 { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23911 { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23912 { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23914 { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
72849 { 13222 /* v_add_co_ci_u32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
72853 { 13222 /* v_add_co_ci_u32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus_isWave64 },
72855 { 13222 /* v_add_co_ci_u32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus_isWave32 },
72860 { 13222 /* v_add_co_ci_u32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
72871 { 13222 /* v_add_co_ci_u32 */, 512 /* 9 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus_isWave64 },
72882 { 13222 /* v_add_co_ci_u32 */, 512 /* 9 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus_isWave32 },
72904 { 13251 /* v_add_f16 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
72927 { 13251 /* v_add_f16 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
72943 { 13261 /* v_add_f32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
72969 { 13261 /* v_add_f32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
73001 { 13355 /* v_add_nc_u32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
73006 { 13355 /* v_add_nc_u32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
73079 { 13444 /* v_and_b32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
73088 { 13444 /* v_and_b32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
73124 { 13503 /* v_ashrrev_i32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
73133 { 13503 /* v_ashrrev_i32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
73153 { 13586 /* v_bfrev_b32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
73177 { 13586 /* v_bfrev_b32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
73179 { 13598 /* v_ceil_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
73213 { 13598 /* v_ceil_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
73215 { 13609 /* v_ceil_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
73252 { 13609 /* v_ceil_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
75916 { 21959 /* v_cndmask_b32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
75918 { 21959 /* v_cndmask_b32 */, 32 /* 5 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus_isWave64 },
75920 { 21959 /* v_cndmask_b32 */, 32 /* 5 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus_isWave32 },
75929 { 21959 /* v_cndmask_b32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
75940 { 21959 /* v_cndmask_b32 */, 256 /* 8 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus_isWave64 },
75945 { 21959 /* v_cndmask_b32 */, 256 /* 8 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus_isWave32 },
75971 { 21973 /* v_cos_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76005 { 21973 /* v_cos_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76007 { 21983 /* v_cos_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76044 { 21983 /* v_cos_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76082 { 22045 /* v_cvt_f16_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76119 { 22045 /* v_cvt_f16_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76121 { 22059 /* v_cvt_f16_i16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76139 { 22059 /* v_cvt_f16_i16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76153 { 22073 /* v_cvt_f16_u16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76171 { 22073 /* v_cvt_f16_u16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76185 { 22087 /* v_cvt_f32_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76222 { 22087 /* v_cvt_f32_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76233 { 22115 /* v_cvt_f32_i32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76253 { 22115 /* v_cvt_f32_i32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76267 { 22129 /* v_cvt_f32_u32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76287 { 22129 /* v_cvt_f32_u32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76301 { 22143 /* v_cvt_f32_ubyte0 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76321 { 22143 /* v_cvt_f32_ubyte0 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76335 { 22160 /* v_cvt_f32_ubyte1 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76355 { 22160 /* v_cvt_f32_ubyte1 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76369 { 22177 /* v_cvt_f32_ubyte2 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76389 { 22177 /* v_cvt_f32_ubyte2 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76403 { 22194 /* v_cvt_f32_ubyte3 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76423 { 22194 /* v_cvt_f32_ubyte3 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76464 { 22253 /* v_cvt_flr_i32_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76490 { 22253 /* v_cvt_flr_i32_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76496 { 22271 /* v_cvt_i16_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76522 { 22271 /* v_cvt_i16_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76530 { 22285 /* v_cvt_i32_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76556 { 22285 /* v_cvt_i32_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76568 { 22313 /* v_cvt_norm_i16_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76594 { 22313 /* v_cvt_norm_i16_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76600 { 22332 /* v_cvt_norm_u16_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76626 { 22332 /* v_cvt_norm_u16_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76628 { 22351 /* v_cvt_off_f32_i4 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76648 { 22351 /* v_cvt_off_f32_i4 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76716 { 22543 /* v_cvt_rpi_i32_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76742 { 22543 /* v_cvt_rpi_i32_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76748 { 22561 /* v_cvt_u16_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76774 { 22561 /* v_cvt_u16_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76782 { 22575 /* v_cvt_u32_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76808 { 22575 /* v_cvt_u32_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76900 { 22781 /* v_dot2c_f32_f16 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDot5Insts_isGFX10Plus },
76911 { 22781 /* v_dot2c_f32_f16 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDot5Insts_isGFX10Plus },
76938 { 22841 /* v_dot4c_i32_i8 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDot6Insts_isGFX10Plus },
76949 { 22841 /* v_dot4c_i32_i8 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDot6Insts_isGFX10Plus },
76976 { 22899 /* v_exp_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77010 { 22899 /* v_exp_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77012 { 22909 /* v_exp_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77049 { 22909 /* v_exp_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77073 { 22936 /* v_ffbh_i32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77097 { 22936 /* v_ffbh_i32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77099 { 22947 /* v_ffbh_u32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77123 { 22947 /* v_ffbh_u32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77125 { 22958 /* v_ffbl_b32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77149 { 22958 /* v_ffbl_b32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77151 { 22969 /* v_floor_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77185 { 22969 /* v_floor_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77187 { 22981 /* v_floor_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77224 { 22981 /* v_floor_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77291 { 23122 /* v_fmac_f16 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77300 { 23122 /* v_fmac_f16 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77302 { 23133 /* v_fmac_f32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77325 { 23133 /* v_fmac_f32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77329 { 23168 /* v_fract_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77363 { 23168 /* v_fract_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77365 { 23180 /* v_fract_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77402 { 23180 /* v_fract_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77417 { 23204 /* v_frexp_exp_i16_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77443 { 23204 /* v_frexp_exp_i16_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77451 { 23224 /* v_frexp_exp_i32_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77477 { 23224 /* v_frexp_exp_i32_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77485 { 23264 /* v_frexp_mant_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77519 { 23264 /* v_frexp_mant_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77521 { 23281 /* v_frexp_mant_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77558 { 23281 /* v_frexp_mant_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77646 { 23439 /* v_ldexp_f16 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77674 { 23439 /* v_ldexp_f16 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77719 { 23501 /* v_log_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77753 { 23501 /* v_log_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77755 { 23511 /* v_log_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77792 { 23511 /* v_log_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77832 { 23603 /* v_lshlrev_b32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77841 { 23603 /* v_lshlrev_b32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77877 { 23667 /* v_lshrrev_b32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77886 { 23667 /* v_lshrrev_b32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77920 { 23705 /* v_mac_f32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77946 { 23705 /* v_mac_f32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77948 { 23715 /* v_mac_legacy_f32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77960 { 23715 /* v_mac_legacy_f32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78077 { 24084 /* v_max_f16 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78100 { 24084 /* v_max_f16 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78116 { 24094 /* v_max_f32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78142 { 24094 /* v_max_f32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78183 { 24124 /* v_max_i32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78192 { 24124 /* v_max_i32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78231 { 24161 /* v_max_u32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78240 { 24161 /* v_max_u32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78366 { 24775 /* v_min_f16 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78389 { 24775 /* v_min_f16 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78405 { 24785 /* v_min_f32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78431 { 24785 /* v_min_f32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78472 { 24815 /* v_min_i32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78481 { 24815 /* v_min_i32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78520 { 24852 /* v_min_u32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78529 { 24852 /* v_min_u32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78549 { 24862 /* v_mov_b32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78573 { 24862 /* v_mov_b32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78575 { 24872 /* v_mov_fed_b32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78599 { 24872 /* v_mov_fed_b32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78610 { 24989 /* v_mul_f16 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78633 { 24989 /* v_mul_f16 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78649 { 24999 /* v_mul_f32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78675 { 24999 /* v_mul_f32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78700 { 25032 /* v_mul_hi_i32_i24 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78709 { 25032 /* v_mul_hi_i32_i24 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78729 { 25062 /* v_mul_hi_u32_u24 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78738 { 25062 /* v_mul_hi_u32_u24 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78758 { 25079 /* v_mul_i32_i24 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78767 { 25079 /* v_mul_i32_i24 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78787 { 25093 /* v_mul_legacy_f32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78813 { 25093 /* v_mul_legacy_f32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78845 { 25149 /* v_mul_u32_u24 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78854 { 25149 /* v_mul_u32_u24 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78880 { 25182 /* v_not_b32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78904 { 25182 /* v_not_b32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78906 { 25202 /* v_or_b32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78915 { 25202 /* v_or_b32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79142 { 25609 /* v_rcp_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79176 { 25609 /* v_rcp_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79178 { 25619 /* v_rcp_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79215 { 25619 /* v_rcp_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79226 { 25639 /* v_rcp_iflag_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79263 { 25639 /* v_rcp_iflag_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79268 { 25707 /* v_rndne_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79302 { 25707 /* v_rndne_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79304 { 25719 /* v_rndne_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79341 { 25719 /* v_rndne_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79358 { 25775 /* v_rsq_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79392 { 25775 /* v_rsq_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79394 { 25785 /* v_rsq_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79431 { 25785 /* v_rsq_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79457 { 25863 /* v_sat_pk_u8_i16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79481 { 25863 /* v_sat_pk_u8_i16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79492 { 25906 /* v_sin_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79526 { 25906 /* v_sin_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79528 { 25916 /* v_sin_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79565 { 25916 /* v_sin_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79567 { 25926 /* v_sqrt_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79601 { 25926 /* v_sqrt_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79603 { 25937 /* v_sqrt_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79640 { 25937 /* v_sqrt_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79651 { 25959 /* v_sub_co_ci_u32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79655 { 25959 /* v_sub_co_ci_u32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus_isWave64 },
79657 { 25959 /* v_sub_co_ci_u32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus_isWave32 },
79662 { 25959 /* v_sub_co_ci_u32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79673 { 25959 /* v_sub_co_ci_u32 */, 512 /* 9 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus_isWave64 },
79684 { 25959 /* v_sub_co_ci_u32 */, 512 /* 9 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus_isWave32 },
79706 { 25988 /* v_sub_f16 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79729 { 25988 /* v_sub_f16 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79745 { 25998 /* v_sub_f32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79771 { 25998 /* v_sub_f32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79794 { 26067 /* v_sub_nc_u32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79799 { 26067 /* v_sub_nc_u32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79898 { 26156 /* v_subrev_co_ci_u32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79902 { 26156 /* v_subrev_co_ci_u32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus_isWave64 },
79904 { 26156 /* v_subrev_co_ci_u32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus_isWave32 },
79909 { 26156 /* v_subrev_co_ci_u32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79920 { 26156 /* v_subrev_co_ci_u32 */, 512 /* 9 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus_isWave64 },
79931 { 26156 /* v_subrev_co_ci_u32 */, 512 /* 9 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus_isWave32 },
79953 { 26191 /* v_subrev_f16 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79976 { 26191 /* v_subrev_f16 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79992 { 26204 /* v_subrev_f32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
80018 { 26204 /* v_subrev_f32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
80037 { 26230 /* v_subrev_nc_u32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
80042 { 26230 /* v_subrev_nc_u32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
80101 { 26314 /* v_trunc_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
80135 { 26314 /* v_trunc_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
80137 { 26326 /* v_trunc_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
80174 { 26326 /* v_trunc_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
80185 { 26376 /* v_xnor_b32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
80194 { 26376 /* v_xnor_b32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
80214 { 26398 /* v_xor_b32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
80223 { 26398 /* v_xor_b32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
80371 case MCK_ImmFI: