reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

 5207   case MCK_ImmClampSI:
 6043   case MCK_ImmClampSI: {
10148   case MCK_ImmClampSI: return "MCK_ImmClampSI";
21442   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
21445   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21446   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21447   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21448   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21449   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21450   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21451   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21452   { 13271 /* v_add_f64 */, AMDGPU::V_ADD_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21453   { 13271 /* v_add_f64 */, AMDGPU::V_ADD_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21454   { 13271 /* v_add_f64 */, AMDGPU::V_ADD_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21455   { 13281 /* v_add_i16 */, AMDGPU::V_ADD_I16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
21457   { 13291 /* v_add_i32 */, AMDGPU::V_ADD_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21460   { 13316 /* v_add_nc_i16 */, AMDGPU::V_ADD_NC_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
21463   { 13355 /* v_add_nc_u32 */, AMDGPU::V_ADD_NC_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21465   { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21466   { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
21469   { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
21470   { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
21471   { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
21510   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21511   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21512   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21513   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21514   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21515   { 13620 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21516   { 13620 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e64_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21517   { 13620 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
21529   { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21530   { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21531   { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21532   { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21533   { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21534   { 13809 /* v_cmp_eq_f64 */, AMDGPU::V_CMP_EQ_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21535   { 13809 /* v_cmp_eq_f64 */, AMDGPU::V_CMP_EQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21536   { 13809 /* v_cmp_eq_f64 */, AMDGPU::V_CMP_EQ_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21553   { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21554   { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21555   { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21556   { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21557   { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21558   { 14075 /* v_cmp_f_f64 */, AMDGPU::V_CMP_F_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21559   { 14075 /* v_cmp_f_f64 */, AMDGPU::V_CMP_F_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21560   { 14075 /* v_cmp_f_f64 */, AMDGPU::V_CMP_F_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21575   { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21576   { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21577   { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21578   { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21579   { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21580   { 14331 /* v_cmp_ge_f64 */, AMDGPU::V_CMP_GE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21581   { 14331 /* v_cmp_ge_f64 */, AMDGPU::V_CMP_GE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21582   { 14331 /* v_cmp_ge_f64 */, AMDGPU::V_CMP_GE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21599   { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21600   { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21601   { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21602   { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21603   { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21604   { 14601 /* v_cmp_gt_f64 */, AMDGPU::V_CMP_GT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21605   { 14601 /* v_cmp_gt_f64 */, AMDGPU::V_CMP_GT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21606   { 14601 /* v_cmp_gt_f64 */, AMDGPU::V_CMP_GT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21623   { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21624   { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21625   { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21626   { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21627   { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21628   { 14871 /* v_cmp_le_f64 */, AMDGPU::V_CMP_LE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21629   { 14871 /* v_cmp_le_f64 */, AMDGPU::V_CMP_LE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21630   { 14871 /* v_cmp_le_f64 */, AMDGPU::V_CMP_LE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21647   { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21648   { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21649   { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21650   { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21651   { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21652   { 15141 /* v_cmp_lg_f64 */, AMDGPU::V_CMP_LG_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21653   { 15141 /* v_cmp_lg_f64 */, AMDGPU::V_CMP_LG_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21654   { 15141 /* v_cmp_lg_f64 */, AMDGPU::V_CMP_LG_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21655   { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21656   { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21657   { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21658   { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21659   { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21660   { 15231 /* v_cmp_lt_f64 */, AMDGPU::V_CMP_LT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21661   { 15231 /* v_cmp_lt_f64 */, AMDGPU::V_CMP_LT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21662   { 15231 /* v_cmp_lt_f64 */, AMDGPU::V_CMP_LT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21695   { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21696   { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21697   { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21698   { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21699   { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21700   { 15685 /* v_cmp_neq_f64 */, AMDGPU::V_CMP_NEQ_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21701   { 15685 /* v_cmp_neq_f64 */, AMDGPU::V_CMP_NEQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21702   { 15685 /* v_cmp_neq_f64 */, AMDGPU::V_CMP_NEQ_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21703   { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21704   { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21705   { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21706   { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21707   { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21708   { 15781 /* v_cmp_nge_f64 */, AMDGPU::V_CMP_NGE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21709   { 15781 /* v_cmp_nge_f64 */, AMDGPU::V_CMP_NGE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21710   { 15781 /* v_cmp_nge_f64 */, AMDGPU::V_CMP_NGE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21711   { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21712   { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21713   { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21714   { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21715   { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21716   { 15877 /* v_cmp_ngt_f64 */, AMDGPU::V_CMP_NGT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21717   { 15877 /* v_cmp_ngt_f64 */, AMDGPU::V_CMP_NGT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21718   { 15877 /* v_cmp_ngt_f64 */, AMDGPU::V_CMP_NGT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21719   { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21720   { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21721   { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21722   { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21723   { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21724   { 15973 /* v_cmp_nle_f64 */, AMDGPU::V_CMP_NLE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21725   { 15973 /* v_cmp_nle_f64 */, AMDGPU::V_CMP_NLE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21726   { 15973 /* v_cmp_nle_f64 */, AMDGPU::V_CMP_NLE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21727   { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21728   { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21729   { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21730   { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21731   { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21732   { 16069 /* v_cmp_nlg_f64 */, AMDGPU::V_CMP_NLG_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21733   { 16069 /* v_cmp_nlg_f64 */, AMDGPU::V_CMP_NLG_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21734   { 16069 /* v_cmp_nlg_f64 */, AMDGPU::V_CMP_NLG_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21735   { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21736   { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21737   { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21738   { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21739   { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21740   { 16165 /* v_cmp_nlt_f64 */, AMDGPU::V_CMP_NLT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21741   { 16165 /* v_cmp_nlt_f64 */, AMDGPU::V_CMP_NLT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21742   { 16165 /* v_cmp_nlt_f64 */, AMDGPU::V_CMP_NLT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21743   { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21744   { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21745   { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21746   { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21747   { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21748   { 16253 /* v_cmp_o_f64 */, AMDGPU::V_CMP_O_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21749   { 16253 /* v_cmp_o_f64 */, AMDGPU::V_CMP_O_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21750   { 16253 /* v_cmp_o_f64 */, AMDGPU::V_CMP_O_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21765   { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21766   { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21767   { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21768   { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21769   { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21770   { 16513 /* v_cmp_tru_f64 */, AMDGPU::V_CMP_TRU_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21771   { 16513 /* v_cmp_tru_f64 */, AMDGPU::V_CMP_TRU_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21772   { 16513 /* v_cmp_tru_f64 */, AMDGPU::V_CMP_TRU_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21773   { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21774   { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21775   { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21776   { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21777   { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21778   { 16601 /* v_cmp_u_f64 */, AMDGPU::V_CMP_U_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21779   { 16601 /* v_cmp_u_f64 */, AMDGPU::V_CMP_U_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21780   { 16601 /* v_cmp_u_f64 */, AMDGPU::V_CMP_U_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21781   { 16629 /* v_cmps_eq_f32 */, AMDGPU::V_CMPS_EQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21782   { 16661 /* v_cmps_eq_f64 */, AMDGPU::V_CMPS_EQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21783   { 16693 /* v_cmps_f_f32 */, AMDGPU::V_CMPS_F_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21784   { 16723 /* v_cmps_f_f64 */, AMDGPU::V_CMPS_F_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21785   { 16753 /* v_cmps_ge_f32 */, AMDGPU::V_CMPS_GE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21786   { 16785 /* v_cmps_ge_f64 */, AMDGPU::V_CMPS_GE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21787   { 16817 /* v_cmps_gt_f32 */, AMDGPU::V_CMPS_GT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21788   { 16849 /* v_cmps_gt_f64 */, AMDGPU::V_CMPS_GT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21789   { 16881 /* v_cmps_le_f32 */, AMDGPU::V_CMPS_LE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21790   { 16913 /* v_cmps_le_f64 */, AMDGPU::V_CMPS_LE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21791   { 16945 /* v_cmps_lg_f32 */, AMDGPU::V_CMPS_LG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21792   { 16977 /* v_cmps_lg_f64 */, AMDGPU::V_CMPS_LG_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21793   { 17009 /* v_cmps_lt_f32 */, AMDGPU::V_CMPS_LT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21794   { 17041 /* v_cmps_lt_f64 */, AMDGPU::V_CMPS_LT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21795   { 17073 /* v_cmps_neq_f32 */, AMDGPU::V_CMPS_NEQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21796   { 17107 /* v_cmps_neq_f64 */, AMDGPU::V_CMPS_NEQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21797   { 17141 /* v_cmps_nge_f32 */, AMDGPU::V_CMPS_NGE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21798   { 17175 /* v_cmps_nge_f64 */, AMDGPU::V_CMPS_NGE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21799   { 17209 /* v_cmps_ngt_f32 */, AMDGPU::V_CMPS_NGT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21800   { 17243 /* v_cmps_ngt_f64 */, AMDGPU::V_CMPS_NGT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21801   { 17277 /* v_cmps_nle_f32 */, AMDGPU::V_CMPS_NLE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21802   { 17311 /* v_cmps_nle_f64 */, AMDGPU::V_CMPS_NLE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21803   { 17345 /* v_cmps_nlg_f32 */, AMDGPU::V_CMPS_NLG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21804   { 17379 /* v_cmps_nlg_f64 */, AMDGPU::V_CMPS_NLG_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21805   { 17413 /* v_cmps_nlt_f32 */, AMDGPU::V_CMPS_NLT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21806   { 17447 /* v_cmps_nlt_f64 */, AMDGPU::V_CMPS_NLT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21807   { 17481 /* v_cmps_o_f32 */, AMDGPU::V_CMPS_O_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21808   { 17511 /* v_cmps_o_f64 */, AMDGPU::V_CMPS_O_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21809   { 17541 /* v_cmps_tru_f32 */, AMDGPU::V_CMPS_TRU_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21810   { 17575 /* v_cmps_tru_f64 */, AMDGPU::V_CMPS_TRU_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21811   { 17609 /* v_cmps_u_f32 */, AMDGPU::V_CMPS_U_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21812   { 17639 /* v_cmps_u_f64 */, AMDGPU::V_CMPS_U_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21813   { 17669 /* v_cmpsx_eq_f32 */, AMDGPU::V_CMPSX_EQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21814   { 17703 /* v_cmpsx_eq_f64 */, AMDGPU::V_CMPSX_EQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21815   { 17737 /* v_cmpsx_f_f32 */, AMDGPU::V_CMPSX_F_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21816   { 17769 /* v_cmpsx_f_f64 */, AMDGPU::V_CMPSX_F_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21817   { 17801 /* v_cmpsx_ge_f32 */, AMDGPU::V_CMPSX_GE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21818   { 17835 /* v_cmpsx_ge_f64 */, AMDGPU::V_CMPSX_GE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21819   { 17869 /* v_cmpsx_gt_f32 */, AMDGPU::V_CMPSX_GT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21820   { 17903 /* v_cmpsx_gt_f64 */, AMDGPU::V_CMPSX_GT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21821   { 17937 /* v_cmpsx_le_f32 */, AMDGPU::V_CMPSX_LE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21822   { 17971 /* v_cmpsx_le_f64 */, AMDGPU::V_CMPSX_LE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21823   { 18005 /* v_cmpsx_lg_f32 */, AMDGPU::V_CMPSX_LG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21824   { 18039 /* v_cmpsx_lg_f64 */, AMDGPU::V_CMPSX_LG_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21825   { 18073 /* v_cmpsx_lt_f32 */, AMDGPU::V_CMPSX_LT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21826   { 18107 /* v_cmpsx_lt_f64 */, AMDGPU::V_CMPSX_LT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21827   { 18141 /* v_cmpsx_neq_f32 */, AMDGPU::V_CMPSX_NEQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21828   { 18177 /* v_cmpsx_neq_f64 */, AMDGPU::V_CMPSX_NEQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21829   { 18213 /* v_cmpsx_nge_f32 */, AMDGPU::V_CMPSX_NGE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21830   { 18249 /* v_cmpsx_nge_f64 */, AMDGPU::V_CMPSX_NGE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21831   { 18285 /* v_cmpsx_ngt_f32 */, AMDGPU::V_CMPSX_NGT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21832   { 18321 /* v_cmpsx_ngt_f64 */, AMDGPU::V_CMPSX_NGT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21833   { 18357 /* v_cmpsx_nle_f32 */, AMDGPU::V_CMPSX_NLE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21834   { 18393 /* v_cmpsx_nle_f64 */, AMDGPU::V_CMPSX_NLE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21835   { 18429 /* v_cmpsx_nlg_f32 */, AMDGPU::V_CMPSX_NLG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21836   { 18465 /* v_cmpsx_nlg_f64 */, AMDGPU::V_CMPSX_NLG_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21837   { 18501 /* v_cmpsx_nlt_f32 */, AMDGPU::V_CMPSX_NLT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21838   { 18537 /* v_cmpsx_nlt_f64 */, AMDGPU::V_CMPSX_NLT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21839   { 18573 /* v_cmpsx_o_f32 */, AMDGPU::V_CMPSX_O_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21840   { 18605 /* v_cmpsx_o_f64 */, AMDGPU::V_CMPSX_O_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21841   { 18637 /* v_cmpsx_tru_f32 */, AMDGPU::V_CMPSX_TRU_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21842   { 18673 /* v_cmpsx_tru_f64 */, AMDGPU::V_CMPSX_TRU_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21843   { 18709 /* v_cmpsx_u_f32 */, AMDGPU::V_CMPSX_U_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21844   { 18741 /* v_cmpsx_u_f64 */, AMDGPU::V_CMPSX_U_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21853   { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21854   { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21855   { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21856   { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21857   { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21858   { 18951 /* v_cmpx_eq_f64 */, AMDGPU::V_CMPX_EQ_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21859   { 18951 /* v_cmpx_eq_f64 */, AMDGPU::V_CMPX_EQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21860   { 18951 /* v_cmpx_eq_f64 */, AMDGPU::V_CMPX_EQ_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21877   { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21878   { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21879   { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21880   { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21881   { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21882   { 19235 /* v_cmpx_f_f64 */, AMDGPU::V_CMPX_F_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21883   { 19235 /* v_cmpx_f_f64 */, AMDGPU::V_CMPX_F_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21884   { 19235 /* v_cmpx_f_f64 */, AMDGPU::V_CMPX_F_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21899   { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21900   { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21901   { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21902   { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21903   { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21904   { 19509 /* v_cmpx_ge_f64 */, AMDGPU::V_CMPX_GE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21905   { 19509 /* v_cmpx_ge_f64 */, AMDGPU::V_CMPX_GE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21906   { 19509 /* v_cmpx_ge_f64 */, AMDGPU::V_CMPX_GE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21923   { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21924   { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21925   { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21926   { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21927   { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21928   { 19797 /* v_cmpx_gt_f64 */, AMDGPU::V_CMPX_GT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21929   { 19797 /* v_cmpx_gt_f64 */, AMDGPU::V_CMPX_GT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21930   { 19797 /* v_cmpx_gt_f64 */, AMDGPU::V_CMPX_GT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21947   { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21948   { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21949   { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21950   { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21951   { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21952   { 20085 /* v_cmpx_le_f64 */, AMDGPU::V_CMPX_LE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21953   { 20085 /* v_cmpx_le_f64 */, AMDGPU::V_CMPX_LE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21954   { 20085 /* v_cmpx_le_f64 */, AMDGPU::V_CMPX_LE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21971   { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21972   { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21973   { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21974   { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21975   { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21976   { 20373 /* v_cmpx_lg_f64 */, AMDGPU::V_CMPX_LG_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21977   { 20373 /* v_cmpx_lg_f64 */, AMDGPU::V_CMPX_LG_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21978   { 20373 /* v_cmpx_lg_f64 */, AMDGPU::V_CMPX_LG_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21979   { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21980   { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
21981   { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21982   { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21983   { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
21984   { 20469 /* v_cmpx_lt_f64 */, AMDGPU::V_CMPX_LT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21985   { 20469 /* v_cmpx_lt_f64 */, AMDGPU::V_CMPX_LT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
21986   { 20469 /* v_cmpx_lt_f64 */, AMDGPU::V_CMPX_LT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22019   { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22020   { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22021   { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22022   { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22023   { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22024   { 20953 /* v_cmpx_neq_f64 */, AMDGPU::V_CMPX_NEQ_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22025   { 20953 /* v_cmpx_neq_f64 */, AMDGPU::V_CMPX_NEQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22026   { 20953 /* v_cmpx_neq_f64 */, AMDGPU::V_CMPX_NEQ_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22027   { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22028   { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22029   { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22030   { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22031   { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22032   { 21055 /* v_cmpx_nge_f64 */, AMDGPU::V_CMPX_NGE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22033   { 21055 /* v_cmpx_nge_f64 */, AMDGPU::V_CMPX_NGE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22034   { 21055 /* v_cmpx_nge_f64 */, AMDGPU::V_CMPX_NGE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22035   { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22036   { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22037   { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22038   { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22039   { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22040   { 21157 /* v_cmpx_ngt_f64 */, AMDGPU::V_CMPX_NGT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22041   { 21157 /* v_cmpx_ngt_f64 */, AMDGPU::V_CMPX_NGT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22042   { 21157 /* v_cmpx_ngt_f64 */, AMDGPU::V_CMPX_NGT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22043   { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22044   { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22045   { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22046   { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22047   { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22048   { 21259 /* v_cmpx_nle_f64 */, AMDGPU::V_CMPX_NLE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22049   { 21259 /* v_cmpx_nle_f64 */, AMDGPU::V_CMPX_NLE_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22050   { 21259 /* v_cmpx_nle_f64 */, AMDGPU::V_CMPX_NLE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22051   { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22052   { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22053   { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22054   { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22055   { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22056   { 21361 /* v_cmpx_nlg_f64 */, AMDGPU::V_CMPX_NLG_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22057   { 21361 /* v_cmpx_nlg_f64 */, AMDGPU::V_CMPX_NLG_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22058   { 21361 /* v_cmpx_nlg_f64 */, AMDGPU::V_CMPX_NLG_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22059   { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22060   { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22061   { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22062   { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22063   { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22064   { 21463 /* v_cmpx_nlt_f64 */, AMDGPU::V_CMPX_NLT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22065   { 21463 /* v_cmpx_nlt_f64 */, AMDGPU::V_CMPX_NLT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22066   { 21463 /* v_cmpx_nlt_f64 */, AMDGPU::V_CMPX_NLT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22067   { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22068   { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22069   { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22070   { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22071   { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22072   { 21557 /* v_cmpx_o_f64 */, AMDGPU::V_CMPX_O_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22073   { 21557 /* v_cmpx_o_f64 */, AMDGPU::V_CMPX_O_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22074   { 21557 /* v_cmpx_o_f64 */, AMDGPU::V_CMPX_O_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22089   { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22090   { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22091   { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22092   { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22093   { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22094   { 21835 /* v_cmpx_tru_f64 */, AMDGPU::V_CMPX_TRU_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22095   { 21835 /* v_cmpx_tru_f64 */, AMDGPU::V_CMPX_TRU_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22096   { 21835 /* v_cmpx_tru_f64 */, AMDGPU::V_CMPX_TRU_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22097   { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22098   { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22099   { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22100   { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22101   { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22102   { 21929 /* v_cmpx_u_f64 */, AMDGPU::V_CMPX_U_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasNoSdstCMPX_isGFX10Plus, { MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22103   { 21929 /* v_cmpx_u_f64 */, AMDGPU::V_CMPX_U_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22104   { 21929 /* v_cmpx_u_f64 */, AMDGPU::V_CMPX_U_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_BoolReg, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22114   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22115   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22116   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22117   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22118   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22119   { 21993 /* v_cubeid_f32 */, AMDGPU::V_CUBEID_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22120   { 21993 /* v_cubeid_f32 */, AMDGPU::V_CUBEID_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22121   { 21993 /* v_cubeid_f32 */, AMDGPU::V_CUBEID_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22122   { 22006 /* v_cubema_f32 */, AMDGPU::V_CUBEMA_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22123   { 22006 /* v_cubema_f32 */, AMDGPU::V_CUBEMA_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22124   { 22006 /* v_cubema_f32 */, AMDGPU::V_CUBEMA_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22125   { 22019 /* v_cubesc_f32 */, AMDGPU::V_CUBESC_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22126   { 22019 /* v_cubesc_f32 */, AMDGPU::V_CUBESC_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22127   { 22019 /* v_cubesc_f32 */, AMDGPU::V_CUBESC_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22128   { 22032 /* v_cubetc_f32 */, AMDGPU::V_CUBETC_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22129   { 22032 /* v_cubetc_f32 */, AMDGPU::V_CUBETC_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22130   { 22032 /* v_cubetc_f32 */, AMDGPU::V_CUBETC_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22131   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22132   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22133   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22134   { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_ImmClampSI, MCK_ImmOModSI }, },
22135   { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_ImmClampSI, MCK_ImmOModSI }, },
22136   { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_ImmClampSI, MCK_ImmOModSI }, },
22137   { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_ImmClampSI, MCK_ImmOModSI }, },
22138   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22139   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22140   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22141   { 22101 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22142   { 22101 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22143   { 22101 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22144   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22145   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22146   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22147   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22148   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22149   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22150   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22151   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22152   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22153   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22154   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22155   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22156   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22157   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22158   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22159   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22160   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22161   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22162   { 22211 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22163   { 22211 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22164   { 22211 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22165   { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22166   { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22167   { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22168   { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22169   { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22170   { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22171   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22172   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22173   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22174   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22175   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22176   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22177   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22178   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22179   { 22299 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22180   { 22299 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22181   { 22299 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22182   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22183   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22184   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22185   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22186   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22187   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22188   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
22195   { 22402 /* v_cvt_pk_u8_f32 */, AMDGPU::V_CVT_PK_U8_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, },
22196   { 22402 /* v_cvt_pk_u8_f32 */, AMDGPU::V_CVT_PK_U8_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, },
22197   { 22402 /* v_cvt_pk_u8_f32 */, AMDGPU::V_CVT_PK_U8_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, },
22199   { 22418 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, },
22200   { 22418 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, },
22201   { 22439 /* v_cvt_pknorm_i16_f16 */, AMDGPU::V_CVT_PKNORM_I16_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22202   { 22439 /* v_cvt_pknorm_i16_f16 */, AMDGPU::V_CVT_PKNORM_I16_F16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22204   { 22460 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22205   { 22460 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22206   { 22460 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22207   { 22481 /* v_cvt_pknorm_u16_f16 */, AMDGPU::V_CVT_PKNORM_U16_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22208   { 22481 /* v_cvt_pknorm_u16_f16 */, AMDGPU::V_CVT_PKNORM_U16_F16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22210   { 22502 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22211   { 22502 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22212   { 22502 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22214   { 22523 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22215   { 22523 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22216   { 22523 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22217   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22218   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22219   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22220   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22221   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22222   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22223   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22224   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22225   { 22589 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22226   { 22589 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22227   { 22589 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22228   { 22603 /* v_div_fixup_f16 */, AMDGPU::V_DIV_FIXUP_F16_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22229   { 22603 /* v_div_fixup_f16 */, AMDGPU::V_DIV_FIXUP_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22230   { 22603 /* v_div_fixup_f16 */, AMDGPU::V_DIV_FIXUP_F16_gfx9_gfx9, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22231   { 22619 /* v_div_fixup_f32 */, AMDGPU::V_DIV_FIXUP_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22232   { 22619 /* v_div_fixup_f32 */, AMDGPU::V_DIV_FIXUP_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22233   { 22619 /* v_div_fixup_f32 */, AMDGPU::V_DIV_FIXUP_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22234   { 22635 /* v_div_fixup_f64 */, AMDGPU::V_DIV_FIXUP_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22235   { 22635 /* v_div_fixup_f64 */, AMDGPU::V_DIV_FIXUP_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22236   { 22635 /* v_div_fixup_f64 */, AMDGPU::V_DIV_FIXUP_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22237   { 22651 /* v_div_fixup_legacy_f16 */, AMDGPU::V_DIV_FIXUP_LEGACY_F16_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22238   { 22674 /* v_div_fmas_f32 */, AMDGPU::V_DIV_FMAS_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22239   { 22674 /* v_div_fmas_f32 */, AMDGPU::V_DIV_FMAS_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22240   { 22674 /* v_div_fmas_f32 */, AMDGPU::V_DIV_FMAS_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22241   { 22689 /* v_div_fmas_f64 */, AMDGPU::V_DIV_FMAS_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22242   { 22689 /* v_div_fmas_f64 */, AMDGPU::V_DIV_FMAS_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22243   { 22689 /* v_div_fmas_f64 */, AMDGPU::V_DIV_FMAS_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22250   { 22736 /* v_dot2_f32_f16 */, AMDGPU::V_DOT2_F32_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_VSrcF32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22251   { 22736 /* v_dot2_f32_f16 */, AMDGPU::V_DOT2_F32_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_VSrcF32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22252   { 22751 /* v_dot2_i32_i16 */, AMDGPU::V_DOT2_I32_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22253   { 22751 /* v_dot2_i32_i16 */, AMDGPU::V_DOT2_I32_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22254   { 22766 /* v_dot2_u32_u16 */, AMDGPU::V_DOT2_U32_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22255   { 22766 /* v_dot2_u32_u16 */, AMDGPU::V_DOT2_U32_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22256   { 22813 /* v_dot4_i32_i8 */, AMDGPU::V_DOT4_I32_I8_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot1Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22257   { 22813 /* v_dot4_i32_i8 */, AMDGPU::V_DOT4_I32_I8_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot1Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22258   { 22827 /* v_dot4_u32_u8 */, AMDGPU::V_DOT4_U32_U8_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22259   { 22827 /* v_dot4_u32_u8 */, AMDGPU::V_DOT4_U32_U8_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22260   { 22856 /* v_dot8_i32_i4 */, AMDGPU::V_DOT8_I32_I4_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot1Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22261   { 22856 /* v_dot8_i32_i4 */, AMDGPU::V_DOT8_I32_I4_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot1Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22262   { 22870 /* v_dot8_u32_u4 */, AMDGPU::V_DOT8_U32_U4_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22263   { 22870 /* v_dot8_u32_u4 */, AMDGPU::V_DOT8_U32_U4_vi, ConvertCustom_cvtVOP3P, AMFBS_HasDot2Insts_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22264   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22265   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22266   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22267   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22268   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22269   { 22919 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_e64_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7GFX8GFX9_isGFX7Only, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22270   { 22919 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22280   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22281   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22282   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22283   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22284   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22285   { 22993 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22286   { 22993 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e64_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22287   { 22993 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22288   { 23005 /* v_fma_f16 */, AMDGPU::V_FMA_F16_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22289   { 23005 /* v_fma_f16 */, AMDGPU::V_FMA_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22290   { 23005 /* v_fma_f16 */, AMDGPU::V_FMA_F16_gfx9_gfx9, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22291   { 23015 /* v_fma_f32 */, AMDGPU::V_FMA_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22292   { 23015 /* v_fma_f32 */, AMDGPU::V_FMA_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22293   { 23015 /* v_fma_f32 */, AMDGPU::V_FMA_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22294   { 23025 /* v_fma_f64 */, AMDGPU::V_FMA_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22295   { 23025 /* v_fma_f64 */, AMDGPU::V_FMA_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22296   { 23025 /* v_fma_f64 */, AMDGPU::V_FMA_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22297   { 23035 /* v_fma_legacy_f16 */, AMDGPU::V_FMA_LEGACY_F16_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22298   { 23052 /* v_fma_mix_f32 */, AMDGPU::V_FMA_MIX_F32_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasFmaMixInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
22299   { 23052 /* v_fma_mix_f32 */, AMDGPU::V_FMA_MIX_F32_vi, ConvertCustom_cvtVOP3P, AMFBS_HasFmaMixInsts_HasVOP3PInsts, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
22300   { 23066 /* v_fma_mixhi_f16 */, AMDGPU::V_FMA_MIXHI_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasFmaMixInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
22301   { 23066 /* v_fma_mixhi_f16 */, AMDGPU::V_FMA_MIXHI_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasFmaMixInsts_HasVOP3PInsts, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
22302   { 23082 /* v_fma_mixlo_f16 */, AMDGPU::V_FMA_MIXLO_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_HasFmaMixInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
22303   { 23082 /* v_fma_mixlo_f16 */, AMDGPU::V_FMA_MIXLO_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasFmaMixInsts_HasVOP3PInsts, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
22304   { 23122 /* v_fmac_f16 */, AMDGPU::V_FMAC_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22305   { 23133 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasDLInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22306   { 23133 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_HasDLInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22307   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22308   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22309   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22310   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22311   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22312   { 23192 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22313   { 23192 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22314   { 23192 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22315   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22316   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
22317   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22318   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22319   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
22320   { 23244 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22321   { 23244 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22322   { 23244 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
22323   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22324   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22325   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22326   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22327   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22328   { 23298 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22329   { 23298 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22330   { 23298 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22331   { 23315 /* v_interp_mov_f32 */, AMDGPU::V_INTERP_MOV_F32_e64_gfx10, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_InterpSlot, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, },
22332   { 23315 /* v_interp_mov_f32 */, AMDGPU::V_INTERP_MOV_F32_e64_vi, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_InterpSlot, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, },
22333   { 23332 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_e64_gfx10, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, },
22334   { 23332 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_e64_vi, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, },
22335   { 23348 /* v_interp_p1ll_f16 */, AMDGPU::V_INTERP_P1LL_F16_gfx10, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmHigh, MCK_ImmClampSI, MCK_ImmOModSI }, },
22336   { 23348 /* v_interp_p1ll_f16 */, AMDGPU::V_INTERP_P1LL_F16_vi, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmHigh, MCK_ImmClampSI, MCK_ImmOModSI }, },
22337   { 23366 /* v_interp_p1lv_f16 */, AMDGPU::V_INTERP_P1LV_F16_gfx10, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP16InputMods, MCK_ImmHigh, MCK_ImmClampSI, MCK_ImmOModSI }, },
22338   { 23366 /* v_interp_p1lv_f16 */, AMDGPU::V_INTERP_P1LV_F16_vi, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP16InputMods, MCK_ImmHigh, MCK_ImmClampSI, MCK_ImmOModSI }, },
22339   { 23384 /* v_interp_p2_f16 */, AMDGPU::V_INTERP_P2_F16_gfx10, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP32InputMods, MCK_ImmHigh, MCK_ImmClampSI }, },
22340   { 23384 /* v_interp_p2_f16 */, AMDGPU::V_INTERP_P2_F16_gfx9_gfx9, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX9Plus_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP32InputMods, MCK_ImmHigh, MCK_ImmClampSI }, },
22341   { 23384 /* v_interp_p2_f16 */, AMDGPU::V_INTERP_P2_F16_vi, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX8Only, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP32InputMods, MCK_ImmHigh, MCK_ImmClampSI }, },
22342   { 23400 /* v_interp_p2_f32 */, AMDGPU::V_INTERP_P2_F32_e64_gfx10, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, },
22343   { 23400 /* v_interp_p2_f32 */, AMDGPU::V_INTERP_P2_F32_e64_vi, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, },
22344   { 23416 /* v_interp_p2_legacy_f16 */, AMDGPU::V_INTERP_P2_LEGACY_F16_gfx9, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP32InputMods, MCK_ImmHigh, MCK_ImmClampSI }, },
22345   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22346   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22348   { 23451 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22349   { 23451 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22350   { 23451 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22351   { 23463 /* v_ldexp_f64 */, AMDGPU::V_LDEXP_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22352   { 23463 /* v_ldexp_f64 */, AMDGPU::V_LDEXP_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22353   { 23463 /* v_ldexp_f64 */, AMDGPU::V_LDEXP_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22357   { 23485 /* v_log_clamp_f32 */, AMDGPU::V_LOG_CLAMP_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22358   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22359   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22360   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22361   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22362   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22363   { 23521 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_e64_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7GFX8GFX9_isGFX7Only, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22364   { 23521 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22387   { 23695 /* v_mac_f16 */, AMDGPU::V_MAC_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22388   { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22389   { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22390   { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22391   { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22392   { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22393   { 23732 /* v_mad_f16 */, AMDGPU::V_MAD_F16_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22394   { 23732 /* v_mad_f16 */, AMDGPU::V_MAD_F16_gfx9_gfx9, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Only_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22395   { 23742 /* v_mad_f32 */, AMDGPU::V_MAD_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22396   { 23742 /* v_mad_f32 */, AMDGPU::V_MAD_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22397   { 23742 /* v_mad_f32 */, AMDGPU::V_MAD_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22398   { 23752 /* v_mad_i16 */, AMDGPU::V_MAD_I16_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8Only, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmClampSI }, },
22399   { 23752 /* v_mad_i16 */, AMDGPU::V_MAD_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22400   { 23752 /* v_mad_i16 */, AMDGPU::V_MAD_I16_gfx9_gfx9, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22401   { 23762 /* v_mad_i32_i16 */, AMDGPU::V_MAD_I32_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmClampSI }, },
22402   { 23762 /* v_mad_i32_i16 */, AMDGPU::V_MAD_I32_I16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmClampSI }, },
22403   { 23776 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22404   { 23776 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22405   { 23776 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22406   { 23790 /* v_mad_i64_i32 */, AMDGPU::V_MAD_I64_I32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22407   { 23790 /* v_mad_i64_i32 */, AMDGPU::V_MAD_I64_I32_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22408   { 23790 /* v_mad_i64_i32 */, AMDGPU::V_MAD_I64_I32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22409   { 23804 /* v_mad_legacy_f16 */, AMDGPU::V_MAD_LEGACY_F16_gfx9, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22410   { 23821 /* v_mad_legacy_f32 */, AMDGPU::V_MAD_LEGACY_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22411   { 23821 /* v_mad_legacy_f32 */, AMDGPU::V_MAD_LEGACY_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22412   { 23821 /* v_mad_legacy_f32 */, AMDGPU::V_MAD_LEGACY_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22413   { 23838 /* v_mad_legacy_i16 */, AMDGPU::V_MAD_LEGACY_I16_gfx9, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmClampSI }, },
22414   { 23855 /* v_mad_legacy_u16 */, AMDGPU::V_MAD_LEGACY_U16_gfx9, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmClampSI }, },
22415   { 23872 /* v_mad_mix_f32 */, AMDGPU::V_MAD_MIX_F32_vi, ConvertCustom_cvtVOP3P, AMFBS_HasMadMixInsts_HasVOP3PInsts, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
22416   { 23886 /* v_mad_mixhi_f16 */, AMDGPU::V_MAD_MIXHI_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasMadMixInsts_HasVOP3PInsts, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
22417   { 23902 /* v_mad_mixlo_f16 */, AMDGPU::V_MAD_MIXLO_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasMadMixInsts_HasVOP3PInsts, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
22418   { 23918 /* v_mad_u16 */, AMDGPU::V_MAD_U16_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8Only, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmClampSI }, },
22419   { 23918 /* v_mad_u16 */, AMDGPU::V_MAD_U16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22420   { 23918 /* v_mad_u16 */, AMDGPU::V_MAD_U16_gfx9_gfx9, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22421   { 23928 /* v_mad_u32_u16 */, AMDGPU::V_MAD_U32_U16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmClampSI }, },
22422   { 23928 /* v_mad_u32_u16 */, AMDGPU::V_MAD_U32_U16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB32, MCK_ImmOpSel, MCK_ImmClampSI }, },
22423   { 23942 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22424   { 23942 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22425   { 23942 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22426   { 23956 /* v_mad_u64_u32 */, AMDGPU::V_MAD_U64_U32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22427   { 23956 /* v_mad_u64_u32 */, AMDGPU::V_MAD_U64_U32_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22428   { 23956 /* v_mad_u64_u32 */, AMDGPU::V_MAD_U64_U32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22429   { 24018 /* v_max3_f16 */, AMDGPU::V_MAX3_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22430   { 24018 /* v_max3_f16 */, AMDGPU::V_MAX3_F16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22431   { 24029 /* v_max3_f32 */, AMDGPU::V_MAX3_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22432   { 24029 /* v_max3_f32 */, AMDGPU::V_MAX3_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22433   { 24029 /* v_max3_f32 */, AMDGPU::V_MAX3_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22434   { 24040 /* v_max3_i16 */, AMDGPU::V_MAX3_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22435   { 24040 /* v_max3_i16 */, AMDGPU::V_MAX3_I16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22439   { 24062 /* v_max3_u16 */, AMDGPU::V_MAX3_U16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22440   { 24062 /* v_max3_u16 */, AMDGPU::V_MAX3_U16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22444   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22445   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22446   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22447   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22448   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22449   { 24104 /* v_max_f64 */, AMDGPU::V_MAX_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22450   { 24104 /* v_max_f64 */, AMDGPU::V_MAX_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22451   { 24104 /* v_max_f64 */, AMDGPU::V_MAX_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22457   { 24134 /* v_max_legacy_f32 */, AMDGPU::V_MAX_LEGACY_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22469   { 24209 /* v_med3_f16 */, AMDGPU::V_MED3_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22470   { 24209 /* v_med3_f16 */, AMDGPU::V_MED3_F16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22471   { 24220 /* v_med3_f32 */, AMDGPU::V_MED3_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22472   { 24220 /* v_med3_f32 */, AMDGPU::V_MED3_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22473   { 24220 /* v_med3_f32 */, AMDGPU::V_MED3_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22474   { 24231 /* v_med3_i16 */, AMDGPU::V_MED3_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22475   { 24231 /* v_med3_i16 */, AMDGPU::V_MED3_I16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22479   { 24253 /* v_med3_u16 */, AMDGPU::V_MED3_U16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22480   { 24253 /* v_med3_u16 */, AMDGPU::V_MED3_U16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22504   { 24709 /* v_min3_f16 */, AMDGPU::V_MIN3_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22505   { 24709 /* v_min3_f16 */, AMDGPU::V_MIN3_F16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22506   { 24720 /* v_min3_f32 */, AMDGPU::V_MIN3_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22507   { 24720 /* v_min3_f32 */, AMDGPU::V_MIN3_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22508   { 24720 /* v_min3_f32 */, AMDGPU::V_MIN3_F32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22509   { 24731 /* v_min3_i16 */, AMDGPU::V_MIN3_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22510   { 24731 /* v_min3_i16 */, AMDGPU::V_MIN3_I16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22514   { 24753 /* v_min3_u16 */, AMDGPU::V_MIN3_U16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22515   { 24753 /* v_min3_u16 */, AMDGPU::V_MIN3_U16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22519   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22520   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22521   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22522   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22523   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22524   { 24795 /* v_min_f64 */, AMDGPU::V_MIN_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22525   { 24795 /* v_min_f64 */, AMDGPU::V_MIN_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22526   { 24795 /* v_min_f64 */, AMDGPU::V_MIN_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22532   { 24825 /* v_min_legacy_f32 */, AMDGPU::V_MIN_LEGACY_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22554   { 24946 /* v_mqsad_pk_u16_u8 */, AMDGPU::V_MQSAD_PK_U16_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22555   { 24946 /* v_mqsad_pk_u16_u8 */, AMDGPU::V_MQSAD_PK_U16_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22556   { 24946 /* v_mqsad_pk_u16_u8 */, AMDGPU::V_MQSAD_PK_U16_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22557   { 24964 /* v_mqsad_u32_u8 */, AMDGPU::V_MQSAD_U32_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_128, MCK_VSrcB64, MCK_VSrcB32, MCK_VReg_128, MCK_ImmClampSI }, },
22558   { 24964 /* v_mqsad_u32_u8 */, AMDGPU::V_MQSAD_U32_U8_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_128, MCK_VSrcB64, MCK_VSrcB32, MCK_VReg_128, MCK_ImmClampSI }, },
22559   { 24964 /* v_mqsad_u32_u8 */, AMDGPU::V_MQSAD_U32_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_128, MCK_VSrcB64, MCK_VSrcB32, MCK_VReg_128, MCK_ImmClampSI }, },
22560   { 24979 /* v_msad_u8 */, AMDGPU::V_MSAD_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22561   { 24979 /* v_msad_u8 */, AMDGPU::V_MSAD_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22562   { 24979 /* v_msad_u8 */, AMDGPU::V_MSAD_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22563   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22564   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22565   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22566   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22567   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22568   { 25009 /* v_mul_f64 */, AMDGPU::V_MUL_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22569   { 25009 /* v_mul_f64 */, AMDGPU::V_MUL_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22570   { 25009 /* v_mul_f64 */, AMDGPU::V_MUL_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22586   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22587   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22588   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22600   { 25163 /* v_mullit_f32 */, AMDGPU::V_MULLIT_F32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22601   { 25163 /* v_mullit_f32 */, AMDGPU::V_MULLIT_F32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22613   { 25211 /* v_pack_b32_f16 */, AMDGPU::V_PACK_B32_F16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22614   { 25211 /* v_pack_b32_f16 */, AMDGPU::V_PACK_B32_F16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
22620   { 25284 /* v_pk_add_f16 */, AMDGPU::V_PK_ADD_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22621   { 25284 /* v_pk_add_f16 */, AMDGPU::V_PK_ADD_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22622   { 25297 /* v_pk_add_i16 */, AMDGPU::V_PK_ADD_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22623   { 25297 /* v_pk_add_i16 */, AMDGPU::V_PK_ADD_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22624   { 25310 /* v_pk_add_u16 */, AMDGPU::V_PK_ADD_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22625   { 25310 /* v_pk_add_u16 */, AMDGPU::V_PK_ADD_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22626   { 25323 /* v_pk_ashrrev_i16 */, AMDGPU::V_PK_ASHRREV_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22627   { 25323 /* v_pk_ashrrev_i16 */, AMDGPU::V_PK_ASHRREV_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22628   { 25340 /* v_pk_fma_f16 */, AMDGPU::V_PK_FMA_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22629   { 25340 /* v_pk_fma_f16 */, AMDGPU::V_PK_FMA_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22630   { 25367 /* v_pk_lshlrev_b16 */, AMDGPU::V_PK_LSHLREV_B16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22631   { 25367 /* v_pk_lshlrev_b16 */, AMDGPU::V_PK_LSHLREV_B16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22632   { 25384 /* v_pk_lshrrev_b16 */, AMDGPU::V_PK_LSHRREV_B16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22633   { 25384 /* v_pk_lshrrev_b16 */, AMDGPU::V_PK_LSHRREV_B16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22634   { 25401 /* v_pk_mad_i16 */, AMDGPU::V_PK_MAD_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22635   { 25401 /* v_pk_mad_i16 */, AMDGPU::V_PK_MAD_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22636   { 25414 /* v_pk_mad_u16 */, AMDGPU::V_PK_MAD_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22637   { 25414 /* v_pk_mad_u16 */, AMDGPU::V_PK_MAD_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22638   { 25427 /* v_pk_max_f16 */, AMDGPU::V_PK_MAX_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22639   { 25427 /* v_pk_max_f16 */, AMDGPU::V_PK_MAX_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22640   { 25440 /* v_pk_max_i16 */, AMDGPU::V_PK_MAX_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22641   { 25440 /* v_pk_max_i16 */, AMDGPU::V_PK_MAX_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22642   { 25453 /* v_pk_max_u16 */, AMDGPU::V_PK_MAX_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22643   { 25453 /* v_pk_max_u16 */, AMDGPU::V_PK_MAX_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22644   { 25466 /* v_pk_min_f16 */, AMDGPU::V_PK_MIN_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22645   { 25466 /* v_pk_min_f16 */, AMDGPU::V_PK_MIN_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22646   { 25479 /* v_pk_min_i16 */, AMDGPU::V_PK_MIN_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22647   { 25479 /* v_pk_min_i16 */, AMDGPU::V_PK_MIN_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22648   { 25492 /* v_pk_min_u16 */, AMDGPU::V_PK_MIN_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22649   { 25492 /* v_pk_min_u16 */, AMDGPU::V_PK_MIN_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22650   { 25505 /* v_pk_mul_f16 */, AMDGPU::V_PK_MUL_F16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22651   { 25505 /* v_pk_mul_f16 */, AMDGPU::V_PK_MUL_F16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2F16, MCK_VSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22652   { 25518 /* v_pk_mul_lo_u16 */, AMDGPU::V_PK_MUL_LO_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22653   { 25518 /* v_pk_mul_lo_u16 */, AMDGPU::V_PK_MUL_LO_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22654   { 25534 /* v_pk_sub_i16 */, AMDGPU::V_PK_SUB_I16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22655   { 25534 /* v_pk_sub_i16 */, AMDGPU::V_PK_SUB_I16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22656   { 25547 /* v_pk_sub_u16 */, AMDGPU::V_PK_SUB_U16_gfx10, ConvertCustom_cvtVOP3P, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22657   { 25547 /* v_pk_sub_u16 */, AMDGPU::V_PK_SUB_U16_vi, ConvertCustom_cvtVOP3P, AMFBS_HasVOP3PInsts, { MCK_VGPR_32, MCK_VSrcV2B16, MCK_VSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
22658   { 25560 /* v_qsad_pk_u16_u8 */, AMDGPU::V_QSAD_PK_U16_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22659   { 25560 /* v_qsad_pk_u16_u8 */, AMDGPU::V_QSAD_PK_U16_U8_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22660   { 25560 /* v_qsad_pk_u16_u8 */, AMDGPU::V_QSAD_PK_U16_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB64, MCK_VSrcB32, MCK_VSrcB64, MCK_ImmClampSI }, },
22661   { 25577 /* v_rcp_clamp_f32 */, AMDGPU::V_RCP_CLAMP_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22662   { 25593 /* v_rcp_clamp_f64 */, AMDGPU::V_RCP_CLAMP_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22663   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22664   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22665   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22666   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22667   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22668   { 25629 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22669   { 25629 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22670   { 25629 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22671   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22672   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22673   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22674   { 25655 /* v_rcp_legacy_f32 */, AMDGPU::V_RCP_LEGACY_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22675   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22676   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22677   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22678   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22679   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22680   { 25731 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22681   { 25731 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e64_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22682   { 25731 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22683   { 25743 /* v_rsq_clamp_f32 */, AMDGPU::V_RSQ_CLAMP_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22684   { 25759 /* v_rsq_clamp_f64 */, AMDGPU::V_RSQ_CLAMP_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22685   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22686   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22687   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22688   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22689   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22690   { 25795 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22691   { 25795 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22692   { 25795 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22693   { 25805 /* v_rsq_legacy_f32 */, AMDGPU::V_RSQ_LEGACY_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22694   { 25822 /* v_sad_hi_u8 */, AMDGPU::V_SAD_HI_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22695   { 25822 /* v_sad_hi_u8 */, AMDGPU::V_SAD_HI_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22696   { 25822 /* v_sad_hi_u8 */, AMDGPU::V_SAD_HI_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22697   { 25834 /* v_sad_u16 */, AMDGPU::V_SAD_U16_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22698   { 25834 /* v_sad_u16 */, AMDGPU::V_SAD_U16_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22699   { 25834 /* v_sad_u16 */, AMDGPU::V_SAD_U16_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22700   { 25844 /* v_sad_u32 */, AMDGPU::V_SAD_U32_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22701   { 25844 /* v_sad_u32 */, AMDGPU::V_SAD_U32_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22702   { 25844 /* v_sad_u32 */, AMDGPU::V_SAD_U32_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22703   { 25854 /* v_sad_u8 */, AMDGPU::V_SAD_U8_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22704   { 25854 /* v_sad_u8 */, AMDGPU::V_SAD_U8_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22705   { 25854 /* v_sad_u8 */, AMDGPU::V_SAD_U8_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22709   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22710   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22711   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22712   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22713   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22714   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22715   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22716   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22717   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22718   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22719   { 25948 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22720   { 25948 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22721   { 25948 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22724   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22727   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22728   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22729   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22730   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22731   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22732   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22733   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22734   { 26008 /* v_sub_i16 */, AMDGPU::V_SUB_I16_vi, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22736   { 26018 /* v_sub_i32 */, AMDGPU::V_SUB_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22737   { 26028 /* v_sub_nc_i16 */, AMDGPU::V_SUB_NC_I16_gfx10, ConvertCustom_cvtVOP3OpSel, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB16, MCK_VSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
22740   { 26067 /* v_sub_nc_u32 */, AMDGPU::V_SUB_NC_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22742   { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22743   { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22746   { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22747   { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22748   { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22751   { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22752   { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22753   { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22756   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_BoolReg, MCK_ImmClampSI }, },
22759   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22760   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22761   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22762   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22763   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22764   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22765   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22766   { 26217 /* v_subrev_i32 */, AMDGPU::V_SUBREV_I32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22767   { 26230 /* v_subrev_nc_u32 */, AMDGPU::V_SUBREV_NC_U32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22769   { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_e64_gfx9, ConvertCustom_cvtVOP3, AMFBS_HasAddNoCarryInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22770   { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8Only, { MCK_VGPR_32, MCK_BoolReg, MCK_VSrcB32, MCK_VSrcB32, MCK_ImmClampSI }, },
22771   { 26297 /* v_trig_preop_f64 */, AMDGPU::V_TRIG_PREOP_F64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22772   { 26297 /* v_trig_preop_f64 */, AMDGPU::V_TRIG_PREOP_F64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22773   { 26297 /* v_trig_preop_f64 */, AMDGPU::V_TRIG_PREOP_F64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22774   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22775   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_e64_vi, ConvertCustom_cvtVOP3, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22776   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22777   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e64_gfx6_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22778   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22779   { 26338 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e64_gfx10, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22780   { 26338 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e64_gfx7, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22781   { 26338 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e64_vi, ConvertCustom_cvtVOP3, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
22797   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22798   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22799   { 13368 /* v_add_u16 */, AMDGPU::V_ADD_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22800   { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22803   { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22804   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22805   { 13489 /* v_ashrrev_i16 */, AMDGPU::V_ASHRREV_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22806   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22807   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22808   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22809   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22810   { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22811   { 13677 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22812   { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22813   { 13779 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22814   { 13839 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22815   { 13869 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22816   { 13929 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22817   { 13959 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22818   { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22819   { 14047 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22820   { 14103 /* v_cmp_f_i16 */, AMDGPU::V_CMP_F_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22821   { 14131 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22822   { 14187 /* v_cmp_f_u16 */, AMDGPU::V_CMP_F_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22823   { 14215 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22824   { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22825   { 14301 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22826   { 14361 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22827   { 14391 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22828   { 14451 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22829   { 14481 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22830   { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22831   { 14571 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22832   { 14631 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22833   { 14661 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22834   { 14721 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22835   { 14751 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22836   { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22837   { 14841 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22838   { 14901 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22839   { 14931 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22840   { 14991 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22841   { 15021 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22842   { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22843   { 15111 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22844   { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22845   { 15201 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22846   { 15261 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22847   { 15291 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22848   { 15351 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22849   { 15381 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22850   { 15441 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22851   { 15471 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22852   { 15531 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22853   { 15561 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22854   { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22855   { 15653 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22856   { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22857   { 15749 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22858   { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22859   { 15845 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22860   { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22861   { 15941 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22862   { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22863   { 16037 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22864   { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22865   { 16133 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22866   { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22867   { 16225 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22868   { 16281 /* v_cmp_t_i16 */, AMDGPU::V_CMP_T_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22869   { 16309 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22870   { 16365 /* v_cmp_t_u16 */, AMDGPU::V_CMP_T_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22871   { 16393 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22872   { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22873   { 16481 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22874   { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22875   { 16573 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22876   { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22877   { 18811 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22878   { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22879   { 18919 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22880   { 18983 /* v_cmpx_eq_i16 */, AMDGPU::V_CMPX_EQ_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22881   { 19015 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22882   { 19079 /* v_cmpx_eq_u16 */, AMDGPU::V_CMPX_EQ_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22883   { 19111 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22884   { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22885   { 19205 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22886   { 19265 /* v_cmpx_f_i16 */, AMDGPU::V_CMPX_F_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22887   { 19295 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22888   { 19355 /* v_cmpx_f_u16 */, AMDGPU::V_CMPX_F_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22889   { 19385 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22890   { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22891   { 19477 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22892   { 19541 /* v_cmpx_ge_i16 */, AMDGPU::V_CMPX_GE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22893   { 19573 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22894   { 19637 /* v_cmpx_ge_u16 */, AMDGPU::V_CMPX_GE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22895   { 19669 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22896   { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22897   { 19765 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22898   { 19829 /* v_cmpx_gt_i16 */, AMDGPU::V_CMPX_GT_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22899   { 19861 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22900   { 19925 /* v_cmpx_gt_u16 */, AMDGPU::V_CMPX_GT_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22901   { 19957 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22902   { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22903   { 20053 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22904   { 20117 /* v_cmpx_le_i16 */, AMDGPU::V_CMPX_LE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22905   { 20149 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22906   { 20213 /* v_cmpx_le_u16 */, AMDGPU::V_CMPX_LE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22907   { 20245 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22908   { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22909   { 20341 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22910   { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22911   { 20437 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22912   { 20501 /* v_cmpx_lt_i16 */, AMDGPU::V_CMPX_LT_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22913   { 20533 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22914   { 20597 /* v_cmpx_lt_u16 */, AMDGPU::V_CMPX_LT_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22915   { 20629 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22916   { 20693 /* v_cmpx_ne_i16 */, AMDGPU::V_CMPX_NE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22917   { 20725 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22918   { 20789 /* v_cmpx_ne_u16 */, AMDGPU::V_CMPX_NE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22919   { 20821 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22920   { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22921   { 20919 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22922   { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22923   { 21021 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22924   { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22925   { 21123 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22926   { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22927   { 21225 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22928   { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22929   { 21327 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22930   { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22931   { 21429 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22932   { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22933   { 21527 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22934   { 21587 /* v_cmpx_t_i16 */, AMDGPU::V_CMPX_T_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22935   { 21617 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22936   { 21677 /* v_cmpx_t_u16 */, AMDGPU::V_CMPX_T_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22937   { 21707 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22938   { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22939   { 21801 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22940   { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22941   { 21899 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_HasSDWA_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22948   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2e, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22949   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22950   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22951   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22952   { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22953   { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22954   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22955   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22956   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22957   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22958   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22959   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22960   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22961   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22962   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22963   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22964   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_isGFX9Plus_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22965   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_isGFX9Plus_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22966   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22967   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22968   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22969   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22970   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22971   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22972   { 22919 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_isGFX7GFX8GFX9_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22973   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22974   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22975   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22976   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22977   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22978   { 23133 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasDLInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22979   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22980   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22981   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22982   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22983   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22984   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22985   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22986   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22987   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22988   { 23521 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_isGFX7GFX8GFX9_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22989   { 23589 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22990   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22991   { 23653 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22992   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22993   { 23695 /* v_mac_f16 */, AMDGPU::V_MAC_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22994   { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22995   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22996   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22997   { 24114 /* v_max_i16 */, AMDGPU::V_MAX_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22998   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22999   { 24151 /* v_max_u16 */, AMDGPU::V_MAX_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23000   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23001   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23002   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23003   { 24805 /* v_min_i16 */, AMDGPU::V_MIN_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23004   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23005   { 24842 /* v_min_u16 */, AMDGPU::V_MIN_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23006   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23007   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23008   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23009   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23010   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23011   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23012   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23013   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23014   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23015   { 25123 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23016   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23018   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23019   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23020   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23021   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23022   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23023   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23024   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23025   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23026   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23027   { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_isGFX9Plus_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23028   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23029   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23030   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23031   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23036   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23037   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23038   { 26080 /* v_sub_u16 */, AMDGPU::V_SUB_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23039   { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23042   { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23045   { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23050   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23051   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23052   { 26246 /* v_subrev_u16 */, AMDGPU::V_SUBREV_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23053   { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA_HasSDWA_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23054   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23055   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23056   { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasDLInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23057   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23063   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23064   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_sdwa_w64_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23065   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23068   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23069   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23070   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23071   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23072   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23073   { 13355 /* v_add_nc_u32 */, AMDGPU::V_ADD_NC_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23074   { 13368 /* v_add_u16 */, AMDGPU::V_ADD_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23075   { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23078   { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23079   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23080   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23081   { 13489 /* v_ashrrev_i16 */, AMDGPU::V_ASHRREV_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23082   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23083   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23084   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23085   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23086   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23087   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23088   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23089   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23352   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2e, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23353   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_w64_gfx10, ConvertCustom_cvtSdwaVOP2e, AMFBS_HasSDWA10_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23354   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2e, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23355   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2e, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23356   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23357   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23358   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23359   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23360   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23361   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23362   { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23363   { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23364   { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23365   { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23366   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23367   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23368   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23369   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23370   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23371   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23372   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23373   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23374   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23375   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23376   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23377   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23378   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23379   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23380   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23381   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23382   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23383   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23384   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23385   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23386   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23387   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23388   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23389   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23390   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23391   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23392   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23393   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23394   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23395   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23396   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23397   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23398   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23399   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23400   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23401   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23402   { 22919 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23403   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23404   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23405   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23406   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23407   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23408   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23409   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23410   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23411   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23412   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23413   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23414   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23415   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23416   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23417   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23418   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23419   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23420   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23421   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23422   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23423   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23424   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23425   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23426   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23427   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23428   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23429   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23430   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23431   { 23521 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23432   { 23589 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23433   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23434   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23435   { 23653 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23436   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23437   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23438   { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23439   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23440   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23441   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23442   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23443   { 24114 /* v_max_i16 */, AMDGPU::V_MAX_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23444   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23445   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23446   { 24151 /* v_max_u16 */, AMDGPU::V_MAX_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23447   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23448   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23449   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23450   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23451   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23452   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23453   { 24805 /* v_min_i16 */, AMDGPU::V_MIN_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23454   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23455   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23456   { 24842 /* v_min_u16 */, AMDGPU::V_MIN_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23457   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23458   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23459   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23460   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23461   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23462   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23463   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23464   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23465   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23466   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23467   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23468   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23469   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23470   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23471   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23472   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23473   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23474   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23475   { 25123 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23476   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23477   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23480   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23481   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23482   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23483   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23485   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23486   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23487   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23488   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23489   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23490   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23491   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23492   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23493   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23494   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23495   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23496   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23497   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23498   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23499   { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23500   { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23501   { 25879 /* v_screen_partition_4se_b32 */, AMDGPU::V_SCREEN_PARTITION_4SE_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23502   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23503   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23504   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23505   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23506   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23507   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23508   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23509   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23512   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23513   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_sdwa_w64_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23514   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23517   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23518   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23519   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23520   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23521   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23522   { 26067 /* v_sub_nc_u32 */, AMDGPU::V_SUB_NC_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23523   { 26080 /* v_sub_u16 */, AMDGPU::V_SUB_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23524   { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23527   { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23530   { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23533   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23534   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_sdwa_w64_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23535   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_sdwa_w32_gfx10, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA10_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC_LO, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23538   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23539   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23540   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23541   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23542   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23543   { 26230 /* v_subrev_nc_u32 */, AMDGPU::V_SUBREV_NC_U32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23544   { 26246 /* v_subrev_u16 */, AMDGPU::V_SUBREV_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23545   { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23546   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23547   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23548   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23549   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23550   { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23551   { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasDLInsts_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23552   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_sdwa_gfx10, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA10_isGFX10Plus, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23553   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, AMFBS_HasSDWA9_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
72851   { 13222 /* v_add_co_ci_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
72862   { 13222 /* v_add_co_ci_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
72873   { 13222 /* v_add_co_ci_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus_isWave64 },
72884   { 13222 /* v_add_co_ci_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus_isWave32 },
72890   { 13238 /* v_add_co_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
72892   { 13238 /* v_add_co_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Only },
72898   { 13238 /* v_add_co_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
72907   { 13251 /* v_add_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
72910   { 13251 /* v_add_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
72917   { 13251 /* v_add_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
72930   { 13251 /* v_add_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
72937   { 13251 /* v_add_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
72946   { 13261 /* v_add_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
72949   { 13261 /* v_add_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
72952   { 13261 /* v_add_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
72959   { 13261 /* v_add_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
72972   { 13261 /* v_add_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
72979   { 13261 /* v_add_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
72986   { 13271 /* v_add_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
72989   { 13271 /* v_add_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
72992   { 13271 /* v_add_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
72993   { 13281 /* v_add_i16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
72996   { 13291 /* v_add_i32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
72997   { 13316 /* v_add_nc_i16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
72999   { 13355 /* v_add_nc_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasAddNoCarryInsts_isGFX10Plus },
73008   { 13355 /* v_add_nc_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
73018   { 13368 /* v_add_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73024   { 13368 /* v_add_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
73029   { 13378 /* v_add_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasAddNoCarryInsts_isGFX9Only },
73031   { 13378 /* v_add_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Only },
73041   { 13378 /* v_add_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
73047   { 13378 /* v_add_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA_isGFX8Only },
73053   { 13388 /* v_addc_co_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Only },
73059   { 13388 /* v_addc_co_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
73065   { 13402 /* v_addc_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73067   { 13402 /* v_addc_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX8Only },
73073   { 13402 /* v_addc_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA_isGFX8Only },
73090   { 13444 /* v_and_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73096   { 13444 /* v_and_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
73102   { 13444 /* v_and_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
73112   { 13489 /* v_ashrrev_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73118   { 13489 /* v_ashrrev_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
73135   { 13503 /* v_ashrrev_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73141   { 13503 /* v_ashrrev_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
73147   { 13503 /* v_ashrrev_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
73159   { 13586 /* v_bfrev_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73164   { 13586 /* v_bfrev_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
73169   { 13586 /* v_bfrev_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
73182   { 13598 /* v_ceil_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
73185   { 13598 /* v_ceil_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
73187   { 13598 /* v_ceil_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73198   { 13598 /* v_ceil_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
73204   { 13598 /* v_ceil_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
73218   { 13609 /* v_ceil_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73221   { 13609 /* v_ceil_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73224   { 13609 /* v_ceil_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73226   { 13609 /* v_ceil_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73237   { 13609 /* v_ceil_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
73243   { 13609 /* v_ceil_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
73255   { 13620 /* v_ceil_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX10Plus },
73258   { 13620 /* v_ceil_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX7Only },
73261   { 13620 /* v_ceil_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX8GFX9 },
73278   { 13641 /* v_cmp_class_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73299   { 13677 /* v_cmp_class_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73310   { 13749 /* v_cmp_eq_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
73313   { 13749 /* v_cmp_eq_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
73323   { 13749 /* v_cmp_eq_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73328   { 13779 /* v_cmp_eq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73331   { 13779 /* v_cmp_eq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73334   { 13779 /* v_cmp_eq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73344   { 13779 /* v_cmp_eq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73349   { 13809 /* v_cmp_eq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73352   { 13809 /* v_cmp_eq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73355   { 13809 /* v_cmp_eq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73367   { 13839 /* v_cmp_eq_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73382   { 13869 /* v_cmp_eq_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73399   { 13929 /* v_cmp_eq_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73414   { 13959 /* v_cmp_eq_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73422   { 14019 /* v_cmp_f_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
73425   { 14019 /* v_cmp_f_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
73435   { 14019 /* v_cmp_f_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73440   { 14047 /* v_cmp_f_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73443   { 14047 /* v_cmp_f_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73446   { 14047 /* v_cmp_f_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73456   { 14047 /* v_cmp_f_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73461   { 14075 /* v_cmp_f_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73464   { 14075 /* v_cmp_f_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73467   { 14075 /* v_cmp_f_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73474   { 14103 /* v_cmp_f_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73489   { 14131 /* v_cmp_f_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73501   { 14187 /* v_cmp_f_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73516   { 14215 /* v_cmp_f_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73524   { 14271 /* v_cmp_ge_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
73527   { 14271 /* v_cmp_ge_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
73537   { 14271 /* v_cmp_ge_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73542   { 14301 /* v_cmp_ge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73545   { 14301 /* v_cmp_ge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73548   { 14301 /* v_cmp_ge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73558   { 14301 /* v_cmp_ge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73563   { 14331 /* v_cmp_ge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73566   { 14331 /* v_cmp_ge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73569   { 14331 /* v_cmp_ge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73581   { 14361 /* v_cmp_ge_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73596   { 14391 /* v_cmp_ge_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73613   { 14451 /* v_cmp_ge_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73628   { 14481 /* v_cmp_ge_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73636   { 14541 /* v_cmp_gt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
73639   { 14541 /* v_cmp_gt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
73649   { 14541 /* v_cmp_gt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73654   { 14571 /* v_cmp_gt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73657   { 14571 /* v_cmp_gt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73660   { 14571 /* v_cmp_gt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73670   { 14571 /* v_cmp_gt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73675   { 14601 /* v_cmp_gt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73678   { 14601 /* v_cmp_gt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73681   { 14601 /* v_cmp_gt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73693   { 14631 /* v_cmp_gt_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73708   { 14661 /* v_cmp_gt_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73725   { 14721 /* v_cmp_gt_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73740   { 14751 /* v_cmp_gt_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73748   { 14811 /* v_cmp_le_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
73751   { 14811 /* v_cmp_le_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
73761   { 14811 /* v_cmp_le_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73766   { 14841 /* v_cmp_le_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73769   { 14841 /* v_cmp_le_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73772   { 14841 /* v_cmp_le_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73782   { 14841 /* v_cmp_le_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73787   { 14871 /* v_cmp_le_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73790   { 14871 /* v_cmp_le_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73793   { 14871 /* v_cmp_le_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73805   { 14901 /* v_cmp_le_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73820   { 14931 /* v_cmp_le_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73837   { 14991 /* v_cmp_le_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73852   { 15021 /* v_cmp_le_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73860   { 15081 /* v_cmp_lg_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
73863   { 15081 /* v_cmp_lg_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
73873   { 15081 /* v_cmp_lg_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73878   { 15111 /* v_cmp_lg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73881   { 15111 /* v_cmp_lg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73884   { 15111 /* v_cmp_lg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73894   { 15111 /* v_cmp_lg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73899   { 15141 /* v_cmp_lg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73902   { 15141 /* v_cmp_lg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73905   { 15141 /* v_cmp_lg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73908   { 15171 /* v_cmp_lt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
73911   { 15171 /* v_cmp_lt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
73921   { 15171 /* v_cmp_lt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73926   { 15201 /* v_cmp_lt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73929   { 15201 /* v_cmp_lt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73932   { 15201 /* v_cmp_lt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73942   { 15201 /* v_cmp_lt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73947   { 15231 /* v_cmp_lt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
73950   { 15231 /* v_cmp_lt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
73953   { 15231 /* v_cmp_lt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
73965   { 15261 /* v_cmp_lt_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73980   { 15291 /* v_cmp_lt_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
73997   { 15351 /* v_cmp_lt_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74012   { 15381 /* v_cmp_lt_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74029   { 15441 /* v_cmp_ne_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74044   { 15471 /* v_cmp_ne_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74061   { 15531 /* v_cmp_ne_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74076   { 15561 /* v_cmp_ne_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74084   { 15621 /* v_cmp_neq_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
74087   { 15621 /* v_cmp_neq_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
74097   { 15621 /* v_cmp_neq_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74102   { 15653 /* v_cmp_neq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74105   { 15653 /* v_cmp_neq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74108   { 15653 /* v_cmp_neq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74118   { 15653 /* v_cmp_neq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74123   { 15685 /* v_cmp_neq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74126   { 15685 /* v_cmp_neq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74129   { 15685 /* v_cmp_neq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74132   { 15717 /* v_cmp_nge_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
74135   { 15717 /* v_cmp_nge_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
74145   { 15717 /* v_cmp_nge_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74150   { 15749 /* v_cmp_nge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74153   { 15749 /* v_cmp_nge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74156   { 15749 /* v_cmp_nge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74166   { 15749 /* v_cmp_nge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74171   { 15781 /* v_cmp_nge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74174   { 15781 /* v_cmp_nge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74177   { 15781 /* v_cmp_nge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74180   { 15813 /* v_cmp_ngt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
74183   { 15813 /* v_cmp_ngt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
74193   { 15813 /* v_cmp_ngt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74198   { 15845 /* v_cmp_ngt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74201   { 15845 /* v_cmp_ngt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74204   { 15845 /* v_cmp_ngt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74214   { 15845 /* v_cmp_ngt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74219   { 15877 /* v_cmp_ngt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74222   { 15877 /* v_cmp_ngt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74225   { 15877 /* v_cmp_ngt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74228   { 15909 /* v_cmp_nle_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
74231   { 15909 /* v_cmp_nle_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
74241   { 15909 /* v_cmp_nle_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74246   { 15941 /* v_cmp_nle_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74249   { 15941 /* v_cmp_nle_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74252   { 15941 /* v_cmp_nle_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74262   { 15941 /* v_cmp_nle_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74267   { 15973 /* v_cmp_nle_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74270   { 15973 /* v_cmp_nle_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74273   { 15973 /* v_cmp_nle_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74276   { 16005 /* v_cmp_nlg_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
74279   { 16005 /* v_cmp_nlg_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
74289   { 16005 /* v_cmp_nlg_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74294   { 16037 /* v_cmp_nlg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74297   { 16037 /* v_cmp_nlg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74300   { 16037 /* v_cmp_nlg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74310   { 16037 /* v_cmp_nlg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74315   { 16069 /* v_cmp_nlg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74318   { 16069 /* v_cmp_nlg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74321   { 16069 /* v_cmp_nlg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74324   { 16101 /* v_cmp_nlt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
74327   { 16101 /* v_cmp_nlt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
74337   { 16101 /* v_cmp_nlt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74342   { 16133 /* v_cmp_nlt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74345   { 16133 /* v_cmp_nlt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74348   { 16133 /* v_cmp_nlt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74358   { 16133 /* v_cmp_nlt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74363   { 16165 /* v_cmp_nlt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74366   { 16165 /* v_cmp_nlt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74369   { 16165 /* v_cmp_nlt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74372   { 16197 /* v_cmp_o_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
74375   { 16197 /* v_cmp_o_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
74385   { 16197 /* v_cmp_o_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74390   { 16225 /* v_cmp_o_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74393   { 16225 /* v_cmp_o_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74396   { 16225 /* v_cmp_o_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74406   { 16225 /* v_cmp_o_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74411   { 16253 /* v_cmp_o_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74414   { 16253 /* v_cmp_o_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74417   { 16253 /* v_cmp_o_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74424   { 16281 /* v_cmp_t_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74439   { 16309 /* v_cmp_t_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74451   { 16365 /* v_cmp_t_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74466   { 16393 /* v_cmp_t_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74474   { 16449 /* v_cmp_tru_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
74477   { 16449 /* v_cmp_tru_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
74487   { 16449 /* v_cmp_tru_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74492   { 16481 /* v_cmp_tru_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74495   { 16481 /* v_cmp_tru_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74498   { 16481 /* v_cmp_tru_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74508   { 16481 /* v_cmp_tru_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74513   { 16513 /* v_cmp_tru_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74516   { 16513 /* v_cmp_tru_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74519   { 16513 /* v_cmp_tru_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74522   { 16545 /* v_cmp_u_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
74525   { 16545 /* v_cmp_u_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
74535   { 16545 /* v_cmp_u_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74540   { 16573 /* v_cmp_u_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74543   { 16573 /* v_cmp_u_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74546   { 16573 /* v_cmp_u_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74556   { 16573 /* v_cmp_u_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74561   { 16601 /* v_cmp_u_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
74564   { 16601 /* v_cmp_u_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74567   { 16601 /* v_cmp_u_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74570   { 16629 /* v_cmps_eq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74573   { 16661 /* v_cmps_eq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74576   { 16693 /* v_cmps_f_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74579   { 16723 /* v_cmps_f_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74582   { 16753 /* v_cmps_ge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74585   { 16785 /* v_cmps_ge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74588   { 16817 /* v_cmps_gt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74591   { 16849 /* v_cmps_gt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74594   { 16881 /* v_cmps_le_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74597   { 16913 /* v_cmps_le_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74600   { 16945 /* v_cmps_lg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74603   { 16977 /* v_cmps_lg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74606   { 17009 /* v_cmps_lt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74609   { 17041 /* v_cmps_lt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74612   { 17073 /* v_cmps_neq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74615   { 17107 /* v_cmps_neq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74618   { 17141 /* v_cmps_nge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74621   { 17175 /* v_cmps_nge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74624   { 17209 /* v_cmps_ngt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74627   { 17243 /* v_cmps_ngt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74630   { 17277 /* v_cmps_nle_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74633   { 17311 /* v_cmps_nle_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74636   { 17345 /* v_cmps_nlg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74639   { 17379 /* v_cmps_nlg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74642   { 17413 /* v_cmps_nlt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74645   { 17447 /* v_cmps_nlt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74648   { 17481 /* v_cmps_o_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74651   { 17511 /* v_cmps_o_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74654   { 17541 /* v_cmps_tru_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74657   { 17575 /* v_cmps_tru_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74660   { 17609 /* v_cmps_u_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74663   { 17639 /* v_cmps_u_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74666   { 17669 /* v_cmpsx_eq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74669   { 17703 /* v_cmpsx_eq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74672   { 17737 /* v_cmpsx_f_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74675   { 17769 /* v_cmpsx_f_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74678   { 17801 /* v_cmpsx_ge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74681   { 17835 /* v_cmpsx_ge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74684   { 17869 /* v_cmpsx_gt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74687   { 17903 /* v_cmpsx_gt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74690   { 17937 /* v_cmpsx_le_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74693   { 17971 /* v_cmpsx_le_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74696   { 18005 /* v_cmpsx_lg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74699   { 18039 /* v_cmpsx_lg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74702   { 18073 /* v_cmpsx_lt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74705   { 18107 /* v_cmpsx_lt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74708   { 18141 /* v_cmpsx_neq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74711   { 18177 /* v_cmpsx_neq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74714   { 18213 /* v_cmpsx_nge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74717   { 18249 /* v_cmpsx_nge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74720   { 18285 /* v_cmpsx_ngt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74723   { 18321 /* v_cmpsx_ngt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74726   { 18357 /* v_cmpsx_nle_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74729   { 18393 /* v_cmpsx_nle_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74732   { 18429 /* v_cmpsx_nlg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74735   { 18465 /* v_cmpsx_nlg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74738   { 18501 /* v_cmpsx_nlt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74741   { 18537 /* v_cmpsx_nlt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74744   { 18573 /* v_cmpsx_o_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74747   { 18605 /* v_cmpsx_o_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74750   { 18637 /* v_cmpsx_tru_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74753   { 18673 /* v_cmpsx_tru_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74756   { 18709 /* v_cmpsx_u_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74759   { 18741 /* v_cmpsx_u_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
74774   { 18773 /* v_cmpx_class_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74793   { 18811 /* v_cmpx_class_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74802   { 18887 /* v_cmpx_eq_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
74805   { 18887 /* v_cmpx_eq_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
74814   { 18887 /* v_cmpx_eq_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74818   { 18919 /* v_cmpx_eq_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
74821   { 18919 /* v_cmpx_eq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74824   { 18919 /* v_cmpx_eq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74833   { 18919 /* v_cmpx_eq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74837   { 18951 /* v_cmpx_eq_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
74840   { 18951 /* v_cmpx_eq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74843   { 18951 /* v_cmpx_eq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74853   { 18983 /* v_cmpx_eq_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74866   { 19015 /* v_cmpx_eq_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74880   { 19079 /* v_cmpx_eq_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74893   { 19111 /* v_cmpx_eq_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74899   { 19175 /* v_cmpx_f_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
74902   { 19175 /* v_cmpx_f_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
74911   { 19175 /* v_cmpx_f_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74915   { 19205 /* v_cmpx_f_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
74918   { 19205 /* v_cmpx_f_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74921   { 19205 /* v_cmpx_f_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74930   { 19205 /* v_cmpx_f_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74934   { 19235 /* v_cmpx_f_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
74937   { 19235 /* v_cmpx_f_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
74940   { 19235 /* v_cmpx_f_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
74947   { 19265 /* v_cmpx_f_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74960   { 19295 /* v_cmpx_f_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74971   { 19355 /* v_cmpx_f_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74984   { 19385 /* v_cmpx_f_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
74990   { 19445 /* v_cmpx_ge_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
74993   { 19445 /* v_cmpx_ge_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
75002   { 19445 /* v_cmpx_ge_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75006   { 19477 /* v_cmpx_ge_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75009   { 19477 /* v_cmpx_ge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75012   { 19477 /* v_cmpx_ge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75021   { 19477 /* v_cmpx_ge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75025   { 19509 /* v_cmpx_ge_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75028   { 19509 /* v_cmpx_ge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75031   { 19509 /* v_cmpx_ge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75041   { 19541 /* v_cmpx_ge_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75054   { 19573 /* v_cmpx_ge_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75068   { 19637 /* v_cmpx_ge_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75081   { 19669 /* v_cmpx_ge_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75087   { 19733 /* v_cmpx_gt_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
75090   { 19733 /* v_cmpx_gt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
75099   { 19733 /* v_cmpx_gt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75103   { 19765 /* v_cmpx_gt_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75106   { 19765 /* v_cmpx_gt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75109   { 19765 /* v_cmpx_gt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75118   { 19765 /* v_cmpx_gt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75122   { 19797 /* v_cmpx_gt_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75125   { 19797 /* v_cmpx_gt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75128   { 19797 /* v_cmpx_gt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75138   { 19829 /* v_cmpx_gt_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75151   { 19861 /* v_cmpx_gt_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75165   { 19925 /* v_cmpx_gt_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75178   { 19957 /* v_cmpx_gt_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75184   { 20021 /* v_cmpx_le_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
75187   { 20021 /* v_cmpx_le_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
75196   { 20021 /* v_cmpx_le_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75200   { 20053 /* v_cmpx_le_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75203   { 20053 /* v_cmpx_le_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75206   { 20053 /* v_cmpx_le_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75215   { 20053 /* v_cmpx_le_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75219   { 20085 /* v_cmpx_le_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75222   { 20085 /* v_cmpx_le_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75225   { 20085 /* v_cmpx_le_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75235   { 20117 /* v_cmpx_le_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75248   { 20149 /* v_cmpx_le_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75262   { 20213 /* v_cmpx_le_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75275   { 20245 /* v_cmpx_le_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75281   { 20309 /* v_cmpx_lg_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
75284   { 20309 /* v_cmpx_lg_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
75293   { 20309 /* v_cmpx_lg_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75297   { 20341 /* v_cmpx_lg_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75300   { 20341 /* v_cmpx_lg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75303   { 20341 /* v_cmpx_lg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75312   { 20341 /* v_cmpx_lg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75316   { 20373 /* v_cmpx_lg_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75319   { 20373 /* v_cmpx_lg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75322   { 20373 /* v_cmpx_lg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75324   { 20405 /* v_cmpx_lt_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
75327   { 20405 /* v_cmpx_lt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
75336   { 20405 /* v_cmpx_lt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75340   { 20437 /* v_cmpx_lt_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75343   { 20437 /* v_cmpx_lt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75346   { 20437 /* v_cmpx_lt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75355   { 20437 /* v_cmpx_lt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75359   { 20469 /* v_cmpx_lt_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75362   { 20469 /* v_cmpx_lt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75365   { 20469 /* v_cmpx_lt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75375   { 20501 /* v_cmpx_lt_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75388   { 20533 /* v_cmpx_lt_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75402   { 20597 /* v_cmpx_lt_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75415   { 20629 /* v_cmpx_lt_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75429   { 20693 /* v_cmpx_ne_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75442   { 20725 /* v_cmpx_ne_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75456   { 20789 /* v_cmpx_ne_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75469   { 20821 /* v_cmpx_ne_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75475   { 20885 /* v_cmpx_neq_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
75478   { 20885 /* v_cmpx_neq_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
75487   { 20885 /* v_cmpx_neq_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75491   { 20919 /* v_cmpx_neq_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75494   { 20919 /* v_cmpx_neq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75497   { 20919 /* v_cmpx_neq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75506   { 20919 /* v_cmpx_neq_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75510   { 20953 /* v_cmpx_neq_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75513   { 20953 /* v_cmpx_neq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75516   { 20953 /* v_cmpx_neq_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75518   { 20987 /* v_cmpx_nge_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
75521   { 20987 /* v_cmpx_nge_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
75530   { 20987 /* v_cmpx_nge_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75534   { 21021 /* v_cmpx_nge_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75537   { 21021 /* v_cmpx_nge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75540   { 21021 /* v_cmpx_nge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75549   { 21021 /* v_cmpx_nge_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75553   { 21055 /* v_cmpx_nge_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75556   { 21055 /* v_cmpx_nge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75559   { 21055 /* v_cmpx_nge_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75561   { 21089 /* v_cmpx_ngt_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
75564   { 21089 /* v_cmpx_ngt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
75573   { 21089 /* v_cmpx_ngt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75577   { 21123 /* v_cmpx_ngt_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75580   { 21123 /* v_cmpx_ngt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75583   { 21123 /* v_cmpx_ngt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75592   { 21123 /* v_cmpx_ngt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75596   { 21157 /* v_cmpx_ngt_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75599   { 21157 /* v_cmpx_ngt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75602   { 21157 /* v_cmpx_ngt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75604   { 21191 /* v_cmpx_nle_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
75607   { 21191 /* v_cmpx_nle_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
75616   { 21191 /* v_cmpx_nle_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75620   { 21225 /* v_cmpx_nle_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75623   { 21225 /* v_cmpx_nle_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75626   { 21225 /* v_cmpx_nle_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75635   { 21225 /* v_cmpx_nle_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75639   { 21259 /* v_cmpx_nle_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75642   { 21259 /* v_cmpx_nle_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75645   { 21259 /* v_cmpx_nle_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75647   { 21293 /* v_cmpx_nlg_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
75650   { 21293 /* v_cmpx_nlg_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
75659   { 21293 /* v_cmpx_nlg_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75663   { 21327 /* v_cmpx_nlg_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75666   { 21327 /* v_cmpx_nlg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75669   { 21327 /* v_cmpx_nlg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75678   { 21327 /* v_cmpx_nlg_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75682   { 21361 /* v_cmpx_nlg_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75685   { 21361 /* v_cmpx_nlg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75688   { 21361 /* v_cmpx_nlg_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75690   { 21395 /* v_cmpx_nlt_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
75693   { 21395 /* v_cmpx_nlt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
75702   { 21395 /* v_cmpx_nlt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75706   { 21429 /* v_cmpx_nlt_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75709   { 21429 /* v_cmpx_nlt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75712   { 21429 /* v_cmpx_nlt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75721   { 21429 /* v_cmpx_nlt_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75725   { 21463 /* v_cmpx_nlt_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75728   { 21463 /* v_cmpx_nlt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75731   { 21463 /* v_cmpx_nlt_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75733   { 21497 /* v_cmpx_o_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
75736   { 21497 /* v_cmpx_o_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
75745   { 21497 /* v_cmpx_o_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75749   { 21527 /* v_cmpx_o_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75752   { 21527 /* v_cmpx_o_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75755   { 21527 /* v_cmpx_o_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75764   { 21527 /* v_cmpx_o_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75768   { 21557 /* v_cmpx_o_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75771   { 21557 /* v_cmpx_o_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75774   { 21557 /* v_cmpx_o_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75781   { 21587 /* v_cmpx_t_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75794   { 21617 /* v_cmpx_t_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75805   { 21677 /* v_cmpx_t_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75818   { 21707 /* v_cmpx_t_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75824   { 21767 /* v_cmpx_tru_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
75827   { 21767 /* v_cmpx_tru_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
75836   { 21767 /* v_cmpx_tru_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75840   { 21801 /* v_cmpx_tru_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75843   { 21801 /* v_cmpx_tru_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75846   { 21801 /* v_cmpx_tru_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75855   { 21801 /* v_cmpx_tru_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75859   { 21835 /* v_cmpx_tru_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75862   { 21835 /* v_cmpx_tru_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75865   { 21835 /* v_cmpx_tru_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75867   { 21869 /* v_cmpx_u_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
75870   { 21869 /* v_cmpx_u_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
75879   { 21869 /* v_cmpx_u_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75883   { 21899 /* v_cmpx_u_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75886   { 21899 /* v_cmpx_u_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75889   { 21899 /* v_cmpx_u_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75898   { 21899 /* v_cmpx_u_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75902   { 21929 /* v_cmpx_u_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasNoSdstCMPX_isGFX10Plus },
75905   { 21929 /* v_cmpx_u_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
75908   { 21929 /* v_cmpx_u_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
75931   { 21959 /* v_cndmask_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
75947   { 21959 /* v_cndmask_b32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus_isWave64 },
75953   { 21959 /* v_cndmask_b32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
75959   { 21959 /* v_cndmask_b32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
75965   { 21959 /* v_cndmask_b32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus_isWave32 },
75974   { 21973 /* v_cos_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
75977   { 21973 /* v_cos_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
75979   { 21973 /* v_cos_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75990   { 21973 /* v_cos_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
75996   { 21973 /* v_cos_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76010   { 21983 /* v_cos_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76013   { 21983 /* v_cos_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76016   { 21983 /* v_cos_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76018   { 21983 /* v_cos_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76029   { 21983 /* v_cos_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76035   { 21983 /* v_cos_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76047   { 21993 /* v_cubeid_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76050   { 21993 /* v_cubeid_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76053   { 21993 /* v_cubeid_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76056   { 22006 /* v_cubema_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76059   { 22006 /* v_cubema_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76062   { 22006 /* v_cubema_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76065   { 22019 /* v_cubesc_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76068   { 22019 /* v_cubesc_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76071   { 22019 /* v_cubesc_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76074   { 22032 /* v_cubetc_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76077   { 22032 /* v_cubetc_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76080   { 22032 /* v_cubetc_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76085   { 22045 /* v_cvt_f16_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76088   { 22045 /* v_cvt_f16_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76091   { 22045 /* v_cvt_f16_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76093   { 22045 /* v_cvt_f16_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76104   { 22045 /* v_cvt_f16_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76110   { 22045 /* v_cvt_f16_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76123   { 22059 /* v_cvt_f16_i16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
76125   { 22059 /* v_cvt_f16_i16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
76131   { 22059 /* v_cvt_f16_i16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
76142   { 22059 /* v_cvt_f16_i16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76148   { 22059 /* v_cvt_f16_i16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76155   { 22073 /* v_cvt_f16_u16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
76157   { 22073 /* v_cvt_f16_u16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
76163   { 22073 /* v_cvt_f16_u16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
76174   { 22073 /* v_cvt_f16_u16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76180   { 22073 /* v_cvt_f16_u16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76188   { 22087 /* v_cvt_f32_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76191   { 22087 /* v_cvt_f32_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76194   { 22087 /* v_cvt_f32_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76196   { 22087 /* v_cvt_f32_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76207   { 22087 /* v_cvt_f32_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76213   { 22087 /* v_cvt_f32_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76225   { 22101 /* v_cvt_f32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76228   { 22101 /* v_cvt_f32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76231   { 22101 /* v_cvt_f32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76235   { 22115 /* v_cvt_f32_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76237   { 22115 /* v_cvt_f32_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76239   { 22115 /* v_cvt_f32_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76245   { 22115 /* v_cvt_f32_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76256   { 22115 /* v_cvt_f32_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76262   { 22115 /* v_cvt_f32_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76269   { 22129 /* v_cvt_f32_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76271   { 22129 /* v_cvt_f32_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76273   { 22129 /* v_cvt_f32_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76279   { 22129 /* v_cvt_f32_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76290   { 22129 /* v_cvt_f32_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76296   { 22129 /* v_cvt_f32_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76303   { 22143 /* v_cvt_f32_ubyte0 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76305   { 22143 /* v_cvt_f32_ubyte0 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76307   { 22143 /* v_cvt_f32_ubyte0 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76313   { 22143 /* v_cvt_f32_ubyte0 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76324   { 22143 /* v_cvt_f32_ubyte0 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76330   { 22143 /* v_cvt_f32_ubyte0 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76337   { 22160 /* v_cvt_f32_ubyte1 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76339   { 22160 /* v_cvt_f32_ubyte1 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76341   { 22160 /* v_cvt_f32_ubyte1 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76347   { 22160 /* v_cvt_f32_ubyte1 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76358   { 22160 /* v_cvt_f32_ubyte1 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76364   { 22160 /* v_cvt_f32_ubyte1 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76371   { 22177 /* v_cvt_f32_ubyte2 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76373   { 22177 /* v_cvt_f32_ubyte2 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76375   { 22177 /* v_cvt_f32_ubyte2 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76381   { 22177 /* v_cvt_f32_ubyte2 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76392   { 22177 /* v_cvt_f32_ubyte2 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76398   { 22177 /* v_cvt_f32_ubyte2 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76405   { 22194 /* v_cvt_f32_ubyte3 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76407   { 22194 /* v_cvt_f32_ubyte3 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76409   { 22194 /* v_cvt_f32_ubyte3 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76415   { 22194 /* v_cvt_f32_ubyte3 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76426   { 22194 /* v_cvt_f32_ubyte3 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76432   { 22194 /* v_cvt_f32_ubyte3 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76438   { 22211 /* v_cvt_f64_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76441   { 22211 /* v_cvt_f64_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76444   { 22211 /* v_cvt_f64_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76446   { 22225 /* v_cvt_f64_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76448   { 22225 /* v_cvt_f64_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76450   { 22225 /* v_cvt_f64_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76452   { 22239 /* v_cvt_f64_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76454   { 22239 /* v_cvt_f64_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76456   { 22239 /* v_cvt_f64_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76458   { 22253 /* v_cvt_flr_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76460   { 22253 /* v_cvt_flr_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76462   { 22253 /* v_cvt_flr_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76466   { 22253 /* v_cvt_flr_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76471   { 22253 /* v_cvt_flr_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76476   { 22253 /* v_cvt_flr_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76492   { 22271 /* v_cvt_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
76494   { 22271 /* v_cvt_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
76498   { 22271 /* v_cvt_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
76503   { 22271 /* v_cvt_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76508   { 22271 /* v_cvt_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76524   { 22285 /* v_cvt_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76526   { 22285 /* v_cvt_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76528   { 22285 /* v_cvt_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76532   { 22285 /* v_cvt_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76537   { 22285 /* v_cvt_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76542   { 22285 /* v_cvt_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76558   { 22299 /* v_cvt_i32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76560   { 22299 /* v_cvt_i32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76562   { 22299 /* v_cvt_i32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76564   { 22313 /* v_cvt_norm_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
76566   { 22313 /* v_cvt_norm_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
76570   { 22313 /* v_cvt_norm_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_HasSDWA },
76575   { 22313 /* v_cvt_norm_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76580   { 22313 /* v_cvt_norm_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76596   { 22332 /* v_cvt_norm_u16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
76598   { 22332 /* v_cvt_norm_u16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
76602   { 22332 /* v_cvt_norm_u16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_HasSDWA },
76607   { 22332 /* v_cvt_norm_u16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76612   { 22332 /* v_cvt_norm_u16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76630   { 22351 /* v_cvt_off_f32_i4 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76632   { 22351 /* v_cvt_off_f32_i4 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76634   { 22351 /* v_cvt_off_f32_i4 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76640   { 22351 /* v_cvt_off_f32_i4 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76651   { 22351 /* v_cvt_off_f32_i4 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76657   { 22351 /* v_cvt_off_f32_i4 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76663   { 22402 /* v_cvt_pk_u8_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76666   { 22402 /* v_cvt_pk_u8_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76669   { 22402 /* v_cvt_pk_u8_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76672   { 22418 /* v_cvt_pkaccum_u8_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76675   { 22418 /* v_cvt_pkaccum_u8_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76677   { 22439 /* v_cvt_pknorm_i16_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
76680   { 22439 /* v_cvt_pknorm_i16_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
76683   { 22460 /* v_cvt_pknorm_i16_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76685   { 22460 /* v_cvt_pknorm_i16_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76687   { 22460 /* v_cvt_pknorm_i16_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76689   { 22481 /* v_cvt_pknorm_u16_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
76692   { 22481 /* v_cvt_pknorm_u16_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
76695   { 22502 /* v_cvt_pknorm_u16_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76697   { 22502 /* v_cvt_pknorm_u16_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76699   { 22502 /* v_cvt_pknorm_u16_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76702   { 22523 /* v_cvt_pkrtz_f16_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76705   { 22523 /* v_cvt_pkrtz_f16_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76708   { 22523 /* v_cvt_pkrtz_f16_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76710   { 22543 /* v_cvt_rpi_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76712   { 22543 /* v_cvt_rpi_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76714   { 22543 /* v_cvt_rpi_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76718   { 22543 /* v_cvt_rpi_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76723   { 22543 /* v_cvt_rpi_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76728   { 22543 /* v_cvt_rpi_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76744   { 22561 /* v_cvt_u16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
76746   { 22561 /* v_cvt_u16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
76750   { 22561 /* v_cvt_u16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
76755   { 22561 /* v_cvt_u16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76760   { 22561 /* v_cvt_u16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76776   { 22575 /* v_cvt_u32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76778   { 22575 /* v_cvt_u32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76780   { 22575 /* v_cvt_u32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76784   { 22575 /* v_cvt_u32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
76789   { 22575 /* v_cvt_u32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
76794   { 22575 /* v_cvt_u32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
76810   { 22589 /* v_cvt_u32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76812   { 22589 /* v_cvt_u32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76814   { 22589 /* v_cvt_u32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76817   { 22603 /* v_div_fixup_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Only },
76819   { 22603 /* v_div_fixup_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76822   { 22603 /* v_div_fixup_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Only },
76826   { 22619 /* v_div_fixup_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76829   { 22619 /* v_div_fixup_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76832   { 22619 /* v_div_fixup_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76835   { 22635 /* v_div_fixup_f64 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76838   { 22635 /* v_div_fixup_f64 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76841   { 22635 /* v_div_fixup_f64 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76844   { 22651 /* v_div_fixup_legacy_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Only },
76847   { 22674 /* v_div_fmas_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76850   { 22674 /* v_div_fmas_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76853   { 22674 /* v_div_fmas_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76856   { 22689 /* v_div_fmas_f64 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
76859   { 22689 /* v_div_fmas_f64 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
76862   { 22689 /* v_div_fmas_f64 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
76869   { 22736 /* v_dot2_f32_f16 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_HasDot2Insts_isGFX10Plus },
76874   { 22736 /* v_dot2_f32_f16 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_HasDot2Insts_HasVOP3PInsts },
76879   { 22751 /* v_dot2_i32_i16 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_HasDot2Insts_isGFX10Plus },
76884   { 22751 /* v_dot2_i32_i16 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_HasDot2Insts_HasVOP3PInsts },
76889   { 22766 /* v_dot2_u32_u16 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_HasDot2Insts_isGFX10Plus },
76894   { 22766 /* v_dot2_u32_u16 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_HasDot2Insts_HasVOP3PInsts },
76917   { 22813 /* v_dot4_i32_i8 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_HasDot1Insts_isGFX10Plus },
76922   { 22813 /* v_dot4_i32_i8 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_HasDot1Insts_HasVOP3PInsts },
76927   { 22827 /* v_dot4_u32_u8 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_HasDot2Insts_isGFX10Plus },
76932   { 22827 /* v_dot4_u32_u8 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_HasDot2Insts_HasVOP3PInsts },
76950   { 22856 /* v_dot8_i32_i4 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_HasDot1Insts_isGFX10Plus },
76955   { 22856 /* v_dot8_i32_i4 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_HasDot1Insts_HasVOP3PInsts },
76960   { 22870 /* v_dot8_u32_u4 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_HasDot2Insts_isGFX10Plus },
76965   { 22870 /* v_dot8_u32_u4 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_HasDot2Insts_HasVOP3PInsts },
76979   { 22899 /* v_exp_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
76982   { 22899 /* v_exp_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
76984   { 22899 /* v_exp_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
76995   { 22899 /* v_exp_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77001   { 22899 /* v_exp_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77015   { 22909 /* v_exp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77018   { 22909 /* v_exp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77021   { 22909 /* v_exp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77023   { 22909 /* v_exp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77034   { 22909 /* v_exp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77040   { 22909 /* v_exp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77052   { 22919 /* v_exp_legacy_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7GFX8GFX9_isGFX7Only },
77055   { 22919 /* v_exp_legacy_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7GFX8GFX9_isGFX8GFX9 },
77057   { 22919 /* v_exp_legacy_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7GFX8GFX9_HasSDWA },
77068   { 22919 /* v_exp_legacy_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77079   { 22936 /* v_ffbh_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77084   { 22936 /* v_ffbh_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77089   { 22936 /* v_ffbh_i32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77105   { 22947 /* v_ffbh_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77110   { 22947 /* v_ffbh_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77115   { 22947 /* v_ffbh_u32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77131   { 22958 /* v_ffbl_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77136   { 22958 /* v_ffbl_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77141   { 22958 /* v_ffbl_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77154   { 22969 /* v_floor_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
77157   { 22969 /* v_floor_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
77159   { 22969 /* v_floor_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
77170   { 22969 /* v_floor_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77176   { 22969 /* v_floor_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77190   { 22981 /* v_floor_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77193   { 22981 /* v_floor_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77196   { 22981 /* v_floor_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77198   { 22981 /* v_floor_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77209   { 22981 /* v_floor_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77215   { 22981 /* v_floor_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77227   { 22993 /* v_floor_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX10Plus },
77230   { 22993 /* v_floor_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX7Only },
77233   { 22993 /* v_floor_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX8GFX9 },
77236   { 23005 /* v_fma_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Only },
77238   { 23005 /* v_fma_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77241   { 23005 /* v_fma_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Only },
77245   { 23015 /* v_fma_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77248   { 23015 /* v_fma_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77251   { 23015 /* v_fma_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77254   { 23025 /* v_fma_f64 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77257   { 23025 /* v_fma_f64 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77260   { 23025 /* v_fma_f64 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77263   { 23035 /* v_fma_legacy_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Only },
77265   { 23052 /* v_fma_mix_f32 */, 64 /* 6 */, MCK_ImmClampSI, AMFBS_HasFmaMixInsts_isGFX10Plus },
77269   { 23052 /* v_fma_mix_f32 */, 64 /* 6 */, MCK_ImmClampSI, AMFBS_HasFmaMixInsts_HasVOP3PInsts },
77273   { 23066 /* v_fma_mixhi_f16 */, 64 /* 6 */, MCK_ImmClampSI, AMFBS_HasFmaMixInsts_isGFX10Plus },
77277   { 23066 /* v_fma_mixhi_f16 */, 64 /* 6 */, MCK_ImmClampSI, AMFBS_HasFmaMixInsts_HasVOP3PInsts },
77281   { 23082 /* v_fma_mixlo_f16 */, 64 /* 6 */, MCK_ImmClampSI, AMFBS_HasFmaMixInsts_isGFX10Plus },
77285   { 23082 /* v_fma_mixlo_f16 */, 64 /* 6 */, MCK_ImmClampSI, AMFBS_HasFmaMixInsts_HasVOP3PInsts },
77294   { 23122 /* v_fmac_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus_isGFX10Plus },
77305   { 23133 /* v_fmac_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasDLInsts_isGFX10Plus },
77308   { 23133 /* v_fmac_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasDLInsts_isGFX8GFX9 },
77315   { 23133 /* v_fmac_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasDLInsts_HasSDWA },
77332   { 23168 /* v_fract_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
77335   { 23168 /* v_fract_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
77337   { 23168 /* v_fract_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
77348   { 23168 /* v_fract_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77354   { 23168 /* v_fract_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77368   { 23180 /* v_fract_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77371   { 23180 /* v_fract_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77374   { 23180 /* v_fract_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77376   { 23180 /* v_fract_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77387   { 23180 /* v_fract_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77393   { 23180 /* v_fract_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77405   { 23192 /* v_fract_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77408   { 23192 /* v_fract_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77411   { 23192 /* v_fract_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77413   { 23204 /* v_frexp_exp_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
77415   { 23204 /* v_frexp_exp_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
77419   { 23204 /* v_frexp_exp_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
77424   { 23204 /* v_frexp_exp_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77429   { 23204 /* v_frexp_exp_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77445   { 23224 /* v_frexp_exp_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77447   { 23224 /* v_frexp_exp_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77449   { 23224 /* v_frexp_exp_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77453   { 23224 /* v_frexp_exp_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77458   { 23224 /* v_frexp_exp_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77463   { 23224 /* v_frexp_exp_i32_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77479   { 23244 /* v_frexp_exp_i32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77481   { 23244 /* v_frexp_exp_i32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77483   { 23244 /* v_frexp_exp_i32_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77488   { 23264 /* v_frexp_mant_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
77491   { 23264 /* v_frexp_mant_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
77493   { 23264 /* v_frexp_mant_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
77504   { 23264 /* v_frexp_mant_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77510   { 23264 /* v_frexp_mant_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77524   { 23281 /* v_frexp_mant_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77527   { 23281 /* v_frexp_mant_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77530   { 23281 /* v_frexp_mant_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77532   { 23281 /* v_frexp_mant_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77543   { 23281 /* v_frexp_mant_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77549   { 23281 /* v_frexp_mant_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77561   { 23298 /* v_frexp_mant_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77564   { 23298 /* v_frexp_mant_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77567   { 23298 /* v_frexp_mant_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77577   { 23315 /* v_interp_mov_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Plus_isGFX10Plus },
77581   { 23315 /* v_interp_mov_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Plus_isGFX8GFX9 },
77591   { 23332 /* v_interp_p1_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Plus_isGFX10Plus },
77595   { 23332 /* v_interp_p1_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Plus_isGFX8GFX9 },
77599   { 23348 /* v_interp_p1ll_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
77604   { 23348 /* v_interp_p1ll_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
77610   { 23366 /* v_interp_p1lv_f16 */, 64 /* 6 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
77616   { 23366 /* v_interp_p1lv_f16 */, 64 /* 6 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
77620   { 23384 /* v_interp_p2_f16 */, 64 /* 6 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
77624   { 23384 /* v_interp_p2_f16 */, 64 /* 6 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX9Only },
77628   { 23384 /* v_interp_p2_f16 */, 64 /* 6 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8Only },
77636   { 23400 /* v_interp_p2_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Plus_isGFX10Plus },
77640   { 23400 /* v_interp_p2_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Plus_isGFX8GFX9 },
77643   { 23416 /* v_interp_p2_legacy_f16 */, 64 /* 6 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX9Only },
77650   { 23439 /* v_ldexp_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
77654   { 23439 /* v_ldexp_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
77663   { 23439 /* v_ldexp_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
77678   { 23439 /* v_ldexp_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77686   { 23439 /* v_ldexp_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77694   { 23451 /* v_ldexp_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77698   { 23451 /* v_ldexp_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77702   { 23451 /* v_ldexp_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77706   { 23463 /* v_ldexp_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77710   { 23463 /* v_ldexp_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77714   { 23463 /* v_ldexp_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77717   { 23485 /* v_log_clamp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
77722   { 23501 /* v_log_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
77725   { 23501 /* v_log_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
77727   { 23501 /* v_log_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
77738   { 23501 /* v_log_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77744   { 23501 /* v_log_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77758   { 23511 /* v_log_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77761   { 23511 /* v_log_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77764   { 23511 /* v_log_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77766   { 23511 /* v_log_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77777   { 23511 /* v_log_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77783   { 23511 /* v_log_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77795   { 23521 /* v_log_legacy_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7GFX8GFX9_isGFX7Only },
77798   { 23521 /* v_log_legacy_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7GFX8GFX9_isGFX8GFX9 },
77800   { 23521 /* v_log_legacy_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7GFX8GFX9_HasSDWA },
77811   { 23521 /* v_log_legacy_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77820   { 23589 /* v_lshlrev_b16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
77826   { 23589 /* v_lshlrev_b16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77843   { 23603 /* v_lshlrev_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77849   { 23603 /* v_lshlrev_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77855   { 23603 /* v_lshlrev_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77865   { 23653 /* v_lshrrev_b16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
77871   { 23653 /* v_lshrrev_b16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77888   { 23667 /* v_lshrrev_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77894   { 23667 /* v_lshrrev_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77900   { 23667 /* v_lshrrev_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
77907   { 23695 /* v_mac_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
77914   { 23695 /* v_mac_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
77923   { 23705 /* v_mac_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77926   { 23705 /* v_mac_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77929   { 23705 /* v_mac_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77936   { 23705 /* v_mac_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
77951   { 23715 /* v_mac_legacy_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
77954   { 23715 /* v_mac_legacy_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
77963   { 23715 /* v_mac_legacy_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
77970   { 23732 /* v_mad_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8Only },
77972   { 23732 /* v_mad_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Only_isGFX9Only },
77976   { 23742 /* v_mad_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77979   { 23742 /* v_mad_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77982   { 23742 /* v_mad_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77983   { 23752 /* v_mad_i16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8Only },
77984   { 23752 /* v_mad_i16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
77986   { 23752 /* v_mad_i16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX9Only },
77988   { 23762 /* v_mad_i32_i16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
77990   { 23762 /* v_mad_i32_i16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
77992   { 23776 /* v_mad_i32_i24 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
77993   { 23776 /* v_mad_i32_i24 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
77994   { 23776 /* v_mad_i32_i24 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
77996   { 23790 /* v_mad_i64_i32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX10Plus },
77998   { 23790 /* v_mad_i64_i32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX7Only },
78000   { 23790 /* v_mad_i64_i32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX8GFX9 },
78003   { 23804 /* v_mad_legacy_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX9Only },
78006   { 23821 /* v_mad_legacy_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78009   { 23821 /* v_mad_legacy_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78012   { 23821 /* v_mad_legacy_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78013   { 23838 /* v_mad_legacy_i16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX9Only },
78014   { 23855 /* v_mad_legacy_u16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX9Only },
78016   { 23872 /* v_mad_mix_f32 */, 64 /* 6 */, MCK_ImmClampSI, AMFBS_HasMadMixInsts_HasVOP3PInsts },
78020   { 23886 /* v_mad_mixhi_f16 */, 64 /* 6 */, MCK_ImmClampSI, AMFBS_HasMadMixInsts_HasVOP3PInsts },
78024   { 23902 /* v_mad_mixlo_f16 */, 64 /* 6 */, MCK_ImmClampSI, AMFBS_HasMadMixInsts_HasVOP3PInsts },
78027   { 23918 /* v_mad_u16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8Only },
78028   { 23918 /* v_mad_u16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78030   { 23918 /* v_mad_u16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX9Only },
78032   { 23928 /* v_mad_u32_u16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78034   { 23928 /* v_mad_u32_u16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78036   { 23942 /* v_mad_u32_u24 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78037   { 23942 /* v_mad_u32_u24 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78038   { 23942 /* v_mad_u32_u24 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78040   { 23956 /* v_mad_u64_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX10Plus },
78042   { 23956 /* v_mad_u64_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX7Only },
78044   { 23956 /* v_mad_u64_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX8GFX9 },
78054   { 24018 /* v_max3_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78057   { 24018 /* v_max3_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78061   { 24029 /* v_max3_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78064   { 24029 /* v_max3_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78067   { 24029 /* v_max3_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78068   { 24040 /* v_max3_i16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78070   { 24040 /* v_max3_i16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78072   { 24062 /* v_max3_u16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78074   { 24062 /* v_max3_u16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78080   { 24084 /* v_max_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
78083   { 24084 /* v_max_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
78090   { 24084 /* v_max_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
78103   { 24084 /* v_max_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78110   { 24084 /* v_max_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78119   { 24094 /* v_max_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78122   { 24094 /* v_max_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78125   { 24094 /* v_max_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78132   { 24094 /* v_max_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78145   { 24094 /* v_max_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78152   { 24094 /* v_max_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78159   { 24104 /* v_max_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78162   { 24104 /* v_max_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78165   { 24104 /* v_max_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78171   { 24114 /* v_max_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
78177   { 24114 /* v_max_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78194   { 24124 /* v_max_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78200   { 24124 /* v_max_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78206   { 24124 /* v_max_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78213   { 24134 /* v_max_legacy_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
78219   { 24151 /* v_max_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
78225   { 24151 /* v_max_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78242   { 24161 /* v_max_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78248   { 24161 /* v_max_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78254   { 24161 /* v_max_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78260   { 24209 /* v_med3_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78263   { 24209 /* v_med3_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78267   { 24220 /* v_med3_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78270   { 24220 /* v_med3_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78273   { 24220 /* v_med3_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78274   { 24231 /* v_med3_i16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78276   { 24231 /* v_med3_i16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78278   { 24253 /* v_med3_u16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78280   { 24253 /* v_med3_u16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78343   { 24709 /* v_min3_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78346   { 24709 /* v_min3_f16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78350   { 24720 /* v_min3_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78353   { 24720 /* v_min3_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78356   { 24720 /* v_min3_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78357   { 24731 /* v_min3_i16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78359   { 24731 /* v_min3_i16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78361   { 24753 /* v_min3_u16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78363   { 24753 /* v_min3_u16 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78369   { 24775 /* v_min_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
78372   { 24775 /* v_min_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
78379   { 24775 /* v_min_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
78392   { 24775 /* v_min_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78399   { 24775 /* v_min_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78408   { 24785 /* v_min_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78411   { 24785 /* v_min_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78414   { 24785 /* v_min_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78421   { 24785 /* v_min_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78434   { 24785 /* v_min_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78441   { 24785 /* v_min_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78448   { 24795 /* v_min_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78451   { 24795 /* v_min_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78454   { 24795 /* v_min_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78460   { 24805 /* v_min_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
78466   { 24805 /* v_min_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78483   { 24815 /* v_min_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78489   { 24815 /* v_min_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78495   { 24815 /* v_min_i32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78502   { 24825 /* v_min_legacy_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
78508   { 24842 /* v_min_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
78514   { 24842 /* v_min_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78531   { 24852 /* v_min_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78537   { 24852 /* v_min_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78543   { 24852 /* v_min_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78555   { 24862 /* v_mov_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78560   { 24862 /* v_mov_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78565   { 24862 /* v_mov_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78581   { 24872 /* v_mov_fed_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78586   { 24872 /* v_mov_fed_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78591   { 24872 /* v_mov_fed_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78600   { 24946 /* v_mqsad_pk_u16_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78601   { 24946 /* v_mqsad_pk_u16_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78602   { 24946 /* v_mqsad_pk_u16_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78603   { 24964 /* v_mqsad_u32_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX10Plus },
78604   { 24964 /* v_mqsad_u32_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX7Only },
78605   { 24964 /* v_mqsad_u32_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX8GFX9 },
78606   { 24979 /* v_msad_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78607   { 24979 /* v_msad_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78608   { 24979 /* v_msad_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78613   { 24989 /* v_mul_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
78616   { 24989 /* v_mul_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
78623   { 24989 /* v_mul_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
78636   { 24989 /* v_mul_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78643   { 24989 /* v_mul_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78652   { 24999 /* v_mul_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78655   { 24999 /* v_mul_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78658   { 24999 /* v_mul_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78665   { 24999 /* v_mul_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78678   { 24999 /* v_mul_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78685   { 24999 /* v_mul_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78692   { 25009 /* v_mul_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78695   { 25009 /* v_mul_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78698   { 25009 /* v_mul_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78711   { 25032 /* v_mul_hi_i32_i24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78717   { 25032 /* v_mul_hi_i32_i24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78723   { 25032 /* v_mul_hi_i32_i24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78740   { 25062 /* v_mul_hi_u32_u24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78746   { 25062 /* v_mul_hi_u32_u24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78752   { 25062 /* v_mul_hi_u32_u24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78769   { 25079 /* v_mul_i32_i24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78775   { 25079 /* v_mul_i32_i24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78781   { 25079 /* v_mul_i32_i24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78790   { 25093 /* v_mul_legacy_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78793   { 25093 /* v_mul_legacy_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
78796   { 25093 /* v_mul_legacy_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
78803   { 25093 /* v_mul_legacy_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78816   { 25093 /* v_mul_legacy_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78823   { 25093 /* v_mul_legacy_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78833   { 25123 /* v_mul_lo_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
78839   { 25123 /* v_mul_lo_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78856   { 25149 /* v_mul_u32_u24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78862   { 25149 /* v_mul_u32_u24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78868   { 25149 /* v_mul_u32_u24 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78875   { 25163 /* v_mullit_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7GFX10_isGFX10Plus },
78878   { 25163 /* v_mullit_f32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7 },
78886   { 25182 /* v_not_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78891   { 25182 /* v_not_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78896   { 25182 /* v_not_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78917   { 25202 /* v_or_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
78923   { 25202 /* v_or_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
78929   { 25202 /* v_or_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
78935   { 25211 /* v_pack_b32_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
78938   { 25211 /* v_pack_b32_f16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
78942   { 25284 /* v_pk_add_f16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78947   { 25284 /* v_pk_add_f16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
78952   { 25297 /* v_pk_add_i16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78957   { 25297 /* v_pk_add_i16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
78962   { 25310 /* v_pk_add_u16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78967   { 25310 /* v_pk_add_u16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
78972   { 25323 /* v_pk_ashrrev_i16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78977   { 25323 /* v_pk_ashrrev_i16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
78982   { 25340 /* v_pk_fma_f16 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78987   { 25340 /* v_pk_fma_f16 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
78992   { 25367 /* v_pk_lshlrev_b16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
78997   { 25367 /* v_pk_lshlrev_b16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79002   { 25384 /* v_pk_lshrrev_b16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79007   { 25384 /* v_pk_lshrrev_b16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79012   { 25401 /* v_pk_mad_i16 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79017   { 25401 /* v_pk_mad_i16 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79022   { 25414 /* v_pk_mad_u16 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79027   { 25414 /* v_pk_mad_u16 */, 256 /* 8 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79032   { 25427 /* v_pk_max_f16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79037   { 25427 /* v_pk_max_f16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79042   { 25440 /* v_pk_max_i16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79047   { 25440 /* v_pk_max_i16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79052   { 25453 /* v_pk_max_u16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79057   { 25453 /* v_pk_max_u16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79062   { 25466 /* v_pk_min_f16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79067   { 25466 /* v_pk_min_f16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79072   { 25479 /* v_pk_min_i16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79077   { 25479 /* v_pk_min_i16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79082   { 25492 /* v_pk_min_u16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79087   { 25492 /* v_pk_min_u16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79092   { 25505 /* v_pk_mul_f16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79097   { 25505 /* v_pk_mul_f16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79102   { 25518 /* v_pk_mul_lo_u16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79107   { 25518 /* v_pk_mul_lo_u16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79112   { 25534 /* v_pk_sub_i16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79117   { 25534 /* v_pk_sub_i16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79122   { 25547 /* v_pk_sub_u16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79127   { 25547 /* v_pk_sub_u16 */, 128 /* 7 */, MCK_ImmClampSI, AMFBS_HasVOP3PInsts },
79132   { 25560 /* v_qsad_pk_u16_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX10Plus },
79133   { 25560 /* v_qsad_pk_u16_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX7Only },
79134   { 25560 /* v_qsad_pk_u16_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX8GFX9 },
79137   { 25577 /* v_rcp_clamp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
79140   { 25593 /* v_rcp_clamp_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
79145   { 25609 /* v_rcp_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
79148   { 25609 /* v_rcp_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
79150   { 25609 /* v_rcp_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
79161   { 25609 /* v_rcp_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79167   { 25609 /* v_rcp_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79181   { 25619 /* v_rcp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79184   { 25619 /* v_rcp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79187   { 25619 /* v_rcp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79189   { 25619 /* v_rcp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
79200   { 25619 /* v_rcp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79206   { 25619 /* v_rcp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79218   { 25629 /* v_rcp_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79221   { 25629 /* v_rcp_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79224   { 25629 /* v_rcp_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79229   { 25639 /* v_rcp_iflag_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79232   { 25639 /* v_rcp_iflag_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79235   { 25639 /* v_rcp_iflag_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79237   { 25639 /* v_rcp_iflag_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
79248   { 25639 /* v_rcp_iflag_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79254   { 25639 /* v_rcp_iflag_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79266   { 25655 /* v_rcp_legacy_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
79271   { 25707 /* v_rndne_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
79274   { 25707 /* v_rndne_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
79276   { 25707 /* v_rndne_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
79287   { 25707 /* v_rndne_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79293   { 25707 /* v_rndne_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79307   { 25719 /* v_rndne_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79310   { 25719 /* v_rndne_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79313   { 25719 /* v_rndne_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79315   { 25719 /* v_rndne_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
79326   { 25719 /* v_rndne_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79332   { 25719 /* v_rndne_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79344   { 25731 /* v_rndne_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX10Plus },
79347   { 25731 /* v_rndne_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX7Only },
79350   { 25731 /* v_rndne_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX8GFX9 },
79353   { 25743 /* v_rsq_clamp_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
79356   { 25759 /* v_rsq_clamp_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
79361   { 25775 /* v_rsq_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
79364   { 25775 /* v_rsq_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
79366   { 25775 /* v_rsq_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
79377   { 25775 /* v_rsq_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79383   { 25775 /* v_rsq_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79397   { 25785 /* v_rsq_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79400   { 25785 /* v_rsq_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79403   { 25785 /* v_rsq_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79405   { 25785 /* v_rsq_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
79416   { 25785 /* v_rsq_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79422   { 25785 /* v_rsq_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79434   { 25795 /* v_rsq_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79437   { 25795 /* v_rsq_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79440   { 25795 /* v_rsq_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79443   { 25805 /* v_rsq_legacy_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7_isGFX6GFX7 },
79444   { 25822 /* v_sad_hi_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79445   { 25822 /* v_sad_hi_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79446   { 25822 /* v_sad_hi_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79447   { 25834 /* v_sad_u16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79448   { 25834 /* v_sad_u16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79449   { 25834 /* v_sad_u16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79450   { 25844 /* v_sad_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79451   { 25844 /* v_sad_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79452   { 25844 /* v_sad_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79453   { 25854 /* v_sad_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79454   { 25854 /* v_sad_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79455   { 25854 /* v_sad_u8 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79463   { 25863 /* v_sat_pk_u8_i16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_HasSDWA },
79468   { 25863 /* v_sat_pk_u8_i16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79473   { 25863 /* v_sat_pk_u8_i16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79487   { 25879 /* v_screen_partition_4se_b32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79495   { 25906 /* v_sin_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
79498   { 25906 /* v_sin_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
79500   { 25906 /* v_sin_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
79511   { 25906 /* v_sin_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79517   { 25906 /* v_sin_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79531   { 25916 /* v_sin_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79534   { 25916 /* v_sin_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79537   { 25916 /* v_sin_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79539   { 25916 /* v_sin_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
79550   { 25916 /* v_sin_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79556   { 25916 /* v_sin_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79570   { 25926 /* v_sqrt_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
79573   { 25926 /* v_sqrt_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
79575   { 25926 /* v_sqrt_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
79586   { 25926 /* v_sqrt_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79592   { 25926 /* v_sqrt_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79606   { 25937 /* v_sqrt_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79609   { 25937 /* v_sqrt_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79612   { 25937 /* v_sqrt_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79614   { 25937 /* v_sqrt_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
79625   { 25937 /* v_sqrt_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79631   { 25937 /* v_sqrt_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79643   { 25948 /* v_sqrt_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79646   { 25948 /* v_sqrt_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79649   { 25948 /* v_sqrt_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79653   { 25959 /* v_sub_co_ci_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79664   { 25959 /* v_sub_co_ci_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79675   { 25959 /* v_sub_co_ci_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus_isWave64 },
79686   { 25959 /* v_sub_co_ci_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus_isWave32 },
79692   { 25975 /* v_sub_co_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79694   { 25975 /* v_sub_co_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Only },
79700   { 25975 /* v_sub_co_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79709   { 25988 /* v_sub_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
79712   { 25988 /* v_sub_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
79719   { 25988 /* v_sub_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
79732   { 25988 /* v_sub_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79739   { 25988 /* v_sub_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79748   { 25998 /* v_sub_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79751   { 25998 /* v_sub_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79754   { 25998 /* v_sub_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
79761   { 25998 /* v_sub_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
79774   { 25998 /* v_sub_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79781   { 25998 /* v_sub_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79786   { 26008 /* v_sub_i16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX8GFX9 },
79789   { 26018 /* v_sub_i32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79790   { 26028 /* v_sub_nc_i16 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Plus_isGFX10Plus },
79792   { 26067 /* v_sub_nc_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasAddNoCarryInsts_isGFX10Plus },
79801   { 26067 /* v_sub_nc_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79811   { 26080 /* v_sub_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
79817   { 26080 /* v_sub_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79822   { 26090 /* v_sub_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasAddNoCarryInsts_isGFX9Only },
79824   { 26090 /* v_sub_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Only },
79834   { 26090 /* v_sub_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79840   { 26090 /* v_sub_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA_isGFX8Only },
79846   { 26100 /* v_subb_co_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Only },
79852   { 26100 /* v_subb_co_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79858   { 26114 /* v_subb_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79860   { 26114 /* v_subb_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX8Only },
79866   { 26114 /* v_subb_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA_isGFX8Only },
79872   { 26125 /* v_subbrev_co_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX9Only },
79878   { 26125 /* v_subbrev_co_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79884   { 26142 /* v_subbrev_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
79886   { 26142 /* v_subbrev_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX8Only },
79892   { 26142 /* v_subbrev_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA_isGFX8Only },
79900   { 26156 /* v_subrev_co_ci_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79911   { 26156 /* v_subrev_co_ci_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79922   { 26156 /* v_subrev_co_ci_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus_isWave64 },
79933   { 26156 /* v_subrev_co_ci_u32 */, 32 /* 5 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus_isWave32 },
79939   { 26175 /* v_subrev_co_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79941   { 26175 /* v_subrev_co_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX9Only },
79947   { 26175 /* v_subrev_co_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
79956   { 26191 /* v_subrev_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
79959   { 26191 /* v_subrev_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
79966   { 26191 /* v_subrev_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
79979   { 26191 /* v_subrev_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
79986   { 26191 /* v_subrev_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
79995   { 26204 /* v_subrev_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
79998   { 26204 /* v_subrev_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
80001   { 26204 /* v_subrev_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
80008   { 26204 /* v_subrev_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
80021   { 26204 /* v_subrev_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
80028   { 26204 /* v_subrev_f32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
80034   { 26217 /* v_subrev_i32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
80035   { 26230 /* v_subrev_nc_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasAddNoCarryInsts_isGFX10Plus },
80044   { 26230 /* v_subrev_nc_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
80054   { 26246 /* v_subrev_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
80060   { 26246 /* v_subrev_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
80065   { 26259 /* v_subrev_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasAddNoCarryInsts_isGFX9Only },
80067   { 26259 /* v_subrev_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_isGFX8Only },
80077   { 26259 /* v_subrev_u32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9_isGFX9Only },
80083   { 26259 /* v_subrev_u32 */, 16 /* 4 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA_isGFX8Only },
80091   { 26297 /* v_trig_preop_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
80095   { 26297 /* v_trig_preop_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
80099   { 26297 /* v_trig_preop_f64 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
80104   { 26314 /* v_trunc_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX10Plus },
80107   { 26314 /* v_trunc_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_isGFX8GFX9 },
80109   { 26314 /* v_trunc_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
80120   { 26314 /* v_trunc_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
80126   { 26314 /* v_trunc_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
80140   { 26326 /* v_trunc_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX10Plus },
80143   { 26326 /* v_trunc_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX6GFX7 },
80146   { 26326 /* v_trunc_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX8GFX9 },
80148   { 26326 /* v_trunc_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
80159   { 26326 /* v_trunc_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
80165   { 26326 /* v_trunc_f32 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
80177   { 26338 /* v_trunc_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX10Plus },
80180   { 26338 /* v_trunc_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX7Only },
80183   { 26338 /* v_trunc_f64 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_isGFX7Plus_isGFX8GFX9 },
80196   { 26376 /* v_xnor_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasDLInsts_HasSDWA },
80202   { 26376 /* v_xnor_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
80208   { 26376 /* v_xnor_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasDLInsts_HasSDWA9 },
80225   { 26398 /* v_xor_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA_HasSDWA },
80231   { 26398 /* v_xor_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA10_isGFX10Plus },
80237   { 26398 /* v_xor_b32 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_HasSDWA9_HasSDWA9 },
80327   case MCK_ImmClampSI: