reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
5294 case MCK_ImmCBSZ: 6267 case MCK_ImmCBSZ: { 10180 case MCK_ImmCBSZ: return "MCK_ImmCBSZ"; 22484 { 24275 /* v_mfma_f32_16x16x16f16 */, AMDGPU::V_MFMA_F32_16X16X16F16_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_128B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_128, MCK_AV_64, MCK_AV_64, MCK_AISrc_128B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22485 { 24298 /* v_mfma_f32_16x16x1f32 */, AMDGPU::V_MFMA_F32_16X16X1F32_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_512F321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_512, MCK_AV_32, MCK_AV_32, MCK_AISrc_512F32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22486 { 24320 /* v_mfma_f32_16x16x2bf16 */, AMDGPU::V_MFMA_F32_16X16X2BF16_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_512B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_512, MCK_AV_32, MCK_AV_32, MCK_AISrc_512B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22487 { 24343 /* v_mfma_f32_16x16x4f16 */, AMDGPU::V_MFMA_F32_16X16X4F16_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_512B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_512, MCK_AV_64, MCK_AV_64, MCK_AISrc_512B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22488 { 24365 /* v_mfma_f32_16x16x4f32 */, AMDGPU::V_MFMA_F32_16X16X4F32_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_128F321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_128, MCK_AV_32, MCK_AV_32, MCK_AISrc_128F32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22489 { 24387 /* v_mfma_f32_16x16x8bf16 */, AMDGPU::V_MFMA_F32_16X16X8BF16_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_128B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_128, MCK_AV_32, MCK_AV_32, MCK_AISrc_128B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22490 { 24410 /* v_mfma_f32_32x32x1f32 */, AMDGPU::V_MFMA_F32_32X32X1F32_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_1024F321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_1024, MCK_AV_32, MCK_AV_32, MCK_AISrc_1024F32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22491 { 24432 /* v_mfma_f32_32x32x2bf16 */, AMDGPU::V_MFMA_F32_32X32X2BF16_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_1024B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_1024, MCK_AV_32, MCK_AV_32, MCK_AISrc_1024B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22492 { 24455 /* v_mfma_f32_32x32x2f32 */, AMDGPU::V_MFMA_F32_32X32X2F32_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_512F321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_512, MCK_AV_32, MCK_AV_32, MCK_AISrc_512F32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22493 { 24477 /* v_mfma_f32_32x32x4bf16 */, AMDGPU::V_MFMA_F32_32X32X4BF16_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_512B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_512, MCK_AV_32, MCK_AV_32, MCK_AISrc_512B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22494 { 24500 /* v_mfma_f32_32x32x4f16 */, AMDGPU::V_MFMA_F32_32X32X4F16_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_1024B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_1024, MCK_AV_64, MCK_AV_64, MCK_AISrc_1024B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22495 { 24522 /* v_mfma_f32_32x32x8f16 */, AMDGPU::V_MFMA_F32_32X32X8F16_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_512B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_512, MCK_AV_64, MCK_AV_64, MCK_AISrc_512B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22496 { 24544 /* v_mfma_f32_4x4x1f32 */, AMDGPU::V_MFMA_F32_4X4X1F32_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_128F321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_128, MCK_AV_32, MCK_AV_32, MCK_AISrc_128F32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22497 { 24564 /* v_mfma_f32_4x4x2bf16 */, AMDGPU::V_MFMA_F32_4X4X2BF16_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_128B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_128, MCK_AV_32, MCK_AV_32, MCK_AISrc_128B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22498 { 24585 /* v_mfma_f32_4x4x4f16 */, AMDGPU::V_MFMA_F32_4X4X4F16_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_128B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_128, MCK_AV_64, MCK_AV_64, MCK_AISrc_128B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22499 { 24605 /* v_mfma_i32_16x16x16i8 */, AMDGPU::V_MFMA_I32_16X16X16I8_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_128B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_128, MCK_AV_32, MCK_AV_32, MCK_AISrc_128B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22500 { 24627 /* v_mfma_i32_16x16x4i8 */, AMDGPU::V_MFMA_I32_16X16X4I8_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_512B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_512, MCK_AV_32, MCK_AV_32, MCK_AISrc_512B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22501 { 24648 /* v_mfma_i32_32x32x4i8 */, AMDGPU::V_MFMA_I32_32X32X4I8_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_1024B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_1024, MCK_AV_32, MCK_AV_32, MCK_AISrc_1024B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22502 { 24669 /* v_mfma_i32_32x32x8i8 */, AMDGPU::V_MFMA_I32_32X32X8I8_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_512B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_512, MCK_AV_32, MCK_AV_32, MCK_AISrc_512B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22503 { 24690 /* v_mfma_i32_4x4x4i8 */, AMDGPU::V_MFMA_I32_4X4X4I8_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_128B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_128, MCK_AV_32, MCK_AV_32, MCK_AISrc_128B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 78283 { 24275 /* v_mfma_f32_16x16x16f16 */, 16 /* 4 */, MCK_ImmCBSZ, AMFBS_HasMAIInsts_HasMAIInsts }, 78286 { 24298 /* v_mfma_f32_16x16x1f32 */, 16 /* 4 */, MCK_ImmCBSZ, AMFBS_HasMAIInsts_HasMAIInsts }, 78289 { 24320 /* v_mfma_f32_16x16x2bf16 */, 16 /* 4 */, MCK_ImmCBSZ, AMFBS_HasMAIInsts_HasMAIInsts }, 78292 { 24343 /* v_mfma_f32_16x16x4f16 */, 16 /* 4 */, MCK_ImmCBSZ, AMFBS_HasMAIInsts_HasMAIInsts }, 78295 { 24365 /* v_mfma_f32_16x16x4f32 */, 16 /* 4 */, MCK_ImmCBSZ, AMFBS_HasMAIInsts_HasMAIInsts }, 78298 { 24387 /* v_mfma_f32_16x16x8bf16 */, 16 /* 4 */, MCK_ImmCBSZ, AMFBS_HasMAIInsts_HasMAIInsts }, 78301 { 24410 /* v_mfma_f32_32x32x1f32 */, 16 /* 4 */, MCK_ImmCBSZ, AMFBS_HasMAIInsts_HasMAIInsts }, 78304 { 24432 /* v_mfma_f32_32x32x2bf16 */, 16 /* 4 */, MCK_ImmCBSZ, AMFBS_HasMAIInsts_HasMAIInsts }, 78307 { 24455 /* v_mfma_f32_32x32x2f32 */, 16 /* 4 */, MCK_ImmCBSZ, AMFBS_HasMAIInsts_HasMAIInsts }, 78310 { 24477 /* v_mfma_f32_32x32x4bf16 */, 16 /* 4 */, MCK_ImmCBSZ, AMFBS_HasMAIInsts_HasMAIInsts }, 78313 { 24500 /* v_mfma_f32_32x32x4f16 */, 16 /* 4 */, MCK_ImmCBSZ, AMFBS_HasMAIInsts_HasMAIInsts }, 78316 { 24522 /* v_mfma_f32_32x32x8f16 */, 16 /* 4 */, MCK_ImmCBSZ, AMFBS_HasMAIInsts_HasMAIInsts }, 78319 { 24544 /* v_mfma_f32_4x4x1f32 */, 16 /* 4 */, MCK_ImmCBSZ, AMFBS_HasMAIInsts_HasMAIInsts }, 78322 { 24564 /* v_mfma_f32_4x4x2bf16 */, 16 /* 4 */, MCK_ImmCBSZ, AMFBS_HasMAIInsts_HasMAIInsts }, 78325 { 24585 /* v_mfma_f32_4x4x4f16 */, 16 /* 4 */, MCK_ImmCBSZ, AMFBS_HasMAIInsts_HasMAIInsts }, 78328 { 24605 /* v_mfma_i32_16x16x16i8 */, 16 /* 4 */, MCK_ImmCBSZ, AMFBS_HasMAIInsts_HasMAIInsts }, 78331 { 24627 /* v_mfma_i32_16x16x4i8 */, 16 /* 4 */, MCK_ImmCBSZ, AMFBS_HasMAIInsts_HasMAIInsts }, 78334 { 24648 /* v_mfma_i32_32x32x4i8 */, 16 /* 4 */, MCK_ImmCBSZ, AMFBS_HasMAIInsts_HasMAIInsts }, 78337 { 24669 /* v_mfma_i32_32x32x8i8 */, 16 /* 4 */, MCK_ImmCBSZ, AMFBS_HasMAIInsts_HasMAIInsts }, 78340 { 24690 /* v_mfma_i32_4x4x4i8 */, 16 /* 4 */, MCK_ImmCBSZ, AMFBS_HasMAIInsts_HasMAIInsts }, 80391 case MCK_ImmCBSZ: