reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

 5258   case MCK_ImmBankMask:
 6183   case MCK_ImmBankMask: {
10168   case MCK_ImmBankMask: return "MCK_ImmBankMask";
23562   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23563   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_dpp_w64_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23564   { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_dpp_w32_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23567   { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7, AMFBS_HasDPP_HasDPP_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23569   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23570   { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23572   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23573   { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23575   { 13355 /* v_add_nc_u32 */, AMDGPU::V_ADD_NC_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23576   { 13368 /* v_add_u16 */, AMDGPU::V_ADD_U16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23577   { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasAddNoCarryInsts_HasDPP_isGFX9Only, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23578   { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7, AMFBS_HasDPP_HasDPP_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23581   { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, AMFBS_HasDPP_HasDPP_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23582   { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, AMFBS_HasDPP_HasDPP_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23584   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23585   { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23586   { 13489 /* v_ashrrev_i16 */, AMDGPU::V_ASHRREV_I16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23588   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23589   { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23591   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23592   { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23594   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23595   { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23597   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23598   { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23608   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23609   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23610   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp_w64_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23611   { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp_w32_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23613   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23614   { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23616   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23617   { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23619   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23620   { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23622   { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23623   { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23625   { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23626   { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23628   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23629   { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23631   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23632   { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23634   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23635   { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23637   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23638   { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23640   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23641   { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23643   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23644   { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23646   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23647   { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23649   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23650   { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23652   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23653   { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23655   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23656   { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23658   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_isGFX9Plus_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23659   { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23661   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_isGFX9Plus_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23662   { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23664   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23665   { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23667   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23668   { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23670   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23671   { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23673   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23674   { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23676   { 22781 /* v_dot2c_f32_f16 */, AMDGPU::V_DOT2C_F32_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDot5Insts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23677   { 22781 /* v_dot2c_f32_f16 */, AMDGPU::V_DOT2C_F32_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDot5Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23678   { 22797 /* v_dot2c_i32_i16 */, AMDGPU::V_DOT2C_I32_I16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDot4Insts_HasDPP, { MCK_VGPR_32, MCK_VRegWithIntInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23680   { 22841 /* v_dot4c_i32_i8 */, AMDGPU::V_DOT4C_I32_I8_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDot6Insts_HasDPP, { MCK_VGPR_32, MCK_VRegWithIntInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23681   { 22841 /* v_dot4c_i32_i8 */, AMDGPU::V_DOT4C_I32_I8_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDot6Insts_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithIntInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23682   { 22884 /* v_dot8c_i32_i4 */, AMDGPU::V_DOT8C_I32_I4_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDot3Insts_HasDPP, { MCK_VGPR_32, MCK_VRegWithIntInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23684   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23685   { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23687   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23688   { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23689   { 22919 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_isGFX7GFX8GFX9_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23691   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23692   { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23694   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23695   { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23697   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23698   { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23700   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23701   { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23703   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23704   { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23706   { 23122 /* v_fmac_f16 */, AMDGPU::V_FMAC_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23708   { 23133 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDLInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23709   { 23133 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23711   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23712   { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23714   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23715   { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23717   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23718   { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23720   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23721   { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23723   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23724   { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23726   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23727   { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23729   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23730   { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23732   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23733   { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23735   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23736   { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23737   { 23521 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_isGFX7GFX8GFX9_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23738   { 23589 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23740   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23741   { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23742   { 23653 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23744   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23745   { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23746   { 23695 /* v_mac_f16 */, AMDGPU::V_MAC_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23748   { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23749   { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23751   { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23753   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23754   { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23756   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23757   { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23758   { 24114 /* v_max_i16 */, AMDGPU::V_MAX_I16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23760   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23761   { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23762   { 24151 /* v_max_u16 */, AMDGPU::V_MAX_U16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23764   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23765   { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23767   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23768   { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23770   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23771   { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23772   { 24805 /* v_min_i16 */, AMDGPU::V_MIN_I16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23774   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23775   { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23776   { 24842 /* v_min_u16 */, AMDGPU::V_MIN_U16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23778   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23779   { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23781   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23782   { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23784   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23785   { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23787   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23788   { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23790   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23791   { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23793   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23794   { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23796   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23797   { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23799   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23800   { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23802   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23803   { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23804   { 25123 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23806   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23807   { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23809   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23810   { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23812   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23813   { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23815   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23816   { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23818   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23819   { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23821   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23822   { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23824   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23825   { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23827   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23828   { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23830   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23831   { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23833   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23834   { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23836   { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_isGFX9Plus_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23837   { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23838   { 25879 /* v_screen_partition_4se_b32 */, AMDGPU::V_SCREEN_PARTITION_4SE_B32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_isGFX9Only_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23840   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23841   { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23843   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23844   { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23846   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23847   { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23849   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23850   { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23856   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23857   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_dpp_w64_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23858   { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_dpp_w32_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23861   { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7, AMFBS_HasDPP_HasDPP_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23863   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23864   { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23866   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23867   { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23869   { 26067 /* v_sub_nc_u32 */, AMDGPU::V_SUB_NC_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23870   { 26080 /* v_sub_u16 */, AMDGPU::V_SUB_U16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23871   { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasAddNoCarryInsts_HasDPP_isGFX9Only, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23872   { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7, AMFBS_HasDPP_HasDPP_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23875   { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, AMFBS_HasDPP_HasDPP_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23876   { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, AMFBS_HasDPP_HasDPP_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23879   { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, AMFBS_HasDPP_HasDPP_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23880   { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, AMFBS_HasDPP_HasDPP_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23886   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23887   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_dpp_w64_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23888   { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_dpp_w32_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23891   { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7, AMFBS_HasDPP_HasDPP_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23893   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23894   { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23896   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23897   { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23899   { 26230 /* v_subrev_nc_u32 */, AMDGPU::V_SUBREV_NC_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23900   { 26246 /* v_subrev_u16 */, AMDGPU::V_SUBREV_U16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23901   { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasAddNoCarryInsts_HasDPP_isGFX9Only, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23902   { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7, AMFBS_HasDPP_HasDPP_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23904   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23905   { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23907   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23908   { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23910   { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDLInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23911   { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23913   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23914   { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
72858   { 13222 /* v_add_co_ci_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
72869   { 13222 /* v_add_co_ci_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus_isWave64 },
72880   { 13222 /* v_add_co_ci_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus_isWave32 },
72895   { 13238 /* v_add_co_u32 */, 64 /* 6 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX9Only },
72914   { 13251 /* v_add_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
72925   { 13251 /* v_add_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
72956   { 13261 /* v_add_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
72967   { 13261 /* v_add_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
73004   { 13355 /* v_add_nc_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
73015   { 13368 /* v_add_u16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
73034   { 13378 /* v_add_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasAddNoCarryInsts_HasDPP_isGFX9Only },
73038   { 13378 /* v_add_u32 */, 64 /* 6 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX8Only },
73056   { 13388 /* v_addc_co_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX9Only },
73070   { 13402 /* v_addc_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX8Only },
73082   { 13444 /* v_and_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
73086   { 13444 /* v_and_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
73109   { 13489 /* v_ashrrev_i16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
73127   { 13503 /* v_ashrrev_i32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
73131   { 13503 /* v_ashrrev_i32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
73156   { 13586 /* v_bfrev_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
73175   { 13586 /* v_bfrev_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
73194   { 13598 /* v_ceil_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
73211   { 13598 /* v_ceil_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
73233   { 13609 /* v_ceil_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
73250   { 13609 /* v_ceil_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
75923   { 21959 /* v_cndmask_b32 */, 64 /* 6 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
75927   { 21959 /* v_cndmask_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
75938   { 21959 /* v_cndmask_b32 */, 64 /* 6 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus_isWave64 },
75943   { 21959 /* v_cndmask_b32 */, 64 /* 6 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus_isWave32 },
75986   { 21973 /* v_cos_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
76003   { 21973 /* v_cos_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76025   { 21983 /* v_cos_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76042   { 21983 /* v_cos_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76100   { 22045 /* v_cvt_f16_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76117   { 22045 /* v_cvt_f16_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76128   { 22059 /* v_cvt_f16_i16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
76137   { 22059 /* v_cvt_f16_i16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76160   { 22073 /* v_cvt_f16_u16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
76169   { 22073 /* v_cvt_f16_u16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76203   { 22087 /* v_cvt_f32_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76220   { 22087 /* v_cvt_f32_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76242   { 22115 /* v_cvt_f32_i32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76251   { 22115 /* v_cvt_f32_i32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76276   { 22129 /* v_cvt_f32_u32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76285   { 22129 /* v_cvt_f32_u32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76310   { 22143 /* v_cvt_f32_ubyte0 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76319   { 22143 /* v_cvt_f32_ubyte0 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76344   { 22160 /* v_cvt_f32_ubyte1 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76353   { 22160 /* v_cvt_f32_ubyte1 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76378   { 22177 /* v_cvt_f32_ubyte2 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76387   { 22177 /* v_cvt_f32_ubyte2 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76412   { 22194 /* v_cvt_f32_ubyte3 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76421   { 22194 /* v_cvt_f32_ubyte3 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76483   { 22253 /* v_cvt_flr_i32_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76488   { 22253 /* v_cvt_flr_i32_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76515   { 22271 /* v_cvt_i16_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
76520   { 22271 /* v_cvt_i16_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76549   { 22285 /* v_cvt_i32_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76554   { 22285 /* v_cvt_i32_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76587   { 22313 /* v_cvt_norm_i16_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_isGFX9Plus_HasDPP },
76592   { 22313 /* v_cvt_norm_i16_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76619   { 22332 /* v_cvt_norm_u16_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_isGFX9Plus_HasDPP },
76624   { 22332 /* v_cvt_norm_u16_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76637   { 22351 /* v_cvt_off_f32_i4 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76646   { 22351 /* v_cvt_off_f32_i4 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76735   { 22543 /* v_cvt_rpi_i32_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76740   { 22543 /* v_cvt_rpi_i32_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76767   { 22561 /* v_cvt_u16_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
76772   { 22561 /* v_cvt_u16_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76801   { 22575 /* v_cvt_u32_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76806   { 22575 /* v_cvt_u32_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76904   { 22781 /* v_dot2c_f32_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDot5Insts_HasDPP },
76909   { 22781 /* v_dot2c_f32_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDot5Insts_isGFX10Plus },
76915   { 22797 /* v_dot2c_i32_i16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDot4Insts_HasDPP },
76942   { 22841 /* v_dot4c_i32_i8 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDot6Insts_HasDPP },
76947   { 22841 /* v_dot4c_i32_i8 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDot6Insts_isGFX10Plus },
76973   { 22884 /* v_dot8c_i32_i4 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDot3Insts_HasDPP },
76991   { 22899 /* v_exp_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
77008   { 22899 /* v_exp_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77030   { 22909 /* v_exp_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77047   { 22909 /* v_exp_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77064   { 22919 /* v_exp_legacy_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_isGFX7GFX8GFX9_HasDPP },
77076   { 22936 /* v_ffbh_i32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77095   { 22936 /* v_ffbh_i32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77102   { 22947 /* v_ffbh_u32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77121   { 22947 /* v_ffbh_u32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77128   { 22958 /* v_ffbl_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77147   { 22958 /* v_ffbl_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77166   { 22969 /* v_floor_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
77183   { 22969 /* v_floor_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77205   { 22981 /* v_floor_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77222   { 22981 /* v_floor_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77298   { 23122 /* v_fmac_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77312   { 23133 /* v_fmac_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDLInsts_HasDPP },
77323   { 23133 /* v_fmac_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77344   { 23168 /* v_fract_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
77361   { 23168 /* v_fract_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77383   { 23180 /* v_fract_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77400   { 23180 /* v_fract_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77436   { 23204 /* v_frexp_exp_i16_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
77441   { 23204 /* v_frexp_exp_i16_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77470   { 23224 /* v_frexp_exp_i32_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77475   { 23224 /* v_frexp_exp_i32_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77500   { 23264 /* v_frexp_mant_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
77517   { 23264 /* v_frexp_mant_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77539   { 23281 /* v_frexp_mant_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77556   { 23281 /* v_frexp_mant_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77659   { 23439 /* v_ldexp_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
77672   { 23439 /* v_ldexp_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77734   { 23501 /* v_log_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
77751   { 23501 /* v_log_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77773   { 23511 /* v_log_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77790   { 23511 /* v_log_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77807   { 23521 /* v_log_legacy_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_isGFX7GFX8GFX9_HasDPP },
77817   { 23589 /* v_lshlrev_b16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
77835   { 23603 /* v_lshlrev_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77839   { 23603 /* v_lshlrev_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77862   { 23653 /* v_lshrrev_b16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
77880   { 23667 /* v_lshrrev_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77884   { 23667 /* v_lshrrev_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77911   { 23695 /* v_mac_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
77933   { 23705 /* v_mac_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77944   { 23705 /* v_mac_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77958   { 23715 /* v_mac_legacy_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78087   { 24084 /* v_max_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
78098   { 24084 /* v_max_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78129   { 24094 /* v_max_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78140   { 24094 /* v_max_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78168   { 24114 /* v_max_i16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
78186   { 24124 /* v_max_i32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78190   { 24124 /* v_max_i32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78216   { 24151 /* v_max_u16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
78234   { 24161 /* v_max_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78238   { 24161 /* v_max_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78376   { 24775 /* v_min_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
78387   { 24775 /* v_min_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78418   { 24785 /* v_min_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78429   { 24785 /* v_min_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78457   { 24805 /* v_min_i16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
78475   { 24815 /* v_min_i32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78479   { 24815 /* v_min_i32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78505   { 24842 /* v_min_u16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
78523   { 24852 /* v_min_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78527   { 24852 /* v_min_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78552   { 24862 /* v_mov_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78571   { 24862 /* v_mov_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78578   { 24872 /* v_mov_fed_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78597   { 24872 /* v_mov_fed_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78620   { 24989 /* v_mul_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
78631   { 24989 /* v_mul_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78662   { 24999 /* v_mul_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78673   { 24999 /* v_mul_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78703   { 25032 /* v_mul_hi_i32_i24 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78707   { 25032 /* v_mul_hi_i32_i24 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78732   { 25062 /* v_mul_hi_u32_u24 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78736   { 25062 /* v_mul_hi_u32_u24 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78761   { 25079 /* v_mul_i32_i24 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78765   { 25079 /* v_mul_i32_i24 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78800   { 25093 /* v_mul_legacy_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78811   { 25093 /* v_mul_legacy_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78830   { 25123 /* v_mul_lo_u16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
78848   { 25149 /* v_mul_u32_u24 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78852   { 25149 /* v_mul_u32_u24 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78883   { 25182 /* v_not_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78902   { 25182 /* v_not_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78909   { 25202 /* v_or_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78913   { 25202 /* v_or_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79157   { 25609 /* v_rcp_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
79174   { 25609 /* v_rcp_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79196   { 25619 /* v_rcp_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
79213   { 25619 /* v_rcp_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79244   { 25639 /* v_rcp_iflag_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
79261   { 25639 /* v_rcp_iflag_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79283   { 25707 /* v_rndne_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
79300   { 25707 /* v_rndne_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79322   { 25719 /* v_rndne_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
79339   { 25719 /* v_rndne_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79373   { 25775 /* v_rsq_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
79390   { 25775 /* v_rsq_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79412   { 25785 /* v_rsq_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
79429   { 25785 /* v_rsq_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79460   { 25863 /* v_sat_pk_u8_i16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_isGFX9Plus_HasDPP },
79479   { 25863 /* v_sat_pk_u8_i16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79484   { 25879 /* v_screen_partition_4se_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_isGFX9Only_HasDPP },
79507   { 25906 /* v_sin_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
79524   { 25906 /* v_sin_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79546   { 25916 /* v_sin_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
79563   { 25916 /* v_sin_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79582   { 25926 /* v_sqrt_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
79599   { 25926 /* v_sqrt_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79621   { 25937 /* v_sqrt_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
79638   { 25937 /* v_sqrt_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79660   { 25959 /* v_sub_co_ci_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79671   { 25959 /* v_sub_co_ci_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus_isWave64 },
79682   { 25959 /* v_sub_co_ci_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus_isWave32 },
79697   { 25975 /* v_sub_co_u32 */, 64 /* 6 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX9Only },
79716   { 25988 /* v_sub_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
79727   { 25988 /* v_sub_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79758   { 25998 /* v_sub_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
79769   { 25998 /* v_sub_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79797   { 26067 /* v_sub_nc_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79808   { 26080 /* v_sub_u16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
79827   { 26090 /* v_sub_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasAddNoCarryInsts_HasDPP_isGFX9Only },
79831   { 26090 /* v_sub_u32 */, 64 /* 6 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX8Only },
79849   { 26100 /* v_subb_co_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX9Only },
79863   { 26114 /* v_subb_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX8Only },
79875   { 26125 /* v_subbrev_co_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX9Only },
79889   { 26142 /* v_subbrev_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX8Only },
79907   { 26156 /* v_subrev_co_ci_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79918   { 26156 /* v_subrev_co_ci_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus_isWave64 },
79929   { 26156 /* v_subrev_co_ci_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus_isWave32 },
79944   { 26175 /* v_subrev_co_u32 */, 64 /* 6 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX9Only },
79963   { 26191 /* v_subrev_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
79974   { 26191 /* v_subrev_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
80005   { 26204 /* v_subrev_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
80016   { 26204 /* v_subrev_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
80040   { 26230 /* v_subrev_nc_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
80051   { 26246 /* v_subrev_u16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
80070   { 26259 /* v_subrev_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasAddNoCarryInsts_HasDPP_isGFX9Only },
80074   { 26259 /* v_subrev_u32 */, 64 /* 6 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX8Only },
80116   { 26314 /* v_trunc_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
80133   { 26314 /* v_trunc_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
80155   { 26326 /* v_trunc_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
80172   { 26326 /* v_trunc_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
80188   { 26376 /* v_xnor_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDLInsts_HasDPP },
80192   { 26376 /* v_xnor_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
80217   { 26398 /* v_xor_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
80221   { 26398 /* v_xor_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
80367   case MCK_ImmBankMask: