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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 5399 case MCK_Imm: {
10056 case MCK_Imm: return "MCK_Imm";
17594 { 8081 /* s_atc_probe */, AMDGPU::S_ATC_PROBE_SGPR_gfx10, Convert__Imm1_0__Reg1_1__Reg1_2, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_Imm, MCK_SReg_64, MCK_SReg_32 }, },
17595 { 8081 /* s_atc_probe */, AMDGPU::S_ATC_PROBE_SGPR_vi, Convert__Imm1_0__Reg1_1__Reg1_2, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_Imm, MCK_SReg_64, MCK_SReg_32 }, },
17596 { 8081 /* s_atc_probe */, AMDGPU::S_ATC_PROBE_IMM_gfx10, Convert__Imm1_0__Reg1_1__ImmSMRDOffset201_2, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_Imm, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
17597 { 8081 /* s_atc_probe */, AMDGPU::S_ATC_PROBE_IMM_vi, Convert__Imm1_0__Reg1_1__ImmSMRDOffset201_2, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_Imm, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
17598 { 8093 /* s_atc_probe_buffer */, AMDGPU::S_ATC_PROBE_BUFFER_SGPR_gfx10, Convert__Imm1_0__Reg1_1__Reg1_2, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_Imm, MCK_SReg_128, MCK_SReg_32 }, },
17599 { 8093 /* s_atc_probe_buffer */, AMDGPU::S_ATC_PROBE_BUFFER_SGPR_vi, Convert__Imm1_0__Reg1_1__Reg1_2, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_Imm, MCK_SReg_128, MCK_SReg_32 }, },
17600 { 8093 /* s_atc_probe_buffer */, AMDGPU::S_ATC_PROBE_BUFFER_IMM_gfx10, Convert__Imm1_0__Reg1_1__ImmSMRDOffset201_2, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_Imm, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
17601 { 8093 /* s_atc_probe_buffer */, AMDGPU::S_ATC_PROBE_BUFFER_IMM_vi, Convert__Imm1_0__Reg1_1__ImmSMRDOffset201_2, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_Imm, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
18233 { 10327 /* s_decperflevel */, AMDGPU::S_DECPERFLEVEL, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
18234 { 10342 /* s_denorm_mode */, AMDGPU::S_DENORM_MODE, Convert__Imm1_0, AMFBS_isGFX10Plus, { MCK_Imm }, },
18271 { 10595 /* s_incperflevel */, AMDGPU::S_INCPERFLEVEL, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
18392 { 11115 /* s_nop */, AMDGPU::S_NOP, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
18479 { 11713 /* s_sethalt */, AMDGPU::S_SETHALT, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
18480 { 11723 /* s_setkill */, AMDGPU::S_SETKILL, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
18484 { 11745 /* s_setprio */, AMDGPU::S_SETPRIO, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
18488 { 11768 /* s_setreg_imm32_b32 */, AMDGPU::S_SETREG_IMM32_B32_gfx10, Convert__Imm1_1__ImmHwreg1_0, AMFBS_isGFX10Plus, { MCK_ImmHwreg, MCK_Imm }, },
18489 { 11768 /* s_setreg_imm32_b32 */, AMDGPU::S_SETREG_IMM32_B32_gfx6_gfx7, Convert__Imm1_1__ImmHwreg1_0, AMFBS_isGFX6GFX7, { MCK_ImmHwreg, MCK_Imm }, },
18490 { 11768 /* s_setreg_imm32_b32 */, AMDGPU::S_SETREG_IMM32_B32_vi, Convert__Imm1_1__ImmHwreg1_0, AMFBS_isGFX8GFX9, { MCK_ImmHwreg, MCK_Imm }, },
18498 { 11827 /* s_sleep */, AMDGPU::S_SLEEP, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
18525 { 11969 /* s_trap */, AMDGPU::S_TRAP, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },