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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 5322 case MCK_Attr: {
10045 case MCK_Attr: return "MCK_Attr";
21193 { 23315 /* v_interp_mov_f32 */, AMDGPU::V_INTERP_MOV_F32_gfx10, Convert__Reg1_0__InterpSlot1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_InterpSlot, MCK_Attr, MCK_AttrChan }, },
21194 { 23315 /* v_interp_mov_f32 */, AMDGPU::V_INTERP_MOV_F32_si, Convert__Reg1_0__InterpSlot1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_InterpSlot, MCK_Attr, MCK_AttrChan }, },
21195 { 23315 /* v_interp_mov_f32 */, AMDGPU::V_INTERP_MOV_F32_vi, Convert__Reg1_0__InterpSlot1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_InterpSlot, MCK_Attr, MCK_AttrChan }, },
21196 { 23332 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_16bank_gfx10, Convert__Reg1_0__Reg1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
21197 { 23332 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_16bank_si, Convert__Reg1_0__Reg1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
21198 { 23332 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_16bank_vi, Convert__Reg1_0__Reg1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
21199 { 23332 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_gfx10, Convert__Reg1_0__Reg1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
21200 { 23332 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_si, Convert__Reg1_0__Reg1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
21201 { 23332 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_vi, Convert__Reg1_0__Reg1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
21202 { 23400 /* v_interp_p2_f32 */, AMDGPU::V_INTERP_P2_F32_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
21203 { 23400 /* v_interp_p2_f32 */, AMDGPU::V_INTERP_P2_F32_si, Convert__Reg1_0__Tie0_1_1__Reg1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
21204 { 23400 /* v_interp_p2_f32 */, AMDGPU::V_INTERP_P2_F32_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Attr1_2__AttrChan1_3, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
22331 { 23315 /* v_interp_mov_f32 */, AMDGPU::V_INTERP_MOV_F32_e64_gfx10, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_InterpSlot, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, },
22332 { 23315 /* v_interp_mov_f32 */, AMDGPU::V_INTERP_MOV_F32_e64_vi, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_InterpSlot, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, },
22333 { 23332 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_e64_gfx10, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, },
22334 { 23332 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_e64_vi, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, },
22335 { 23348 /* v_interp_p1ll_f16 */, AMDGPU::V_INTERP_P1LL_F16_gfx10, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmHigh, MCK_ImmClampSI, MCK_ImmOModSI }, },
22336 { 23348 /* v_interp_p1ll_f16 */, AMDGPU::V_INTERP_P1LL_F16_vi, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmHigh, MCK_ImmClampSI, MCK_ImmOModSI }, },
22337 { 23366 /* v_interp_p1lv_f16 */, AMDGPU::V_INTERP_P1LV_F16_gfx10, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP16InputMods, MCK_ImmHigh, MCK_ImmClampSI, MCK_ImmOModSI }, },
22338 { 23366 /* v_interp_p1lv_f16 */, AMDGPU::V_INTERP_P1LV_F16_vi, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP16InputMods, MCK_ImmHigh, MCK_ImmClampSI, MCK_ImmOModSI }, },
22339 { 23384 /* v_interp_p2_f16 */, AMDGPU::V_INTERP_P2_F16_gfx10, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP32InputMods, MCK_ImmHigh, MCK_ImmClampSI }, },
22340 { 23384 /* v_interp_p2_f16 */, AMDGPU::V_INTERP_P2_F16_gfx9_gfx9, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX9Plus_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP32InputMods, MCK_ImmHigh, MCK_ImmClampSI }, },
22341 { 23384 /* v_interp_p2_f16 */, AMDGPU::V_INTERP_P2_F16_vi, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX8Only, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP32InputMods, MCK_ImmHigh, MCK_ImmClampSI }, },
22342 { 23400 /* v_interp_p2_f32 */, AMDGPU::V_INTERP_P2_F32_e64_gfx10, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX8Plus_isGFX10Plus, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, },
22343 { 23400 /* v_interp_p2_f32 */, AMDGPU::V_INTERP_P2_F32_e64_vi, ConvertCustom_cvtVOP3Interp, AMFBS_isGFX8Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, },
22344 { 23416 /* v_interp_p2_legacy_f16 */, AMDGPU::V_INTERP_P2_LEGACY_F16_gfx9, ConvertCustom_cvtVOP3Interp, AMFBS_Has16BitInsts_isGFX9Only, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP32InputMods, MCK_ImmHigh, MCK_ImmClampSI }, },
77568 { 23315 /* v_interp_mov_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX10Plus },
77570 { 23315 /* v_interp_mov_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX6GFX7 },
77572 { 23315 /* v_interp_mov_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX8GFX9 },
77574 { 23315 /* v_interp_mov_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX8Plus_isGFX10Plus },
77578 { 23315 /* v_interp_mov_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX8Plus_isGFX8GFX9 },
77582 { 23332 /* v_interp_p1_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX10Plus },
77583 { 23332 /* v_interp_p1_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX6GFX7 },
77584 { 23332 /* v_interp_p1_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX8GFX9 },
77585 { 23332 /* v_interp_p1_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX10Plus },
77586 { 23332 /* v_interp_p1_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX6GFX7 },
77587 { 23332 /* v_interp_p1_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX8GFX9 },
77588 { 23332 /* v_interp_p1_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX8Plus_isGFX10Plus },
77592 { 23332 /* v_interp_p1_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX8Plus_isGFX8GFX9 },
77596 { 23348 /* v_interp_p1ll_f16 */, 4 /* 2 */, MCK_Attr, AMFBS_Has16BitInsts_isGFX10Plus },
77601 { 23348 /* v_interp_p1ll_f16 */, 4 /* 2 */, MCK_Attr, AMFBS_Has16BitInsts_isGFX8GFX9 },
77606 { 23366 /* v_interp_p1lv_f16 */, 4 /* 2 */, MCK_Attr, AMFBS_Has16BitInsts_isGFX10Plus },
77612 { 23366 /* v_interp_p1lv_f16 */, 4 /* 2 */, MCK_Attr, AMFBS_Has16BitInsts_isGFX8GFX9 },
77618 { 23384 /* v_interp_p2_f16 */, 4 /* 2 */, MCK_Attr, AMFBS_Has16BitInsts_isGFX10Plus },
77622 { 23384 /* v_interp_p2_f16 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX9Plus_isGFX9Only },
77626 { 23384 /* v_interp_p2_f16 */, 4 /* 2 */, MCK_Attr, AMFBS_Has16BitInsts_isGFX8Only },
77630 { 23400 /* v_interp_p2_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX10Plus },
77631 { 23400 /* v_interp_p2_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX6GFX7 },
77632 { 23400 /* v_interp_p2_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX8GFX9 },
77633 { 23400 /* v_interp_p2_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX8Plus_isGFX10Plus },
77637 { 23400 /* v_interp_p2_f32 */, 4 /* 2 */, MCK_Attr, AMFBS_isGFX8Plus_isGFX8GFX9 },
77641 { 23416 /* v_interp_p2_legacy_f16 */, 4 /* 2 */, MCK_Attr, AMFBS_Has16BitInsts_isGFX9Only },
80249 case MCK_Attr:
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 6991 case MCK_Attr: