reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
5142 return B == MCK_AV_64; 5148 case MCK_AV_64: return true; 10042 case MCK_AV_64: return "MCK_AV_64"; 22484 { 24275 /* v_mfma_f32_16x16x16f16 */, AMDGPU::V_MFMA_F32_16X16X16F16_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_128B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_128, MCK_AV_64, MCK_AV_64, MCK_AISrc_128B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22484 { 24275 /* v_mfma_f32_16x16x16f16 */, AMDGPU::V_MFMA_F32_16X16X16F16_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_128B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_128, MCK_AV_64, MCK_AV_64, MCK_AISrc_128B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22487 { 24343 /* v_mfma_f32_16x16x4f16 */, AMDGPU::V_MFMA_F32_16X16X4F16_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_512B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_512, MCK_AV_64, MCK_AV_64, MCK_AISrc_512B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22487 { 24343 /* v_mfma_f32_16x16x4f16 */, AMDGPU::V_MFMA_F32_16X16X4F16_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_512B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_512, MCK_AV_64, MCK_AV_64, MCK_AISrc_512B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22494 { 24500 /* v_mfma_f32_32x32x4f16 */, AMDGPU::V_MFMA_F32_32X32X4F16_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_1024B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_1024, MCK_AV_64, MCK_AV_64, MCK_AISrc_1024B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22494 { 24500 /* v_mfma_f32_32x32x4f16 */, AMDGPU::V_MFMA_F32_32X32X4F16_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_1024B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_1024, MCK_AV_64, MCK_AV_64, MCK_AISrc_1024B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22495 { 24522 /* v_mfma_f32_32x32x8f16 */, AMDGPU::V_MFMA_F32_32X32X8F16_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_512B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_512, MCK_AV_64, MCK_AV_64, MCK_AISrc_512B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22495 { 24522 /* v_mfma_f32_32x32x8f16 */, AMDGPU::V_MFMA_F32_32X32X8F16_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_512B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_512, MCK_AV_64, MCK_AV_64, MCK_AISrc_512B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22498 { 24585 /* v_mfma_f32_4x4x4f16 */, AMDGPU::V_MFMA_F32_4X4X4F16_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_128B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_128, MCK_AV_64, MCK_AV_64, MCK_AISrc_128B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, }, 22498 { 24585 /* v_mfma_f32_4x4x4f16 */, AMDGPU::V_MFMA_F32_4X4X4F16_vi, Convert__Reg1_0__Reg1_1__Reg1_2__AISrc_128B321_3__ImmCBSZ1_4__ImmABID1_5__ImmBLGP1_6, AMFBS_HasMAIInsts_HasMAIInsts, { MCK_AReg_128, MCK_AV_64, MCK_AV_64, MCK_AISrc_128B32, MCK_ImmCBSZ, MCK_ImmABID, MCK_ImmBLGP }, },