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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc18898 { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
18899 { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
18900 { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
18901 { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
18930 { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
18931 { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
18932 { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
18933 { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19026 { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19027 { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19028 { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19029 { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19114 { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19115 { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19116 { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19117 { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19210 { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19211 { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19212 { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19213 { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19306 { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19307 { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19308 { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19309 { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19402 { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19403 { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19404 { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19405 { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19434 { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19435 { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19436 { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19437 { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19594 { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19595 { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19596 { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19597 { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19626 { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19627 { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19628 { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19629 { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19658 { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19659 { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19660 { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19661 { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19690 { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19691 { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19692 { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19693 { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19722 { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19723 { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19724 { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19725 { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19754 { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19755 { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19756 { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19757 { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19786 { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19787 { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19788 { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19789 { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19874 { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19875 { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19876 { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19877 { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19906 { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19907 { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
19908 { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_e32_gfx10, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
19909 { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20194 { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20195 { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20220 { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20221 { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20298 { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20299 { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20372 { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20373 { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20450 { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20451 { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20528 { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20529 { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20606 { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20607 { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20632 { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20633 { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20762 { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20763 { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20788 { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20789 { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20814 { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20815 { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20840 { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20841 { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20866 { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20867 { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20892 { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20893 { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20918 { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20919 { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
20992 { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
20993 { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },
21018 { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
21019 { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcF16, MCK_VGPR_32 }, },