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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc18962 { 13839 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
18963 { 13839 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
18964 { 13839 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
18965 { 13839 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
18994 { 13929 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
18995 { 13929 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
18996 { 13929 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
18997 { 13929 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19057 { 14103 /* v_cmp_f_i16 */, AMDGPU::V_CMP_F_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19058 { 14103 /* v_cmp_f_i16 */, AMDGPU::V_CMP_F_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19085 { 14187 /* v_cmp_f_u16 */, AMDGPU::V_CMP_F_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19086 { 14187 /* v_cmp_f_u16 */, AMDGPU::V_CMP_F_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19146 { 14361 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19147 { 14361 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19148 { 14361 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19149 { 14361 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19178 { 14451 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19179 { 14451 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19180 { 14451 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19181 { 14451 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19242 { 14631 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19243 { 14631 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19244 { 14631 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19245 { 14631 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19274 { 14721 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19275 { 14721 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19276 { 14721 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19277 { 14721 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19338 { 14901 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19339 { 14901 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19340 { 14901 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19341 { 14901 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19370 { 14991 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19371 { 14991 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19372 { 14991 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19373 { 14991 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19466 { 15261 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19467 { 15261 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19468 { 15261 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19469 { 15261 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19498 { 15351 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19499 { 15351 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19500 { 15351 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19501 { 15351 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19530 { 15441 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19531 { 15441 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19532 { 15441 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19533 { 15441 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19562 { 15531 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19563 { 15531 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19564 { 15531 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_e32_gfx10, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX10Plus_isGFX10Plus_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19565 { 15531 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19817 { 16281 /* v_cmp_t_i16 */, AMDGPU::V_CMP_T_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19818 { 16281 /* v_cmp_t_i16 */, AMDGPU::V_CMP_T_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
19845 { 16365 /* v_cmp_t_u16 */, AMDGPU::V_CMP_T_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
19846 { 16365 /* v_cmp_t_u16 */, AMDGPU::V_CMP_T_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20246 { 18983 /* v_cmpx_eq_i16 */, AMDGPU::V_CMPX_EQ_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
20247 { 18983 /* v_cmpx_eq_i16 */, AMDGPU::V_CMPX_EQ_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20272 { 19079 /* v_cmpx_eq_u16 */, AMDGPU::V_CMPX_EQ_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
20273 { 19079 /* v_cmpx_eq_u16 */, AMDGPU::V_CMPX_EQ_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20323 { 19265 /* v_cmpx_f_i16 */, AMDGPU::V_CMPX_F_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
20324 { 19265 /* v_cmpx_f_i16 */, AMDGPU::V_CMPX_F_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20347 { 19355 /* v_cmpx_f_u16 */, AMDGPU::V_CMPX_F_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
20348 { 19355 /* v_cmpx_f_u16 */, AMDGPU::V_CMPX_F_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20398 { 19541 /* v_cmpx_ge_i16 */, AMDGPU::V_CMPX_GE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
20399 { 19541 /* v_cmpx_ge_i16 */, AMDGPU::V_CMPX_GE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20424 { 19637 /* v_cmpx_ge_u16 */, AMDGPU::V_CMPX_GE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
20425 { 19637 /* v_cmpx_ge_u16 */, AMDGPU::V_CMPX_GE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20476 { 19829 /* v_cmpx_gt_i16 */, AMDGPU::V_CMPX_GT_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
20477 { 19829 /* v_cmpx_gt_i16 */, AMDGPU::V_CMPX_GT_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20502 { 19925 /* v_cmpx_gt_u16 */, AMDGPU::V_CMPX_GT_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
20503 { 19925 /* v_cmpx_gt_u16 */, AMDGPU::V_CMPX_GT_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20554 { 20117 /* v_cmpx_le_i16 */, AMDGPU::V_CMPX_LE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
20555 { 20117 /* v_cmpx_le_i16 */, AMDGPU::V_CMPX_LE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20580 { 20213 /* v_cmpx_le_u16 */, AMDGPU::V_CMPX_LE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
20581 { 20213 /* v_cmpx_le_u16 */, AMDGPU::V_CMPX_LE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20658 { 20501 /* v_cmpx_lt_i16 */, AMDGPU::V_CMPX_LT_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
20659 { 20501 /* v_cmpx_lt_i16 */, AMDGPU::V_CMPX_LT_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20684 { 20597 /* v_cmpx_lt_u16 */, AMDGPU::V_CMPX_LT_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
20685 { 20597 /* v_cmpx_lt_u16 */, AMDGPU::V_CMPX_LT_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20710 { 20693 /* v_cmpx_ne_i16 */, AMDGPU::V_CMPX_NE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
20711 { 20693 /* v_cmpx_ne_i16 */, AMDGPU::V_CMPX_NE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20736 { 20789 /* v_cmpx_ne_u16 */, AMDGPU::V_CMPX_NE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
20737 { 20789 /* v_cmpx_ne_u16 */, AMDGPU::V_CMPX_NE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20943 { 21587 /* v_cmpx_t_i16 */, AMDGPU::V_CMPX_T_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
20944 { 21587 /* v_cmpx_t_i16 */, AMDGPU::V_CMPX_T_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },
20967 { 21677 /* v_cmpx_t_u16 */, AMDGPU::V_CMPX_T_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave64, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
20968 { 21677 /* v_cmpx_t_u16 */, AMDGPU::V_CMPX_T_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, AMFBS_isGFX8GFX9_isGFX8GFX9_isWave32, { MCK_VCC_LO, MCK_VSrcB16, MCK_VGPR_32 }, },