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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc18960 { 13839 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
18961 { 13839 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
18966 { 13852 /* v_cmp_eq_i16_e32 */, AMDGPU::V_CMP_EQ_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
18967 { 13852 /* v_cmp_eq_i16_e32 */, AMDGPU::V_CMP_EQ_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
18992 { 13929 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
18993 { 13929 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
18998 { 13942 /* v_cmp_eq_u16_e32 */, AMDGPU::V_CMP_EQ_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
18999 { 13942 /* v_cmp_eq_u16_e32 */, AMDGPU::V_CMP_EQ_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19056 { 14103 /* v_cmp_f_i16 */, AMDGPU::V_CMP_F_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19059 { 14115 /* v_cmp_f_i16_e32 */, AMDGPU::V_CMP_F_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19084 { 14187 /* v_cmp_f_u16 */, AMDGPU::V_CMP_F_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19087 { 14199 /* v_cmp_f_u16_e32 */, AMDGPU::V_CMP_F_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19144 { 14361 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
19145 { 14361 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19150 { 14374 /* v_cmp_ge_i16_e32 */, AMDGPU::V_CMP_GE_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
19151 { 14374 /* v_cmp_ge_i16_e32 */, AMDGPU::V_CMP_GE_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19176 { 14451 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
19177 { 14451 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19182 { 14464 /* v_cmp_ge_u16_e32 */, AMDGPU::V_CMP_GE_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
19183 { 14464 /* v_cmp_ge_u16_e32 */, AMDGPU::V_CMP_GE_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19240 { 14631 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
19241 { 14631 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19246 { 14644 /* v_cmp_gt_i16_e32 */, AMDGPU::V_CMP_GT_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
19247 { 14644 /* v_cmp_gt_i16_e32 */, AMDGPU::V_CMP_GT_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19272 { 14721 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
19273 { 14721 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19278 { 14734 /* v_cmp_gt_u16_e32 */, AMDGPU::V_CMP_GT_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
19279 { 14734 /* v_cmp_gt_u16_e32 */, AMDGPU::V_CMP_GT_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19336 { 14901 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
19337 { 14901 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19342 { 14914 /* v_cmp_le_i16_e32 */, AMDGPU::V_CMP_LE_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
19343 { 14914 /* v_cmp_le_i16_e32 */, AMDGPU::V_CMP_LE_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19368 { 14991 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
19369 { 14991 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19374 { 15004 /* v_cmp_le_u16_e32 */, AMDGPU::V_CMP_LE_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
19375 { 15004 /* v_cmp_le_u16_e32 */, AMDGPU::V_CMP_LE_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19464 { 15261 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
19465 { 15261 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19470 { 15274 /* v_cmp_lt_i16_e32 */, AMDGPU::V_CMP_LT_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
19471 { 15274 /* v_cmp_lt_i16_e32 */, AMDGPU::V_CMP_LT_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19496 { 15351 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
19497 { 15351 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19502 { 15364 /* v_cmp_lt_u16_e32 */, AMDGPU::V_CMP_LT_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
19503 { 15364 /* v_cmp_lt_u16_e32 */, AMDGPU::V_CMP_LT_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19528 { 15441 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
19529 { 15441 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19534 { 15454 /* v_cmp_ne_i16_e32 */, AMDGPU::V_CMP_NE_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
19535 { 15454 /* v_cmp_ne_i16_e32 */, AMDGPU::V_CMP_NE_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19560 { 15531 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
19561 { 15531 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19566 { 15544 /* v_cmp_ne_u16_e32 */, AMDGPU::V_CMP_NE_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
19567 { 15544 /* v_cmp_ne_u16_e32 */, AMDGPU::V_CMP_NE_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19816 { 16281 /* v_cmp_t_i16 */, AMDGPU::V_CMP_T_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19819 { 16293 /* v_cmp_t_i16_e32 */, AMDGPU::V_CMP_T_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19844 { 16365 /* v_cmp_t_u16 */, AMDGPU::V_CMP_T_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
19847 { 16377 /* v_cmp_t_u16_e32 */, AMDGPU::V_CMP_T_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20244 { 18983 /* v_cmpx_eq_i16 */, AMDGPU::V_CMPX_EQ_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20245 { 18983 /* v_cmpx_eq_i16 */, AMDGPU::V_CMPX_EQ_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20248 { 18997 /* v_cmpx_eq_i16_e32 */, AMDGPU::V_CMPX_EQ_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20249 { 18997 /* v_cmpx_eq_i16_e32 */, AMDGPU::V_CMPX_EQ_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20270 { 19079 /* v_cmpx_eq_u16 */, AMDGPU::V_CMPX_EQ_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20271 { 19079 /* v_cmpx_eq_u16 */, AMDGPU::V_CMPX_EQ_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20274 { 19093 /* v_cmpx_eq_u16_e32 */, AMDGPU::V_CMPX_EQ_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20275 { 19093 /* v_cmpx_eq_u16_e32 */, AMDGPU::V_CMPX_EQ_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20322 { 19265 /* v_cmpx_f_i16 */, AMDGPU::V_CMPX_F_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20325 { 19278 /* v_cmpx_f_i16_e32 */, AMDGPU::V_CMPX_F_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20346 { 19355 /* v_cmpx_f_u16 */, AMDGPU::V_CMPX_F_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20349 { 19368 /* v_cmpx_f_u16_e32 */, AMDGPU::V_CMPX_F_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20396 { 19541 /* v_cmpx_ge_i16 */, AMDGPU::V_CMPX_GE_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20397 { 19541 /* v_cmpx_ge_i16 */, AMDGPU::V_CMPX_GE_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20400 { 19555 /* v_cmpx_ge_i16_e32 */, AMDGPU::V_CMPX_GE_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20401 { 19555 /* v_cmpx_ge_i16_e32 */, AMDGPU::V_CMPX_GE_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20422 { 19637 /* v_cmpx_ge_u16 */, AMDGPU::V_CMPX_GE_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20423 { 19637 /* v_cmpx_ge_u16 */, AMDGPU::V_CMPX_GE_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20426 { 19651 /* v_cmpx_ge_u16_e32 */, AMDGPU::V_CMPX_GE_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20427 { 19651 /* v_cmpx_ge_u16_e32 */, AMDGPU::V_CMPX_GE_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20474 { 19829 /* v_cmpx_gt_i16 */, AMDGPU::V_CMPX_GT_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20475 { 19829 /* v_cmpx_gt_i16 */, AMDGPU::V_CMPX_GT_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20478 { 19843 /* v_cmpx_gt_i16_e32 */, AMDGPU::V_CMPX_GT_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20479 { 19843 /* v_cmpx_gt_i16_e32 */, AMDGPU::V_CMPX_GT_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20500 { 19925 /* v_cmpx_gt_u16 */, AMDGPU::V_CMPX_GT_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20501 { 19925 /* v_cmpx_gt_u16 */, AMDGPU::V_CMPX_GT_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20504 { 19939 /* v_cmpx_gt_u16_e32 */, AMDGPU::V_CMPX_GT_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20505 { 19939 /* v_cmpx_gt_u16_e32 */, AMDGPU::V_CMPX_GT_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20552 { 20117 /* v_cmpx_le_i16 */, AMDGPU::V_CMPX_LE_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20553 { 20117 /* v_cmpx_le_i16 */, AMDGPU::V_CMPX_LE_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20556 { 20131 /* v_cmpx_le_i16_e32 */, AMDGPU::V_CMPX_LE_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20557 { 20131 /* v_cmpx_le_i16_e32 */, AMDGPU::V_CMPX_LE_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20578 { 20213 /* v_cmpx_le_u16 */, AMDGPU::V_CMPX_LE_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20579 { 20213 /* v_cmpx_le_u16 */, AMDGPU::V_CMPX_LE_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20582 { 20227 /* v_cmpx_le_u16_e32 */, AMDGPU::V_CMPX_LE_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20583 { 20227 /* v_cmpx_le_u16_e32 */, AMDGPU::V_CMPX_LE_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20656 { 20501 /* v_cmpx_lt_i16 */, AMDGPU::V_CMPX_LT_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20657 { 20501 /* v_cmpx_lt_i16 */, AMDGPU::V_CMPX_LT_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20660 { 20515 /* v_cmpx_lt_i16_e32 */, AMDGPU::V_CMPX_LT_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20661 { 20515 /* v_cmpx_lt_i16_e32 */, AMDGPU::V_CMPX_LT_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20682 { 20597 /* v_cmpx_lt_u16 */, AMDGPU::V_CMPX_LT_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20683 { 20597 /* v_cmpx_lt_u16 */, AMDGPU::V_CMPX_LT_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20686 { 20611 /* v_cmpx_lt_u16_e32 */, AMDGPU::V_CMPX_LT_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20687 { 20611 /* v_cmpx_lt_u16_e32 */, AMDGPU::V_CMPX_LT_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20708 { 20693 /* v_cmpx_ne_i16 */, AMDGPU::V_CMPX_NE_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20709 { 20693 /* v_cmpx_ne_i16 */, AMDGPU::V_CMPX_NE_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20712 { 20707 /* v_cmpx_ne_i16_e32 */, AMDGPU::V_CMPX_NE_I16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20713 { 20707 /* v_cmpx_ne_i16_e32 */, AMDGPU::V_CMPX_NE_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20734 { 20789 /* v_cmpx_ne_u16 */, AMDGPU::V_CMPX_NE_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20735 { 20789 /* v_cmpx_ne_u16 */, AMDGPU::V_CMPX_NE_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20738 { 20803 /* v_cmpx_ne_u16_e32 */, AMDGPU::V_CMPX_NE_U16_e32_gfx10, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VSrcB16, MCK_VGPR_32 }, },
20739 { 20803 /* v_cmpx_ne_u16_e32 */, AMDGPU::V_CMPX_NE_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20942 { 21587 /* v_cmpx_t_i16 */, AMDGPU::V_CMPX_T_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20945 { 21600 /* v_cmpx_t_i16_e32 */, AMDGPU::V_CMPX_T_I16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20966 { 21677 /* v_cmpx_t_u16 */, AMDGPU::V_CMPX_T_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_isGFX8GFX9_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },
20969 { 21690 /* v_cmpx_t_u16_e32 */, AMDGPU::V_CMPX_T_U16_e32_vi, Convert__VSrcB161_0__Reg1_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VSrcB16, MCK_VGPR_32 }, },