|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc18890 { 13620 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_VSrcF64 }, },
18891 { 13620 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e32_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_VSrcF64 }, },
18892 { 13620 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcF64 }, },
21066 { 22101 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF64 }, },
21067 { 22101 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF64 }, },
21068 { 22101 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF64 }, },
21104 { 22299 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF64 }, },
21105 { 22299 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF64 }, },
21106 { 22299 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF64 }, },
21129 { 22589 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF64 }, },
21130 { 22589 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF64 }, },
21131 { 22589 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF64 }, },
21159 { 22993 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_VSrcF64 }, },
21160 { 22993 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e32_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_VSrcF64 }, },
21161 { 22993 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcF64 }, },
21174 { 23192 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcF64 }, },
21175 { 23192 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcF64 }, },
21176 { 23192 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcF64 }, },
21182 { 23244 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF64 }, },
21183 { 23244 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF64 }, },
21184 { 23244 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF64 }, },
21190 { 23298 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcF64 }, },
21191 { 23298 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcF64 }, },
21192 { 23298 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcF64 }, },
21320 { 25593 /* v_rcp_clamp_f64 */, AMDGPU::V_RCP_CLAMP_F64_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcF64 }, },
21326 { 25629 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcF64 }, },
21327 { 25629 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcF64 }, },
21328 { 25629 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcF64 }, },
21342 { 25731 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_VSrcF64 }, },
21343 { 25731 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e32_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_VSrcF64 }, },
21344 { 25731 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcF64 }, },
21346 { 25759 /* v_rsq_clamp_f64 */, AMDGPU::V_RSQ_CLAMP_F64_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcF64 }, },
21352 { 25795 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcF64 }, },
21353 { 25795 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcF64 }, },
21354 { 25795 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcF64 }, },
21369 { 25948 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcF64 }, },
21370 { 25948 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcF64 }, },
21371 { 25948 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcF64 }, },
21422 { 26338 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e32_gfx10, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX10Plus, { MCK_VReg_64, MCK_VSrcF64 }, },
21423 { 26338 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e32_gfx7, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX7Only, { MCK_VReg_64, MCK_VSrcF64 }, },
21424 { 26338 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, AMFBS_isGFX7Plus_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcF64 }, },