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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc18859 { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
18860 { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
18861 { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21116 { 22418 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21117 { 22460 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21118 { 22502 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21119 { 22523 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21120 { 22523 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21207 { 23451 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21230 { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7GFX10_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21231 { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21242 { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21243 { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21244 { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21249 { 24134 /* v_max_legacy_f32 */, AMDGPU::V_MAX_LEGACY_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21258 { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21259 { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21260 { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21265 { 24825 /* v_min_legacy_f32 */, AMDGPU::V_MIN_LEGACY_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21288 { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21289 { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21290 { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21300 { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21301 { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21302 { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21380 { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21381 { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21382 { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21406 { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21407 { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
21408 { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },