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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc18887 { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
18888 { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
18889 { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21053 { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21054 { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21055 { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21056 { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21057 { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21058 { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21087 { 22211 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcF32 }, },
21088 { 22211 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcF32 }, },
21089 { 22211 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcF32 }, },
21096 { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21097 { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21098 { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21101 { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21102 { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21103 { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21121 { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21122 { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21123 { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21126 { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21127 { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21128 { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21140 { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21141 { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21142 { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21143 { 22919 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_e32_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX7GFX8GFX9_isGFX7Only, { MCK_VGPR_32, MCK_VSrcF32 }, },
21144 { 22919 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21156 { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21157 { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21158 { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21171 { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21172 { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21173 { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21179 { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21180 { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21181 { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21187 { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21188 { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21189 { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21208 { 23485 /* v_log_clamp_f32 */, AMDGPU::V_LOG_CLAMP_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21211 { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21212 { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21213 { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21214 { 23521 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_e32_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX7GFX8GFX9_isGFX7Only, { MCK_VGPR_32, MCK_VSrcF32 }, },
21215 { 23521 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX7GFX8GFX9_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21319 { 25577 /* v_rcp_clamp_f32 */, AMDGPU::V_RCP_CLAMP_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21323 { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21324 { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21325 { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21329 { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21330 { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21331 { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21332 { 25655 /* v_rcp_legacy_f32 */, AMDGPU::V_RCP_LEGACY_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21339 { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21340 { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21341 { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21345 { 25743 /* v_rsq_clamp_f32 */, AMDGPU::V_RSQ_CLAMP_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21349 { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21350 { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21351 { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21355 { 25805 /* v_rsq_legacy_f32 */, AMDGPU::V_RSQ_LEGACY_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21361 { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21362 { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21363 { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21366 { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21367 { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21368 { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },
21419 { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e32_gfx10, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF32 }, },
21420 { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF32 }, },
21421 { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF32 }, },