reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
18857 { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, }, 18858 { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, }, 21205 { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, }, 21206 { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, }, 21240 { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, }, 21241 { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, }, 21256 { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, }, 21257 { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, }, 21286 { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, }, 21287 { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, }, 21378 { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, }, 21379 { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, }, 21404 { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, }, 21405 { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },