reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
18885 { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, }, 18886 { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21051 { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21052 { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21063 { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21064 { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e32_gfx6_gfx7, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21065 { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21099 { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21100 { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21107 { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21108 { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21109 { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21110 { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21124 { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21125 { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21138 { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21139 { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21154 { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21155 { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21169 { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21170 { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21177 { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21178 { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21185 { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21186 { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21209 { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21210 { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21321 { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21322 { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21337 { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21338 { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21347 { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21348 { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21359 { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21360 { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21364 { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21365 { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21417 { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_e32_gfx10, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcF16 }, }, 21418 { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, AMFBS_Has16BitInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcF16 }, },