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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc21456 { 13291 /* v_add_i32 */, AMDGPU::V_ADD_I32_gfx9_gfx9, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX9Plus_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21461 { 13329 /* v_add_nc_i32 */, AMDGPU::V_ADD_NC_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21478 { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21479 { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21480 { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21483 { 13467 /* v_ashr_i32 */, AMDGPU::V_ASHR_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21487 { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21488 { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21489 { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21492 { 13531 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21493 { 13531 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21494 { 13531 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21504 { 13576 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21505 { 13576 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
21506 { 13576 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22189 { 22368 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22190 { 22368 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22191 { 22368 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22192 { 22385 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22193 { 22385 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22194 { 22385 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22367 { 23553 /* v_lshl_b32 */, AMDGPU::V_LSHL_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22373 { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22374 { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22375 { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22378 { 23631 /* v_lshr_b32 */, AMDGPU::V_LSHR_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22382 { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22383 { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22384 { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22454 { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22455 { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22456 { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22460 { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22461 { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22462 { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22463 { 24171 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22464 { 24171 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22465 { 24171 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22466 { 24190 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22467 { 24190 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22468 { 24190 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22529 { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22530 { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22531 { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22535 { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22536 { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22537 { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22571 { 25019 /* v_mul_hi_i32 */, AMDGPU::V_MUL_HI_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22572 { 25019 /* v_mul_hi_i32 */, AMDGPU::V_MUL_HI_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22573 { 25019 /* v_mul_hi_i32 */, AMDGPU::V_MUL_HI_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22574 { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22575 { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22576 { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22577 { 25049 /* v_mul_hi_u32 */, AMDGPU::V_MUL_HI_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22578 { 25049 /* v_mul_hi_u32 */, AMDGPU::V_MUL_HI_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22579 { 25049 /* v_mul_hi_u32 */, AMDGPU::V_MUL_HI_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22580 { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22581 { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22582 { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22583 { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22584 { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22585 { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22589 { 25110 /* v_mul_lo_i32 */, AMDGPU::V_MUL_LO_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22590 { 25110 /* v_mul_lo_i32 */, AMDGPU::V_MUL_LO_I32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22591 { 25110 /* v_mul_lo_i32 */, AMDGPU::V_MUL_LO_I32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22594 { 25136 /* v_mul_lo_u32 */, AMDGPU::V_MUL_LO_U32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22595 { 25136 /* v_mul_lo_u32 */, AMDGPU::V_MUL_LO_U32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22596 { 25136 /* v_mul_lo_u32 */, AMDGPU::V_MUL_LO_U32_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22597 { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22598 { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22599 { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22610 { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22611 { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22612 { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22735 { 26018 /* v_sub_i32 */, AMDGPU::V_SUB_I32_gfx9_gfx9, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX9Plus_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22738 { 26041 /* v_sub_nc_i32 */, AMDGPU::V_SUB_NC_I32_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22784 { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_HasDLInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22785 { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_HasDLInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22787 { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22788 { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },
22789 { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e64_vi, Convert__Reg1_0__VSrcB321_1__VSrcB321_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VSrcB32 }, },