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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc18851 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18863 { 13355 /* v_add_nc_u32 */, AMDGPU::V_ADD_NC_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_HasAddNoCarryInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18865 { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_HasAddNoCarryInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18872 { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18873 { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18874 { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18875 { 13467 /* v_ashr_i32 */, AMDGPU::V_ASHR_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18877 { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18878 { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18879 { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18880 { 13531 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
18881 { 13576 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21042 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21043 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21044 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21045 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21046 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21047 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21048 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21049 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21050 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21114 { 22368 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21115 { 22385 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21216 { 23553 /* v_lshl_b32 */, AMDGPU::V_LSHL_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21218 { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21219 { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21220 { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21221 { 23631 /* v_lshr_b32 */, AMDGPU::V_LSHR_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7GFX10_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21223 { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21224 { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21225 { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21246 { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21247 { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21248 { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21251 { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21252 { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21253 { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21254 { 24171 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21255 { 24190 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21262 { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21263 { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21264 { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21267 { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21268 { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21269 { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21291 { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21292 { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21293 { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21294 { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21295 { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21296 { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21297 { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21298 { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21299 { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21304 { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21305 { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21306 { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21313 { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21314 { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21315 { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21372 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21384 { 26067 /* v_sub_nc_u32 */, AMDGPU::V_SUB_NC_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_HasAddNoCarryInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21386 { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_HasAddNoCarryInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21398 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21410 { 26230 /* v_subrev_nc_u32 */, AMDGPU::V_SUBREV_NC_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_HasAddNoCarryInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21412 { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_HasAddNoCarryInsts_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21428 { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_HasDLInsts_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21429 { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_HasDLInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21430 { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21431 { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
21432 { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
22108 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22109 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22110 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22111 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22112 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22113 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22942 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22943 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22944 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22945 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22946 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22947 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23346 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23347 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23348 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23349 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23350 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23351 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23599 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23600 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23601 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23602 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX6GFX7_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23603 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX8GFX9_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23604 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1__Reg1_2, AMFBS_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },