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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc18882 { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
18883 { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
18884 { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21069 { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21070 { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21071 { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21072 { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21073 { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21074 { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21075 { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21076 { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21077 { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21078 { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21079 { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21080 { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21081 { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21082 { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21083 { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21084 { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21085 { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21086 { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21090 { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB32 }, },
21091 { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB32 }, },
21092 { 22225 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB32 }, },
21093 { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VReg_64, MCK_VSrcB32 }, },
21094 { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VReg_64, MCK_VSrcB32 }, },
21095 { 22239 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VReg_64, MCK_VSrcB32 }, },
21111 { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21112 { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21113 { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21145 { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21146 { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21147 { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21148 { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21149 { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21150 { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21151 { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21152 { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21153 { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21270 { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21271 { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21272 { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21273 { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21274 { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21275 { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21276 { 24886 /* v_movreld_b32 */, AMDGPU::V_MOVRELD_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21277 { 24886 /* v_movreld_b32 */, AMDGPU::V_MOVRELD_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21278 { 24886 /* v_movreld_b32 */, AMDGPU::V_MOVRELD_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21282 { 24914 /* v_movrelsd_2_b32 */, AMDGPU::V_MOVRELSD_2_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21283 { 24931 /* v_movrelsd_b32 */, AMDGPU::V_MOVRELSD_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21284 { 24931 /* v_movrelsd_b32 */, AMDGPU::V_MOVRELSD_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21285 { 24931 /* v_movrelsd_b32 */, AMDGPU::V_MOVRELSD_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21310 { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21311 { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_e32_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21312 { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21356 { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_e32_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21357 { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
21358 { 25879 /* v_screen_partition_4se_b32 */, AMDGPU::V_SCREEN_PARTITION_4SE_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX9Only_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32 }, },
21507 { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
21508 { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
21509 { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22271 { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22272 { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22273 { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22274 { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22275 { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22276 { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22277 { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22278 { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22279 { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22538 { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22539 { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22540 { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22541 { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22542 { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22543 { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22544 { 24886 /* v_movreld_b32 */, AMDGPU::V_MOVRELD_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22545 { 24886 /* v_movreld_b32 */, AMDGPU::V_MOVRELD_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22546 { 24886 /* v_movreld_b32 */, AMDGPU::V_MOVRELD_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22550 { 24914 /* v_movrelsd_2_b32 */, AMDGPU::V_MOVRELSD_2_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22551 { 24931 /* v_movrelsd_b32 */, AMDGPU::V_MOVRELSD_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22552 { 24931 /* v_movrelsd_b32 */, AMDGPU::V_MOVRELSD_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22553 { 24931 /* v_movrelsd_b32 */, AMDGPU::V_MOVRELSD_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_HasMovrel_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22605 { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22606 { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_e64_gfx6_gfx7, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX6GFX7, { MCK_VGPR_32, MCK_VSrcB32 }, },
22607 { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22706 { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_e64_gfx10, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX9Plus_isGFX10Plus, { MCK_VGPR_32, MCK_VSrcB32 }, },
22707 { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX9Plus_isGFX8GFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
22708 { 25879 /* v_screen_partition_4se_b32 */, AMDGPU::V_SCREEN_PARTITION_4SE_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, AMFBS_isGFX9Only_isGFX9Only, { MCK_VGPR_32, MCK_VSrcB32 }, },